hw/timer/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/timer/m48t59.h"
  27 #include "qemu/timer.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/isa/isa.h"
  31 #include "exec/address-spaces.h"
  32
  33 //#define DEBUG_NVRAM
  34
  35 #if defined(DEBUG_NVRAM)
  36 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  37 #else
  38 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
  39 #endif
  40
  41 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
  42 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
  43     OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
  44 #define M48TXX_SYS_BUS_CLASS(klass) \
  45     OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
  46 #define M48TXX_SYS_BUS(obj) \
  47     OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
  48
  49 #define TYPE_M48TXX_ISA "isa-m48txx"
  50 #define M48TXX_ISA_GET_CLASS(obj) \
  51     OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
  52 #define M48TXX_ISA_CLASS(klass) \
  53     OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
  54 #define M48TXX_ISA(obj) \
  55     OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
  56
  57 /*
  58  * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
  59  * alarm and a watchdog timer and related control registers. In the
  60  * PPC platform there is also a nvram lock function.
  61  */
  62
  63 typedef struct M48txxInfo {
  64     const char *isa_name;
  65     const char *sysbus_name;
  66     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  67     uint32_t size;
  68 } M48txxInfo;
  69
  70 /*
  71  * Chipset docs:
  72  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  73  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  74  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  75  */
  76
  77 typedef struct M48t59State {
  78     /* Hardware parameters */
  79     qemu_irq IRQ;
  80     MemoryRegion iomem;
  81     uint32_t size;
  82     /* RTC management */
  83     time_t   time_offset;
  84     time_t   stop_time;
  85     /* Alarm & watchdog */
  86     struct tm alarm;
  87     QEMUTimer *alrm_timer;
  88     QEMUTimer *wd_timer;
  89     /* NVRAM storage */
  90     uint8_t *buffer;
  91     /* Model parameters */
  92     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  93     /* NVRAM storage */
  94     uint16_t addr;
  95     uint8_t  lock;
  96 } M48t59State;
  97
  98 typedef struct M48txxISAState {
  99     ISADevice parent_obj;
 100     M48t59State state;
 101     uint32_t io_base;
 102     MemoryRegion io;
 103 } M48txxISAState;
 104
 105 typedef struct M48txxISADeviceClass {
 106     ISADeviceClass parent_class;
 107     M48txxInfo info;
 108 } M48txxISADeviceClass;
 109
 110 typedef struct M48txxSysBusState {
 111     SysBusDevice parent_obj;
 112     M48t59State state;
 113     MemoryRegion io;
 114 } M48txxSysBusState;
 115
 116 typedef struct M48txxSysBusDeviceClass {
 117     SysBusDeviceClass parent_class;
 118     M48txxInfo info;
 119 } M48txxSysBusDeviceClass;
 120
 121 static M48txxInfo m48txx_info[] = {
 122     {
 123         .sysbus_name = "sysbus-m48t02",
 124         .model = 2,
 125         .size = 0x800,
 126     },{
 127         .sysbus_name = "sysbus-m48t08",
 128         .model = 8,
 129         .size = 0x2000,
 130     },{
 131         .isa_name = "isa-m48t59",
 132         .model = 59,
 133         .size = 0x2000,
 134     }
 135 };
 136
 137
 138 /* Fake timer functions */
 139
 140 /* Alarm management */
 141 static void alarm_cb (void *opaque)
 142 {
 143     struct tm tm;
 144     uint64_t next_time;
 145     M48t59State *NVRAM = opaque;
 146
 147     qemu_set_irq(NVRAM->IRQ, 1);
 148     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
 149         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 150         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 151         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 152         /* Repeat once a month */
 153         qemu_get_timedate(&tm, NVRAM->time_offset);
 154         tm.tm_mon++;
 155         if (tm.tm_mon == 13) {
 156             tm.tm_mon = 1;
 157             tm.tm_year++;
 158         }
 159         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 160     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 161                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 162                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 163                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 164         /* Repeat once a day */
 165         next_time = 24 * 60 * 60;
 166     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 167                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 168                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 169                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 170         /* Repeat once an hour */
 171         next_time = 60 * 60;
 172     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 173                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 174                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 175                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 176         /* Repeat once a minute */
 177         next_time = 60;
 178     } else {
 179         /* Repeat once a second */
 180         next_time = 1;
 181     }
 182     timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
 183                     next_time * 1000);
 184     qemu_set_irq(NVRAM->IRQ, 0);
 185 }
 186
 187 static void set_alarm(M48t59State *NVRAM)
 188 {
 189     int diff;
 190     if (NVRAM->alrm_timer != NULL) {
 191         timer_del(NVRAM->alrm_timer);
 192         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 193         if (diff > 0)
 194             timer_mod(NVRAM->alrm_timer, diff * 1000);
 195     }
 196 }
 197
 198 /* RTC management helpers */
 199 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 200 {
 201     qemu_get_timedate(tm, NVRAM->time_offset);
 202 }
 203
 204 static void set_time(M48t59State *NVRAM, struct tm *tm)
 205 {
 206     NVRAM->time_offset = qemu_timedate_diff(tm);
 207     set_alarm(NVRAM);
 208 }
 209
 210 /* Watchdog management */
 211 static void watchdog_cb (void *opaque)
 212 {
 213     M48t59State *NVRAM = opaque;
 214
 215     NVRAM->buffer[0x1FF0] |= 0x80;
 216     if (NVRAM->buffer[0x1FF7] & 0x80) {
 217         NVRAM->buffer[0x1FF7] = 0x00;
 218         NVRAM->buffer[0x1FFC] &= ~0x40;
 219         /* May it be a hw CPU Reset instead ? */
 220         qemu_system_reset_request();
 221     } else {
 222         qemu_set_irq(NVRAM->IRQ, 1);
 223         qemu_set_irq(NVRAM->IRQ, 0);
 224     }
 225 }
 226
 227 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 228 {
 229     uint64_t interval; /* in 1/16 seconds */
 230
 231     NVRAM->buffer[0x1FF0] &= ~0x80;
 232     if (NVRAM->wd_timer != NULL) {
 233         timer_del(NVRAM->wd_timer);
 234         if (value != 0) {
 235             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 236             timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 237                            ((interval * 1000) >> 4));
 238         }
 239     }
 240 }
 241
 242 /* Direct access to NVRAM */
 243 static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
 244 {
 245     struct tm tm;
 246     int tmp;
 247
 248     if (addr > 0x1FF8 && addr < 0x2000)
 249         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 250
 251     /* check for NVRAM access */
 252     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 253         (NVRAM->model == 8 && addr < 0x1ff8) ||
 254         (NVRAM->model == 59 && addr < 0x1ff0)) {
 255         goto do_write;
 256     }
 257
 258     /* TOD access */
 259     switch (addr) {
 260     case 0x1FF0:
 261         /* flags register : read-only */
 262         break;
 263     case 0x1FF1:
 264         /* unused */
 265         break;
 266     case 0x1FF2:
 267         /* alarm seconds */
 268         tmp = from_bcd(val & 0x7F);
 269         if (tmp >= 0 && tmp <= 59) {
 270             NVRAM->alarm.tm_sec = tmp;
 271             NVRAM->buffer[0x1FF2] = val;
 272             set_alarm(NVRAM);
 273         }
 274         break;
 275     case 0x1FF3:
 276         /* alarm minutes */
 277         tmp = from_bcd(val & 0x7F);
 278         if (tmp >= 0 && tmp <= 59) {
 279             NVRAM->alarm.tm_min = tmp;
 280             NVRAM->buffer[0x1FF3] = val;
 281             set_alarm(NVRAM);
 282         }
 283         break;
 284     case 0x1FF4:
 285         /* alarm hours */
 286         tmp = from_bcd(val & 0x3F);
 287         if (tmp >= 0 && tmp <= 23) {
 288             NVRAM->alarm.tm_hour = tmp;
 289             NVRAM->buffer[0x1FF4] = val;
 290             set_alarm(NVRAM);
 291         }
 292         break;
 293     case 0x1FF5:
 294         /* alarm date */
 295         tmp = from_bcd(val & 0x3F);
 296         if (tmp != 0) {
 297             NVRAM->alarm.tm_mday = tmp;
 298             NVRAM->buffer[0x1FF5] = val;
 299             set_alarm(NVRAM);
 300         }
 301         break;
 302     case 0x1FF6:
 303         /* interrupts */
 304         NVRAM->buffer[0x1FF6] = val;
 305         break;
 306     case 0x1FF7:
 307         /* watchdog */
 308         NVRAM->buffer[0x1FF7] = val;
 309         set_up_watchdog(NVRAM, val);
 310         break;
 311     case 0x1FF8:
 312     case 0x07F8:
 313         /* control */
 314        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 315         break;
 316     case 0x1FF9:
 317     case 0x07F9:
 318         /* seconds (BCD) */
 319         tmp = from_bcd(val & 0x7F);
 320         if (tmp >= 0 && tmp <= 59) {
 321             get_time(NVRAM, &tm);
 322             tm.tm_sec = tmp;
 323             set_time(NVRAM, &tm);
 324         }
 325         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 326             if (val & 0x80) {
 327                 NVRAM->stop_time = time(NULL);
 328             } else {
 329                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 330                 NVRAM->stop_time = 0;
 331             }
 332         }
 333         NVRAM->buffer[addr] = val & 0x80;
 334         break;
 335     case 0x1FFA:
 336     case 0x07FA:
 337         /* minutes (BCD) */
 338         tmp = from_bcd(val & 0x7F);
 339         if (tmp >= 0 && tmp <= 59) {
 340             get_time(NVRAM, &tm);
 341             tm.tm_min = tmp;
 342             set_time(NVRAM, &tm);
 343         }
 344         break;
 345     case 0x1FFB:
 346     case 0x07FB:
 347         /* hours (BCD) */
 348         tmp = from_bcd(val & 0x3F);
 349         if (tmp >= 0 && tmp <= 23) {
 350             get_time(NVRAM, &tm);
 351             tm.tm_hour = tmp;
 352             set_time(NVRAM, &tm);
 353         }
 354         break;
 355     case 0x1FFC:
 356     case 0x07FC:
 357         /* day of the week / century */
 358         tmp = from_bcd(val & 0x07);
 359         get_time(NVRAM, &tm);
 360         tm.tm_wday = tmp;
 361         set_time(NVRAM, &tm);
 362         NVRAM->buffer[addr] = val & 0x40;
 363         break;
 364     case 0x1FFD:
 365     case 0x07FD:
 366         /* date (BCD) */
 367        tmp = from_bcd(val & 0x3F);
 368         if (tmp != 0) {
 369             get_time(NVRAM, &tm);
 370             tm.tm_mday = tmp;
 371             set_time(NVRAM, &tm);
 372         }
 373         break;
 374     case 0x1FFE:
 375     case 0x07FE:
 376         /* month */
 377         tmp = from_bcd(val & 0x1F);
 378         if (tmp >= 1 && tmp <= 12) {
 379             get_time(NVRAM, &tm);
 380             tm.tm_mon = tmp - 1;
 381             set_time(NVRAM, &tm);
 382         }
 383         break;
 384     case 0x1FFF:
 385     case 0x07FF:
 386         /* year */
 387         tmp = from_bcd(val);
 388         if (tmp >= 0 && tmp <= 99) {
 389             get_time(NVRAM, &tm);
 390             if (NVRAM->model == 8) {
 391                 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
 392             } else {
 393                 tm.tm_year = from_bcd(val);
 394             }
 395             set_time(NVRAM, &tm);
 396         }
 397         break;
 398     default:
 399         /* Check lock registers state */
 400         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 401             break;
 402         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 403             break;
 404     do_write:
 405         if (addr < NVRAM->size) {
 406             NVRAM->buffer[addr] = val & 0xFF;
 407         }
 408         break;
 409     }
 410 }
 411
 412 static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
 413 {
 414     struct tm tm;
 415     uint32_t retval = 0xFF;
 416
 417     /* check for NVRAM access */
 418     if ((NVRAM->model == 2 && addr < 0x078f) ||
 419         (NVRAM->model == 8 && addr < 0x1ff8) ||
 420         (NVRAM->model == 59 && addr < 0x1ff0)) {
 421         goto do_read;
 422     }
 423
 424     /* TOD access */
 425     switch (addr) {
 426     case 0x1FF0:
 427         /* flags register */
 428         goto do_read;
 429     case 0x1FF1:
 430         /* unused */
 431         retval = 0;
 432         break;
 433     case 0x1FF2:
 434         /* alarm seconds */
 435         goto do_read;
 436     case 0x1FF3:
 437         /* alarm minutes */
 438         goto do_read;
 439     case 0x1FF4:
 440         /* alarm hours */
 441         goto do_read;
 442     case 0x1FF5:
 443         /* alarm date */
 444         goto do_read;
 445     case 0x1FF6:
 446         /* interrupts */
 447         goto do_read;
 448     case 0x1FF7:
 449         /* A read resets the watchdog */
 450         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 451         goto do_read;
 452     case 0x1FF8:
 453     case 0x07F8:
 454         /* control */
 455         goto do_read;
 456     case 0x1FF9:
 457     case 0x07F9:
 458         /* seconds (BCD) */
 459         get_time(NVRAM, &tm);
 460         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 461         break;
 462     case 0x1FFA:
 463     case 0x07FA:
 464         /* minutes (BCD) */
 465         get_time(NVRAM, &tm);
 466         retval = to_bcd(tm.tm_min);
 467         break;
 468     case 0x1FFB:
 469     case 0x07FB:
 470         /* hours (BCD) */
 471         get_time(NVRAM, &tm);
 472         retval = to_bcd(tm.tm_hour);
 473         break;
 474     case 0x1FFC:
 475     case 0x07FC:
 476         /* day of the week / century */
 477         get_time(NVRAM, &tm);
 478         retval = NVRAM->buffer[addr] | tm.tm_wday;
 479         break;
 480     case 0x1FFD:
 481     case 0x07FD:
 482         /* date */
 483         get_time(NVRAM, &tm);
 484         retval = to_bcd(tm.tm_mday);
 485         break;
 486     case 0x1FFE:
 487     case 0x07FE:
 488         /* month */
 489         get_time(NVRAM, &tm);
 490         retval = to_bcd(tm.tm_mon + 1);
 491         break;
 492     case 0x1FFF:
 493     case 0x07FF:
 494         /* year */
 495         get_time(NVRAM, &tm);
 496         if (NVRAM->model == 8) {
 497             retval = to_bcd(tm.tm_year - 68); // Base year is 1968
 498         } else {
 499             retval = to_bcd(tm.tm_year);
 500         }
 501         break;
 502     default:
 503         /* Check lock registers state */
 504         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 505             break;
 506         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 507             break;
 508     do_read:
 509         if (addr < NVRAM->size) {
 510             retval = NVRAM->buffer[addr];
 511         }
 512         break;
 513     }
 514     if (addr > 0x1FF9 && addr < 0x2000)
 515        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 516
 517     return retval;
 518 }
 519
 520 static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
 521 {
 522     NVRAM->lock ^= 1 << lock;
 523 }
 524
 525 /* IO access to NVRAM */
 526 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
 527                          unsigned size)
 528 {
 529     M48t59State *NVRAM = opaque;
 530
 531     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 532     switch (addr) {
 533     case 0:
 534         NVRAM->addr &= ~0x00FF;
 535         NVRAM->addr |= val;
 536         break;
 537     case 1:
 538         NVRAM->addr &= ~0xFF00;
 539         NVRAM->addr |= val << 8;
 540         break;
 541     case 3:
 542         m48t59_write(NVRAM, NVRAM->addr, val);
 543         NVRAM->addr = 0x0000;
 544         break;
 545     default:
 546         break;
 547     }
 548 }
 549
 550 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
 551 {
 552     M48t59State *NVRAM = opaque;
 553     uint32_t retval;
 554
 555     switch (addr) {
 556     case 3:
 557         retval = m48t59_read(NVRAM, NVRAM->addr);
 558         break;
 559     default:
 560         retval = -1;
 561         break;
 562     }
 563     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 564
 565     return retval;
 566 }
 567
 568 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
 569 {
 570     M48t59State *NVRAM = opaque;
 571
 572     m48t59_write(NVRAM, addr, value & 0xff);
 573 }
 574
 575 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
 576 {
 577     M48t59State *NVRAM = opaque;
 578
 579     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 580     m48t59_write(NVRAM, addr + 1, value & 0xff);
 581 }
 582
 583 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
 584 {
 585     M48t59State *NVRAM = opaque;
 586
 587     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 588     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 589     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 590     m48t59_write(NVRAM, addr + 3, value & 0xff);
 591 }
 592
 593 static uint32_t nvram_readb (void *opaque, hwaddr addr)
 594 {
 595     M48t59State *NVRAM = opaque;
 596     uint32_t retval;
 597
 598     retval = m48t59_read(NVRAM, addr);
 599     return retval;
 600 }
 601
 602 static uint32_t nvram_readw (void *opaque, hwaddr addr)
 603 {
 604     M48t59State *NVRAM = opaque;
 605     uint32_t retval;
 606
 607     retval = m48t59_read(NVRAM, addr) << 8;
 608     retval |= m48t59_read(NVRAM, addr + 1);
 609     return retval;
 610 }
 611
 612 static uint32_t nvram_readl (void *opaque, hwaddr addr)
 613 {
 614     M48t59State *NVRAM = opaque;
 615     uint32_t retval;
 616
 617     retval = m48t59_read(NVRAM, addr) << 24;
 618     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 619     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 620     retval |= m48t59_read(NVRAM, addr + 3);
 621     return retval;
 622 }
 623
 624 static const MemoryRegionOps nvram_ops = {
 625     .old_mmio = {
 626         .read = { nvram_readb, nvram_readw, nvram_readl, },
 627         .write = { nvram_writeb, nvram_writew, nvram_writel, },
 628     },
 629     .endianness = DEVICE_NATIVE_ENDIAN,
 630 };
 631
 632 static const VMStateDescription vmstate_m48t59 = {
 633     .name = "m48t59",
 634     .version_id = 1,
 635     .minimum_version_id = 1,
 636     .fields = (VMStateField[]) {
 637         VMSTATE_UINT8(lock, M48t59State),
 638         VMSTATE_UINT16(addr, M48t59State),
 639         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
 640         VMSTATE_END_OF_LIST()
 641     }
 642 };
 643
 644 static void m48t59_reset_common(M48t59State *NVRAM)
 645 {
 646     NVRAM->addr = 0;
 647     NVRAM->lock = 0;
 648     if (NVRAM->alrm_timer != NULL)
 649         timer_del(NVRAM->alrm_timer);
 650
 651     if (NVRAM->wd_timer != NULL)
 652         timer_del(NVRAM->wd_timer);
 653 }
 654
 655 static void m48t59_reset_isa(DeviceState *d)
 656 {
 657     M48txxISAState *isa = M48TXX_ISA(d);
 658     M48t59State *NVRAM = &isa->state;
 659
 660     m48t59_reset_common(NVRAM);
 661 }
 662
 663 static void m48t59_reset_sysbus(DeviceState *d)
 664 {
 665     M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
 666     M48t59State *NVRAM = &sys->state;
 667
 668     m48t59_reset_common(NVRAM);
 669 }
 670
 671 static const MemoryRegionOps m48t59_io_ops = {
 672     .read = NVRAM_readb,
 673     .write = NVRAM_writeb,
 674     .impl = {
 675         .min_access_size = 1,
 676         .max_access_size = 1,
 677     },
 678     .endianness = DEVICE_LITTLE_ENDIAN,
 679 };
 680
 681 /* Initialisation routine */
 682 Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
 683                    uint32_t io_base, uint16_t size, int model)
 684 {
 685     DeviceState *dev;
 686     SysBusDevice *s;
 687     int i;
 688
 689     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 690         if (!m48txx_info[i].sysbus_name ||
 691             m48txx_info[i].size != size ||
 692             m48txx_info[i].model != model) {
 693             continue;
 694         }
 695
 696         dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
 697         qdev_init_nofail(dev);
 698         s = SYS_BUS_DEVICE(dev);
 699         sysbus_connect_irq(s, 0, IRQ);
 700         if (io_base != 0) {
 701             memory_region_add_subregion(get_system_io(), io_base,
 702                                         sysbus_mmio_get_region(s, 1));
 703         }
 704         if (mem_base != 0) {
 705             sysbus_mmio_map(s, 0, mem_base);
 706         }
 707
 708         return NVRAM(s);
 709     }
 710
 711     assert(false);
 712     return NULL;
 713 }
 714
 715 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
 716                        int model)
 717 {
 718     DeviceState *dev;
 719     int i;
 720
 721     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 722         if (!m48txx_info[i].isa_name ||
 723             m48txx_info[i].size != size ||
 724             m48txx_info[i].model != model) {
 725             continue;
 726         }
 727
 728         dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
 729         qdev_prop_set_uint32(dev, "iobase", io_base);
 730         qdev_init_nofail(dev);
 731         return NVRAM(dev);
 732     }
 733
 734     assert(false);
 735     return NULL;
 736 }
 737
 738 static void m48t59_realize_common(M48t59State *s, Error **errp)
 739 {
 740     s->buffer = g_malloc0(s->size);
 741     if (s->model == 59) {
 742         s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
 743         s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
 744     }
 745     qemu_get_timedate(&s->alarm, 0);
 746
 747     vmstate_register(NULL, -1, &vmstate_m48t59, s);
 748 }
 749
 750 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
 751 {
 752     M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
 753     ISADevice *isadev = ISA_DEVICE(dev);
 754     M48txxISAState *d = M48TXX_ISA(dev);
 755     M48t59State *s = &d->state;
 756
 757     s->model = u->info.model;
 758     s->size = u->info.size;
 759     isa_init_irq(isadev, &s->IRQ, 8);
 760     m48t59_realize_common(s, errp);
 761     memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
 762     if (d->io_base != 0) {
 763         isa_register_ioport(isadev, &d->io, d->io_base);
 764     }
 765 }
 766
 767 static int m48t59_init1(SysBusDevice *dev)
 768 {
 769     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
 770     M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
 771     Object *o = OBJECT(dev);
 772     M48t59State *s = &d->state;
 773     Error *err = NULL;
 774
 775     s->model = u->info.model;
 776     s->size = u->info.size;
 777     sysbus_init_irq(dev, &s->IRQ);
 778
 779     memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
 780                           s->size);
 781     memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
 782     sysbus_init_mmio(dev, &s->iomem);
 783     sysbus_init_mmio(dev, &d->io);
 784     m48t59_realize_common(s, &err);
 785     if (err != NULL) {
 786         error_free(err);
 787         return -1;
 788     }
 789
 790     return 0;
 791 }
 792
 793 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
 794 {
 795     M48txxISAState *d = M48TXX_ISA(obj);
 796     return m48t59_read(&d->state, addr);
 797 }
 798
 799 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
 800 {
 801     M48txxISAState *d = M48TXX_ISA(obj);
 802     m48t59_write(&d->state, addr, val);
 803 }
 804
 805 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
 806 {
 807     M48txxISAState *d = M48TXX_ISA(obj);
 808     m48t59_toggle_lock(&d->state, lock);
 809 }
 810
 811 static Property m48t59_isa_properties[] = {
 812     DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
 813     DEFINE_PROP_END_OF_LIST(),
 814 };
 815
 816 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
 817 {
 818     DeviceClass *dc = DEVICE_CLASS(klass);
 819     NvramClass *nc = NVRAM_CLASS(klass);
 820
 821     dc->realize = m48t59_isa_realize;
 822     dc->reset = m48t59_reset_isa;
 823     dc->props = m48t59_isa_properties;
 824     nc->read = m48txx_isa_read;
 825     nc->write = m48txx_isa_write;
 826     nc->toggle_lock = m48txx_isa_toggle_lock;
 827 }
 828
 829 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
 830 {
 831     M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
 832     M48txxInfo *info = data;
 833
 834     u->info = *info;
 835 }
 836
 837 static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
 838 {
 839     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 840     return m48t59_read(&d->state, addr);
 841 }
 842
 843 static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
 844 {
 845     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 846     m48t59_write(&d->state, addr, val);
 847 }
 848
 849 static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
 850 {
 851     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 852     m48t59_toggle_lock(&d->state, lock);
 853 }
 854
 855 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
 856 {
 857     DeviceClass *dc = DEVICE_CLASS(klass);
 858     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 859     NvramClass *nc = NVRAM_CLASS(klass);
 860
 861     k->init = m48t59_init1;
 862     dc->reset = m48t59_reset_sysbus;
 863     nc->read = m48txx_sysbus_read;
 864     nc->write = m48txx_sysbus_write;
 865     nc->toggle_lock = m48txx_sysbus_toggle_lock;
 866 }
 867
 868 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
 869 {
 870     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
 871     M48txxInfo *info = data;
 872
 873     u->info = *info;
 874 }
 875
 876 static const TypeInfo nvram_info = {
 877     .name = TYPE_NVRAM,
 878     .parent = TYPE_INTERFACE,
 879     .class_size = sizeof(NvramClass),
 880 };
 881
 882 static const TypeInfo m48txx_sysbus_type_info = {
 883     .name = TYPE_M48TXX_SYS_BUS,
 884     .parent = TYPE_SYS_BUS_DEVICE,
 885     .instance_size = sizeof(M48txxSysBusState),
 886     .abstract = true,
 887     .class_init = m48txx_sysbus_class_init,
 888     .interfaces = (InterfaceInfo[]) {
 889         { TYPE_NVRAM },
 890         { }
 891     }
 892 };
 893
 894 static const TypeInfo m48txx_isa_type_info = {
 895     .name = TYPE_M48TXX_ISA,
 896     .parent = TYPE_ISA_DEVICE,
 897     .instance_size = sizeof(M48txxISAState),
 898     .abstract = true,
 899     .class_init = m48txx_isa_class_init,
 900     .interfaces = (InterfaceInfo[]) {
 901         { TYPE_NVRAM },
 902         { }
 903     }
 904 };
 905
 906 static void m48t59_register_types(void)
 907 {
 908     TypeInfo sysbus_type_info = {
 909         .parent = TYPE_M48TXX_SYS_BUS,
 910         .class_size = sizeof(M48txxSysBusDeviceClass),
 911         .class_init = m48txx_sysbus_concrete_class_init,
 912     };
 913     TypeInfo isa_type_info = {
 914         .parent = TYPE_M48TXX_ISA,
 915         .class_size = sizeof(M48txxISADeviceClass),
 916         .class_init = m48txx_isa_concrete_class_init,
 917     };
 918     int i;
 919
 920     type_register_static(&nvram_info);
 921     type_register_static(&m48txx_sysbus_type_info);
 922     type_register_static(&m48txx_isa_type_info);
 923
 924     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 925         if (m48txx_info[i].sysbus_name) {
 926             sysbus_type_info.name = m48txx_info[i].sysbus_name;
 927             sysbus_type_info.class_data = &m48txx_info[i];
 928             type_register(&sysbus_type_info);
 929         }
 930
 931         if (m48txx_info[i].isa_name) {
 932             isa_type_info.name = m48txx_info[i].isa_name;
 933             isa_type_info.class_data = &m48txx_info[i];
 934             type_register(&isa_type_info);
 935         }
 936     }
 937 }
 938
 939 type_init(m48t59_register_types)