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e1000: unfold mac_reg_tosave array
[qemu/cris-port.git] / hw / e1000.c
blobda37f82951001b9fb4dab3715003141abb606e48
1 /*
2 * QEMU e1000 emulation
3 *
4 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
5 * Copyright (c) 2008 Qumranet
6 * Based on work done by:
7 * Copyright (c) 2007 Dan Aloni
8 * Copyright (c) 2004 Antony T Curtis
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24
25 #include "hw.h"
26 #include "pci.h"
27 #include "net.h"
28 #include "loader.h"
29
30 #include "e1000_hw.h"
31
32 #define DEBUG
33
34 #ifdef DEBUG
35 enum {
36 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
37 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
38 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
39 DEBUG_RXFILTER, DEBUG_NOTYET,
40 };
41 #define DBGBIT(x) (1<<DEBUG_##x)
42 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
43
44 #define DBGOUT(what, fmt, ...) do { \
45 if (debugflags & DBGBIT(what)) \
46 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
47 } while (0)
48 #else
49 #define DBGOUT(what, fmt, ...) do {} while (0)
50 #endif
51
52 #define IOPORT_SIZE 0x40
53 #define PNPMMIO_SIZE 0x20000
54
55 /*
56 * HW models:
57 * E1000_DEV_ID_82540EM works with Windows and Linux
58 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
59 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
60 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
61 * Others never tested
62 */
63 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
64
65 /*
66 * May need to specify additional MAC-to-PHY entries --
67 * Intel's Windows driver refuses to initialize unless they match
68 */
69 enum {
70 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
71 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
72 /* default to E1000_DEV_ID_82540EM */ 0xc20
73 };
74
75 typedef struct E1000State_st {
76 PCIDevice dev;
77 VLANClientState *vc;
78 NICConf conf;
79 int mmio_index;
80
81 uint32_t mac_reg[0x8000];
82 uint16_t phy_reg[0x20];
83 uint16_t eeprom_data[64];
84
85 uint32_t rxbuf_size;
86 uint32_t rxbuf_min_shift;
87 int check_rxov;
88 struct e1000_tx {
89 unsigned char header[256];
90 unsigned char vlan_header[4];
91 unsigned char vlan[4];
92 unsigned char data[0x10000];
93 uint16_t size;
94 unsigned char sum_needed;
95 unsigned char vlan_needed;
96 uint8_t ipcss;
97 uint8_t ipcso;
98 uint16_t ipcse;
99 uint8_t tucss;
100 uint8_t tucso;
101 uint16_t tucse;
102 uint8_t hdr_len;
103 uint16_t mss;
104 uint32_t paylen;
105 uint16_t tso_frames;
106 char tse;
107 int8_t ip;
108 int8_t tcp;
109 char cptse; // current packet tse bit
110 } tx;
111
112 struct {
113 uint32_t val_in; // shifted in from guest driver
114 uint16_t bitnum_in;
115 uint16_t bitnum_out;
116 uint16_t reading;
117 uint32_t old_eecd;
118 } eecd_state;
119 } E1000State;
120
121 #define defreg(x) x = (E1000_##x>>2)
122 enum {
123 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
124 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
125 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
126 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
127 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
128 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
129 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
130 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
131 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
132 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
133 defreg(VET),
134 };
135
136 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
137 static const char phy_regcap[0x20] = {
138 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
139 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
140 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
141 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
142 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
143 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
144 };
145
146 static void
147 ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
148 uint32_t size, int type)
149 {
150 DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
151 }
152
153 static void
154 set_interrupt_cause(E1000State *s, int index, uint32_t val)
155 {
156 if (val)
157 val |= E1000_ICR_INT_ASSERTED;
158 s->mac_reg[ICR] = val;
159 s->mac_reg[ICS] = val;
160 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
161 }
162
163 static void
164 set_ics(E1000State *s, int index, uint32_t val)
165 {
166 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
167 s->mac_reg[IMS]);
168 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
169 }
170
171 static int
172 rxbufsize(uint32_t v)
173 {
174 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
175 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
176 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
177 switch (v) {
178 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
179 return 16384;
180 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
181 return 8192;
182 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
183 return 4096;
184 case E1000_RCTL_SZ_1024:
185 return 1024;
186 case E1000_RCTL_SZ_512:
187 return 512;
188 case E1000_RCTL_SZ_256:
189 return 256;
190 }
191 return 2048;
192 }
193
194 static void
195 set_ctrl(E1000State *s, int index, uint32_t val)
196 {
197 /* RST is self clearing */
198 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
199 }
200
201 static void
202 set_rx_control(E1000State *s, int index, uint32_t val)
203 {
204 s->mac_reg[RCTL] = val;
205 s->rxbuf_size = rxbufsize(val);
206 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
207 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
208 s->mac_reg[RCTL]);
209 }
210
211 static void
212 set_mdic(E1000State *s, int index, uint32_t val)
213 {
214 uint32_t data = val & E1000_MDIC_DATA_MASK;
215 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
216
217 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
218 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
219 else if (val & E1000_MDIC_OP_READ) {
220 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
221 if (!(phy_regcap[addr] & PHY_R)) {
222 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
223 val |= E1000_MDIC_ERROR;
224 } else
225 val = (val ^ data) | s->phy_reg[addr];
226 } else if (val & E1000_MDIC_OP_WRITE) {
227 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
228 if (!(phy_regcap[addr] & PHY_W)) {
229 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
230 val |= E1000_MDIC_ERROR;
231 } else
232 s->phy_reg[addr] = data;
233 }
234 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
235 set_ics(s, 0, E1000_ICR_MDAC);
236 }
237
238 static uint32_t
239 get_eecd(E1000State *s, int index)
240 {
241 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
242
243 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
244 s->eecd_state.bitnum_out, s->eecd_state.reading);
245 if (!s->eecd_state.reading ||
246 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
247 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
248 ret |= E1000_EECD_DO;
249 return ret;
250 }
251
252 static void
253 set_eecd(E1000State *s, int index, uint32_t val)
254 {
255 uint32_t oldval = s->eecd_state.old_eecd;
256
257 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
258 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
259 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
260 return;
261 if (!(E1000_EECD_SK & val)) { // falling edge
262 s->eecd_state.bitnum_out++;
263 return;
264 }
265 if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset)
266 memset(&s->eecd_state, 0, sizeof s->eecd_state);
267 /*
268 * restore old_eecd's E1000_EECD_SK (known to be on)
269 * to avoid false detection of a clock edge
270 */
271 s->eecd_state.old_eecd = E1000_EECD_SK;
272 return;
273 }
274 s->eecd_state.val_in <<= 1;
275 if (val & E1000_EECD_DI)
276 s->eecd_state.val_in |= 1;
277 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
278 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
279 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
280 EEPROM_READ_OPCODE_MICROWIRE);
281 }
282 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
283 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
284 s->eecd_state.reading);
285 }
286
287 static uint32_t
288 flash_eerd_read(E1000State *s, int x)
289 {
290 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
291
292 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
293 return (s->mac_reg[EERD]);
294
295 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
296 return (E1000_EEPROM_RW_REG_DONE | r);
297
298 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
299 E1000_EEPROM_RW_REG_DONE | r);
300 }
301
302 static void
303 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
304 {
305 uint32_t sum;
306
307 if (cse && cse < n)
308 n = cse + 1;
309 if (sloc < n-1) {
310 sum = net_checksum_add(n-css, data+css);
311 cpu_to_be16wu((uint16_t *)(data + sloc),
312 net_checksum_finish(sum));
313 }
314 }
315
316 static inline int
317 vlan_enabled(E1000State *s)
318 {
319 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
320 }
321
322 static inline int
323 vlan_rx_filter_enabled(E1000State *s)
324 {
325 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
326 }
327
328 static inline int
329 is_vlan_packet(E1000State *s, const uint8_t *buf)
330 {
331 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
332 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
333 }
334
335 static inline int
336 is_vlan_txd(uint32_t txd_lower)
337 {
338 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
339 }
340
341 static void
342 xmit_seg(E1000State *s)
343 {
344 uint16_t len, *sp;
345 unsigned int frames = s->tx.tso_frames, css, sofar, n;
346 struct e1000_tx *tp = &s->tx;
347
348 if (tp->tse && tp->cptse) {
349 css = tp->ipcss;
350 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
351 frames, tp->size, css);
352 if (tp->ip) { // IPv4
353 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
354 tp->size - css);
355 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
356 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
357 } else // IPv6
358 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
359 tp->size - css);
360 css = tp->tucss;
361 len = tp->size - css;
362 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
363 if (tp->tcp) {
364 sofar = frames * tp->mss;
365 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
366 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
367 if (tp->paylen - sofar > tp->mss)
368 tp->data[css + 13] &= ~9; // PSH, FIN
369 } else // UDP
370 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
371 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
372 // add pseudo-header length before checksum calculation
373 sp = (uint16_t *)(tp->data + tp->tucso);
374 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
375 }
376 tp->tso_frames++;
377 }
378
379 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
380 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
381 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
382 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
383 if (tp->vlan_needed) {
384 memmove(tp->vlan, tp->data, 12);
385 memcpy(tp->data + 8, tp->vlan_header, 4);
386 qemu_send_packet(s->vc, tp->vlan, tp->size + 4);
387 } else
388 qemu_send_packet(s->vc, tp->data, tp->size);
389 s->mac_reg[TPT]++;
390 s->mac_reg[GPTC]++;
391 n = s->mac_reg[TOTL];
392 if ((s->mac_reg[TOTL] += s->tx.size) < n)
393 s->mac_reg[TOTH]++;
394 }
395
396 static void
397 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
398 {
399 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
400 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
401 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
402 unsigned int msh = 0xfffff, hdr = 0;
403 uint64_t addr;
404 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
405 struct e1000_tx *tp = &s->tx;
406
407 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
408 op = le32_to_cpu(xp->cmd_and_length);
409 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
410 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
411 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
412 tp->tucss = xp->upper_setup.tcp_fields.tucss;
413 tp->tucso = xp->upper_setup.tcp_fields.tucso;
414 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
415 tp->paylen = op & 0xfffff;
416 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
417 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
418 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
419 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
420 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
421 tp->tso_frames = 0;
422 if (tp->tucso == 0) { // this is probably wrong
423 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
424 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
425 }
426 return;
427 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
428 // data descriptor
429 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
430 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
431 } else
432 // legacy descriptor
433 tp->cptse = 0;
434
435 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
436 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
437 tp->vlan_needed = 1;
438 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
439 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
440 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
441 le16_to_cpu(dp->upper.fields.special));
442 }
443
444 addr = le64_to_cpu(dp->buffer_addr);
445 if (tp->tse && tp->cptse) {
446 hdr = tp->hdr_len;
447 msh = hdr + tp->mss;
448 do {
449 bytes = split_size;
450 if (tp->size + bytes > msh)
451 bytes = msh - tp->size;
452 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
453 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
454 memmove(tp->header, tp->data, hdr);
455 tp->size = sz;
456 addr += bytes;
457 if (sz == msh) {
458 xmit_seg(s);
459 memmove(tp->data, tp->header, hdr);
460 tp->size = hdr;
461 }
462 } while (split_size -= bytes);
463 } else if (!tp->tse && tp->cptse) {
464 // context descriptor TSE is not set, while data descriptor TSE is set
465 DBGOUT(TXERR, "TCP segmentaion Error\n");
466 } else {
467 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
468 tp->size += split_size;
469 }
470
471 if (!(txd_lower & E1000_TXD_CMD_EOP))
472 return;
473 if (!(tp->tse && tp->cptse && tp->size < hdr))
474 xmit_seg(s);
475 tp->tso_frames = 0;
476 tp->sum_needed = 0;
477 tp->vlan_needed = 0;
478 tp->size = 0;
479 tp->cptse = 0;
480 }
481
482 static uint32_t
483 txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
484 {
485 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
486
487 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
488 return 0;
489 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
490 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
491 dp->upper.data = cpu_to_le32(txd_upper);
492 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
493 (void *)&dp->upper, sizeof(dp->upper));
494 return E1000_ICR_TXDW;
495 }
496
497 static void
498 start_xmit(E1000State *s)
499 {
500 target_phys_addr_t base;
501 struct e1000_tx_desc desc;
502 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
503
504 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
505 DBGOUT(TX, "tx disabled\n");
506 return;
507 }
508
509 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
510 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
511 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
512 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
513
514 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
515 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
516 desc.upper.data);
517
518 process_tx_desc(s, &desc);
519 cause |= txdesc_writeback(base, &desc);
520
521 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
522 s->mac_reg[TDH] = 0;
523 /*
524 * the following could happen only if guest sw assigns
525 * bogus values to TDT/TDLEN.
526 * there's nothing too intelligent we could do about this.
527 */
528 if (s->mac_reg[TDH] == tdh_start) {
529 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
530 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
531 break;
532 }
533 }
534 set_ics(s, 0, cause);
535 }
536
537 static int
538 receive_filter(E1000State *s, const uint8_t *buf, int size)
539 {
540 static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
541 static int mta_shift[] = {4, 3, 2, 0};
542 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
543
544 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
545 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
546 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
547 ((vid >> 5) & 0x7f));
548 if ((vfta & (1 << (vid & 0x1f))) == 0)
549 return 0;
550 }
551
552 if (rctl & E1000_RCTL_UPE) // promiscuous
553 return 1;
554
555 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
556 return 1;
557
558 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
559 return 1;
560
561 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
562 if (!(rp[1] & E1000_RAH_AV))
563 continue;
564 ra[0] = cpu_to_le32(rp[0]);
565 ra[1] = cpu_to_le32(rp[1]);
566 if (!memcmp(buf, (uint8_t *)ra, 6)) {
567 DBGOUT(RXFILTER,
568 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
569 (int)(rp - s->mac_reg - RA)/2,
570 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
571 return 1;
572 }
573 }
574 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
575 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
576
577 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
578 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
579 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
580 return 1;
581 DBGOUT(RXFILTER,
582 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
583 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
584 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
585 s->mac_reg[MTA + (f >> 5)]);
586
587 return 0;
588 }
589
590 static void
591 e1000_set_link_status(VLANClientState *vc)
592 {
593 E1000State *s = vc->opaque;
594 uint32_t old_status = s->mac_reg[STATUS];
595
596 if (vc->link_down)
597 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
598 else
599 s->mac_reg[STATUS] |= E1000_STATUS_LU;
600
601 if (s->mac_reg[STATUS] != old_status)
602 set_ics(s, 0, E1000_ICR_LSC);
603 }
604
605 static int
606 e1000_can_receive(VLANClientState *vc)
607 {
608 E1000State *s = vc->opaque;
609
610 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
611 }
612
613 static ssize_t
614 e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
615 {
616 E1000State *s = vc->opaque;
617 struct e1000_rx_desc desc;
618 target_phys_addr_t base;
619 unsigned int n, rdt;
620 uint32_t rdh_start;
621 uint16_t vlan_special = 0;
622 uint8_t vlan_status = 0, vlan_offset = 0;
623
624 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
625 return -1;
626
627 if (size > s->rxbuf_size) {
628 DBGOUT(RX, "packet too large for buffers (%lu > %d)\n",
629 (unsigned long)size, s->rxbuf_size);
630 return -1;
631 }
632
633 if (!receive_filter(s, buf, size))
634 return size;
635
636 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
637 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
638 memmove((void *)(buf + 4), buf, 12);
639 vlan_status = E1000_RXD_STAT_VP;
640 vlan_offset = 4;
641 size -= 4;
642 }
643
644 rdh_start = s->mac_reg[RDH];
645 size += 4; // for the header
646 do {
647 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
648 set_ics(s, 0, E1000_ICS_RXO);
649 return -1;
650 }
651 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
652 sizeof(desc) * s->mac_reg[RDH];
653 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
654 desc.special = vlan_special;
655 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
656 if (desc.buffer_addr) {
657 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
658 (void *)(buf + vlan_offset), size);
659 desc.length = cpu_to_le16(size);
660 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
661 } else // as per intel docs; skip descriptors with null buf addr
662 DBGOUT(RX, "Null RX descriptor!!\n");
663 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
664
665 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
666 s->mac_reg[RDH] = 0;
667 s->check_rxov = 1;
668 /* see comment in start_xmit; same here */
669 if (s->mac_reg[RDH] == rdh_start) {
670 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
671 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
672 set_ics(s, 0, E1000_ICS_RXO);
673 return -1;
674 }
675 } while (desc.buffer_addr == 0);
676
677 s->mac_reg[GPRC]++;
678 s->mac_reg[TPR]++;
679 n = s->mac_reg[TORL];
680 if ((s->mac_reg[TORL] += size) < n)
681 s->mac_reg[TORH]++;
682
683 n = E1000_ICS_RXT0;
684 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
685 rdt += s->mac_reg[RDLEN] / sizeof(desc);
686 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
687 s->rxbuf_min_shift)
688 n |= E1000_ICS_RXDMT0;
689
690 set_ics(s, 0, n);
691
692 return size;
693 }
694
695 static uint32_t
696 mac_readreg(E1000State *s, int index)
697 {
698 return s->mac_reg[index];
699 }
700
701 static uint32_t
702 mac_icr_read(E1000State *s, int index)
703 {
704 uint32_t ret = s->mac_reg[ICR];
705
706 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
707 set_interrupt_cause(s, 0, 0);
708 return ret;
709 }
710
711 static uint32_t
712 mac_read_clr4(E1000State *s, int index)
713 {
714 uint32_t ret = s->mac_reg[index];
715
716 s->mac_reg[index] = 0;
717 return ret;
718 }
719
720 static uint32_t
721 mac_read_clr8(E1000State *s, int index)
722 {
723 uint32_t ret = s->mac_reg[index];
724
725 s->mac_reg[index] = 0;
726 s->mac_reg[index-1] = 0;
727 return ret;
728 }
729
730 static void
731 mac_writereg(E1000State *s, int index, uint32_t val)
732 {
733 s->mac_reg[index] = val;
734 }
735
736 static void
737 set_rdt(E1000State *s, int index, uint32_t val)
738 {
739 s->check_rxov = 0;
740 s->mac_reg[index] = val & 0xffff;
741 }
742
743 static void
744 set_16bit(E1000State *s, int index, uint32_t val)
745 {
746 s->mac_reg[index] = val & 0xffff;
747 }
748
749 static void
750 set_dlen(E1000State *s, int index, uint32_t val)
751 {
752 s->mac_reg[index] = val & 0xfff80;
753 }
754
755 static void
756 set_tctl(E1000State *s, int index, uint32_t val)
757 {
758 s->mac_reg[index] = val;
759 s->mac_reg[TDT] &= 0xffff;
760 start_xmit(s);
761 }
762
763 static void
764 set_icr(E1000State *s, int index, uint32_t val)
765 {
766 DBGOUT(INTERRUPT, "set_icr %x\n", val);
767 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
768 }
769
770 static void
771 set_imc(E1000State *s, int index, uint32_t val)
772 {
773 s->mac_reg[IMS] &= ~val;
774 set_ics(s, 0, 0);
775 }
776
777 static void
778 set_ims(E1000State *s, int index, uint32_t val)
779 {
780 s->mac_reg[IMS] |= val;
781 set_ics(s, 0, 0);
782 }
783
784 #define getreg(x) [x] = mac_readreg
785 static uint32_t (*macreg_readops[])(E1000State *, int) = {
786 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
787 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
788 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
789 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
790 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
791
792 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
793 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
794 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
795 [CRCERRS ... MPC] = &mac_readreg,
796 [RA ... RA+31] = &mac_readreg,
797 [MTA ... MTA+127] = &mac_readreg,
798 [VFTA ... VFTA+127] = &mac_readreg,
799 };
800 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
801
802 #define putreg(x) [x] = mac_writereg
803 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
804 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
805 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
806 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
807 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
808 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
809 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
810 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
811 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
812 [RA ... RA+31] = &mac_writereg,
813 [MTA ... MTA+127] = &mac_writereg,
814 [VFTA ... VFTA+127] = &mac_writereg,
815 };
816 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
817
818 static void
819 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
820 {
821 E1000State *s = opaque;
822 unsigned int index = (addr & 0x1ffff) >> 2;
823
824 #ifdef TARGET_WORDS_BIGENDIAN
825 val = bswap32(val);
826 #endif
827 if (index < NWRITEOPS && macreg_writeops[index])
828 macreg_writeops[index](s, index, val);
829 else if (index < NREADOPS && macreg_readops[index])
830 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
831 else
832 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
833 index<<2, val);
834 }
835
836 static void
837 e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
838 {
839 // emulate hw without byte enables: no RMW
840 e1000_mmio_writel(opaque, addr & ~3,
841 (val & 0xffff) << (8*(addr & 3)));
842 }
843
844 static void
845 e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
846 {
847 // emulate hw without byte enables: no RMW
848 e1000_mmio_writel(opaque, addr & ~3,
849 (val & 0xff) << (8*(addr & 3)));
850 }
851
852 static uint32_t
853 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
854 {
855 E1000State *s = opaque;
856 unsigned int index = (addr & 0x1ffff) >> 2;
857
858 if (index < NREADOPS && macreg_readops[index])
859 {
860 uint32_t val = macreg_readops[index](s, index);
861 #ifdef TARGET_WORDS_BIGENDIAN
862 val = bswap32(val);
863 #endif
864 return val;
865 }
866 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
867 return 0;
868 }
869
870 static uint32_t
871 e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
872 {
873 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
874 (8 * (addr & 3))) & 0xff;
875 }
876
877 static uint32_t
878 e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
879 {
880 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
881 (8 * (addr & 3))) & 0xffff;
882 }
883
884 static const struct {
885 int size;
886 int array0;
887 } mac_regarraystosave[] = { {32, RA}, {128, MTA}, {128, VFTA} };
888 enum { MAC_NARRAYS = ARRAY_SIZE(mac_regarraystosave) };
889
890 static void
891 nic_save(QEMUFile *f, void *opaque)
892 {
893 E1000State *s = opaque;
894 int i, j;
895
896 pci_device_save(&s->dev, f);
897 qemu_put_be32(f, 0);
898 qemu_put_be32s(f, &s->rxbuf_size);
899 qemu_put_be32s(f, &s->rxbuf_min_shift);
900 qemu_put_be32s(f, &s->eecd_state.val_in);
901 qemu_put_be16s(f, &s->eecd_state.bitnum_in);
902 qemu_put_be16s(f, &s->eecd_state.bitnum_out);
903 qemu_put_be16s(f, &s->eecd_state.reading);
904 qemu_put_be32s(f, &s->eecd_state.old_eecd);
905 qemu_put_8s(f, &s->tx.ipcss);
906 qemu_put_8s(f, &s->tx.ipcso);
907 qemu_put_be16s(f, &s->tx.ipcse);
908 qemu_put_8s(f, &s->tx.tucss);
909 qemu_put_8s(f, &s->tx.tucso);
910 qemu_put_be16s(f, &s->tx.tucse);
911 qemu_put_be32s(f, &s->tx.paylen);
912 qemu_put_8s(f, &s->tx.hdr_len);
913 qemu_put_be16s(f, &s->tx.mss);
914 qemu_put_be16s(f, &s->tx.size);
915 qemu_put_be16s(f, &s->tx.tso_frames);
916 qemu_put_8s(f, &s->tx.sum_needed);
917 qemu_put_s8s(f, &s->tx.ip);
918 qemu_put_s8s(f, &s->tx.tcp);
919 qemu_put_buffer(f, s->tx.header, sizeof s->tx.header);
920 qemu_put_buffer(f, s->tx.data, sizeof s->tx.data);
921 for (i = 0; i < 64; i++)
922 qemu_put_be16s(f, s->eeprom_data + i);
923 for (i = 0; i < 0x20; i++)
924 qemu_put_be16s(f, s->phy_reg + i);
925 qemu_put_be32s(f, &s->mac_reg[CTRL]);
926 qemu_put_be32s(f, &s->mac_reg[EECD]);
927 qemu_put_be32s(f, &s->mac_reg[EERD]);
928 qemu_put_be32s(f, &s->mac_reg[GPRC]);
929 qemu_put_be32s(f, &s->mac_reg[GPTC]);
930 qemu_put_be32s(f, &s->mac_reg[ICR]);
931 qemu_put_be32s(f, &s->mac_reg[ICS]);
932 qemu_put_be32s(f, &s->mac_reg[IMC]);
933 qemu_put_be32s(f, &s->mac_reg[IMS]);
934 qemu_put_be32s(f, &s->mac_reg[LEDCTL]);
935 qemu_put_be32s(f, &s->mac_reg[MANC]);
936 qemu_put_be32s(f, &s->mac_reg[MDIC]);
937 qemu_put_be32s(f, &s->mac_reg[MPC]);
938 qemu_put_be32s(f, &s->mac_reg[PBA]);
939 qemu_put_be32s(f, &s->mac_reg[RCTL]);
940 qemu_put_be32s(f, &s->mac_reg[RDBAH]);
941 qemu_put_be32s(f, &s->mac_reg[RDBAL]);
942 qemu_put_be32s(f, &s->mac_reg[RDH]);
943 qemu_put_be32s(f, &s->mac_reg[RDLEN]);
944 qemu_put_be32s(f, &s->mac_reg[RDT]);
945 qemu_put_be32s(f, &s->mac_reg[STATUS]);
946 qemu_put_be32s(f, &s->mac_reg[SWSM]);
947 qemu_put_be32s(f, &s->mac_reg[TCTL]);
948 qemu_put_be32s(f, &s->mac_reg[TDBAH]);
949 qemu_put_be32s(f, &s->mac_reg[TDBAL]);
950 qemu_put_be32s(f, &s->mac_reg[TDH]);
951 qemu_put_be32s(f, &s->mac_reg[TDLEN]);
952 qemu_put_be32s(f, &s->mac_reg[TDT]);
953 qemu_put_be32s(f, &s->mac_reg[TORH]);
954 qemu_put_be32s(f, &s->mac_reg[TORL]);
955 qemu_put_be32s(f, &s->mac_reg[TOTH]);
956 qemu_put_be32s(f, &s->mac_reg[TOTL]);
957 qemu_put_be32s(f, &s->mac_reg[TPR]);
958 qemu_put_be32s(f, &s->mac_reg[TPT]);
959 qemu_put_be32s(f, &s->mac_reg[TXDCTL]);
960 qemu_put_be32s(f, &s->mac_reg[WUFC]);
961 qemu_put_be32s(f, &s->mac_reg[VET]);
962 for (i = 0; i < MAC_NARRAYS; i++)
963 for (j = 0; j < mac_regarraystosave[i].size; j++)
964 qemu_put_be32s(f,
965 s->mac_reg + mac_regarraystosave[i].array0 + j);
966 }
967
968 static int
969 nic_load(QEMUFile *f, void *opaque, int version_id)
970 {
971 E1000State *s = opaque;
972 int i, j, ret;
973
974 if ((ret = pci_device_load(&s->dev, f)) < 0)
975 return ret;
976 if (version_id == 1)
977 qemu_get_sbe32s(f, &i); /* once some unused instance id */
978 qemu_get_be32(f); /* Ignored. Was mmio_base. */
979 qemu_get_be32s(f, &s->rxbuf_size);
980 qemu_get_be32s(f, &s->rxbuf_min_shift);
981 qemu_get_be32s(f, &s->eecd_state.val_in);
982 qemu_get_be16s(f, &s->eecd_state.bitnum_in);
983 qemu_get_be16s(f, &s->eecd_state.bitnum_out);
984 qemu_get_be16s(f, &s->eecd_state.reading);
985 qemu_get_be32s(f, &s->eecd_state.old_eecd);
986 qemu_get_8s(f, &s->tx.ipcss);
987 qemu_get_8s(f, &s->tx.ipcso);
988 qemu_get_be16s(f, &s->tx.ipcse);
989 qemu_get_8s(f, &s->tx.tucss);
990 qemu_get_8s(f, &s->tx.tucso);
991 qemu_get_be16s(f, &s->tx.tucse);
992 qemu_get_be32s(f, &s->tx.paylen);
993 qemu_get_8s(f, &s->tx.hdr_len);
994 qemu_get_be16s(f, &s->tx.mss);
995 qemu_get_be16s(f, &s->tx.size);
996 qemu_get_be16s(f, &s->tx.tso_frames);
997 qemu_get_8s(f, &s->tx.sum_needed);
998 qemu_get_s8s(f, &s->tx.ip);
999 qemu_get_s8s(f, &s->tx.tcp);
1000 qemu_get_buffer(f, s->tx.header, sizeof s->tx.header);
1001 qemu_get_buffer(f, s->tx.data, sizeof s->tx.data);
1002 for (i = 0; i < 64; i++)
1003 qemu_get_be16s(f, s->eeprom_data + i);
1004 for (i = 0; i < 0x20; i++)
1005 qemu_get_be16s(f, s->phy_reg + i);
1006 qemu_get_be32s(f, &s->mac_reg[CTRL]);
1007 qemu_get_be32s(f, &s->mac_reg[EECD]);
1008 qemu_get_be32s(f, &s->mac_reg[EERD]);
1009 qemu_get_be32s(f, &s->mac_reg[GPRC]);
1010 qemu_get_be32s(f, &s->mac_reg[GPTC]);
1011 qemu_get_be32s(f, &s->mac_reg[ICR]);
1012 qemu_get_be32s(f, &s->mac_reg[ICS]);
1013 qemu_get_be32s(f, &s->mac_reg[IMC]);
1014 qemu_get_be32s(f, &s->mac_reg[IMS]);
1015 qemu_get_be32s(f, &s->mac_reg[LEDCTL]);
1016 qemu_get_be32s(f, &s->mac_reg[MANC]);
1017 qemu_get_be32s(f, &s->mac_reg[MDIC]);
1018 qemu_get_be32s(f, &s->mac_reg[MPC]);
1019 qemu_get_be32s(f, &s->mac_reg[PBA]);
1020 qemu_get_be32s(f, &s->mac_reg[RCTL]);
1021 qemu_get_be32s(f, &s->mac_reg[RDBAH]);
1022 qemu_get_be32s(f, &s->mac_reg[RDBAL]);
1023 qemu_get_be32s(f, &s->mac_reg[RDH]);
1024 qemu_get_be32s(f, &s->mac_reg[RDLEN]);
1025 qemu_get_be32s(f, &s->mac_reg[RDT]);
1026 qemu_get_be32s(f, &s->mac_reg[STATUS]);
1027 qemu_get_be32s(f, &s->mac_reg[SWSM]);
1028 qemu_get_be32s(f, &s->mac_reg[TCTL]);
1029 qemu_get_be32s(f, &s->mac_reg[TDBAH]);
1030 qemu_get_be32s(f, &s->mac_reg[TDBAL]);
1031 qemu_get_be32s(f, &s->mac_reg[TDH]);
1032 qemu_get_be32s(f, &s->mac_reg[TDLEN]);
1033 qemu_get_be32s(f, &s->mac_reg[TDT]);
1034 qemu_get_be32s(f, &s->mac_reg[TORH]);
1035 qemu_get_be32s(f, &s->mac_reg[TORL]);
1036 qemu_get_be32s(f, &s->mac_reg[TOTH]);
1037 qemu_get_be32s(f, &s->mac_reg[TOTL]);
1038 qemu_get_be32s(f, &s->mac_reg[TPR]);
1039 qemu_get_be32s(f, &s->mac_reg[TPT]);
1040 qemu_get_be32s(f, &s->mac_reg[TXDCTL]);
1041 qemu_get_be32s(f, &s->mac_reg[WUFC]);
1042 qemu_get_be32s(f, &s->mac_reg[VET]);
1043 for (i = 0; i < MAC_NARRAYS; i++)
1044 for (j = 0; j < mac_regarraystosave[i].size; j++)
1045 qemu_get_be32s(f,
1046 s->mac_reg + mac_regarraystosave[i].array0 + j);
1047 return 0;
1048 }
1049
1050 static const uint16_t e1000_eeprom_template[64] = {
1051 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1052 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1053 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1054 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1055 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1056 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1057 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1058 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1059 };
1060
1061 static const uint16_t phy_reg_init[] = {
1062 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
1063 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
1064 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
1065 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
1066 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
1067 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
1068 };
1069
1070 static const uint32_t mac_reg_init[] = {
1071 [PBA] = 0x00100030,
1072 [LEDCTL] = 0x602,
1073 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1074 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1075 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1076 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1077 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1078 E1000_STATUS_LU,
1079 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1080 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1081 E1000_MANC_RMCP_EN,
1082 };
1083
1084 /* PCI interface */
1085
1086 static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
1087 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1088 };
1089
1090 static CPUReadMemoryFunc * const e1000_mmio_read[] = {
1091 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1092 };
1093
1094 static void
1095 e1000_mmio_map(PCIDevice *pci_dev, int region_num,
1096 uint32_t addr, uint32_t size, int type)
1097 {
1098 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1099 int i;
1100 const uint32_t excluded_regs[] = {
1101 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1102 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1103 };
1104
1105
1106 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
1107
1108 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
1109 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1110
1111 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1112 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1113 excluded_regs[i + 1] -
1114 excluded_regs[i] - 4);
1115 }
1116
1117 static void
1118 e1000_cleanup(VLANClientState *vc)
1119 {
1120 E1000State *d = vc->opaque;
1121
1122 d->vc = NULL;
1123 }
1124
1125 static int
1126 pci_e1000_uninit(PCIDevice *dev)
1127 {
1128 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1129
1130 cpu_unregister_io_memory(d->mmio_index);
1131 qemu_del_vlan_client(d->vc);
1132 unregister_savevm("e1000", d);
1133 return 0;
1134 }
1135
1136 static void e1000_reset(void *opaque)
1137 {
1138 E1000State *d = opaque;
1139
1140 memset(d->phy_reg, 0, sizeof d->phy_reg);
1141 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1142 memset(d->mac_reg, 0, sizeof d->mac_reg);
1143 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1144 d->rxbuf_min_shift = 1;
1145 memset(&d->tx, 0, sizeof d->tx);
1146 }
1147
1148 static int pci_e1000_init(PCIDevice *pci_dev)
1149 {
1150 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1151 uint8_t *pci_conf;
1152 uint16_t checksum = 0;
1153 static const char info_str[] = "e1000";
1154 int i;
1155 uint8_t *macaddr;
1156
1157 pci_conf = d->dev.config;
1158
1159 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1160 pci_config_set_device_id(pci_conf, E1000_DEVID);
1161 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
1162 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
1163 pci_conf[0x08] = 0x03;
1164 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1165 pci_conf[0x0c] = 0x10;
1166
1167 pci_conf[0x3d] = 1; // interrupt pin 0
1168
1169 d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
1170 e1000_mmio_write, d);
1171
1172 pci_register_bar((PCIDevice *)d, 0, PNPMMIO_SIZE,
1173 PCI_ADDRESS_SPACE_MEM, e1000_mmio_map);
1174
1175 pci_register_bar((PCIDevice *)d, 1, IOPORT_SIZE,
1176 PCI_ADDRESS_SPACE_IO, ioport_map);
1177
1178 memmove(d->eeprom_data, e1000_eeprom_template,
1179 sizeof e1000_eeprom_template);
1180 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1181 macaddr = d->conf.macaddr.a;
1182 for (i = 0; i < 3; i++)
1183 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1184 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1185 checksum += d->eeprom_data[i];
1186 checksum = (uint16_t) EEPROM_SUM - checksum;
1187 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1188
1189 d->vc = qemu_new_vlan_client(NET_CLIENT_TYPE_NIC,
1190 d->conf.vlan, d->conf.peer,
1191 d->dev.qdev.info->name, d->dev.qdev.id,
1192 e1000_can_receive, e1000_receive, NULL,
1193 NULL, e1000_cleanup, d);
1194 d->vc->link_status_changed = e1000_set_link_status;
1195
1196 qemu_format_nic_info_str(d->vc, macaddr);
1197
1198 register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1199 e1000_reset(d);
1200
1201 #if 0 /* rom bev support is broken -> can't load unconditionally */
1202 if (!pci_dev->qdev.hotplugged) {
1203 static int loaded = 0;
1204 if (!loaded) {
1205 rom_add_option("pxe-e1000.bin");
1206 loaded = 1;
1207 }
1208 }
1209 #endif
1210 return 0;
1211 }
1212
1213 static void qdev_e1000_reset(DeviceState *dev)
1214 {
1215 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1216 e1000_reset(d);
1217 }
1218
1219 static PCIDeviceInfo e1000_info = {
1220 .qdev.name = "e1000",
1221 .qdev.desc = "Intel Gigabit Ethernet",
1222 .qdev.size = sizeof(E1000State),
1223 .qdev.reset = qdev_e1000_reset,
1224 .init = pci_e1000_init,
1225 .exit = pci_e1000_uninit,
1226 .qdev.props = (Property[]) {
1227 DEFINE_NIC_PROPERTIES(E1000State, conf),
1228 DEFINE_PROP_END_OF_LIST(),
1229 }
1230 };
1231
1232 static void e1000_register_devices(void)
1233 {
1234 pci_qdev_register(&e1000_info);
1235 }
1236
1237 device_init(e1000_register_devices)
CRIS target port of Qemu