hw/ide/via.c

   1 /*
   2  * QEMU IDE Emulation: PCI VIA82C686B support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include <hw/hw.h>
  27 #include <hw/i386/pc.h>
  28 #include <hw/pci/pci.h>
  29 #include <hw/isa/isa.h>
  30 #include "sysemu/block-backend.h"
  31 #include "sysemu/sysemu.h"
  32 #include "sysemu/dma.h"
  33
  34 #include <hw/ide/pci.h>
  35
  36 static uint64_t bmdma_read(void *opaque, hwaddr addr,
  37                            unsigned size)
  38 {
  39     BMDMAState *bm = opaque;
  40     uint32_t val;
  41
  42     if (size != 1) {
  43         return ((uint64_t)1 << (size * 8)) - 1;
  44     }
  45
  46     switch (addr & 3) {
  47     case 0:
  48         val = bm->cmd;
  49         break;
  50     case 2:
  51         val = bm->status;
  52         break;
  53     default:
  54         val = 0xff;
  55         break;
  56     }
  57 #ifdef DEBUG_IDE
  58     printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
  59 #endif
  60     return val;
  61 }
  62
  63 static void bmdma_write(void *opaque, hwaddr addr,
  64                         uint64_t val, unsigned size)
  65 {
  66     BMDMAState *bm = opaque;
  67
  68     if (size != 1) {
  69         return;
  70     }
  71
  72 #ifdef DEBUG_IDE
  73     printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
  74 #endif
  75     switch (addr & 3) {
  76     case 0:
  77         bmdma_cmd_writeb(bm, val);
  78         break;
  79     case 2:
  80         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
  81         break;
  82     default:;
  83     }
  84 }
  85
  86 static const MemoryRegionOps via_bmdma_ops = {
  87     .read = bmdma_read,
  88     .write = bmdma_write,
  89 };
  90
  91 static void bmdma_setup_bar(PCIIDEState *d)
  92 {
  93     int i;
  94
  95     memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
  96     for(i = 0;i < 2; i++) {
  97         BMDMAState *bm = &d->bmdma[i];
  98
  99         memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
 100                               "via-bmdma", 4);
 101         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 102         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 103                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 104         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 105     }
 106 }
 107
 108 static void via_reset(void *opaque)
 109 {
 110     PCIIDEState *d = opaque;
 111     PCIDevice *pd = PCI_DEVICE(d);
 112     uint8_t *pci_conf = pd->config;
 113     int i;
 114
 115     for (i = 0; i < 2; i++) {
 116         ide_bus_reset(&d->bus[i]);
 117     }
 118
 119     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
 120     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 121                  PCI_STATUS_DEVSEL_MEDIUM);
 122
 123     pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
 124     pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
 125     pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
 126     pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
 127     pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
 128     pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
 129
 130     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
 131     pci_set_long(pci_conf + 0x40, 0x0a090600);
 132     /* IDE misc configuration 1/2/3 */
 133     pci_set_long(pci_conf + 0x44, 0x00c00068);
 134     /* IDE Timing control */
 135     pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
 136     /* IDE Address Setup Time */
 137     pci_set_long(pci_conf + 0x4c, 0x000000ff);
 138     /* UltraDMA Extended Timing Control*/
 139     pci_set_long(pci_conf + 0x50, 0x07070707);
 140     /* UltraDMA FIFO Control */
 141     pci_set_long(pci_conf + 0x54, 0x00000004);
 142     /* IDE primary sector size */
 143     pci_set_long(pci_conf + 0x60, 0x00000200);
 144     /* IDE secondary sector size */
 145     pci_set_long(pci_conf + 0x68, 0x00000200);
 146     /* PCI PM Block */
 147     pci_set_long(pci_conf + 0xc0, 0x00020001);
 148 }
 149
 150 static void vt82c686b_init_ports(PCIIDEState *d) {
 151     static const struct {
 152         int iobase;
 153         int iobase2;
 154         int isairq;
 155     } port_info[] = {
 156         {0x1f0, 0x3f6, 14},
 157         {0x170, 0x376, 15},
 158     };
 159     int i;
 160
 161     for (i = 0; i < 2; i++) {
 162         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
 163         ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
 164                         port_info[i].iobase2);
 165         ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
 166
 167         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 168         d->bmdma[i].bus = &d->bus[i];
 169         ide_register_restart_cb(&d->bus[i]);
 170     }
 171 }
 172
 173 /* via ide func */
 174 static void vt82c686b_ide_realize(PCIDevice *dev, Error **errp)
 175 {
 176     PCIIDEState *d = PCI_IDE(dev);
 177     uint8_t *pci_conf = dev->config;
 178
 179     pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
 180     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 181
 182     qemu_register_reset(via_reset, d);
 183     bmdma_setup_bar(d);
 184     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 185
 186     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 187
 188     vt82c686b_init_ports(d);
 189 }
 190
 191 static void vt82c686b_ide_exitfn(PCIDevice *dev)
 192 {
 193     PCIIDEState *d = PCI_IDE(dev);
 194     unsigned i;
 195
 196     for (i = 0; i < 2; ++i) {
 197         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 198         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 199     }
 200 }
 201
 202 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
 203 {
 204     PCIDevice *dev;
 205
 206     dev = pci_create_simple(bus, devfn, "via-ide");
 207     pci_ide_create_devs(dev, hd_table);
 208 }
 209
 210 static void via_ide_class_init(ObjectClass *klass, void *data)
 211 {
 212     DeviceClass *dc = DEVICE_CLASS(klass);
 213     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 214
 215     k->realize = vt82c686b_ide_realize;
 216     k->exit = vt82c686b_ide_exitfn;
 217     k->vendor_id = PCI_VENDOR_ID_VIA;
 218     k->device_id = PCI_DEVICE_ID_VIA_IDE;
 219     k->revision = 0x06;
 220     k->class_id = PCI_CLASS_STORAGE_IDE;
 221     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 222 }
 223
 224 static const TypeInfo via_ide_info = {
 225     .name          = "via-ide",
 226     .parent        = TYPE_PCI_IDE,
 227     .class_init    = via_ide_class_init,
 228 };
 229
 230 static void via_ide_register_types(void)
 231 {
 232     type_register_static(&via_ide_info);
 233 }
 234
 235 type_init(via_ide_register_types)