1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
57 #include "hw/acpi/aml-build.h"
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
64 * a little bit, there should be plenty of free space since the DSDT
65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
68 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70 #define ACPI_BUILD_TABLE_SIZE 0x20000
72 /* #define DEBUG_ACPI_BUILD */
73 #ifdef DEBUG_ACPI_BUILD
74 #define ACPI_BUILD_DPRINTF(fmt, ...) \
75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
77 #define ACPI_BUILD_DPRINTF(fmt, ...)
80 typedef struct AcpiCpuInfo
{
81 DECLARE_BITMAP(found_cpus
, ACPI_CPU_HOTPLUG_ID_LIMIT
);
84 typedef struct AcpiMcfgInfo
{
89 typedef struct AcpiPmInfo
{
95 uint8_t acpi_enable_cmd
;
96 uint8_t acpi_disable_cmd
;
98 uint32_t gpe0_blk_len
;
100 uint16_t cpu_hp_io_base
;
101 uint16_t cpu_hp_io_len
;
102 uint16_t mem_hp_io_base
;
103 uint16_t mem_hp_io_len
;
104 uint16_t pcihp_io_base
;
105 uint16_t pcihp_io_len
;
108 typedef struct AcpiMiscInfo
{
110 TPMVersion tpm_version
;
111 const unsigned char *dsdt_code
;
113 uint16_t pvpanic_port
;
114 uint16_t applesmc_io_base
;
117 typedef struct AcpiBuildPciBusHotplugState
{
118 GArray
*device_table
;
119 GArray
*notify_table
;
120 struct AcpiBuildPciBusHotplugState
*parent
;
121 bool pcihp_bridge_en
;
122 } AcpiBuildPciBusHotplugState
;
124 static void acpi_get_dsdt(AcpiMiscInfo
*info
)
126 Object
*piix
= piix4_pm_find();
127 Object
*lpc
= ich9_lpc_find();
128 assert(!!piix
!= !!lpc
);
131 info
->dsdt_code
= AcpiDsdtAmlCode
;
132 info
->dsdt_size
= sizeof AcpiDsdtAmlCode
;
135 info
->dsdt_code
= Q35AcpiDsdtAmlCode
;
136 info
->dsdt_size
= sizeof Q35AcpiDsdtAmlCode
;
141 int acpi_add_cpu_info(Object
*o
, void *opaque
)
143 AcpiCpuInfo
*cpu
= opaque
;
146 if (object_dynamic_cast(o
, TYPE_CPU
)) {
147 apic_id
= object_property_get_int(o
, "apic-id", NULL
);
148 assert(apic_id
< ACPI_CPU_HOTPLUG_ID_LIMIT
);
150 set_bit(apic_id
, cpu
->found_cpus
);
153 object_child_foreach(o
, acpi_add_cpu_info
, opaque
);
157 static void acpi_get_cpu_info(AcpiCpuInfo
*cpu
)
159 Object
*root
= object_get_root();
161 memset(cpu
->found_cpus
, 0, sizeof cpu
->found_cpus
);
162 object_child_foreach(root
, acpi_add_cpu_info
, cpu
);
165 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
167 Object
*piix
= piix4_pm_find();
168 Object
*lpc
= ich9_lpc_find();
172 pm
->pcihp_io_base
= 0;
173 pm
->pcihp_io_len
= 0;
176 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
178 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
180 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
184 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
188 pm
->cpu_hp_io_len
= ACPI_GPE_PROC_LEN
;
189 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
190 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
192 /* Fill in optional s3/s4 related properties */
193 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
195 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
197 pm
->s3_disabled
= false;
200 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
202 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
204 pm
->s4_disabled
= false;
207 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
209 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
215 /* Fill in mandatory properties */
216 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
218 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
219 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
221 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
222 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
224 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
226 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
228 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
230 pm
->pcihp_bridge_en
=
231 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
235 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
237 info
->has_hpet
= hpet_find();
238 info
->tpm_version
= tpm_get_version();
239 info
->pvpanic_port
= pvpanic_port();
240 info
->applesmc_io_base
= applesmc_port();
244 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
245 * On i386 arch we only have two pci hosts, so we can look only for them.
247 static Object
*acpi_get_i386_pci_host(void)
251 host
= OBJECT_CHECK(PCIHostState
,
252 object_resolve_path("/machine/i440fx", NULL
),
253 TYPE_PCI_HOST_BRIDGE
);
255 host
= OBJECT_CHECK(PCIHostState
,
256 object_resolve_path("/machine/q35", NULL
),
257 TYPE_PCI_HOST_BRIDGE
);
263 static void acpi_get_pci_info(PcPciInfo
*info
)
268 pci_host
= acpi_get_i386_pci_host();
271 info
->w32
.begin
= object_property_get_int(pci_host
,
272 PCI_HOST_PROP_PCI_HOLE_START
,
274 info
->w32
.end
= object_property_get_int(pci_host
,
275 PCI_HOST_PROP_PCI_HOLE_END
,
277 info
->w64
.begin
= object_property_get_int(pci_host
,
278 PCI_HOST_PROP_PCI_HOLE64_START
,
280 info
->w64
.end
= object_property_get_int(pci_host
,
281 PCI_HOST_PROP_PCI_HOLE64_END
,
285 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
287 static void acpi_align_size(GArray
*blob
, unsigned align
)
289 /* Align size to multiple of given size. This reduces the chance
290 * we need to change size in the future (breaking cross version migration).
292 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
297 build_facs(GArray
*table_data
, GArray
*linker
, PcGuestInfo
*guest_info
)
299 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
300 memcpy(&facs
->signature
, "FACS", 4);
301 facs
->length
= cpu_to_le32(sizeof(*facs
));
304 /* Load chipset information in FADT */
305 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
309 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
310 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
311 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
312 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
313 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
314 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
315 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
316 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
317 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
318 /* EVT, CNT, TMR length matches hw/acpi/core.c */
319 fadt
->pm1_evt_len
= 4;
320 fadt
->pm1_cnt_len
= 2;
321 fadt
->pm_tmr_len
= 4;
322 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
323 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
324 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
325 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
326 (1 << ACPI_FADT_F_PROC_C1
) |
327 (1 << ACPI_FADT_F_SLP_BUTTON
) |
328 (1 << ACPI_FADT_F_RTC_S4
));
329 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
330 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
331 * For more than 8 CPUs, "Clustered Logical" mode has to be used
334 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
341 build_fadt(GArray
*table_data
, GArray
*linker
, AcpiPmInfo
*pm
,
342 unsigned facs
, unsigned dsdt
)
344 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
346 fadt
->firmware_ctrl
= cpu_to_le32(facs
);
347 /* FACS address to be filled by Guest linker */
348 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
349 ACPI_BUILD_TABLE_FILE
,
350 table_data
, &fadt
->firmware_ctrl
,
351 sizeof fadt
->firmware_ctrl
);
353 fadt
->dsdt
= cpu_to_le32(dsdt
);
354 /* DSDT address to be filled by Guest linker */
355 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
356 ACPI_BUILD_TABLE_FILE
,
357 table_data
, &fadt
->dsdt
,
360 fadt_setup(fadt
, pm
);
362 build_header(linker
, table_data
,
363 (void *)fadt
, "FACP", sizeof(*fadt
), 1);
367 build_madt(GArray
*table_data
, GArray
*linker
, AcpiCpuInfo
*cpu
,
368 PcGuestInfo
*guest_info
)
370 int madt_start
= table_data
->len
;
372 AcpiMultipleApicTable
*madt
;
373 AcpiMadtIoApic
*io_apic
;
374 AcpiMadtIntsrcovr
*intsrcovr
;
375 AcpiMadtLocalNmi
*local_nmi
;
378 madt
= acpi_data_push(table_data
, sizeof *madt
);
379 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
380 madt
->flags
= cpu_to_le32(1);
382 for (i
= 0; i
< guest_info
->apic_id_limit
; i
++) {
383 AcpiMadtProcessorApic
*apic
= acpi_data_push(table_data
, sizeof *apic
);
384 apic
->type
= ACPI_APIC_PROCESSOR
;
385 apic
->length
= sizeof(*apic
);
386 apic
->processor_id
= i
;
387 apic
->local_apic_id
= i
;
388 if (test_bit(i
, cpu
->found_cpus
)) {
389 apic
->flags
= cpu_to_le32(1);
391 apic
->flags
= cpu_to_le32(0);
394 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
395 io_apic
->type
= ACPI_APIC_IO
;
396 io_apic
->length
= sizeof(*io_apic
);
397 #define ACPI_BUILD_IOAPIC_ID 0x0
398 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
399 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
400 io_apic
->interrupt
= cpu_to_le32(0);
402 if (guest_info
->apic_xrupt_override
) {
403 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
404 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
405 intsrcovr
->length
= sizeof(*intsrcovr
);
406 intsrcovr
->source
= 0;
407 intsrcovr
->gsi
= cpu_to_le32(2);
408 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
410 for (i
= 1; i
< 16; i
++) {
411 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
412 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
413 /* No need for a INT source override structure. */
416 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
417 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
418 intsrcovr
->length
= sizeof(*intsrcovr
);
419 intsrcovr
->source
= i
;
420 intsrcovr
->gsi
= cpu_to_le32(i
);
421 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
424 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
425 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
426 local_nmi
->length
= sizeof(*local_nmi
);
427 local_nmi
->processor_id
= 0xff; /* all processors */
428 local_nmi
->flags
= cpu_to_le16(0);
429 local_nmi
->lint
= 1; /* ACPI_LINT1 */
431 build_header(linker
, table_data
,
432 (void *)(table_data
->data
+ madt_start
), "APIC",
433 table_data
->len
- madt_start
, 1);
436 #include "hw/i386/ssdt-tpm.hex"
437 #include "hw/i386/ssdt-tpm2.hex"
439 /* Assign BSEL property to all buses. In the future, this can be changed
440 * to only assign to buses that support hotplug.
442 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
444 unsigned *bsel_alloc
= opaque
;
447 if (qbus_is_hotpluggable(BUS(bus
))) {
448 bus_bsel
= g_malloc(sizeof *bus_bsel
);
450 *bus_bsel
= (*bsel_alloc
)++;
451 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
458 static void acpi_set_pci_info(void)
460 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
461 unsigned bsel_alloc
= 0;
464 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
465 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
469 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
472 int32_t devfn
= PCI_DEVFN(slot
, 0);
474 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
)));
475 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
476 aml_append(method
, if_ctx
);
479 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
480 bool pcihp_bridge_en
)
482 Aml
*dev
, *notify_method
, *method
;
487 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
489 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
491 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
492 notify_method
= aml_method("DVNT", 2);
495 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
498 PCIDevice
*pdev
= bus
->devices
[i
];
499 int slot
= PCI_SLOT(i
);
500 bool hotplug_enabled_dev
;
504 if (bsel
) { /* add hotplug slots for non present devices */
505 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
506 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
507 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
508 method
= aml_method("_EJ0", 1);
510 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
512 aml_append(dev
, method
);
513 aml_append(parent_scope
, dev
);
515 build_append_pcihp_notify_entry(notify_method
, slot
);
520 pc
= PCI_DEVICE_GET_CLASS(pdev
);
521 dc
= DEVICE_GET_CLASS(pdev
);
523 /* When hotplug for bridges is enabled, bridges are
524 * described in ACPI separately (see build_pci_bus_end).
525 * In this case they aren't themselves hot-pluggable.
526 * Hotplugged bridges *are* hot-pluggable.
528 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
529 !DEVICE(pdev
)->hotplugged
;
531 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
533 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
537 /* start to compose PCI slot descriptor */
538 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
539 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
541 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
542 /* add VGA specific AML methods */
545 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
551 method
= aml_method("_S1D", 0);
552 aml_append(method
, aml_return(aml_int(0)));
553 aml_append(dev
, method
);
555 method
= aml_method("_S2D", 0);
556 aml_append(method
, aml_return(aml_int(0)));
557 aml_append(dev
, method
);
559 method
= aml_method("_S3D", 0);
560 aml_append(method
, aml_return(aml_int(s3d
)));
561 aml_append(dev
, method
);
562 } else if (hotplug_enabled_dev
) {
563 /* add _SUN/_EJ0 to make slot hotpluggable */
564 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
566 method
= aml_method("_EJ0", 1);
568 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
570 aml_append(dev
, method
);
573 build_append_pcihp_notify_entry(notify_method
, slot
);
575 } else if (bridge_in_acpi
) {
577 * device is coldplugged bridge,
578 * add child device descriptions into its scope
580 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
582 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
584 /* slot descriptor has been composed, add it into parent context */
585 aml_append(parent_scope
, dev
);
589 aml_append(parent_scope
, notify_method
);
592 /* Append PCNT method to notify about events on local and child buses.
593 * Add unconditionally for root since DSDT expects it.
595 method
= aml_method("PCNT", 0);
597 /* If bus supports hotplug select it and notify about local events */
599 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
600 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
602 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
605 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
609 /* Notify about child bus events in any case */
610 if (pcihp_bridge_en
) {
611 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
612 int32_t devfn
= sec
->parent_dev
->devfn
;
614 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
617 aml_append(parent_scope
, method
);
618 qobject_decref(bsel
);
622 * initialize_route - Initialize the interrupt routing rule
623 * through a specific LINK:
624 * if (lnk_idx == idx)
625 * route using link 'link_name'
627 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
628 Aml
*lnk_idx
, int idx
)
630 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
631 Aml
*pkg
= aml_package(4);
633 aml_append(pkg
, aml_int(0));
634 aml_append(pkg
, aml_int(0));
635 aml_append(pkg
, aml_name("%s", link_name
));
636 aml_append(pkg
, aml_int(0));
637 aml_append(if_ctx
, aml_store(pkg
, route
));
643 * build_prt - Define interrupt rounting rules
645 * Returns an array of 128 routes, one for each device,
646 * based on device location.
647 * The main goal is to equaly distribute the interrupts
648 * over the 4 existing ACPI links (works only for i440fx).
649 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
652 static Aml
*build_prt(void)
654 Aml
*method
, *while_ctx
, *pin
, *res
;
656 method
= aml_method("_PRT", 0);
659 aml_append(method
, aml_store(aml_package(128), res
));
660 aml_append(method
, aml_store(aml_int(0), pin
));
662 /* while (pin < 128) */
663 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
665 Aml
*slot
= aml_local(2);
666 Aml
*lnk_idx
= aml_local(3);
667 Aml
*route
= aml_local(4);
669 /* slot = pin >> 2 */
670 aml_append(while_ctx
,
671 aml_store(aml_shiftright(pin
, aml_int(2)), slot
));
672 /* lnk_idx = (slot + pin) & 3 */
673 aml_append(while_ctx
,
674 aml_store(aml_and(aml_add(pin
, slot
), aml_int(3)), lnk_idx
));
676 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
677 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
678 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
679 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
680 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
682 /* route[0] = 0x[slot]FFFF */
683 aml_append(while_ctx
,
684 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF)),
685 aml_index(route
, aml_int(0))));
686 /* route[1] = pin & 3 */
687 aml_append(while_ctx
,
688 aml_store(aml_and(pin
, aml_int(3)), aml_index(route
, aml_int(1))));
689 /* res[pin] = route */
690 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
692 aml_append(while_ctx
, aml_increment(pin
));
694 aml_append(method
, while_ctx
);
696 aml_append(method
, aml_return(res
));
701 typedef struct CrsRangeEntry
{
706 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
708 CrsRangeEntry
*entry
;
710 entry
= g_malloc(sizeof(*entry
));
712 entry
->limit
= limit
;
714 g_ptr_array_add(ranges
, entry
);
717 static void crs_range_free(gpointer data
)
719 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
723 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
725 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
726 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
728 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
732 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
733 * interval, computes the 'free' ranges from the same interval.
734 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
735 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
737 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
738 uint64_t start
, uint64_t end
)
740 GPtrArray
*free_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
741 uint64_t free_base
= start
;
744 g_ptr_array_sort(ranges
, crs_range_compare
);
745 for (i
= 0; i
< ranges
->len
; i
++) {
746 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
748 if (free_base
< used
->base
) {
749 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
752 free_base
= used
->limit
+ 1;
755 if (free_base
< end
) {
756 crs_range_insert(free_ranges
, free_base
, end
);
759 g_ptr_array_set_size(ranges
, 0);
760 for (i
= 0; i
< free_ranges
->len
; i
++) {
761 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
764 g_ptr_array_free(free_ranges
, false);
767 static Aml
*build_crs(PCIHostState
*host
,
768 GPtrArray
*io_ranges
, GPtrArray
*mem_ranges
)
770 Aml
*crs
= aml_resource_template();
771 uint8_t max_bus
= pci_bus_num(host
->bus
);
775 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
777 uint64_t range_base
, range_limit
;
778 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
784 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
785 PCIIORegion
*r
= &dev
->io_regions
[i
];
787 range_base
= r
->addr
;
788 range_limit
= r
->addr
+ r
->size
- 1;
791 * Work-around for old bioses
792 * that do not support multiple root buses
794 if (!range_base
|| range_base
> range_limit
) {
798 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
800 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
801 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
806 range_limit
- range_base
+ 1));
807 crs_range_insert(io_ranges
, range_base
, range_limit
);
808 } else { /* "memory" */
810 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
811 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
817 range_limit
- range_base
+ 1));
818 crs_range_insert(mem_ranges
, range_base
, range_limit
);
822 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
823 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
824 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
825 if (subordinate
> max_bus
) {
826 max_bus
= subordinate
;
829 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
830 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
833 * Work-around for old bioses
834 * that do not support multiple root buses
836 if (range_base
&& range_base
<= range_limit
) {
838 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
839 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
844 range_limit
- range_base
+ 1));
845 crs_range_insert(io_ranges
, range_base
, range_limit
);
849 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
851 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
854 * Work-around for old bioses
855 * that do not support multiple root buses
857 if (range_base
&& range_base
<= range_limit
) {
859 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
860 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
866 range_limit
- range_base
+ 1));
867 crs_range_insert(mem_ranges
, range_base
, range_limit
);
871 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
873 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
876 * Work-around for old bioses
877 * that do not support multiple root buses
879 if (range_base
&& range_base
<= range_limit
) {
881 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
882 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
888 range_limit
- range_base
+ 1));
889 crs_range_insert(mem_ranges
, range_base
, range_limit
);
895 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
897 pci_bus_num(host
->bus
),
900 max_bus
- pci_bus_num(host
->bus
) + 1));
906 build_ssdt(GArray
*table_data
, GArray
*linker
,
907 AcpiCpuInfo
*cpu
, AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
908 PcPciInfo
*pci
, PcGuestInfo
*guest_info
)
910 MachineState
*machine
= MACHINE(qdev_get_machine());
911 uint32_t nr_mem
= machine
->ram_slots
;
912 unsigned acpi_cpus
= guest_info
->apic_id_limit
;
913 Aml
*ssdt
, *sb_scope
, *scope
, *pkg
, *dev
, *method
, *crs
, *field
, *ifctx
;
915 GPtrArray
*io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
916 GPtrArray
*mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
917 CrsRangeEntry
*entry
;
918 int root_bus_limit
= 0xFF;
921 ssdt
= init_aml_allocator();
922 /* The current AML generator can cover the APIC ID range [0..255],
923 * inclusive, for VCPU hotplug. */
924 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT
> 256);
925 g_assert(acpi_cpus
<= ACPI_CPU_HOTPLUG_ID_LIMIT
);
927 /* Reserve space for header */
928 acpi_data_push(ssdt
->buf
, sizeof(AcpiTableHeader
));
930 /* Extra PCI root buses are implemented only for i440fx */
933 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
934 uint8_t bus_num
= pci_bus_num(bus
);
935 uint8_t numa_node
= pci_bus_numa_node(bus
);
937 /* look only for expander root buses */
938 if (!pci_bus_is_root(bus
)) {
942 if (bus_num
< root_bus_limit
) {
943 root_bus_limit
= bus_num
- 1;
946 scope
= aml_scope("\\_SB");
947 dev
= aml_device("PC%.02X", bus_num
);
948 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
949 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
950 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
952 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
953 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
956 aml_append(dev
, build_prt());
957 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
),
958 io_ranges
, mem_ranges
);
959 aml_append(dev
, aml_name_decl("_CRS", crs
));
960 aml_append(scope
, dev
);
961 aml_append(ssdt
, scope
);
965 scope
= aml_scope("\\_SB.PCI0");
966 /* build PCI0._CRS */
967 crs
= aml_resource_template();
969 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
970 0x0000, 0x0, root_bus_limit
,
971 0x0000, root_bus_limit
+ 1));
972 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
975 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
976 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
977 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
979 crs_replace_with_free_ranges(io_ranges
, 0x0D00, 0xFFFF);
980 for (i
= 0; i
< io_ranges
->len
; i
++) {
981 entry
= g_ptr_array_index(io_ranges
, i
);
983 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
984 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
985 0x0000, entry
->base
, entry
->limit
,
986 0x0000, entry
->limit
- entry
->base
+ 1));
990 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
991 AML_CACHEABLE
, AML_READ_WRITE
,
992 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
994 crs_replace_with_free_ranges(mem_ranges
, pci
->w32
.begin
, pci
->w32
.end
- 1);
995 for (i
= 0; i
< mem_ranges
->len
; i
++) {
996 entry
= g_ptr_array_index(mem_ranges
, i
);
998 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
999 AML_NON_CACHEABLE
, AML_READ_WRITE
,
1000 0, entry
->base
, entry
->limit
,
1001 0, entry
->limit
- entry
->base
+ 1));
1004 if (pci
->w64
.begin
) {
1006 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1007 AML_CACHEABLE
, AML_READ_WRITE
,
1008 0, pci
->w64
.begin
, pci
->w64
.end
- 1, 0,
1009 pci
->w64
.end
- pci
->w64
.begin
));
1011 aml_append(scope
, aml_name_decl("_CRS", crs
));
1013 /* reserve GPE0 block resources */
1014 dev
= aml_device("GPE0");
1015 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1016 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
1017 /* device present, functioning, decoding, not shown in UI */
1018 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1019 crs
= aml_resource_template();
1021 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
1023 aml_append(dev
, aml_name_decl("_CRS", crs
));
1024 aml_append(scope
, dev
);
1026 g_ptr_array_free(io_ranges
, true);
1027 g_ptr_array_free(mem_ranges
, true);
1029 /* reserve PCIHP resources */
1030 if (pm
->pcihp_io_len
) {
1031 dev
= aml_device("PHPR");
1032 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1034 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1035 /* device present, functioning, decoding, not shown in UI */
1036 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1037 crs
= aml_resource_template();
1039 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
1042 aml_append(dev
, aml_name_decl("_CRS", crs
));
1043 aml_append(scope
, dev
);
1045 aml_append(ssdt
, scope
);
1047 /* create S3_ / S4_ / S5_ packages if necessary */
1048 scope
= aml_scope("\\");
1049 if (!pm
->s3_disabled
) {
1050 pkg
= aml_package(4);
1051 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1052 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1053 aml_append(pkg
, aml_int(0)); /* reserved */
1054 aml_append(pkg
, aml_int(0)); /* reserved */
1055 aml_append(scope
, aml_name_decl("_S3", pkg
));
1058 if (!pm
->s4_disabled
) {
1059 pkg
= aml_package(4);
1060 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
1061 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1062 aml_append(pkg
, aml_int(pm
->s4_val
));
1063 aml_append(pkg
, aml_int(0)); /* reserved */
1064 aml_append(pkg
, aml_int(0)); /* reserved */
1065 aml_append(scope
, aml_name_decl("_S4", pkg
));
1068 pkg
= aml_package(4);
1069 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1070 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1071 aml_append(pkg
, aml_int(0)); /* reserved */
1072 aml_append(pkg
, aml_int(0)); /* reserved */
1073 aml_append(scope
, aml_name_decl("_S5", pkg
));
1074 aml_append(ssdt
, scope
);
1076 if (misc
->applesmc_io_base
) {
1077 scope
= aml_scope("\\_SB.PCI0.ISA");
1078 dev
= aml_device("SMC");
1080 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
1081 /* device present, functioning, decoding, not shown in UI */
1082 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1084 crs
= aml_resource_template();
1086 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
1087 0x01, APPLESMC_MAX_DATA_LENGTH
)
1089 aml_append(crs
, aml_irq_no_flags(6));
1090 aml_append(dev
, aml_name_decl("_CRS", crs
));
1092 aml_append(scope
, dev
);
1093 aml_append(ssdt
, scope
);
1096 if (misc
->pvpanic_port
) {
1097 scope
= aml_scope("\\_SB.PCI0.ISA");
1099 dev
= aml_device("PEVT");
1100 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
1102 crs
= aml_resource_template();
1104 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
1106 aml_append(dev
, aml_name_decl("_CRS", crs
));
1108 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
1109 misc
->pvpanic_port
, 1));
1110 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_PRESERVE
);
1111 aml_append(field
, aml_named_field("PEPT", 8));
1112 aml_append(dev
, field
);
1114 /* device present, functioning, decoding, not shown in UI */
1115 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1117 method
= aml_method("RDPT", 0);
1118 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
1119 aml_append(method
, aml_return(aml_local(0)));
1120 aml_append(dev
, method
);
1122 method
= aml_method("WRPT", 1);
1123 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
1124 aml_append(dev
, method
);
1126 aml_append(scope
, dev
);
1127 aml_append(ssdt
, scope
);
1130 sb_scope
= aml_scope("\\_SB");
1132 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
1133 dev
= aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE
));
1134 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1136 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
1138 /* device present, functioning, decoding, not shown in UI */
1139 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1140 crs
= aml_resource_template();
1142 aml_io(AML_DECODE16
, pm
->cpu_hp_io_base
, pm
->cpu_hp_io_base
, 1,
1145 aml_append(dev
, aml_name_decl("_CRS", crs
));
1146 aml_append(sb_scope
, dev
);
1147 /* declare CPU hotplug MMIO region and PRS field to access it */
1148 aml_append(sb_scope
, aml_operation_region(
1149 "PRST", AML_SYSTEM_IO
, pm
->cpu_hp_io_base
, pm
->cpu_hp_io_len
));
1150 field
= aml_field("PRST", AML_BYTE_ACC
, AML_PRESERVE
);
1151 aml_append(field
, aml_named_field("PRS", 256));
1152 aml_append(sb_scope
, field
);
1154 /* build Processor object for each processor */
1155 for (i
= 0; i
< acpi_cpus
; i
++) {
1156 dev
= aml_processor(i
, 0, 0, "CP%.02X", i
);
1158 method
= aml_method("_MAT", 0);
1159 aml_append(method
, aml_return(aml_call1("CPMA", aml_int(i
))));
1160 aml_append(dev
, method
);
1162 method
= aml_method("_STA", 0);
1163 aml_append(method
, aml_return(aml_call1("CPST", aml_int(i
))));
1164 aml_append(dev
, method
);
1166 method
= aml_method("_EJ0", 1);
1168 aml_return(aml_call2("CPEJ", aml_int(i
), aml_arg(0)))
1170 aml_append(dev
, method
);
1172 aml_append(sb_scope
, dev
);
1176 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1178 /* Arg0 = Processor ID = APIC ID */
1179 method
= aml_method("NTFY", 2);
1180 for (i
= 0; i
< acpi_cpus
; i
++) {
1181 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1183 aml_notify(aml_name("CP%.02X", i
), aml_arg(1))
1185 aml_append(method
, ifctx
);
1187 aml_append(sb_scope
, method
);
1189 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1191 * Note: The ability to create variable-sized packages was first
1192 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1193 * ith up to 255 elements. Windows guests up to win2k8 fail when
1194 * VarPackageOp is used.
1196 pkg
= acpi_cpus
<= 255 ? aml_package(acpi_cpus
) :
1197 aml_varpackage(acpi_cpus
);
1199 for (i
= 0; i
< acpi_cpus
; i
++) {
1200 uint8_t b
= test_bit(i
, cpu
->found_cpus
) ? 0x01 : 0x00;
1201 aml_append(pkg
, aml_int(b
));
1203 aml_append(sb_scope
, aml_name_decl("CPON", pkg
));
1205 /* build memory devices */
1206 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
1207 scope
= aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE
));
1209 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER
), aml_int(nr_mem
))
1212 crs
= aml_resource_template();
1214 aml_io(AML_DECODE16
, pm
->mem_hp_io_base
, pm
->mem_hp_io_base
, 0,
1217 aml_append(scope
, aml_name_decl("_CRS", crs
));
1219 aml_append(scope
, aml_operation_region(
1220 stringify(MEMORY_HOTPLUG_IO_REGION
), AML_SYSTEM_IO
,
1221 pm
->mem_hp_io_base
, pm
->mem_hp_io_len
)
1224 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), AML_DWORD_ACC
,
1226 aml_append(field
, /* read only */
1227 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW
), 32));
1228 aml_append(field
, /* read only */
1229 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH
), 32));
1230 aml_append(field
, /* read only */
1231 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW
), 32));
1232 aml_append(field
, /* read only */
1233 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH
), 32));
1234 aml_append(field
, /* read only */
1235 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY
), 32));
1236 aml_append(scope
, field
);
1238 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), AML_BYTE_ACC
,
1239 AML_WRITE_AS_ZEROS
);
1240 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
1241 aml_append(field
, /* 1 if enabled, read only */
1242 aml_named_field(stringify(MEMORY_SLOT_ENABLED
), 1));
1244 /*(read) 1 if has a insert event. (write) 1 to clear event */
1245 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT
), 1));
1247 /* (read) 1 if has a remove event. (write) 1 to clear event */
1248 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT
), 1));
1250 /* initiates device eject, write only */
1251 aml_named_field(stringify(MEMORY_SLOT_EJECT
), 1));
1252 aml_append(scope
, field
);
1254 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), AML_DWORD_ACC
,
1256 aml_append(field
, /* DIMM selector, write only */
1257 aml_named_field(stringify(MEMORY_SLOT_SLECTOR
), 32));
1258 aml_append(field
, /* _OST event code, write only */
1259 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT
), 32));
1260 aml_append(field
, /* _OST status code, write only */
1261 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS
), 32));
1262 aml_append(scope
, field
);
1264 aml_append(sb_scope
, scope
);
1266 for (i
= 0; i
< nr_mem
; i
++) {
1267 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1270 dev
= aml_device("MP%02X", i
);
1271 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
1272 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1274 method
= aml_method("_CRS", 0);
1275 s
= BASEPATH
stringify(MEMORY_SLOT_CRS_METHOD
);
1276 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1277 aml_append(dev
, method
);
1279 method
= aml_method("_STA", 0);
1280 s
= BASEPATH
stringify(MEMORY_SLOT_STATUS_METHOD
);
1281 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1282 aml_append(dev
, method
);
1284 method
= aml_method("_PXM", 0);
1285 s
= BASEPATH
stringify(MEMORY_SLOT_PROXIMITY_METHOD
);
1286 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1287 aml_append(dev
, method
);
1289 method
= aml_method("_OST", 3);
1290 s
= BASEPATH
stringify(MEMORY_SLOT_OST_METHOD
);
1291 aml_append(method
, aml_return(aml_call4(
1292 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1294 aml_append(dev
, method
);
1296 method
= aml_method("_EJ0", 1);
1297 s
= BASEPATH
stringify(MEMORY_SLOT_EJECT_METHOD
);
1298 aml_append(method
, aml_return(aml_call2(
1299 s
, aml_name("_UID"), aml_arg(0))));
1300 aml_append(dev
, method
);
1302 aml_append(sb_scope
, dev
);
1305 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1306 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1308 method
= aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD
), 2);
1309 for (i
= 0; i
< nr_mem
; i
++) {
1310 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1312 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
1314 aml_append(method
, ifctx
);
1316 aml_append(sb_scope
, method
);
1322 pci_host
= acpi_get_i386_pci_host();
1324 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
1328 Aml
*scope
= aml_scope("PCI0");
1329 /* Scan all PCI buses. Generate tables to support hotplug. */
1330 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
1331 aml_append(sb_scope
, scope
);
1334 aml_append(ssdt
, sb_scope
);
1337 /* copy AML table into ACPI tables blob and patch header there */
1338 g_array_append_vals(table_data
, ssdt
->buf
->data
, ssdt
->buf
->len
);
1339 build_header(linker
, table_data
,
1340 (void *)(table_data
->data
+ table_data
->len
- ssdt
->buf
->len
),
1341 "SSDT", ssdt
->buf
->len
, 1);
1342 free_aml_allocator();
1346 build_hpet(GArray
*table_data
, GArray
*linker
)
1350 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
1351 /* Note timer_block_id value must be kept in sync with value advertised by
1354 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
1355 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
1356 build_header(linker
, table_data
,
1357 (void *)hpet
, "HPET", sizeof(*hpet
), 1);
1361 build_tpm_tcpa(GArray
*table_data
, GArray
*linker
, GArray
*tcpalog
)
1363 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
1364 uint64_t log_area_start_address
= acpi_data_len(tcpalog
);
1366 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
1367 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
1368 tcpa
->log_area_start_address
= cpu_to_le64(log_area_start_address
);
1370 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, 1,
1371 false /* high memory */);
1373 /* log area start address to be filled by Guest linker */
1374 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
1375 ACPI_BUILD_TPMLOG_FILE
,
1376 table_data
, &tcpa
->log_area_start_address
,
1377 sizeof(tcpa
->log_area_start_address
));
1379 build_header(linker
, table_data
,
1380 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2);
1382 acpi_data_push(tcpalog
, TPM_LOG_AREA_MINIMUM_SIZE
);
1386 build_tpm_ssdt(GArray
*table_data
, GArray
*linker
)
1390 tpm_ptr
= acpi_data_push(table_data
, sizeof(ssdt_tpm_aml
));
1391 memcpy(tpm_ptr
, ssdt_tpm_aml
, sizeof(ssdt_tpm_aml
));
1395 build_tpm2(GArray
*table_data
, GArray
*linker
)
1397 Acpi20TPM2
*tpm2_ptr
;
1400 tpm_ptr
= acpi_data_push(table_data
, sizeof(ssdt_tpm2_aml
));
1401 memcpy(tpm_ptr
, ssdt_tpm2_aml
, sizeof(ssdt_tpm2_aml
));
1403 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
1405 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
1406 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
1407 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
1409 build_header(linker
, table_data
,
1410 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4);
1414 MEM_AFFINITY_NOFLAGS
= 0,
1415 MEM_AFFINITY_ENABLED
= (1 << 0),
1416 MEM_AFFINITY_HOTPLUGGABLE
= (1 << 1),
1417 MEM_AFFINITY_NON_VOLATILE
= (1 << 2),
1418 } MemoryAffinityFlags
;
1421 acpi_build_srat_memory(AcpiSratMemoryAffinity
*numamem
, uint64_t base
,
1422 uint64_t len
, int node
, MemoryAffinityFlags flags
)
1424 numamem
->type
= ACPI_SRAT_MEMORY
;
1425 numamem
->length
= sizeof(*numamem
);
1426 memset(numamem
->proximity
, 0, 4);
1427 numamem
->proximity
[0] = node
;
1428 numamem
->flags
= cpu_to_le32(flags
);
1429 numamem
->base_addr
= cpu_to_le64(base
);
1430 numamem
->range_length
= cpu_to_le64(len
);
1434 build_srat(GArray
*table_data
, GArray
*linker
, PcGuestInfo
*guest_info
)
1436 AcpiSystemResourceAffinityTable
*srat
;
1437 AcpiSratProcessorAffinity
*core
;
1438 AcpiSratMemoryAffinity
*numamem
;
1442 int srat_start
, numa_start
, slots
;
1443 uint64_t mem_len
, mem_base
, next_base
;
1444 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1445 ram_addr_t hotplugabble_address_space_size
=
1446 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
1449 srat_start
= table_data
->len
;
1451 srat
= acpi_data_push(table_data
, sizeof *srat
);
1452 srat
->reserved1
= cpu_to_le32(1);
1453 core
= (void *)(srat
+ 1);
1455 for (i
= 0; i
< guest_info
->apic_id_limit
; ++i
) {
1456 core
= acpi_data_push(table_data
, sizeof *core
);
1457 core
->type
= ACPI_SRAT_PROCESSOR
;
1458 core
->length
= sizeof(*core
);
1459 core
->local_apic_id
= i
;
1460 curnode
= guest_info
->node_cpu
[i
];
1461 core
->proximity_lo
= curnode
;
1462 memset(core
->proximity_hi
, 0, 3);
1463 core
->local_sapic_eid
= 0;
1464 core
->flags
= cpu_to_le32(1);
1468 /* the memory map is a bit tricky, it contains at least one hole
1469 * from 640k-1M and possibly another one from 3.5G-4G.
1472 numa_start
= table_data
->len
;
1474 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1475 acpi_build_srat_memory(numamem
, 0, 640*1024, 0, MEM_AFFINITY_ENABLED
);
1476 next_base
= 1024 * 1024;
1477 for (i
= 1; i
< guest_info
->numa_nodes
+ 1; ++i
) {
1478 mem_base
= next_base
;
1479 mem_len
= guest_info
->node_mem
[i
- 1];
1481 mem_len
-= 1024 * 1024;
1483 next_base
= mem_base
+ mem_len
;
1485 /* Cut out the ACPI_PCI hole */
1486 if (mem_base
<= guest_info
->ram_size_below_4g
&&
1487 next_base
> guest_info
->ram_size_below_4g
) {
1488 mem_len
-= next_base
- guest_info
->ram_size_below_4g
;
1490 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1491 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1492 MEM_AFFINITY_ENABLED
);
1494 mem_base
= 1ULL << 32;
1495 mem_len
= next_base
- guest_info
->ram_size_below_4g
;
1496 next_base
+= (1ULL << 32) - guest_info
->ram_size_below_4g
;
1498 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1499 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1500 MEM_AFFINITY_ENABLED
);
1502 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
1503 for (; slots
< guest_info
->numa_nodes
+ 2; slots
++) {
1504 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1505 acpi_build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
1509 * Entry is required for Windows to enable memory hotplug in OS.
1510 * Memory devices may override proximity set by this entry,
1511 * providing _PXM method if necessary.
1513 if (hotplugabble_address_space_size
) {
1514 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1515 acpi_build_srat_memory(numamem
, pcms
->hotplug_memory_base
,
1516 hotplugabble_address_space_size
, 0,
1517 MEM_AFFINITY_HOTPLUGGABLE
|
1518 MEM_AFFINITY_ENABLED
);
1521 build_header(linker
, table_data
,
1522 (void *)(table_data
->data
+ srat_start
),
1524 table_data
->len
- srat_start
, 1);
1528 build_mcfg_q35(GArray
*table_data
, GArray
*linker
, AcpiMcfgInfo
*info
)
1530 AcpiTableMcfg
*mcfg
;
1532 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
1534 mcfg
= acpi_data_push(table_data
, len
);
1535 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
1536 /* Only a single allocation so no need to play with segments */
1537 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
1538 mcfg
->allocation
[0].start_bus_number
= 0;
1539 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
1541 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1542 * To avoid table size changes (which create migration issues),
1543 * always create the table even if there are no allocations,
1544 * but set the signature to a reserved value in this case.
1545 * ACPI spec requires OSPMs to ignore such tables.
1547 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
1548 /* Reserved signature: ignored by OSPM */
1553 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1);
1557 build_dmar_q35(GArray
*table_data
, GArray
*linker
)
1559 int dmar_start
= table_data
->len
;
1561 AcpiTableDmar
*dmar
;
1562 AcpiDmarHardwareUnit
*drhd
;
1564 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
1565 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
1566 dmar
->flags
= 0; /* No intr_remap for now */
1568 /* DMAR Remapping Hardware Unit Definition structure */
1569 drhd
= acpi_data_push(table_data
, sizeof(*drhd
));
1570 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
1571 drhd
->length
= cpu_to_le16(sizeof(*drhd
)); /* No device scope now */
1572 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
1573 drhd
->pci_segment
= cpu_to_le16(0);
1574 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
1576 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
1577 "DMAR", table_data
->len
- dmar_start
, 1);
1581 build_dsdt(GArray
*table_data
, GArray
*linker
, AcpiMiscInfo
*misc
)
1583 AcpiTableHeader
*dsdt
;
1585 assert(misc
->dsdt_code
&& misc
->dsdt_size
);
1587 dsdt
= acpi_data_push(table_data
, misc
->dsdt_size
);
1588 memcpy(dsdt
, misc
->dsdt_code
, misc
->dsdt_size
);
1590 memset(dsdt
, 0, sizeof *dsdt
);
1591 build_header(linker
, table_data
, dsdt
, "DSDT",
1592 misc
->dsdt_size
, 1);
1596 build_rsdp(GArray
*rsdp_table
, GArray
*linker
, unsigned rsdt
)
1598 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
1600 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, 16,
1601 true /* fseg memory */);
1603 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
1604 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
1605 rsdp
->rsdt_physical_address
= cpu_to_le32(rsdt
);
1606 /* Address to be filled by Guest linker */
1607 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_RSDP_FILE
,
1608 ACPI_BUILD_TABLE_FILE
,
1609 rsdp_table
, &rsdp
->rsdt_physical_address
,
1610 sizeof rsdp
->rsdt_physical_address
);
1612 /* Checksum to be filled by Guest linker */
1613 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
1614 rsdp
, rsdp
, sizeof *rsdp
, &rsdp
->checksum
);
1620 struct AcpiBuildState
{
1621 /* Copy of table in RAM (for patching). */
1622 MemoryRegion
*table_mr
;
1623 /* Is table patched? */
1625 PcGuestInfo
*guest_info
;
1627 MemoryRegion
*rsdp_mr
;
1628 MemoryRegion
*linker_mr
;
1631 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
1636 pci_host
= acpi_get_i386_pci_host();
1639 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
1643 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
1646 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
1648 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
1653 static bool acpi_has_iommu(void)
1656 Object
*intel_iommu
;
1658 intel_iommu
= object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE
,
1660 return intel_iommu
&& !ambiguous
;
1664 void acpi_build(PcGuestInfo
*guest_info
, AcpiBuildTables
*tables
)
1666 GArray
*table_offsets
;
1667 unsigned facs
, ssdt
, dsdt
, rsdt
;
1675 GArray
*tables_blob
= tables
->table_data
;
1677 acpi_get_cpu_info(&cpu
);
1678 acpi_get_pm_info(&pm
);
1679 acpi_get_dsdt(&misc
);
1680 acpi_get_misc_info(&misc
);
1681 acpi_get_pci_info(&pci
);
1683 table_offsets
= g_array_new(false, true /* clear */,
1685 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1687 bios_linker_loader_alloc(tables
->linker
, ACPI_BUILD_TABLE_FILE
,
1688 64 /* Ensure FACS is aligned */,
1689 false /* high memory */);
1692 * FACS is pointed to by FADT.
1693 * We place it first since it's the only table that has alignment
1696 facs
= tables_blob
->len
;
1697 build_facs(tables_blob
, tables
->linker
, guest_info
);
1699 /* DSDT is pointed to by FADT */
1700 dsdt
= tables_blob
->len
;
1701 build_dsdt(tables_blob
, tables
->linker
, &misc
);
1703 /* Count the size of the DSDT and SSDT, we will need it for legacy
1704 * sizing of ACPI tables.
1706 aml_len
+= tables_blob
->len
- dsdt
;
1708 /* ACPI tables pointed to by RSDT */
1709 acpi_add_table(table_offsets
, tables_blob
);
1710 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
);
1712 ssdt
= tables_blob
->len
;
1713 acpi_add_table(table_offsets
, tables_blob
);
1714 build_ssdt(tables_blob
, tables
->linker
, &cpu
, &pm
, &misc
, &pci
,
1716 aml_len
+= tables_blob
->len
- ssdt
;
1718 acpi_add_table(table_offsets
, tables_blob
);
1719 build_madt(tables_blob
, tables
->linker
, &cpu
, guest_info
);
1721 if (misc
.has_hpet
) {
1722 acpi_add_table(table_offsets
, tables_blob
);
1723 build_hpet(tables_blob
, tables
->linker
);
1725 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
1726 acpi_add_table(table_offsets
, tables_blob
);
1727 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
1729 acpi_add_table(table_offsets
, tables_blob
);
1730 switch (misc
.tpm_version
) {
1731 case TPM_VERSION_1_2
:
1732 build_tpm_ssdt(tables_blob
, tables
->linker
);
1734 case TPM_VERSION_2_0
:
1735 build_tpm2(tables_blob
, tables
->linker
);
1741 if (guest_info
->numa_nodes
) {
1742 acpi_add_table(table_offsets
, tables_blob
);
1743 build_srat(tables_blob
, tables
->linker
, guest_info
);
1745 if (acpi_get_mcfg(&mcfg
)) {
1746 acpi_add_table(table_offsets
, tables_blob
);
1747 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
1749 if (acpi_has_iommu()) {
1750 acpi_add_table(table_offsets
, tables_blob
);
1751 build_dmar_q35(tables_blob
, tables
->linker
);
1754 /* Add tables supplied by user (if any) */
1755 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
1756 unsigned len
= acpi_table_len(u
);
1758 acpi_add_table(table_offsets
, tables_blob
);
1759 g_array_append_vals(tables_blob
, u
, len
);
1762 /* RSDT is pointed to by RSDP */
1763 rsdt
= tables_blob
->len
;
1764 build_rsdt(tables_blob
, tables
->linker
, table_offsets
);
1766 /* RSDP is in FSEG memory, so allocate it separately */
1767 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
1769 /* We'll expose it all to Guest so we want to reduce
1770 * chance of size changes.
1772 * We used to align the tables to 4k, but of course this would
1773 * too simple to be enough. 4k turned out to be too small an
1774 * alignment very soon, and in fact it is almost impossible to
1775 * keep the table size stable for all (max_cpus, max_memory_slots)
1776 * combinations. So the table size is always 64k for pc-i440fx-2.1
1777 * and we give an error if the table grows beyond that limit.
1779 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1780 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1781 * than 2.0 and we can always pad the smaller tables with zeros. We can
1782 * then use the exact size of the 2.0 tables.
1784 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1786 if (guest_info
->legacy_acpi_table_size
) {
1787 /* Subtracting aml_len gives the size of fixed tables. Then add the
1788 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1790 int legacy_aml_len
=
1791 guest_info
->legacy_acpi_table_size
+
1792 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
1793 int legacy_table_size
=
1794 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
1795 ACPI_BUILD_ALIGN_SIZE
);
1796 if (tables_blob
->len
> legacy_table_size
) {
1797 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1798 error_report("Warning: migration may not work.");
1800 g_array_set_size(tables_blob
, legacy_table_size
);
1802 /* Make sure we have a buffer in case we need to resize the tables. */
1803 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
1804 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1805 error_report("Warning: ACPI tables are larger than 64k.");
1806 error_report("Warning: migration may not work.");
1807 error_report("Warning: please remove CPUs, NUMA nodes, "
1808 "memory slots or PCI bridges.");
1810 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
1813 acpi_align_size(tables
->linker
, ACPI_BUILD_ALIGN_SIZE
);
1815 /* Cleanup memory that's no longer used. */
1816 g_array_free(table_offsets
, true);
1819 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
1821 uint32_t size
= acpi_data_len(data
);
1823 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1824 memory_region_ram_resize(mr
, size
, &error_abort
);
1826 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
1827 memory_region_set_dirty(mr
, 0, size
);
1830 static void acpi_build_update(void *build_opaque
, uint32_t offset
)
1832 AcpiBuildState
*build_state
= build_opaque
;
1833 AcpiBuildTables tables
;
1835 /* No state to update or already patched? Nothing to do. */
1836 if (!build_state
|| build_state
->patched
) {
1839 build_state
->patched
= 1;
1841 acpi_build_tables_init(&tables
);
1843 acpi_build(build_state
->guest_info
, &tables
);
1845 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
1847 if (build_state
->rsdp
) {
1848 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
1850 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
1853 acpi_ram_update(build_state
->linker_mr
, tables
.linker
);
1854 acpi_build_tables_cleanup(&tables
, true);
1857 static void acpi_build_reset(void *build_opaque
)
1859 AcpiBuildState
*build_state
= build_opaque
;
1860 build_state
->patched
= 0;
1863 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
1864 GArray
*blob
, const char *name
,
1867 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
1868 name
, acpi_build_update
, build_state
);
1871 static const VMStateDescription vmstate_acpi_build
= {
1872 .name
= "acpi_build",
1874 .minimum_version_id
= 1,
1875 .fields
= (VMStateField
[]) {
1876 VMSTATE_UINT8(patched
, AcpiBuildState
),
1877 VMSTATE_END_OF_LIST()
1881 void acpi_setup(PcGuestInfo
*guest_info
)
1883 AcpiBuildTables tables
;
1884 AcpiBuildState
*build_state
;
1886 if (!guest_info
->fw_cfg
) {
1887 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1891 if (!guest_info
->has_acpi_build
) {
1892 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1896 if (!acpi_enabled
) {
1897 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1901 build_state
= g_malloc0(sizeof *build_state
);
1903 build_state
->guest_info
= guest_info
;
1905 acpi_set_pci_info();
1907 acpi_build_tables_init(&tables
);
1908 acpi_build(build_state
->guest_info
, &tables
);
1910 /* Now expose it all to Guest */
1911 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
1912 ACPI_BUILD_TABLE_FILE
,
1913 ACPI_BUILD_TABLE_MAX_SIZE
);
1914 assert(build_state
->table_mr
!= NULL
);
1916 build_state
->linker_mr
=
1917 acpi_add_rom_blob(build_state
, tables
.linker
, "etc/table-loader", 0);
1919 fw_cfg_add_file(guest_info
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
1920 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
1922 if (!guest_info
->rsdp_in_ram
) {
1924 * Keep for compatibility with old machine types.
1925 * Though RSDP is small, its contents isn't immutable, so
1926 * we'll update it along with the rest of tables on guest access.
1928 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
1930 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
1931 fw_cfg_add_file_callback(guest_info
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
1932 acpi_build_update
, build_state
,
1933 build_state
->rsdp
, rsdp_size
);
1934 build_state
->rsdp_mr
= NULL
;
1936 build_state
->rsdp
= NULL
;
1937 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
1938 ACPI_BUILD_RSDP_FILE
, 0);
1941 qemu_register_reset(acpi_build_reset
, build_state
);
1942 acpi_build_reset(build_state
);
1943 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
1945 /* Cleanup tables but don't free the memory: we track it
1948 acpi_build_tables_cleanup(&tables
, false);