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pc: acpi-build: create memory hotplug IO region dynamically
[qemu/cris-port.git] / hw / i386 / acpi-build.c
blob98553f8acb14ae98ef5dfc0f233b1e18d8f9fed9
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/range.h"
30 #include "qemu/error-report.h"
31 #include "hw/pci/pci.h"
32 #include "qom/cpu.h"
33 #include "hw/i386/pc.h"
34 #include "target-i386/cpu.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/i386/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
53
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "exec/ram_addr.h"
62
63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
65 * a little bit, there should be plenty of free space since the DSDT
66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 */
68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
69 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70
71 #define ACPI_BUILD_TABLE_SIZE 0x20000
72
73 /* Reserve RAM space for tables: add another order of magnitude. */
74 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 typedef struct AcpiCpuInfo {
85 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
86 } AcpiCpuInfo;
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
104 uint16_t cpu_hp_io_base;
105 uint16_t cpu_hp_io_len;
106 uint16_t mem_hp_io_base;
107 uint16_t mem_hp_io_len;
108 } AcpiPmInfo;
109
110 typedef struct AcpiMiscInfo {
111 bool has_hpet;
112 bool has_tpm;
113 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
114 const unsigned char *dsdt_code;
115 unsigned dsdt_size;
116 uint16_t pvpanic_port;
117 } AcpiMiscInfo;
118
119 typedef struct AcpiBuildPciBusHotplugState {
120 GArray *device_table;
121 GArray *notify_table;
122 struct AcpiBuildPciBusHotplugState *parent;
123 bool pcihp_bridge_en;
124 } AcpiBuildPciBusHotplugState;
125
126 static void acpi_get_dsdt(AcpiMiscInfo *info)
127 {
128 uint16_t *applesmc_sta;
129 Object *piix = piix4_pm_find();
130 Object *lpc = ich9_lpc_find();
131 assert(!!piix != !!lpc);
132
133 if (piix) {
134 info->dsdt_code = AcpiDsdtAmlCode;
135 info->dsdt_size = sizeof AcpiDsdtAmlCode;
136 applesmc_sta = piix_dsdt_applesmc_sta;
137 }
138 if (lpc) {
139 info->dsdt_code = Q35AcpiDsdtAmlCode;
140 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
141 applesmc_sta = q35_dsdt_applesmc_sta;
142 }
143
144 /* Patch in appropriate value for AppleSMC _STA */
145 *(uint8_t *)(info->dsdt_code + *applesmc_sta) =
146 applesmc_find() ? 0x0b : 0x00;
147 }
148
149 static
150 int acpi_add_cpu_info(Object *o, void *opaque)
151 {
152 AcpiCpuInfo *cpu = opaque;
153 uint64_t apic_id;
154
155 if (object_dynamic_cast(o, TYPE_CPU)) {
156 apic_id = object_property_get_int(o, "apic-id", NULL);
157 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
158
159 set_bit(apic_id, cpu->found_cpus);
160 }
161
162 object_child_foreach(o, acpi_add_cpu_info, opaque);
163 return 0;
164 }
165
166 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
167 {
168 Object *root = object_get_root();
169
170 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
171 object_child_foreach(root, acpi_add_cpu_info, cpu);
172 }
173
174 static void acpi_get_pm_info(AcpiPmInfo *pm)
175 {
176 Object *piix = piix4_pm_find();
177 Object *lpc = ich9_lpc_find();
178 Object *obj = NULL;
179 QObject *o;
180
181 if (piix) {
182 obj = piix;
183 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
184 }
185 if (lpc) {
186 obj = lpc;
187 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
188 }
189 assert(obj);
190
191 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
192 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
193 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
194
195 /* Fill in optional s3/s4 related properties */
196 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
197 if (o) {
198 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
199 } else {
200 pm->s3_disabled = false;
201 }
202 qobject_decref(o);
203 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
204 if (o) {
205 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
206 } else {
207 pm->s4_disabled = false;
208 }
209 qobject_decref(o);
210 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
211 if (o) {
212 pm->s4_val = qint_get_int(qobject_to_qint(o));
213 } else {
214 pm->s4_val = false;
215 }
216 qobject_decref(o);
217
218 /* Fill in mandatory properties */
219 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
220
221 pm->acpi_enable_cmd = object_property_get_int(obj,
222 ACPI_PM_PROP_ACPI_ENABLE_CMD,
223 NULL);
224 pm->acpi_disable_cmd = object_property_get_int(obj,
225 ACPI_PM_PROP_ACPI_DISABLE_CMD,
226 NULL);
227 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
228 NULL);
229 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
230 NULL);
231 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
232 NULL);
233 pm->pcihp_bridge_en =
234 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
235 NULL);
236 }
237
238 static void acpi_get_misc_info(AcpiMiscInfo *info)
239 {
240 info->has_hpet = hpet_find();
241 info->has_tpm = tpm_find();
242 info->pvpanic_port = pvpanic_port();
243 }
244
245 static void acpi_get_pci_info(PcPciInfo *info)
246 {
247 Object *pci_host;
248 bool ambiguous;
249
250 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
251 g_assert(!ambiguous);
252 g_assert(pci_host);
253
254 info->w32.begin = object_property_get_int(pci_host,
255 PCI_HOST_PROP_PCI_HOLE_START,
256 NULL);
257 info->w32.end = object_property_get_int(pci_host,
258 PCI_HOST_PROP_PCI_HOLE_END,
259 NULL);
260 info->w64.begin = object_property_get_int(pci_host,
261 PCI_HOST_PROP_PCI_HOLE64_START,
262 NULL);
263 info->w64.end = object_property_get_int(pci_host,
264 PCI_HOST_PROP_PCI_HOLE64_END,
265 NULL);
266 }
267
268 #define ACPI_BUILD_APPNAME "Bochs"
269 #define ACPI_BUILD_APPNAME6 "BOCHS "
270 #define ACPI_BUILD_APPNAME4 "BXPC"
271
272 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
273 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
274 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
275
276 static void
277 build_header(GArray *linker, GArray *table_data,
278 AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
279 {
280 memcpy(&h->signature, sig, 4);
281 h->length = cpu_to_le32(len);
282 h->revision = rev;
283 memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
284 memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
285 memcpy(h->oem_table_id + 4, sig, 4);
286 h->oem_revision = cpu_to_le32(1);
287 memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
288 h->asl_compiler_revision = cpu_to_le32(1);
289 h->checksum = 0;
290 /* Checksum to be filled in by Guest linker */
291 bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
292 table_data->data, h, len, &h->checksum);
293 }
294
295 static GArray *build_alloc_method(const char *name, uint8_t arg_count)
296 {
297 GArray *method = build_alloc_array();
298
299 build_append_namestring(method, "%s", name);
300 build_append_byte(method, arg_count); /* MethodFlags: ArgCount */
301
302 return method;
303 }
304
305 static void build_append_and_cleanup_method(GArray *device, GArray *method)
306 {
307 uint8_t op = 0x14; /* MethodOp */
308
309 build_package(method, op);
310
311 build_append_array(device, method);
312 build_free_array(method);
313 }
314
315 /* End here */
316 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
317
318 static inline void *acpi_data_push(GArray *table_data, unsigned size)
319 {
320 unsigned off = table_data->len;
321 g_array_set_size(table_data, off + size);
322 return table_data->data + off;
323 }
324
325 static unsigned acpi_data_len(GArray *table)
326 {
327 #if GLIB_CHECK_VERSION(2, 22, 0)
328 assert(g_array_get_element_size(table) == 1);
329 #endif
330 return table->len;
331 }
332
333 static void acpi_align_size(GArray *blob, unsigned align)
334 {
335 /* Align size to multiple of given size. This reduces the chance
336 * we need to change size in the future (breaking cross version migration).
337 */
338 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
339 }
340
341 /* Set a value within table in a safe manner */
342 #define ACPI_BUILD_SET_LE(table, size, off, bits, val) \
343 do { \
344 uint64_t ACPI_BUILD_SET_LE_val = cpu_to_le64(val); \
345 memcpy(acpi_data_get_ptr(table, size, off, \
346 (bits) / BITS_PER_BYTE), \
347 &ACPI_BUILD_SET_LE_val, \
348 (bits) / BITS_PER_BYTE); \
349 } while (0)
350
351 static inline void *acpi_data_get_ptr(uint8_t *table_data, unsigned table_size,
352 unsigned off, unsigned size)
353 {
354 assert(off + size > off);
355 assert(off + size <= table_size);
356 return table_data + off;
357 }
358
359 static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
360 {
361 uint32_t offset = cpu_to_le32(table_data->len);
362 g_array_append_val(table_offsets, offset);
363 }
364
365 /* FACS */
366 static void
367 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
368 {
369 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
370 memcpy(&facs->signature, "FACS", 4);
371 facs->length = cpu_to_le32(sizeof(*facs));
372 }
373
374 /* Load chipset information in FADT */
375 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
376 {
377 fadt->model = 1;
378 fadt->reserved1 = 0;
379 fadt->sci_int = cpu_to_le16(pm->sci_int);
380 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
381 fadt->acpi_enable = pm->acpi_enable_cmd;
382 fadt->acpi_disable = pm->acpi_disable_cmd;
383 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
384 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
385 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
386 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
387 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
388 /* EVT, CNT, TMR length matches hw/acpi/core.c */
389 fadt->pm1_evt_len = 4;
390 fadt->pm1_cnt_len = 2;
391 fadt->pm_tmr_len = 4;
392 fadt->gpe0_blk_len = pm->gpe0_blk_len;
393 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
394 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
395 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
396 (1 << ACPI_FADT_F_PROC_C1) |
397 (1 << ACPI_FADT_F_SLP_BUTTON) |
398 (1 << ACPI_FADT_F_RTC_S4));
399 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
400 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
401 * For more than 8 CPUs, "Clustered Logical" mode has to be used
402 */
403 if (max_cpus > 8) {
404 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
405 }
406 }
407
408
409 /* FADT */
410 static void
411 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
412 unsigned facs, unsigned dsdt)
413 {
414 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
415
416 fadt->firmware_ctrl = cpu_to_le32(facs);
417 /* FACS address to be filled by Guest linker */
418 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
419 ACPI_BUILD_TABLE_FILE,
420 table_data, &fadt->firmware_ctrl,
421 sizeof fadt->firmware_ctrl);
422
423 fadt->dsdt = cpu_to_le32(dsdt);
424 /* DSDT address to be filled by Guest linker */
425 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
426 ACPI_BUILD_TABLE_FILE,
427 table_data, &fadt->dsdt,
428 sizeof fadt->dsdt);
429
430 fadt_setup(fadt, pm);
431
432 build_header(linker, table_data,
433 (void *)fadt, "FACP", sizeof(*fadt), 1);
434 }
435
436 static void
437 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
438 PcGuestInfo *guest_info)
439 {
440 int madt_start = table_data->len;
441
442 AcpiMultipleApicTable *madt;
443 AcpiMadtIoApic *io_apic;
444 AcpiMadtIntsrcovr *intsrcovr;
445 AcpiMadtLocalNmi *local_nmi;
446 int i;
447
448 madt = acpi_data_push(table_data, sizeof *madt);
449 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
450 madt->flags = cpu_to_le32(1);
451
452 for (i = 0; i < guest_info->apic_id_limit; i++) {
453 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
454 apic->type = ACPI_APIC_PROCESSOR;
455 apic->length = sizeof(*apic);
456 apic->processor_id = i;
457 apic->local_apic_id = i;
458 if (test_bit(i, cpu->found_cpus)) {
459 apic->flags = cpu_to_le32(1);
460 } else {
461 apic->flags = cpu_to_le32(0);
462 }
463 }
464 io_apic = acpi_data_push(table_data, sizeof *io_apic);
465 io_apic->type = ACPI_APIC_IO;
466 io_apic->length = sizeof(*io_apic);
467 #define ACPI_BUILD_IOAPIC_ID 0x0
468 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
469 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
470 io_apic->interrupt = cpu_to_le32(0);
471
472 if (guest_info->apic_xrupt_override) {
473 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
474 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
475 intsrcovr->length = sizeof(*intsrcovr);
476 intsrcovr->source = 0;
477 intsrcovr->gsi = cpu_to_le32(2);
478 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
479 }
480 for (i = 1; i < 16; i++) {
481 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
482 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
483 /* No need for a INT source override structure. */
484 continue;
485 }
486 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
487 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
488 intsrcovr->length = sizeof(*intsrcovr);
489 intsrcovr->source = i;
490 intsrcovr->gsi = cpu_to_le32(i);
491 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
492 }
493
494 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
495 local_nmi->type = ACPI_APIC_LOCAL_NMI;
496 local_nmi->length = sizeof(*local_nmi);
497 local_nmi->processor_id = 0xff; /* all processors */
498 local_nmi->flags = cpu_to_le16(0);
499 local_nmi->lint = 1; /* ACPI_LINT1 */
500
501 build_header(linker, table_data,
502 (void *)(table_data->data + madt_start), "APIC",
503 table_data->len - madt_start, 1);
504 }
505
506 /* Encode a hex value */
507 static inline char acpi_get_hex(uint32_t val)
508 {
509 val &= 0x0f;
510 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
511 }
512
513 /* 0x5B 0x82 DeviceOp PkgLength NameString */
514 #define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
515 #define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
516 #define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
517 #define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
518 #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
519 #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
520
521 #define ACPI_PCINOHP_OFFSET_HEX (*ssdt_pcinohp_name - *ssdt_pcinohp_start + 1)
522 #define ACPI_PCINOHP_OFFSET_ADR (*ssdt_pcinohp_adr - *ssdt_pcinohp_start)
523 #define ACPI_PCINOHP_SIZEOF (*ssdt_pcinohp_end - *ssdt_pcinohp_start)
524 #define ACPI_PCINOHP_AML (ssdp_pcihp_aml + *ssdt_pcinohp_start)
525
526 #define ACPI_PCIVGA_OFFSET_HEX (*ssdt_pcivga_name - *ssdt_pcivga_start + 1)
527 #define ACPI_PCIVGA_OFFSET_ADR (*ssdt_pcivga_adr - *ssdt_pcivga_start)
528 #define ACPI_PCIVGA_SIZEOF (*ssdt_pcivga_end - *ssdt_pcivga_start)
529 #define ACPI_PCIVGA_AML (ssdp_pcihp_aml + *ssdt_pcivga_start)
530
531 #define ACPI_PCIQXL_OFFSET_HEX (*ssdt_pciqxl_name - *ssdt_pciqxl_start + 1)
532 #define ACPI_PCIQXL_OFFSET_ADR (*ssdt_pciqxl_adr - *ssdt_pciqxl_start)
533 #define ACPI_PCIQXL_SIZEOF (*ssdt_pciqxl_end - *ssdt_pciqxl_start)
534 #define ACPI_PCIQXL_AML (ssdp_pcihp_aml + *ssdt_pciqxl_start)
535
536 #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
537 #define ACPI_SSDT_HEADER_LENGTH 36
538
539 #include "hw/i386/ssdt-misc.hex"
540 #include "hw/i386/ssdt-pcihp.hex"
541 #include "hw/i386/ssdt-tpm.hex"
542
543 static void patch_pcihp(int slot, uint8_t *ssdt_ptr)
544 {
545 unsigned devfn = PCI_DEVFN(slot, 0);
546
547 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
548 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
549 ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
550 ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
551 }
552
553 static void patch_pcinohp(int slot, uint8_t *ssdt_ptr)
554 {
555 unsigned devfn = PCI_DEVFN(slot, 0);
556
557 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
558 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
559 ssdt_ptr[ACPI_PCINOHP_OFFSET_ADR + 2] = slot;
560 }
561
562 static void patch_pcivga(int slot, uint8_t *ssdt_ptr)
563 {
564 unsigned devfn = PCI_DEVFN(slot, 0);
565
566 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
567 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX + 1] = acpi_get_hex(devfn);
568 ssdt_ptr[ACPI_PCIVGA_OFFSET_ADR + 2] = slot;
569 }
570
571 static void patch_pciqxl(int slot, uint8_t *ssdt_ptr)
572 {
573 unsigned devfn = PCI_DEVFN(slot, 0);
574
575 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
576 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX + 1] = acpi_get_hex(devfn);
577 ssdt_ptr[ACPI_PCIQXL_OFFSET_ADR + 2] = slot;
578 }
579
580 /* Assign BSEL property to all buses. In the future, this can be changed
581 * to only assign to buses that support hotplug.
582 */
583 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
584 {
585 unsigned *bsel_alloc = opaque;
586 unsigned *bus_bsel;
587
588 if (qbus_is_hotpluggable(BUS(bus))) {
589 bus_bsel = g_malloc(sizeof *bus_bsel);
590
591 *bus_bsel = (*bsel_alloc)++;
592 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
593 bus_bsel, NULL);
594 }
595
596 return bsel_alloc;
597 }
598
599 static void acpi_set_pci_info(void)
600 {
601 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
602 unsigned bsel_alloc = 0;
603
604 if (bus) {
605 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
606 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
607 }
608 }
609
610 static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state,
611 AcpiBuildPciBusHotplugState *parent,
612 bool pcihp_bridge_en)
613 {
614 state->parent = parent;
615 state->device_table = build_alloc_array();
616 state->notify_table = build_alloc_array();
617 state->pcihp_bridge_en = pcihp_bridge_en;
618 }
619
620 static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state)
621 {
622 build_free_array(state->device_table);
623 build_free_array(state->notify_table);
624 }
625
626 static void *build_pci_bus_begin(PCIBus *bus, void *parent_state)
627 {
628 AcpiBuildPciBusHotplugState *parent = parent_state;
629 AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child);
630
631 build_pci_bus_state_init(child, parent, parent->pcihp_bridge_en);
632
633 return child;
634 }
635
636 static void build_pci_bus_end(PCIBus *bus, void *bus_state)
637 {
638 AcpiBuildPciBusHotplugState *child = bus_state;
639 AcpiBuildPciBusHotplugState *parent = child->parent;
640 GArray *bus_table = build_alloc_array();
641 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
642 DECLARE_BITMAP(slot_device_present, PCI_SLOT_MAX);
643 DECLARE_BITMAP(slot_device_system, PCI_SLOT_MAX);
644 DECLARE_BITMAP(slot_device_vga, PCI_SLOT_MAX);
645 DECLARE_BITMAP(slot_device_qxl, PCI_SLOT_MAX);
646 uint8_t op;
647 int i;
648 QObject *bsel;
649 GArray *method;
650 bool bus_hotplug_support = false;
651
652 /*
653 * Skip bridge subtree creation if bridge hotplug is disabled
654 * to make acpi tables compatible with legacy machine types.
655 * Skip creation for hotplugged bridges as well.
656 */
657 if (bus->parent_dev && (!child->pcihp_bridge_en ||
658 DEVICE(bus->parent_dev)->hotplugged)) {
659 build_free_array(bus_table);
660 build_pci_bus_state_cleanup(child);
661 g_free(child);
662 return;
663 }
664
665 if (bus->parent_dev) {
666 op = 0x82; /* DeviceOp */
667 build_append_namestring(bus_table, "S%.02X",
668 bus->parent_dev->devfn);
669 build_append_byte(bus_table, 0x08); /* NameOp */
670 build_append_namestring(bus_table, "_SUN");
671 build_append_int(bus_table, PCI_SLOT(bus->parent_dev->devfn));
672 build_append_byte(bus_table, 0x08); /* NameOp */
673 build_append_namestring(bus_table, "_ADR");
674 build_append_int(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) |
675 PCI_FUNC(bus->parent_dev->devfn));
676 } else {
677 op = 0x10; /* ScopeOp */;
678 build_append_namestring(bus_table, "PCI0");
679 }
680
681 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
682 if (bsel) {
683 build_append_byte(bus_table, 0x08); /* NameOp */
684 build_append_namestring(bus_table, "BSEL");
685 build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel)));
686 memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable);
687 } else {
688 /* No bsel - no slots are hot-pluggable */
689 memset(slot_hotplug_enable, 0x00, sizeof slot_hotplug_enable);
690 }
691
692 memset(slot_device_present, 0x00, sizeof slot_device_present);
693 memset(slot_device_system, 0x00, sizeof slot_device_present);
694 memset(slot_device_vga, 0x00, sizeof slot_device_vga);
695 memset(slot_device_qxl, 0x00, sizeof slot_device_qxl);
696
697 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
698 DeviceClass *dc;
699 PCIDeviceClass *pc;
700 PCIDevice *pdev = bus->devices[i];
701 int slot = PCI_SLOT(i);
702 bool bridge_in_acpi;
703
704 if (!pdev) {
705 continue;
706 }
707
708 set_bit(slot, slot_device_present);
709 pc = PCI_DEVICE_GET_CLASS(pdev);
710 dc = DEVICE_GET_CLASS(pdev);
711
712 /* When hotplug for bridges is enabled, bridges are
713 * described in ACPI separately (see build_pci_bus_end).
714 * In this case they aren't themselves hot-pluggable.
715 * Hotplugged bridges *are* hot-pluggable.
716 */
717 bridge_in_acpi = pc->is_bridge && child->pcihp_bridge_en &&
718 !DEVICE(pdev)->hotplugged;
719
720 if (pc->class_id == PCI_CLASS_BRIDGE_ISA || bridge_in_acpi) {
721 set_bit(slot, slot_device_system);
722 }
723
724 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
725 set_bit(slot, slot_device_vga);
726
727 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
728 set_bit(slot, slot_device_qxl);
729 }
730 }
731
732 if (!dc->hotpluggable || bridge_in_acpi) {
733 clear_bit(slot, slot_hotplug_enable);
734 }
735 }
736
737 /* Append Device object for each slot */
738 for (i = 0; i < PCI_SLOT_MAX; i++) {
739 bool can_eject = test_bit(i, slot_hotplug_enable);
740 bool present = test_bit(i, slot_device_present);
741 bool vga = test_bit(i, slot_device_vga);
742 bool qxl = test_bit(i, slot_device_qxl);
743 bool system = test_bit(i, slot_device_system);
744 if (can_eject) {
745 void *pcihp = acpi_data_push(bus_table,
746 ACPI_PCIHP_SIZEOF);
747 memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
748 patch_pcihp(i, pcihp);
749 bus_hotplug_support = true;
750 } else if (qxl) {
751 void *pcihp = acpi_data_push(bus_table,
752 ACPI_PCIQXL_SIZEOF);
753 memcpy(pcihp, ACPI_PCIQXL_AML, ACPI_PCIQXL_SIZEOF);
754 patch_pciqxl(i, pcihp);
755 } else if (vga) {
756 void *pcihp = acpi_data_push(bus_table,
757 ACPI_PCIVGA_SIZEOF);
758 memcpy(pcihp, ACPI_PCIVGA_AML, ACPI_PCIVGA_SIZEOF);
759 patch_pcivga(i, pcihp);
760 } else if (system) {
761 /* Nothing to do: system devices are in DSDT or in SSDT above. */
762 } else if (present) {
763 void *pcihp = acpi_data_push(bus_table,
764 ACPI_PCINOHP_SIZEOF);
765 memcpy(pcihp, ACPI_PCINOHP_AML, ACPI_PCINOHP_SIZEOF);
766 patch_pcinohp(i, pcihp);
767 }
768 }
769
770 if (bsel) {
771 method = build_alloc_method("DVNT", 2);
772
773 for (i = 0; i < PCI_SLOT_MAX; i++) {
774 GArray *notify;
775 uint8_t op;
776
777 if (!test_bit(i, slot_hotplug_enable)) {
778 continue;
779 }
780
781 notify = build_alloc_array();
782 op = 0xA0; /* IfOp */
783
784 build_append_byte(notify, 0x7B); /* AndOp */
785 build_append_byte(notify, 0x68); /* Arg0Op */
786 build_append_int(notify, 0x1U << i);
787 build_append_byte(notify, 0x00); /* NullName */
788 build_append_byte(notify, 0x86); /* NotifyOp */
789 build_append_namestring(notify, "S%.02X", PCI_DEVFN(i, 0));
790 build_append_byte(notify, 0x69); /* Arg1Op */
791
792 /* Pack it up */
793 build_package(notify, op);
794
795 build_append_array(method, notify);
796
797 build_free_array(notify);
798 }
799
800 build_append_and_cleanup_method(bus_table, method);
801 }
802
803 /* Append PCNT method to notify about events on local and child buses.
804 * Add unconditionally for root since DSDT expects it.
805 */
806 if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) {
807 method = build_alloc_method("PCNT", 0);
808
809 /* If bus supports hotplug select it and notify about local events */
810 if (bsel) {
811 build_append_byte(method, 0x70); /* StoreOp */
812 build_append_int(method, qint_get_int(qobject_to_qint(bsel)));
813 build_append_namestring(method, "BNUM");
814 build_append_namestring(method, "DVNT");
815 build_append_namestring(method, "PCIU");
816 build_append_int(method, 1); /* Device Check */
817 build_append_namestring(method, "DVNT");
818 build_append_namestring(method, "PCID");
819 build_append_int(method, 3); /* Eject Request */
820 }
821
822 /* Notify about child bus events in any case */
823 build_append_array(method, child->notify_table);
824
825 build_append_and_cleanup_method(bus_table, method);
826
827 /* Append description of child buses */
828 build_append_array(bus_table, child->device_table);
829
830 /* Pack it up */
831 if (bus->parent_dev) {
832 build_extop_package(bus_table, op);
833 } else {
834 build_package(bus_table, op);
835 }
836
837 /* Append our bus description to parent table */
838 build_append_array(parent->device_table, bus_table);
839
840 /* Also tell parent how to notify us, invoking PCNT method.
841 * At the moment this is not needed for root as we have a single root.
842 */
843 if (bus->parent_dev) {
844 build_append_namestring(parent->notify_table, "^PCNT.S%.02X",
845 bus->parent_dev->devfn);
846 }
847 }
848
849 qobject_decref(bsel);
850 build_free_array(bus_table);
851 build_pci_bus_state_cleanup(child);
852 g_free(child);
853 }
854
855 static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
856 {
857 ACPI_BUILD_SET_LE(start, size, acpi_pci32_start[0], 32, pci->w32.begin);
858
859 ACPI_BUILD_SET_LE(start, size, acpi_pci32_end[0], 32, pci->w32.end - 1);
860
861 if (pci->w64.end || pci->w64.begin) {
862 ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 1);
863 ACPI_BUILD_SET_LE(start, size, acpi_pci64_start[0], 64, pci->w64.begin);
864 ACPI_BUILD_SET_LE(start, size, acpi_pci64_end[0], 64, pci->w64.end - 1);
865 ACPI_BUILD_SET_LE(start, size, acpi_pci64_length[0], 64, pci->w64.end - pci->w64.begin);
866 } else {
867 ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 0);
868 }
869 }
870
871 static void
872 build_ssdt(GArray *table_data, GArray *linker,
873 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
874 PcPciInfo *pci, PcGuestInfo *guest_info)
875 {
876 MachineState *machine = MACHINE(qdev_get_machine());
877 uint32_t nr_mem = machine->ram_slots;
878 unsigned acpi_cpus = guest_info->apic_id_limit;
879 uint8_t *ssdt_ptr;
880 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
881 int i;
882
883 ssdt = init_aml_allocator();
884 /* The current AML generator can cover the APIC ID range [0..255],
885 * inclusive, for VCPU hotplug. */
886 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
887 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
888
889 /* Copy header and patch values in the S3_ / S4_ / S5_ packages */
890 ssdt_ptr = acpi_data_push(ssdt->buf, sizeof(ssdp_misc_aml));
891 memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
892
893 patch_pci_windows(pci, ssdt_ptr, sizeof(ssdp_misc_aml));
894
895 /* create S3_ / S4_ / S5_ packages if necessary */
896 scope = aml_scope("\\");
897 if (!pm->s3_disabled) {
898 pkg = aml_package(4);
899 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
900 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
901 aml_append(pkg, aml_int(0)); /* reserved */
902 aml_append(pkg, aml_int(0)); /* reserved */
903 aml_append(scope, aml_name_decl("_S3", pkg));
904 }
905
906 if (!pm->s4_disabled) {
907 pkg = aml_package(4);
908 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
909 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
910 aml_append(pkg, aml_int(pm->s4_val));
911 aml_append(pkg, aml_int(0)); /* reserved */
912 aml_append(pkg, aml_int(0)); /* reserved */
913 aml_append(scope, aml_name_decl("_S4", pkg));
914 }
915
916 pkg = aml_package(4);
917 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
918 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
919 aml_append(pkg, aml_int(0)); /* reserved */
920 aml_append(pkg, aml_int(0)); /* reserved */
921 aml_append(scope, aml_name_decl("_S5", pkg));
922 aml_append(ssdt, scope);
923
924 if (misc->pvpanic_port) {
925 scope = aml_scope("\\_SB.PCI0.ISA");
926
927 dev = aml_device("PEVR");
928 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
929
930 crs = aml_resource_template();
931 aml_append(crs,
932 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
933 );
934 aml_append(dev, aml_name_decl("_CRS", crs));
935
936 aml_append(dev, aml_operation_region("PEOR", aml_system_io,
937 misc->pvpanic_port, 1));
938 field = aml_field("PEOR", aml_byte_acc);
939 aml_append(field, aml_named_field("PEPT", 8));
940 aml_append(dev, field);
941
942 method = aml_method("RDPT", 0);
943 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
944 aml_append(method, aml_return(aml_local(0)));
945 aml_append(dev, method);
946
947 method = aml_method("WRPT", 1);
948 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
949 aml_append(dev, method);
950
951 aml_append(scope, dev);
952 aml_append(ssdt, scope);
953 }
954
955 sb_scope = aml_scope("_SB");
956 {
957 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
958 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
959 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
960 aml_append(dev,
961 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
962 );
963 /* device present, functioning, decoding, not shown in UI */
964 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
965 crs = aml_resource_template();
966 aml_append(crs,
967 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
968 pm->cpu_hp_io_len)
969 );
970 aml_append(dev, aml_name_decl("_CRS", crs));
971 aml_append(sb_scope, dev);
972 /* declare CPU hotplug MMIO region and PRS field to access it */
973 aml_append(sb_scope, aml_operation_region(
974 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
975 field = aml_field("PRST", aml_byte_acc);
976 aml_append(field, aml_named_field("PRS", 256));
977 aml_append(sb_scope, field);
978
979 /* build Processor object for each processor */
980 for (i = 0; i < acpi_cpus; i++) {
981 dev = aml_processor(i, 0, 0, "CP%.02X", i);
982
983 method = aml_method("_MAT", 0);
984 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
985 aml_append(dev, method);
986
987 method = aml_method("_STA", 0);
988 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
989 aml_append(dev, method);
990
991 method = aml_method("_EJ0", 1);
992 aml_append(method,
993 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
994 );
995 aml_append(dev, method);
996
997 aml_append(sb_scope, dev);
998 }
999
1000 /* build this code:
1001 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1002 */
1003 /* Arg0 = Processor ID = APIC ID */
1004 method = aml_method("NTFY", 2);
1005 for (i = 0; i < acpi_cpus; i++) {
1006 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1007 aml_append(ifctx,
1008 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1009 );
1010 aml_append(method, ifctx);
1011 }
1012 aml_append(sb_scope, method);
1013
1014 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1015 *
1016 * Note: The ability to create variable-sized packages was first
1017 * ntroduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1018 * ith up to 255 elements. Windows guests up to win2k8 fail when
1019 * VarPackageOp is used.
1020 */
1021 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1022 aml_varpackage(acpi_cpus);
1023
1024 for (i = 0; i < acpi_cpus; i++) {
1025 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1026 aml_append(pkg, aml_int(b));
1027 }
1028 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1029
1030 /* build memory devices */
1031 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1032 scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE));
1033 aml_append(scope,
1034 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem))
1035 );
1036
1037 crs = aml_resource_template();
1038 aml_append(crs,
1039 aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
1040 pm->mem_hp_io_len)
1041 );
1042 aml_append(scope, aml_name_decl("_CRS", crs));
1043
1044 aml_append(scope, aml_operation_region(
1045 stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io,
1046 pm->mem_hp_io_base, pm->mem_hp_io_len)
1047 );
1048
1049 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1050 aml_append(field, /* read only */
1051 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
1052 aml_append(field, /* read only */
1053 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32));
1054 aml_append(field, /* read only */
1055 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32));
1056 aml_append(field, /* read only */
1057 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32));
1058 aml_append(field, /* read only */
1059 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
1060 aml_append(scope, field);
1061
1062 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc);
1063 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1064 aml_append(field, /* 1 if enabled, read only */
1065 aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
1066 aml_append(field,
1067 /*(read) 1 if has a insert event. (write) 1 to clear event */
1068 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1));
1069 aml_append(scope, field);
1070
1071 field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc);
1072 aml_append(field, /* DIMM selector, write only */
1073 aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
1074 aml_append(field, /* _OST event code, write only */
1075 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32));
1076 aml_append(field, /* _OST status code, write only */
1077 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32));
1078 aml_append(scope, field);
1079
1080 aml_append(sb_scope, scope);
1081
1082 for (i = 0; i < nr_mem; i++) {
1083 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1084 const char *s;
1085
1086 dev = aml_device("MP%02X", i);
1087 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1088 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1089
1090 method = aml_method("_CRS", 0);
1091 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1092 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1093 aml_append(dev, method);
1094
1095 method = aml_method("_STA", 0);
1096 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1097 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1098 aml_append(dev, method);
1099
1100 method = aml_method("_PXM", 0);
1101 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1102 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1103 aml_append(dev, method);
1104
1105 method = aml_method("_OST", 3);
1106 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1107 aml_append(method, aml_return(aml_call4(
1108 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1109 )));
1110 aml_append(dev, method);
1111
1112 aml_append(sb_scope, dev);
1113 }
1114
1115 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1116 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ...
1117 */
1118 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2);
1119 for (i = 0; i < nr_mem; i++) {
1120 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1121 aml_append(ifctx,
1122 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1123 );
1124 aml_append(method, ifctx);
1125 }
1126 aml_append(sb_scope, method);
1127
1128 {
1129 AcpiBuildPciBusHotplugState hotplug_state;
1130 Object *pci_host;
1131 PCIBus *bus = NULL;
1132 bool ambiguous;
1133
1134 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1135 if (!ambiguous && pci_host) {
1136 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1137 }
1138
1139 build_pci_bus_state_init(&hotplug_state, NULL, pm->pcihp_bridge_en);
1140
1141 if (bus) {
1142 /* Scan all PCI buses. Generate tables to support hotplug. */
1143 pci_for_each_bus_depth_first(bus, build_pci_bus_begin,
1144 build_pci_bus_end, &hotplug_state);
1145 }
1146
1147 build_append_array(sb_scope->buf, hotplug_state.device_table);
1148 build_pci_bus_state_cleanup(&hotplug_state);
1149 }
1150 aml_append(ssdt, sb_scope);
1151 }
1152
1153 /* copy AML table into ACPI tables blob and patch header there */
1154 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1155 build_header(linker, table_data,
1156 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1157 "SSDT", ssdt->buf->len, 1);
1158 free_aml_allocator();
1159 }
1160
1161 static void
1162 build_hpet(GArray *table_data, GArray *linker)
1163 {
1164 Acpi20Hpet *hpet;
1165
1166 hpet = acpi_data_push(table_data, sizeof(*hpet));
1167 /* Note timer_block_id value must be kept in sync with value advertised by
1168 * emulated hpet
1169 */
1170 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1171 hpet->addr.address = cpu_to_le64(HPET_BASE);
1172 build_header(linker, table_data,
1173 (void *)hpet, "HPET", sizeof(*hpet), 1);
1174 }
1175
1176 static void
1177 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1178 {
1179 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1180 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1181
1182 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1183 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1184 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1185
1186 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1187 false /* high memory */);
1188
1189 /* log area start address to be filled by Guest linker */
1190 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1191 ACPI_BUILD_TPMLOG_FILE,
1192 table_data, &tcpa->log_area_start_address,
1193 sizeof(tcpa->log_area_start_address));
1194
1195 build_header(linker, table_data,
1196 (void *)tcpa, "TCPA", sizeof(*tcpa), 2);
1197
1198 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1199 }
1200
1201 static void
1202 build_tpm_ssdt(GArray *table_data, GArray *linker)
1203 {
1204 void *tpm_ptr;
1205
1206 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml));
1207 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml));
1208 }
1209
1210 typedef enum {
1211 MEM_AFFINITY_NOFLAGS = 0,
1212 MEM_AFFINITY_ENABLED = (1 << 0),
1213 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1214 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1215 } MemoryAffinityFlags;
1216
1217 static void
1218 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1219 uint64_t len, int node, MemoryAffinityFlags flags)
1220 {
1221 numamem->type = ACPI_SRAT_MEMORY;
1222 numamem->length = sizeof(*numamem);
1223 memset(numamem->proximity, 0, 4);
1224 numamem->proximity[0] = node;
1225 numamem->flags = cpu_to_le32(flags);
1226 numamem->base_addr = cpu_to_le64(base);
1227 numamem->range_length = cpu_to_le64(len);
1228 }
1229
1230 static void
1231 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1232 {
1233 AcpiSystemResourceAffinityTable *srat;
1234 AcpiSratProcessorAffinity *core;
1235 AcpiSratMemoryAffinity *numamem;
1236
1237 int i;
1238 uint64_t curnode;
1239 int srat_start, numa_start, slots;
1240 uint64_t mem_len, mem_base, next_base;
1241 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1242 ram_addr_t hotplugabble_address_space_size =
1243 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1244 NULL);
1245
1246 srat_start = table_data->len;
1247
1248 srat = acpi_data_push(table_data, sizeof *srat);
1249 srat->reserved1 = cpu_to_le32(1);
1250 core = (void *)(srat + 1);
1251
1252 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1253 core = acpi_data_push(table_data, sizeof *core);
1254 core->type = ACPI_SRAT_PROCESSOR;
1255 core->length = sizeof(*core);
1256 core->local_apic_id = i;
1257 curnode = guest_info->node_cpu[i];
1258 core->proximity_lo = curnode;
1259 memset(core->proximity_hi, 0, 3);
1260 core->local_sapic_eid = 0;
1261 core->flags = cpu_to_le32(1);
1262 }
1263
1264
1265 /* the memory map is a bit tricky, it contains at least one hole
1266 * from 640k-1M and possibly another one from 3.5G-4G.
1267 */
1268 next_base = 0;
1269 numa_start = table_data->len;
1270
1271 numamem = acpi_data_push(table_data, sizeof *numamem);
1272 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1273 next_base = 1024 * 1024;
1274 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1275 mem_base = next_base;
1276 mem_len = guest_info->node_mem[i - 1];
1277 if (i == 1) {
1278 mem_len -= 1024 * 1024;
1279 }
1280 next_base = mem_base + mem_len;
1281
1282 /* Cut out the ACPI_PCI hole */
1283 if (mem_base <= guest_info->ram_size_below_4g &&
1284 next_base > guest_info->ram_size_below_4g) {
1285 mem_len -= next_base - guest_info->ram_size_below_4g;
1286 if (mem_len > 0) {
1287 numamem = acpi_data_push(table_data, sizeof *numamem);
1288 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1289 MEM_AFFINITY_ENABLED);
1290 }
1291 mem_base = 1ULL << 32;
1292 mem_len = next_base - guest_info->ram_size_below_4g;
1293 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1294 }
1295 numamem = acpi_data_push(table_data, sizeof *numamem);
1296 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1297 MEM_AFFINITY_ENABLED);
1298 }
1299 slots = (table_data->len - numa_start) / sizeof *numamem;
1300 for (; slots < guest_info->numa_nodes + 2; slots++) {
1301 numamem = acpi_data_push(table_data, sizeof *numamem);
1302 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1303 }
1304
1305 /*
1306 * Entry is required for Windows to enable memory hotplug in OS.
1307 * Memory devices may override proximity set by this entry,
1308 * providing _PXM method if necessary.
1309 */
1310 if (hotplugabble_address_space_size) {
1311 numamem = acpi_data_push(table_data, sizeof *numamem);
1312 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base,
1313 hotplugabble_address_space_size, 0,
1314 MEM_AFFINITY_HOTPLUGGABLE |
1315 MEM_AFFINITY_ENABLED);
1316 }
1317
1318 build_header(linker, table_data,
1319 (void *)(table_data->data + srat_start),
1320 "SRAT",
1321 table_data->len - srat_start, 1);
1322 }
1323
1324 static void
1325 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1326 {
1327 AcpiTableMcfg *mcfg;
1328 const char *sig;
1329 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1330
1331 mcfg = acpi_data_push(table_data, len);
1332 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1333 /* Only a single allocation so no need to play with segments */
1334 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1335 mcfg->allocation[0].start_bus_number = 0;
1336 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1337
1338 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1339 * To avoid table size changes (which create migration issues),
1340 * always create the table even if there are no allocations,
1341 * but set the signature to a reserved value in this case.
1342 * ACPI spec requires OSPMs to ignore such tables.
1343 */
1344 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1345 /* Reserved signature: ignored by OSPM */
1346 sig = "QEMU";
1347 } else {
1348 sig = "MCFG";
1349 }
1350 build_header(linker, table_data, (void *)mcfg, sig, len, 1);
1351 }
1352
1353 static void
1354 build_dmar_q35(GArray *table_data, GArray *linker)
1355 {
1356 int dmar_start = table_data->len;
1357
1358 AcpiTableDmar *dmar;
1359 AcpiDmarHardwareUnit *drhd;
1360
1361 dmar = acpi_data_push(table_data, sizeof(*dmar));
1362 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1363 dmar->flags = 0; /* No intr_remap for now */
1364
1365 /* DMAR Remapping Hardware Unit Definition structure */
1366 drhd = acpi_data_push(table_data, sizeof(*drhd));
1367 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1368 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1369 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1370 drhd->pci_segment = cpu_to_le16(0);
1371 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1372
1373 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1374 "DMAR", table_data->len - dmar_start, 1);
1375 }
1376
1377 static void
1378 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1379 {
1380 AcpiTableHeader *dsdt;
1381
1382 assert(misc->dsdt_code && misc->dsdt_size);
1383
1384 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1385 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1386
1387 memset(dsdt, 0, sizeof *dsdt);
1388 build_header(linker, table_data, dsdt, "DSDT",
1389 misc->dsdt_size, 1);
1390 }
1391
1392 /* Build final rsdt table */
1393 static void
1394 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
1395 {
1396 AcpiRsdtDescriptorRev1 *rsdt;
1397 size_t rsdt_len;
1398 int i;
1399
1400 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
1401 rsdt = acpi_data_push(table_data, rsdt_len);
1402 memcpy(rsdt->table_offset_entry, table_offsets->data,
1403 sizeof(uint32_t) * table_offsets->len);
1404 for (i = 0; i < table_offsets->len; ++i) {
1405 /* rsdt->table_offset_entry to be filled by Guest linker */
1406 bios_linker_loader_add_pointer(linker,
1407 ACPI_BUILD_TABLE_FILE,
1408 ACPI_BUILD_TABLE_FILE,
1409 table_data, &rsdt->table_offset_entry[i],
1410 sizeof(uint32_t));
1411 }
1412 build_header(linker, table_data,
1413 (void *)rsdt, "RSDT", rsdt_len, 1);
1414 }
1415
1416 static GArray *
1417 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1418 {
1419 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1420
1421 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1422 true /* fseg memory */);
1423
1424 memcpy(&rsdp->signature, "RSD PTR ", 8);
1425 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1426 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1427 /* Address to be filled by Guest linker */
1428 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1429 ACPI_BUILD_TABLE_FILE,
1430 rsdp_table, &rsdp->rsdt_physical_address,
1431 sizeof rsdp->rsdt_physical_address);
1432 rsdp->checksum = 0;
1433 /* Checksum to be filled by Guest linker */
1434 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1435 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1436
1437 return rsdp_table;
1438 }
1439
1440 typedef
1441 struct AcpiBuildTables {
1442 GArray *table_data;
1443 GArray *rsdp;
1444 GArray *tcpalog;
1445 GArray *linker;
1446 } AcpiBuildTables;
1447
1448 static inline void acpi_build_tables_init(AcpiBuildTables *tables)
1449 {
1450 tables->rsdp = g_array_new(false, true /* clear */, 1);
1451 tables->table_data = g_array_new(false, true /* clear */, 1);
1452 tables->tcpalog = g_array_new(false, true /* clear */, 1);
1453 tables->linker = bios_linker_loader_init();
1454 }
1455
1456 static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
1457 {
1458 void *linker_data = bios_linker_loader_cleanup(tables->linker);
1459 g_free(linker_data);
1460 g_array_free(tables->rsdp, true);
1461 g_array_free(tables->table_data, true);
1462 g_array_free(tables->tcpalog, mfre);
1463 }
1464
1465 typedef
1466 struct AcpiBuildState {
1467 /* Copy of table in RAM (for patching). */
1468 ram_addr_t table_ram;
1469 /* Is table patched? */
1470 uint8_t patched;
1471 PcGuestInfo *guest_info;
1472 void *rsdp;
1473 ram_addr_t rsdp_ram;
1474 ram_addr_t linker_ram;
1475 } AcpiBuildState;
1476
1477 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1478 {
1479 Object *pci_host;
1480 QObject *o;
1481 bool ambiguous;
1482
1483 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1484 g_assert(!ambiguous);
1485 g_assert(pci_host);
1486
1487 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1488 if (!o) {
1489 return false;
1490 }
1491 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1492 qobject_decref(o);
1493
1494 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1495 assert(o);
1496 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1497 qobject_decref(o);
1498 return true;
1499 }
1500
1501 static bool acpi_has_iommu(void)
1502 {
1503 bool ambiguous;
1504 Object *intel_iommu;
1505
1506 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1507 &ambiguous);
1508 return intel_iommu && !ambiguous;
1509 }
1510
1511 static
1512 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1513 {
1514 GArray *table_offsets;
1515 unsigned facs, ssdt, dsdt, rsdt;
1516 AcpiCpuInfo cpu;
1517 AcpiPmInfo pm;
1518 AcpiMiscInfo misc;
1519 AcpiMcfgInfo mcfg;
1520 PcPciInfo pci;
1521 uint8_t *u;
1522 size_t aml_len = 0;
1523 GArray *tables_blob = tables->table_data;
1524
1525 acpi_get_cpu_info(&cpu);
1526 acpi_get_pm_info(&pm);
1527 acpi_get_dsdt(&misc);
1528 acpi_get_misc_info(&misc);
1529 acpi_get_pci_info(&pci);
1530
1531 table_offsets = g_array_new(false, true /* clear */,
1532 sizeof(uint32_t));
1533 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1534
1535 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1536 64 /* Ensure FACS is aligned */,
1537 false /* high memory */);
1538
1539 /*
1540 * FACS is pointed to by FADT.
1541 * We place it first since it's the only table that has alignment
1542 * requirements.
1543 */
1544 facs = tables_blob->len;
1545 build_facs(tables_blob, tables->linker, guest_info);
1546
1547 /* DSDT is pointed to by FADT */
1548 dsdt = tables_blob->len;
1549 build_dsdt(tables_blob, tables->linker, &misc);
1550
1551 /* Count the size of the DSDT and SSDT, we will need it for legacy
1552 * sizing of ACPI tables.
1553 */
1554 aml_len += tables_blob->len - dsdt;
1555
1556 /* ACPI tables pointed to by RSDT */
1557 acpi_add_table(table_offsets, tables_blob);
1558 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1559
1560 ssdt = tables_blob->len;
1561 acpi_add_table(table_offsets, tables_blob);
1562 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1563 guest_info);
1564 aml_len += tables_blob->len - ssdt;
1565
1566 acpi_add_table(table_offsets, tables_blob);
1567 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1568
1569 if (misc.has_hpet) {
1570 acpi_add_table(table_offsets, tables_blob);
1571 build_hpet(tables_blob, tables->linker);
1572 }
1573 if (misc.has_tpm) {
1574 acpi_add_table(table_offsets, tables_blob);
1575 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1576
1577 acpi_add_table(table_offsets, tables_blob);
1578 build_tpm_ssdt(tables_blob, tables->linker);
1579 }
1580 if (guest_info->numa_nodes) {
1581 acpi_add_table(table_offsets, tables_blob);
1582 build_srat(tables_blob, tables->linker, guest_info);
1583 }
1584 if (acpi_get_mcfg(&mcfg)) {
1585 acpi_add_table(table_offsets, tables_blob);
1586 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1587 }
1588 if (acpi_has_iommu()) {
1589 acpi_add_table(table_offsets, tables_blob);
1590 build_dmar_q35(tables_blob, tables->linker);
1591 }
1592
1593 /* Add tables supplied by user (if any) */
1594 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1595 unsigned len = acpi_table_len(u);
1596
1597 acpi_add_table(table_offsets, tables_blob);
1598 g_array_append_vals(tables_blob, u, len);
1599 }
1600
1601 /* RSDT is pointed to by RSDP */
1602 rsdt = tables_blob->len;
1603 build_rsdt(tables_blob, tables->linker, table_offsets);
1604
1605 /* RSDP is in FSEG memory, so allocate it separately */
1606 build_rsdp(tables->rsdp, tables->linker, rsdt);
1607
1608 /* We'll expose it all to Guest so we want to reduce
1609 * chance of size changes.
1610 *
1611 * We used to align the tables to 4k, but of course this would
1612 * too simple to be enough. 4k turned out to be too small an
1613 * alignment very soon, and in fact it is almost impossible to
1614 * keep the table size stable for all (max_cpus, max_memory_slots)
1615 * combinations. So the table size is always 64k for pc-i440fx-2.1
1616 * and we give an error if the table grows beyond that limit.
1617 *
1618 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1619 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1620 * than 2.0 and we can always pad the smaller tables with zeros. We can
1621 * then use the exact size of the 2.0 tables.
1622 *
1623 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1624 */
1625 if (guest_info->legacy_acpi_table_size) {
1626 /* Subtracting aml_len gives the size of fixed tables. Then add the
1627 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1628 */
1629 int legacy_aml_len =
1630 guest_info->legacy_acpi_table_size +
1631 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1632 int legacy_table_size =
1633 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1634 ACPI_BUILD_ALIGN_SIZE);
1635 if (tables_blob->len > legacy_table_size) {
1636 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1637 error_report("Warning: migration may not work.");
1638 }
1639 g_array_set_size(tables_blob, legacy_table_size);
1640 } else {
1641 /* Make sure we have a buffer in case we need to resize the tables. */
1642 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1643 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1644 error_report("Warning: ACPI tables are larger than 64k.");
1645 error_report("Warning: migration may not work.");
1646 error_report("Warning: please remove CPUs, NUMA nodes, "
1647 "memory slots or PCI bridges.");
1648 }
1649 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1650 }
1651
1652 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1653
1654 /* Cleanup memory that's no longer used. */
1655 g_array_free(table_offsets, true);
1656 }
1657
1658 static void acpi_ram_update(ram_addr_t ram, GArray *data)
1659 {
1660 uint32_t size = acpi_data_len(data);
1661
1662 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1663 qemu_ram_resize(ram, size, &error_abort);
1664
1665 memcpy(qemu_get_ram_ptr(ram), data->data, size);
1666 cpu_physical_memory_set_dirty_range_nocode(ram, size);
1667 }
1668
1669 static void acpi_build_update(void *build_opaque, uint32_t offset)
1670 {
1671 AcpiBuildState *build_state = build_opaque;
1672 AcpiBuildTables tables;
1673
1674 /* No state to update or already patched? Nothing to do. */
1675 if (!build_state || build_state->patched) {
1676 return;
1677 }
1678 build_state->patched = 1;
1679
1680 acpi_build_tables_init(&tables);
1681
1682 acpi_build(build_state->guest_info, &tables);
1683
1684 acpi_ram_update(build_state->table_ram, tables.table_data);
1685
1686 if (build_state->rsdp) {
1687 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1688 } else {
1689 acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
1690 }
1691
1692 acpi_ram_update(build_state->linker_ram, tables.linker);
1693 acpi_build_tables_cleanup(&tables, true);
1694 }
1695
1696 static void acpi_build_reset(void *build_opaque)
1697 {
1698 AcpiBuildState *build_state = build_opaque;
1699 build_state->patched = 0;
1700 }
1701
1702 static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
1703 const char *name, uint64_t max_size)
1704 {
1705 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1706 name, acpi_build_update, build_state);
1707 }
1708
1709 static const VMStateDescription vmstate_acpi_build = {
1710 .name = "acpi_build",
1711 .version_id = 1,
1712 .minimum_version_id = 1,
1713 .fields = (VMStateField[]) {
1714 VMSTATE_UINT8(patched, AcpiBuildState),
1715 VMSTATE_END_OF_LIST()
1716 },
1717 };
1718
1719 void acpi_setup(PcGuestInfo *guest_info)
1720 {
1721 AcpiBuildTables tables;
1722 AcpiBuildState *build_state;
1723
1724 if (!guest_info->fw_cfg) {
1725 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1726 return;
1727 }
1728
1729 if (!guest_info->has_acpi_build) {
1730 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1731 return;
1732 }
1733
1734 if (!acpi_enabled) {
1735 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1736 return;
1737 }
1738
1739 build_state = g_malloc0(sizeof *build_state);
1740
1741 build_state->guest_info = guest_info;
1742
1743 acpi_set_pci_info();
1744
1745 acpi_build_tables_init(&tables);
1746 acpi_build(build_state->guest_info, &tables);
1747
1748 /* Now expose it all to Guest */
1749 build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
1750 ACPI_BUILD_TABLE_FILE,
1751 ACPI_BUILD_TABLE_MAX_SIZE);
1752 assert(build_state->table_ram != RAM_ADDR_MAX);
1753
1754 build_state->linker_ram =
1755 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1756
1757 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1758 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1759
1760 if (!guest_info->rsdp_in_ram) {
1761 /*
1762 * Keep for compatibility with old machine types.
1763 * Though RSDP is small, its contents isn't immutable, so
1764 * we'll update it along with the rest of tables on guest access.
1765 */
1766 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1767
1768 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1769 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1770 acpi_build_update, build_state,
1771 build_state->rsdp, rsdp_size);
1772 build_state->rsdp_ram = (ram_addr_t)-1;
1773 } else {
1774 build_state->rsdp = NULL;
1775 build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
1776 ACPI_BUILD_RSDP_FILE, 0);
1777 }
1778
1779 qemu_register_reset(acpi_build_reset, build_state);
1780 acpi_build_reset(build_state);
1781 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1782
1783 /* Cleanup tables but don't free the memory: we track it
1784 * in build_state.
1785 */
1786 acpi_build_tables_cleanup(&tables, false);
1787 }
CRIS target port of Qemu