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pc: acpi: move COM devices from DSDT to SSDT
[qemu/cris-port.git] / hw / i386 / acpi-build.c
blobb0c82b6fe9a2eb585548d2918db56529b791993d
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "hw/mem/nvdimm.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/timer/hpet.h"
56
57 #include "hw/i386/q35-acpi-dsdt.hex"
58 #include "hw/i386/acpi-dsdt.hex"
59
60 #include "hw/acpi/aml-build.h"
61
62 #include "qapi/qmp/qint.h"
63 #include "qom/qom-qobject.h"
64
65 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
66 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
67 * a little bit, there should be plenty of free space since the DSDT
68 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
69 */
70 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
71 #define ACPI_BUILD_ALIGN_SIZE 0x1000
72
73 #define ACPI_BUILD_TABLE_SIZE 0x20000
74
75 /* #define DEBUG_ACPI_BUILD */
76 #ifdef DEBUG_ACPI_BUILD
77 #define ACPI_BUILD_DPRINTF(fmt, ...) \
78 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
79 #else
80 #define ACPI_BUILD_DPRINTF(fmt, ...)
81 #endif
82
83 typedef struct AcpiCpuInfo {
84 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
85 } AcpiCpuInfo;
86
87 typedef struct AcpiMcfgInfo {
88 uint64_t mcfg_base;
89 uint32_t mcfg_size;
90 } AcpiMcfgInfo;
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 uint16_t sci_int;
98 uint8_t acpi_enable_cmd;
99 uint8_t acpi_disable_cmd;
100 uint32_t gpe0_blk;
101 uint32_t gpe0_blk_len;
102 uint32_t io_base;
103 uint16_t cpu_hp_io_base;
104 uint16_t cpu_hp_io_len;
105 uint16_t mem_hp_io_base;
106 uint16_t mem_hp_io_len;
107 uint16_t pcihp_io_base;
108 uint16_t pcihp_io_len;
109 } AcpiPmInfo;
110
111 typedef struct AcpiMiscInfo {
112 bool has_hpet;
113 TPMVersion tpm_version;
114 const unsigned char *dsdt_code;
115 unsigned dsdt_size;
116 uint16_t pvpanic_port;
117 uint16_t applesmc_io_base;
118 } AcpiMiscInfo;
119
120 typedef struct AcpiBuildPciBusHotplugState {
121 GArray *device_table;
122 GArray *notify_table;
123 struct AcpiBuildPciBusHotplugState *parent;
124 bool pcihp_bridge_en;
125 } AcpiBuildPciBusHotplugState;
126
127 static void acpi_get_dsdt(AcpiMiscInfo *info)
128 {
129 Object *piix = piix4_pm_find();
130 Object *lpc = ich9_lpc_find();
131 assert(!!piix != !!lpc);
132
133 if (piix) {
134 info->dsdt_code = AcpiDsdtAmlCode;
135 info->dsdt_size = sizeof AcpiDsdtAmlCode;
136 }
137 if (lpc) {
138 info->dsdt_code = Q35AcpiDsdtAmlCode;
139 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
140 }
141 }
142
143 static
144 int acpi_add_cpu_info(Object *o, void *opaque)
145 {
146 AcpiCpuInfo *cpu = opaque;
147 uint64_t apic_id;
148
149 if (object_dynamic_cast(o, TYPE_CPU)) {
150 apic_id = object_property_get_int(o, "apic-id", NULL);
151 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
152
153 set_bit(apic_id, cpu->found_cpus);
154 }
155
156 object_child_foreach(o, acpi_add_cpu_info, opaque);
157 return 0;
158 }
159
160 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
161 {
162 Object *root = object_get_root();
163
164 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
165 object_child_foreach(root, acpi_add_cpu_info, cpu);
166 }
167
168 static void acpi_get_pm_info(AcpiPmInfo *pm)
169 {
170 Object *piix = piix4_pm_find();
171 Object *lpc = ich9_lpc_find();
172 Object *obj = NULL;
173 QObject *o;
174
175 pm->cpu_hp_io_base = 0;
176 pm->pcihp_io_base = 0;
177 pm->pcihp_io_len = 0;
178 if (piix) {
179 obj = piix;
180 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
181 pm->pcihp_io_base =
182 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
183 pm->pcihp_io_len =
184 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
185 }
186 if (lpc) {
187 obj = lpc;
188 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
189 }
190 assert(obj);
191
192 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
193 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
194 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
195
196 /* Fill in optional s3/s4 related properties */
197 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
198 if (o) {
199 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
200 } else {
201 pm->s3_disabled = false;
202 }
203 qobject_decref(o);
204 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
205 if (o) {
206 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
207 } else {
208 pm->s4_disabled = false;
209 }
210 qobject_decref(o);
211 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
212 if (o) {
213 pm->s4_val = qint_get_int(qobject_to_qint(o));
214 } else {
215 pm->s4_val = false;
216 }
217 qobject_decref(o);
218
219 /* Fill in mandatory properties */
220 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
221
222 pm->acpi_enable_cmd = object_property_get_int(obj,
223 ACPI_PM_PROP_ACPI_ENABLE_CMD,
224 NULL);
225 pm->acpi_disable_cmd = object_property_get_int(obj,
226 ACPI_PM_PROP_ACPI_DISABLE_CMD,
227 NULL);
228 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
229 NULL);
230 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
231 NULL);
232 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
233 NULL);
234 pm->pcihp_bridge_en =
235 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
236 NULL);
237 }
238
239 static void acpi_get_misc_info(AcpiMiscInfo *info)
240 {
241 info->has_hpet = hpet_find();
242 info->tpm_version = tpm_get_version();
243 info->pvpanic_port = pvpanic_port();
244 info->applesmc_io_base = applesmc_port();
245 }
246
247 /*
248 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
249 * On i386 arch we only have two pci hosts, so we can look only for them.
250 */
251 static Object *acpi_get_i386_pci_host(void)
252 {
253 PCIHostState *host;
254
255 host = OBJECT_CHECK(PCIHostState,
256 object_resolve_path("/machine/i440fx", NULL),
257 TYPE_PCI_HOST_BRIDGE);
258 if (!host) {
259 host = OBJECT_CHECK(PCIHostState,
260 object_resolve_path("/machine/q35", NULL),
261 TYPE_PCI_HOST_BRIDGE);
262 }
263
264 return OBJECT(host);
265 }
266
267 static void acpi_get_pci_info(PcPciInfo *info)
268 {
269 Object *pci_host;
270
271
272 pci_host = acpi_get_i386_pci_host();
273 g_assert(pci_host);
274
275 info->w32.begin = object_property_get_int(pci_host,
276 PCI_HOST_PROP_PCI_HOLE_START,
277 NULL);
278 info->w32.end = object_property_get_int(pci_host,
279 PCI_HOST_PROP_PCI_HOLE_END,
280 NULL);
281 info->w64.begin = object_property_get_int(pci_host,
282 PCI_HOST_PROP_PCI_HOLE64_START,
283 NULL);
284 info->w64.end = object_property_get_int(pci_host,
285 PCI_HOST_PROP_PCI_HOLE64_END,
286 NULL);
287 }
288
289 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
290
291 static void acpi_align_size(GArray *blob, unsigned align)
292 {
293 /* Align size to multiple of given size. This reduces the chance
294 * we need to change size in the future (breaking cross version migration).
295 */
296 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
297 }
298
299 /* FACS */
300 static void
301 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
302 {
303 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
304 memcpy(&facs->signature, "FACS", 4);
305 facs->length = cpu_to_le32(sizeof(*facs));
306 }
307
308 /* Load chipset information in FADT */
309 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
310 {
311 fadt->model = 1;
312 fadt->reserved1 = 0;
313 fadt->sci_int = cpu_to_le16(pm->sci_int);
314 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
315 fadt->acpi_enable = pm->acpi_enable_cmd;
316 fadt->acpi_disable = pm->acpi_disable_cmd;
317 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
318 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
319 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
320 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
321 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
322 /* EVT, CNT, TMR length matches hw/acpi/core.c */
323 fadt->pm1_evt_len = 4;
324 fadt->pm1_cnt_len = 2;
325 fadt->pm_tmr_len = 4;
326 fadt->gpe0_blk_len = pm->gpe0_blk_len;
327 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
328 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
329 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
330 (1 << ACPI_FADT_F_PROC_C1) |
331 (1 << ACPI_FADT_F_SLP_BUTTON) |
332 (1 << ACPI_FADT_F_RTC_S4));
333 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
334 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
335 * For more than 8 CPUs, "Clustered Logical" mode has to be used
336 */
337 if (max_cpus > 8) {
338 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
339 }
340 fadt->century = RTC_CENTURY;
341 }
342
343
344 /* FADT */
345 static void
346 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
347 unsigned facs, unsigned dsdt)
348 {
349 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
350
351 fadt->firmware_ctrl = cpu_to_le32(facs);
352 /* FACS address to be filled by Guest linker */
353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
354 ACPI_BUILD_TABLE_FILE,
355 table_data, &fadt->firmware_ctrl,
356 sizeof fadt->firmware_ctrl);
357
358 fadt->dsdt = cpu_to_le32(dsdt);
359 /* DSDT address to be filled by Guest linker */
360 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
361 ACPI_BUILD_TABLE_FILE,
362 table_data, &fadt->dsdt,
363 sizeof fadt->dsdt);
364
365 fadt_setup(fadt, pm);
366
367 build_header(linker, table_data,
368 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL);
369 }
370
371 static void
372 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
373 PcGuestInfo *guest_info)
374 {
375 int madt_start = table_data->len;
376
377 AcpiMultipleApicTable *madt;
378 AcpiMadtIoApic *io_apic;
379 AcpiMadtIntsrcovr *intsrcovr;
380 AcpiMadtLocalNmi *local_nmi;
381 int i;
382
383 madt = acpi_data_push(table_data, sizeof *madt);
384 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
385 madt->flags = cpu_to_le32(1);
386
387 for (i = 0; i < guest_info->apic_id_limit; i++) {
388 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
389 apic->type = ACPI_APIC_PROCESSOR;
390 apic->length = sizeof(*apic);
391 apic->processor_id = i;
392 apic->local_apic_id = i;
393 if (test_bit(i, cpu->found_cpus)) {
394 apic->flags = cpu_to_le32(1);
395 } else {
396 apic->flags = cpu_to_le32(0);
397 }
398 }
399 io_apic = acpi_data_push(table_data, sizeof *io_apic);
400 io_apic->type = ACPI_APIC_IO;
401 io_apic->length = sizeof(*io_apic);
402 #define ACPI_BUILD_IOAPIC_ID 0x0
403 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
404 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
405 io_apic->interrupt = cpu_to_le32(0);
406
407 if (guest_info->apic_xrupt_override) {
408 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
409 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
410 intsrcovr->length = sizeof(*intsrcovr);
411 intsrcovr->source = 0;
412 intsrcovr->gsi = cpu_to_le32(2);
413 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
414 }
415 for (i = 1; i < 16; i++) {
416 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
417 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
418 /* No need for a INT source override structure. */
419 continue;
420 }
421 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
422 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
423 intsrcovr->length = sizeof(*intsrcovr);
424 intsrcovr->source = i;
425 intsrcovr->gsi = cpu_to_le32(i);
426 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
427 }
428
429 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
430 local_nmi->type = ACPI_APIC_LOCAL_NMI;
431 local_nmi->length = sizeof(*local_nmi);
432 local_nmi->processor_id = 0xff; /* all processors */
433 local_nmi->flags = cpu_to_le16(0);
434 local_nmi->lint = 1; /* ACPI_LINT1 */
435
436 build_header(linker, table_data,
437 (void *)(table_data->data + madt_start), "APIC",
438 table_data->len - madt_start, 1, NULL);
439 }
440
441 /* Assign BSEL property to all buses. In the future, this can be changed
442 * to only assign to buses that support hotplug.
443 */
444 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
445 {
446 unsigned *bsel_alloc = opaque;
447 unsigned *bus_bsel;
448
449 if (qbus_is_hotpluggable(BUS(bus))) {
450 bus_bsel = g_malloc(sizeof *bus_bsel);
451
452 *bus_bsel = (*bsel_alloc)++;
453 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
454 bus_bsel, NULL);
455 }
456
457 return bsel_alloc;
458 }
459
460 static void acpi_set_pci_info(void)
461 {
462 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
463 unsigned bsel_alloc = 0;
464
465 if (bus) {
466 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
467 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
468 }
469 }
470
471 static void build_append_pcihp_notify_entry(Aml *method, int slot)
472 {
473 Aml *if_ctx;
474 int32_t devfn = PCI_DEVFN(slot, 0);
475
476 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
477 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
478 aml_append(method, if_ctx);
479 }
480
481 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
482 bool pcihp_bridge_en)
483 {
484 Aml *dev, *notify_method, *method;
485 QObject *bsel;
486 PCIBus *sec;
487 int i;
488
489 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
490 if (bsel) {
491 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
492
493 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
494 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
495 }
496
497 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
498 DeviceClass *dc;
499 PCIDeviceClass *pc;
500 PCIDevice *pdev = bus->devices[i];
501 int slot = PCI_SLOT(i);
502 bool hotplug_enabled_dev;
503 bool bridge_in_acpi;
504
505 if (!pdev) {
506 if (bsel) { /* add hotplug slots for non present devices */
507 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
508 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
509 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
510 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
511 aml_append(method,
512 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
513 );
514 aml_append(dev, method);
515 aml_append(parent_scope, dev);
516
517 build_append_pcihp_notify_entry(notify_method, slot);
518 }
519 continue;
520 }
521
522 pc = PCI_DEVICE_GET_CLASS(pdev);
523 dc = DEVICE_GET_CLASS(pdev);
524
525 /* When hotplug for bridges is enabled, bridges are
526 * described in ACPI separately (see build_pci_bus_end).
527 * In this case they aren't themselves hot-pluggable.
528 * Hotplugged bridges *are* hot-pluggable.
529 */
530 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
531 !DEVICE(pdev)->hotplugged;
532
533 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
534
535 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
536 continue;
537 }
538
539 /* start to compose PCI slot descriptor */
540 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
541 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
542
543 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
544 /* add VGA specific AML methods */
545 int s3d;
546
547 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
548 s3d = 3;
549 } else {
550 s3d = 0;
551 }
552
553 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
554 aml_append(method, aml_return(aml_int(0)));
555 aml_append(dev, method);
556
557 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
558 aml_append(method, aml_return(aml_int(0)));
559 aml_append(dev, method);
560
561 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
562 aml_append(method, aml_return(aml_int(s3d)));
563 aml_append(dev, method);
564 } else if (hotplug_enabled_dev) {
565 /* add _SUN/_EJ0 to make slot hotpluggable */
566 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
567
568 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
569 aml_append(method,
570 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
571 );
572 aml_append(dev, method);
573
574 if (bsel) {
575 build_append_pcihp_notify_entry(notify_method, slot);
576 }
577 } else if (bridge_in_acpi) {
578 /*
579 * device is coldplugged bridge,
580 * add child device descriptions into its scope
581 */
582 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
583
584 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
585 }
586 /* slot descriptor has been composed, add it into parent context */
587 aml_append(parent_scope, dev);
588 }
589
590 if (bsel) {
591 aml_append(parent_scope, notify_method);
592 }
593
594 /* Append PCNT method to notify about events on local and child buses.
595 * Add unconditionally for root since DSDT expects it.
596 */
597 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
598
599 /* If bus supports hotplug select it and notify about local events */
600 if (bsel) {
601 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
602 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
603 aml_append(method,
604 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
605 );
606 aml_append(method,
607 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
608 );
609 }
610
611 /* Notify about child bus events in any case */
612 if (pcihp_bridge_en) {
613 QLIST_FOREACH(sec, &bus->child, sibling) {
614 int32_t devfn = sec->parent_dev->devfn;
615
616 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
617 }
618 }
619 aml_append(parent_scope, method);
620 qobject_decref(bsel);
621 }
622
623 /*
624 * initialize_route - Initialize the interrupt routing rule
625 * through a specific LINK:
626 * if (lnk_idx == idx)
627 * route using link 'link_name'
628 */
629 static Aml *initialize_route(Aml *route, const char *link_name,
630 Aml *lnk_idx, int idx)
631 {
632 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
633 Aml *pkg = aml_package(4);
634
635 aml_append(pkg, aml_int(0));
636 aml_append(pkg, aml_int(0));
637 aml_append(pkg, aml_name("%s", link_name));
638 aml_append(pkg, aml_int(0));
639 aml_append(if_ctx, aml_store(pkg, route));
640
641 return if_ctx;
642 }
643
644 /*
645 * build_prt - Define interrupt rounting rules
646 *
647 * Returns an array of 128 routes, one for each device,
648 * based on device location.
649 * The main goal is to equaly distribute the interrupts
650 * over the 4 existing ACPI links (works only for i440fx).
651 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
652 *
653 */
654 static Aml *build_prt(void)
655 {
656 Aml *method, *while_ctx, *pin, *res;
657
658 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
659 res = aml_local(0);
660 pin = aml_local(1);
661 aml_append(method, aml_store(aml_package(128), res));
662 aml_append(method, aml_store(aml_int(0), pin));
663
664 /* while (pin < 128) */
665 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
666 {
667 Aml *slot = aml_local(2);
668 Aml *lnk_idx = aml_local(3);
669 Aml *route = aml_local(4);
670
671 /* slot = pin >> 2 */
672 aml_append(while_ctx,
673 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
674 /* lnk_idx = (slot + pin) & 3 */
675 aml_append(while_ctx,
676 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
677 lnk_idx));
678
679 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
680 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
681 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
682 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
683 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
684
685 /* route[0] = 0x[slot]FFFF */
686 aml_append(while_ctx,
687 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
688 NULL),
689 aml_index(route, aml_int(0))));
690 /* route[1] = pin & 3 */
691 aml_append(while_ctx,
692 aml_store(aml_and(pin, aml_int(3), NULL),
693 aml_index(route, aml_int(1))));
694 /* res[pin] = route */
695 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
696 /* pin++ */
697 aml_append(while_ctx, aml_increment(pin));
698 }
699 aml_append(method, while_ctx);
700 /* return res*/
701 aml_append(method, aml_return(res));
702
703 return method;
704 }
705
706 typedef struct CrsRangeEntry {
707 uint64_t base;
708 uint64_t limit;
709 } CrsRangeEntry;
710
711 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
712 {
713 CrsRangeEntry *entry;
714
715 entry = g_malloc(sizeof(*entry));
716 entry->base = base;
717 entry->limit = limit;
718
719 g_ptr_array_add(ranges, entry);
720 }
721
722 static void crs_range_free(gpointer data)
723 {
724 CrsRangeEntry *entry = (CrsRangeEntry *)data;
725 g_free(entry);
726 }
727
728 static gint crs_range_compare(gconstpointer a, gconstpointer b)
729 {
730 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
731 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
732
733 return (int64_t)entry_a->base - (int64_t)entry_b->base;
734 }
735
736 /*
737 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
738 * interval, computes the 'free' ranges from the same interval.
739 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
740 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
741 */
742 static void crs_replace_with_free_ranges(GPtrArray *ranges,
743 uint64_t start, uint64_t end)
744 {
745 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
746 uint64_t free_base = start;
747 int i;
748
749 g_ptr_array_sort(ranges, crs_range_compare);
750 for (i = 0; i < ranges->len; i++) {
751 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
752
753 if (free_base < used->base) {
754 crs_range_insert(free_ranges, free_base, used->base - 1);
755 }
756
757 free_base = used->limit + 1;
758 }
759
760 if (free_base < end) {
761 crs_range_insert(free_ranges, free_base, end);
762 }
763
764 g_ptr_array_set_size(ranges, 0);
765 for (i = 0; i < free_ranges->len; i++) {
766 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
767 }
768
769 g_ptr_array_free(free_ranges, false);
770 }
771
772 /*
773 * crs_range_merge - merges adjacent ranges in the given array.
774 * Array elements are deleted and replaced with the merged ranges.
775 */
776 static void crs_range_merge(GPtrArray *range)
777 {
778 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
779 CrsRangeEntry *entry;
780 uint64_t range_base, range_limit;
781 int i;
782
783 if (!range->len) {
784 return;
785 }
786
787 g_ptr_array_sort(range, crs_range_compare);
788
789 entry = g_ptr_array_index(range, 0);
790 range_base = entry->base;
791 range_limit = entry->limit;
792 for (i = 1; i < range->len; i++) {
793 entry = g_ptr_array_index(range, i);
794 if (entry->base - 1 == range_limit) {
795 range_limit = entry->limit;
796 } else {
797 crs_range_insert(tmp, range_base, range_limit);
798 range_base = entry->base;
799 range_limit = entry->limit;
800 }
801 }
802 crs_range_insert(tmp, range_base, range_limit);
803
804 g_ptr_array_set_size(range, 0);
805 for (i = 0; i < tmp->len; i++) {
806 entry = g_ptr_array_index(tmp, i);
807 crs_range_insert(range, entry->base, entry->limit);
808 }
809 g_ptr_array_free(tmp, true);
810 }
811
812 static Aml *build_crs(PCIHostState *host,
813 GPtrArray *io_ranges, GPtrArray *mem_ranges)
814 {
815 Aml *crs = aml_resource_template();
816 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
817 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
818 CrsRangeEntry *entry;
819 uint8_t max_bus = pci_bus_num(host->bus);
820 uint8_t type;
821 int devfn;
822 int i;
823
824 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
825 uint64_t range_base, range_limit;
826 PCIDevice *dev = host->bus->devices[devfn];
827
828 if (!dev) {
829 continue;
830 }
831
832 for (i = 0; i < PCI_NUM_REGIONS; i++) {
833 PCIIORegion *r = &dev->io_regions[i];
834
835 range_base = r->addr;
836 range_limit = r->addr + r->size - 1;
837
838 /*
839 * Work-around for old bioses
840 * that do not support multiple root buses
841 */
842 if (!range_base || range_base > range_limit) {
843 continue;
844 }
845
846 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
847 crs_range_insert(host_io_ranges, range_base, range_limit);
848 } else { /* "memory" */
849 crs_range_insert(host_mem_ranges, range_base, range_limit);
850 }
851 }
852
853 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
854 if (type == PCI_HEADER_TYPE_BRIDGE) {
855 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
856 if (subordinate > max_bus) {
857 max_bus = subordinate;
858 }
859
860 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
861 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
862
863 /*
864 * Work-around for old bioses
865 * that do not support multiple root buses
866 */
867 if (range_base && range_base <= range_limit) {
868 crs_range_insert(host_io_ranges, range_base, range_limit);
869 }
870
871 range_base =
872 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
873 range_limit =
874 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
875
876 /*
877 * Work-around for old bioses
878 * that do not support multiple root buses
879 */
880 if (range_base && range_base <= range_limit) {
881 crs_range_insert(host_mem_ranges, range_base, range_limit);
882 }
883
884 range_base =
885 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
886 range_limit =
887 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
888
889 /*
890 * Work-around for old bioses
891 * that do not support multiple root buses
892 */
893 if (range_base && range_base <= range_limit) {
894 crs_range_insert(host_mem_ranges, range_base, range_limit);
895 }
896 }
897 }
898
899 crs_range_merge(host_io_ranges);
900 for (i = 0; i < host_io_ranges->len; i++) {
901 entry = g_ptr_array_index(host_io_ranges, i);
902 aml_append(crs,
903 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
904 AML_POS_DECODE, AML_ENTIRE_RANGE,
905 0, entry->base, entry->limit, 0,
906 entry->limit - entry->base + 1));
907 crs_range_insert(io_ranges, entry->base, entry->limit);
908 }
909 g_ptr_array_free(host_io_ranges, true);
910
911 crs_range_merge(host_mem_ranges);
912 for (i = 0; i < host_mem_ranges->len; i++) {
913 entry = g_ptr_array_index(host_mem_ranges, i);
914 aml_append(crs,
915 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
916 AML_MAX_FIXED, AML_NON_CACHEABLE,
917 AML_READ_WRITE,
918 0, entry->base, entry->limit, 0,
919 entry->limit - entry->base + 1));
920 crs_range_insert(mem_ranges, entry->base, entry->limit);
921 }
922 g_ptr_array_free(host_mem_ranges, true);
923
924 aml_append(crs,
925 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
926 0,
927 pci_bus_num(host->bus),
928 max_bus,
929 0,
930 max_bus - pci_bus_num(host->bus) + 1));
931
932 return crs;
933 }
934
935 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
936 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
937 {
938 int i;
939 Aml *dev;
940 Aml *crs;
941 Aml *pkg;
942 Aml *field;
943 Aml *ifctx;
944 Aml *method;
945
946 /* The current AML generator can cover the APIC ID range [0..255],
947 * inclusive, for VCPU hotplug. */
948 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
949 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
950
951 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
952 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
953 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
954 aml_append(dev,
955 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
956 );
957 /* device present, functioning, decoding, not shown in UI */
958 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
959 crs = aml_resource_template();
960 aml_append(crs,
961 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
962 pm->cpu_hp_io_len)
963 );
964 aml_append(dev, aml_name_decl("_CRS", crs));
965 aml_append(sb_scope, dev);
966 /* declare CPU hotplug MMIO region and PRS field to access it */
967 aml_append(sb_scope, aml_operation_region(
968 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
969 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
970 aml_append(field, aml_named_field("PRS", 256));
971 aml_append(sb_scope, field);
972
973 /* build Processor object for each processor */
974 for (i = 0; i < acpi_cpus; i++) {
975 dev = aml_processor(i, 0, 0, "CP%.02X", i);
976
977 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
978 aml_append(method,
979 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
980 aml_append(dev, method);
981
982 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
983 aml_append(method,
984 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
985 aml_append(dev, method);
986
987 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
988 aml_append(method,
989 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
990 );
991 aml_append(dev, method);
992
993 aml_append(sb_scope, dev);
994 }
995
996 /* build this code:
997 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
998 */
999 /* Arg0 = Processor ID = APIC ID */
1000 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1001 for (i = 0; i < acpi_cpus; i++) {
1002 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1003 aml_append(ifctx,
1004 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1005 );
1006 aml_append(method, ifctx);
1007 }
1008 aml_append(sb_scope, method);
1009
1010 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1011 *
1012 * Note: The ability to create variable-sized packages was first
1013 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1014 * ith up to 255 elements. Windows guests up to win2k8 fail when
1015 * VarPackageOp is used.
1016 */
1017 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1018 aml_varpackage(acpi_cpus);
1019
1020 for (i = 0; i < acpi_cpus; i++) {
1021 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1022 aml_append(pkg, aml_int(b));
1023 }
1024 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1025 }
1026
1027 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1028 uint16_t io_base, uint16_t io_len)
1029 {
1030 int i;
1031 Aml *scope;
1032 Aml *crs;
1033 Aml *field;
1034 Aml *dev;
1035 Aml *method;
1036 Aml *ifctx;
1037
1038 /* build memory devices */
1039 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1040 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1041 aml_append(scope,
1042 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1043 );
1044
1045 crs = aml_resource_template();
1046 aml_append(crs,
1047 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1048 );
1049 aml_append(scope, aml_name_decl("_CRS", crs));
1050
1051 aml_append(scope, aml_operation_region(
1052 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1053 io_base, io_len)
1054 );
1055
1056 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1057 AML_NOLOCK, AML_PRESERVE);
1058 aml_append(field, /* read only */
1059 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1060 aml_append(field, /* read only */
1061 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1062 aml_append(field, /* read only */
1063 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1064 aml_append(field, /* read only */
1065 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1066 aml_append(field, /* read only */
1067 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1068 aml_append(scope, field);
1069
1070 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1071 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1072 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1073 aml_append(field, /* 1 if enabled, read only */
1074 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1075 aml_append(field,
1076 /*(read) 1 if has a insert event. (write) 1 to clear event */
1077 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1078 aml_append(field,
1079 /* (read) 1 if has a remove event. (write) 1 to clear event */
1080 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1081 aml_append(field,
1082 /* initiates device eject, write only */
1083 aml_named_field(MEMORY_SLOT_EJECT, 1));
1084 aml_append(scope, field);
1085
1086 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1087 AML_NOLOCK, AML_PRESERVE);
1088 aml_append(field, /* DIMM selector, write only */
1089 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1090 aml_append(field, /* _OST event code, write only */
1091 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1092 aml_append(field, /* _OST status code, write only */
1093 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1094 aml_append(scope, field);
1095 aml_append(sb_scope, scope);
1096
1097 for (i = 0; i < nr_mem; i++) {
1098 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1099 const char *s;
1100
1101 dev = aml_device("MP%02X", i);
1102 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1103 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1104
1105 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1106 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1107 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1108 aml_append(dev, method);
1109
1110 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1111 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1112 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1113 aml_append(dev, method);
1114
1115 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1116 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1117 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1118 aml_append(dev, method);
1119
1120 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1121 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1122
1123 aml_append(method, aml_return(aml_call4(
1124 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1125 )));
1126 aml_append(dev, method);
1127
1128 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1129 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1130 aml_append(method, aml_return(aml_call2(
1131 s, aml_name("_UID"), aml_arg(0))));
1132 aml_append(dev, method);
1133
1134 aml_append(sb_scope, dev);
1135 }
1136
1137 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1138 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1139 */
1140 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1141 for (i = 0; i < nr_mem; i++) {
1142 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1143 aml_append(ifctx,
1144 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1145 );
1146 aml_append(method, ifctx);
1147 }
1148 aml_append(sb_scope, method);
1149 }
1150
1151 static void build_hpet_aml(Aml *table)
1152 {
1153 Aml *crs;
1154 Aml *field;
1155 Aml *method;
1156 Aml *if_ctx;
1157 Aml *scope = aml_scope("_SB");
1158 Aml *dev = aml_device("HPET");
1159 Aml *zero = aml_int(0);
1160 Aml *id = aml_local(0);
1161 Aml *period = aml_local(1);
1162
1163 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1164 aml_append(dev, aml_name_decl("_UID", zero));
1165
1166 aml_append(dev,
1167 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, HPET_BASE, HPET_LEN));
1168 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1169 aml_append(field, aml_named_field("VEND", 32));
1170 aml_append(field, aml_named_field("PRD", 32));
1171 aml_append(dev, field);
1172
1173 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1174 aml_append(method, aml_store(aml_name("VEND"), id));
1175 aml_append(method, aml_store(aml_name("PRD"), period));
1176 aml_append(method, aml_shiftright(id, aml_int(16), id));
1177 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1178 aml_equal(id, aml_int(0xffff))));
1179 {
1180 aml_append(if_ctx, aml_return(zero));
1181 }
1182 aml_append(method, if_ctx);
1183
1184 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1185 aml_lgreater(period, aml_int(100000000))));
1186 {
1187 aml_append(if_ctx, aml_return(zero));
1188 }
1189 aml_append(method, if_ctx);
1190
1191 aml_append(method, aml_return(aml_int(0x0F)));
1192 aml_append(dev, method);
1193
1194 crs = aml_resource_template();
1195 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1196 aml_append(dev, aml_name_decl("_CRS", crs));
1197
1198 aml_append(scope, dev);
1199 aml_append(table, scope);
1200 }
1201
1202 static Aml *build_fdc_device_aml(void)
1203 {
1204 Aml *dev;
1205 Aml *crs;
1206 Aml *method;
1207 Aml *if_ctx;
1208 Aml *else_ctx;
1209 Aml *zero = aml_int(0);
1210 Aml *is_present = aml_local(0);
1211
1212 dev = aml_device("FDC0");
1213 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1214
1215 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1216 aml_append(method, aml_store(aml_name("FDEN"), is_present));
1217 if_ctx = aml_if(aml_equal(is_present, zero));
1218 {
1219 aml_append(if_ctx, aml_return(aml_int(0x00)));
1220 }
1221 aml_append(method, if_ctx);
1222 else_ctx = aml_else();
1223 {
1224 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1225 }
1226 aml_append(method, else_ctx);
1227 aml_append(dev, method);
1228
1229 crs = aml_resource_template();
1230 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1231 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1232 aml_append(crs, aml_irq_no_flags(6));
1233 aml_append(crs,
1234 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1235 aml_append(dev, aml_name_decl("_CRS", crs));
1236
1237 return dev;
1238 }
1239
1240 static Aml *build_rtc_device_aml(void)
1241 {
1242 Aml *dev;
1243 Aml *crs;
1244
1245 dev = aml_device("RTC");
1246 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1247 crs = aml_resource_template();
1248 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1249 aml_append(crs, aml_irq_no_flags(8));
1250 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1251 aml_append(dev, aml_name_decl("_CRS", crs));
1252
1253 return dev;
1254 }
1255
1256 static Aml *build_kbd_device_aml(void)
1257 {
1258 Aml *dev;
1259 Aml *crs;
1260 Aml *method;
1261
1262 dev = aml_device("KBD");
1263 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1264
1265 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1266 aml_append(method, aml_return(aml_int(0x0f)));
1267 aml_append(dev, method);
1268
1269 crs = aml_resource_template();
1270 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1271 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1272 aml_append(crs, aml_irq_no_flags(1));
1273 aml_append(dev, aml_name_decl("_CRS", crs));
1274
1275 return dev;
1276 }
1277
1278 static Aml *build_mouse_device_aml(void)
1279 {
1280 Aml *dev;
1281 Aml *crs;
1282 Aml *method;
1283
1284 dev = aml_device("MOU");
1285 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1286
1287 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1288 aml_append(method, aml_return(aml_int(0x0f)));
1289 aml_append(dev, method);
1290
1291 crs = aml_resource_template();
1292 aml_append(crs, aml_irq_no_flags(12));
1293 aml_append(dev, aml_name_decl("_CRS", crs));
1294
1295 return dev;
1296 }
1297
1298 static Aml *build_lpt_device_aml(void)
1299 {
1300 Aml *dev;
1301 Aml *crs;
1302 Aml *method;
1303 Aml *if_ctx;
1304 Aml *else_ctx;
1305 Aml *zero = aml_int(0);
1306 Aml *is_present = aml_local(0);
1307
1308 dev = aml_device("LPT");
1309 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1310
1311 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1312 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1313 if_ctx = aml_if(aml_equal(is_present, zero));
1314 {
1315 aml_append(if_ctx, aml_return(aml_int(0x00)));
1316 }
1317 aml_append(method, if_ctx);
1318 else_ctx = aml_else();
1319 {
1320 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1321 }
1322 aml_append(method, else_ctx);
1323 aml_append(dev, method);
1324
1325 crs = aml_resource_template();
1326 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1327 aml_append(crs, aml_irq_no_flags(7));
1328 aml_append(dev, aml_name_decl("_CRS", crs));
1329
1330 return dev;
1331 }
1332
1333 static Aml *build_com_device_aml(uint8_t uid)
1334 {
1335 Aml *dev;
1336 Aml *crs;
1337 Aml *method;
1338 Aml *if_ctx;
1339 Aml *else_ctx;
1340 Aml *zero = aml_int(0);
1341 Aml *is_present = aml_local(0);
1342 const char *enabled_field = "CAEN";
1343 uint8_t irq = 4;
1344 uint16_t io_port = 0x03F8;
1345
1346 assert(uid == 1 || uid == 2);
1347 if (uid == 2) {
1348 enabled_field = "CBEN";
1349 irq = 3;
1350 io_port = 0x02F8;
1351 }
1352
1353 dev = aml_device("COM%d", uid);
1354 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1355 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1356
1357 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1358 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1359 if_ctx = aml_if(aml_equal(is_present, zero));
1360 {
1361 aml_append(if_ctx, aml_return(aml_int(0x00)));
1362 }
1363 aml_append(method, if_ctx);
1364 else_ctx = aml_else();
1365 {
1366 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1367 }
1368 aml_append(method, else_ctx);
1369 aml_append(dev, method);
1370
1371 crs = aml_resource_template();
1372 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1373 aml_append(crs, aml_irq_no_flags(irq));
1374 aml_append(dev, aml_name_decl("_CRS", crs));
1375
1376 return dev;
1377 }
1378
1379 static void build_isa_devices_aml(Aml *table)
1380 {
1381 Aml *scope = aml_scope("_SB.PCI0.ISA");
1382
1383 aml_append(scope, build_rtc_device_aml());
1384 aml_append(scope, build_kbd_device_aml());
1385 aml_append(scope, build_mouse_device_aml());
1386 aml_append(scope, build_fdc_device_aml());
1387 aml_append(scope, build_lpt_device_aml());
1388 aml_append(scope, build_com_device_aml(1));
1389 aml_append(scope, build_com_device_aml(2));
1390
1391 aml_append(table, scope);
1392 }
1393
1394 static void build_dbg_aml(Aml *table)
1395 {
1396 Aml *field;
1397 Aml *method;
1398 Aml *while_ctx;
1399 Aml *scope = aml_scope("\\");
1400 Aml *buf = aml_local(0);
1401 Aml *len = aml_local(1);
1402 Aml *idx = aml_local(2);
1403
1404 aml_append(scope,
1405 aml_operation_region("DBG", AML_SYSTEM_IO, 0x0402, 0x01));
1406 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1407 aml_append(field, aml_named_field("DBGB", 8));
1408 aml_append(scope, field);
1409
1410 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1411
1412 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1413 aml_append(method, aml_to_buffer(buf, buf));
1414 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1415 aml_append(method, aml_store(aml_int(0), idx));
1416
1417 while_ctx = aml_while(aml_lless(idx, len));
1418 aml_append(while_ctx,
1419 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1420 aml_append(while_ctx, aml_increment(idx));
1421 aml_append(method, while_ctx);
1422
1423 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1424 aml_append(scope, method);
1425
1426 aml_append(table, scope);
1427 }
1428
1429 static void
1430 build_ssdt(GArray *table_data, GArray *linker,
1431 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
1432 PcPciInfo *pci, PcGuestInfo *guest_info)
1433 {
1434 MachineState *machine = MACHINE(qdev_get_machine());
1435 uint32_t nr_mem = machine->ram_slots;
1436 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field;
1437 PCIBus *bus = NULL;
1438 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1439 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1440 CrsRangeEntry *entry;
1441 int root_bus_limit = 0xFF;
1442 int i;
1443
1444 ssdt = init_aml_allocator();
1445
1446 /* Reserve space for header */
1447 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
1448
1449 build_dbg_aml(ssdt);
1450 build_hpet_aml(ssdt);
1451 build_isa_devices_aml(ssdt);
1452 build_cpu_hotplug_aml(ssdt);
1453 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
1454 pm->mem_hp_io_len);
1455
1456 scope = aml_scope("\\_GPE");
1457 {
1458 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
1459 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
1460 aml_append(scope, method);
1461
1462 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1463 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1464 aml_append(scope, method);
1465 }
1466 aml_append(ssdt, scope);
1467
1468 bus = PC_MACHINE(machine)->bus;
1469 if (bus) {
1470 QLIST_FOREACH(bus, &bus->child, sibling) {
1471 uint8_t bus_num = pci_bus_num(bus);
1472 uint8_t numa_node = pci_bus_numa_node(bus);
1473
1474 /* look only for expander root buses */
1475 if (!pci_bus_is_root(bus)) {
1476 continue;
1477 }
1478
1479 if (bus_num < root_bus_limit) {
1480 root_bus_limit = bus_num - 1;
1481 }
1482
1483 scope = aml_scope("\\_SB");
1484 dev = aml_device("PC%.02X", bus_num);
1485 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1486 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1487 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1488
1489 if (numa_node != NUMA_NODE_UNASSIGNED) {
1490 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1491 }
1492
1493 aml_append(dev, build_prt());
1494 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
1495 io_ranges, mem_ranges);
1496 aml_append(dev, aml_name_decl("_CRS", crs));
1497 aml_append(scope, dev);
1498 aml_append(ssdt, scope);
1499 }
1500 }
1501
1502 scope = aml_scope("\\_SB.PCI0");
1503 /* build PCI0._CRS */
1504 crs = aml_resource_template();
1505 aml_append(crs,
1506 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1507 0x0000, 0x0, root_bus_limit,
1508 0x0000, root_bus_limit + 1));
1509 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1510
1511 aml_append(crs,
1512 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1513 AML_POS_DECODE, AML_ENTIRE_RANGE,
1514 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1515
1516 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
1517 for (i = 0; i < io_ranges->len; i++) {
1518 entry = g_ptr_array_index(io_ranges, i);
1519 aml_append(crs,
1520 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1521 AML_POS_DECODE, AML_ENTIRE_RANGE,
1522 0x0000, entry->base, entry->limit,
1523 0x0000, entry->limit - entry->base + 1));
1524 }
1525
1526 aml_append(crs,
1527 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1528 AML_CACHEABLE, AML_READ_WRITE,
1529 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1530
1531 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
1532 for (i = 0; i < mem_ranges->len; i++) {
1533 entry = g_ptr_array_index(mem_ranges, i);
1534 aml_append(crs,
1535 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1536 AML_NON_CACHEABLE, AML_READ_WRITE,
1537 0, entry->base, entry->limit,
1538 0, entry->limit - entry->base + 1));
1539 }
1540
1541 if (pci->w64.begin) {
1542 aml_append(crs,
1543 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1544 AML_CACHEABLE, AML_READ_WRITE,
1545 0, pci->w64.begin, pci->w64.end - 1, 0,
1546 pci->w64.end - pci->w64.begin));
1547 }
1548 aml_append(scope, aml_name_decl("_CRS", crs));
1549
1550 /* reserve GPE0 block resources */
1551 dev = aml_device("GPE0");
1552 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1553 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1554 /* device present, functioning, decoding, not shown in UI */
1555 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1556 crs = aml_resource_template();
1557 aml_append(crs,
1558 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1559 );
1560 aml_append(dev, aml_name_decl("_CRS", crs));
1561 aml_append(scope, dev);
1562
1563 g_ptr_array_free(io_ranges, true);
1564 g_ptr_array_free(mem_ranges, true);
1565
1566 /* reserve PCIHP resources */
1567 if (pm->pcihp_io_len) {
1568 dev = aml_device("PHPR");
1569 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1570 aml_append(dev,
1571 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1572 /* device present, functioning, decoding, not shown in UI */
1573 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1574 crs = aml_resource_template();
1575 aml_append(crs,
1576 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1577 pm->pcihp_io_len)
1578 );
1579 aml_append(dev, aml_name_decl("_CRS", crs));
1580 aml_append(scope, dev);
1581 }
1582 aml_append(ssdt, scope);
1583
1584 /* create S3_ / S4_ / S5_ packages if necessary */
1585 scope = aml_scope("\\");
1586 if (!pm->s3_disabled) {
1587 pkg = aml_package(4);
1588 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1589 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1590 aml_append(pkg, aml_int(0)); /* reserved */
1591 aml_append(pkg, aml_int(0)); /* reserved */
1592 aml_append(scope, aml_name_decl("_S3", pkg));
1593 }
1594
1595 if (!pm->s4_disabled) {
1596 pkg = aml_package(4);
1597 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1598 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1599 aml_append(pkg, aml_int(pm->s4_val));
1600 aml_append(pkg, aml_int(0)); /* reserved */
1601 aml_append(pkg, aml_int(0)); /* reserved */
1602 aml_append(scope, aml_name_decl("_S4", pkg));
1603 }
1604
1605 pkg = aml_package(4);
1606 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1607 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1608 aml_append(pkg, aml_int(0)); /* reserved */
1609 aml_append(pkg, aml_int(0)); /* reserved */
1610 aml_append(scope, aml_name_decl("_S5", pkg));
1611 aml_append(ssdt, scope);
1612
1613 if (misc->applesmc_io_base) {
1614 scope = aml_scope("\\_SB.PCI0.ISA");
1615 dev = aml_device("SMC");
1616
1617 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1618 /* device present, functioning, decoding, not shown in UI */
1619 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1620
1621 crs = aml_resource_template();
1622 aml_append(crs,
1623 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1624 0x01, APPLESMC_MAX_DATA_LENGTH)
1625 );
1626 aml_append(crs, aml_irq_no_flags(6));
1627 aml_append(dev, aml_name_decl("_CRS", crs));
1628
1629 aml_append(scope, dev);
1630 aml_append(ssdt, scope);
1631 }
1632
1633 if (misc->pvpanic_port) {
1634 scope = aml_scope("\\_SB.PCI0.ISA");
1635
1636 dev = aml_device("PEVT");
1637 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1638
1639 crs = aml_resource_template();
1640 aml_append(crs,
1641 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1642 );
1643 aml_append(dev, aml_name_decl("_CRS", crs));
1644
1645 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1646 misc->pvpanic_port, 1));
1647 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1648 aml_append(field, aml_named_field("PEPT", 8));
1649 aml_append(dev, field);
1650
1651 /* device present, functioning, decoding, shown in UI */
1652 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1653
1654 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1655 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1656 aml_append(method, aml_return(aml_local(0)));
1657 aml_append(dev, method);
1658
1659 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1660 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1661 aml_append(dev, method);
1662
1663 aml_append(scope, dev);
1664 aml_append(ssdt, scope);
1665 }
1666
1667 sb_scope = aml_scope("\\_SB");
1668 {
1669 build_processor_devices(sb_scope, guest_info->apic_id_limit, cpu, pm);
1670
1671 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
1672 pm->mem_hp_io_len);
1673
1674 {
1675 Object *pci_host;
1676 PCIBus *bus = NULL;
1677
1678 pci_host = acpi_get_i386_pci_host();
1679 if (pci_host) {
1680 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1681 }
1682
1683 if (bus) {
1684 Aml *scope = aml_scope("PCI0");
1685 /* Scan all PCI buses. Generate tables to support hotplug. */
1686 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1687
1688 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
1689 dev = aml_device("ISA.TPM");
1690 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
1691 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1692 crs = aml_resource_template();
1693 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1694 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1695 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
1696 aml_append(dev, aml_name_decl("_CRS", crs));
1697 aml_append(scope, dev);
1698 }
1699
1700 aml_append(sb_scope, scope);
1701 }
1702 }
1703 aml_append(ssdt, sb_scope);
1704 }
1705
1706 /* copy AML table into ACPI tables blob and patch header there */
1707 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1708 build_header(linker, table_data,
1709 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1710 "SSDT", ssdt->buf->len, 1, NULL);
1711 free_aml_allocator();
1712 }
1713
1714 static void
1715 build_hpet(GArray *table_data, GArray *linker)
1716 {
1717 Acpi20Hpet *hpet;
1718
1719 hpet = acpi_data_push(table_data, sizeof(*hpet));
1720 /* Note timer_block_id value must be kept in sync with value advertised by
1721 * emulated hpet
1722 */
1723 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1724 hpet->addr.address = cpu_to_le64(HPET_BASE);
1725 build_header(linker, table_data,
1726 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL);
1727 }
1728
1729 static void
1730 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1731 {
1732 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1733 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1734
1735 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1736 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1737 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1738
1739 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1740 false /* high memory */);
1741
1742 /* log area start address to be filled by Guest linker */
1743 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1744 ACPI_BUILD_TPMLOG_FILE,
1745 table_data, &tcpa->log_area_start_address,
1746 sizeof(tcpa->log_area_start_address));
1747
1748 build_header(linker, table_data,
1749 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL);
1750
1751 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1752 }
1753
1754 static void
1755 build_tpm2(GArray *table_data, GArray *linker)
1756 {
1757 Acpi20TPM2 *tpm2_ptr;
1758
1759 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
1760
1761 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
1762 tpm2_ptr->control_area_address = cpu_to_le64(0);
1763 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
1764
1765 build_header(linker, table_data,
1766 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL);
1767 }
1768
1769 typedef enum {
1770 MEM_AFFINITY_NOFLAGS = 0,
1771 MEM_AFFINITY_ENABLED = (1 << 0),
1772 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1773 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1774 } MemoryAffinityFlags;
1775
1776 static void
1777 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1778 uint64_t len, int node, MemoryAffinityFlags flags)
1779 {
1780 numamem->type = ACPI_SRAT_MEMORY;
1781 numamem->length = sizeof(*numamem);
1782 memset(numamem->proximity, 0, 4);
1783 numamem->proximity[0] = node;
1784 numamem->flags = cpu_to_le32(flags);
1785 numamem->base_addr = cpu_to_le64(base);
1786 numamem->range_length = cpu_to_le64(len);
1787 }
1788
1789 static void
1790 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1791 {
1792 AcpiSystemResourceAffinityTable *srat;
1793 AcpiSratProcessorAffinity *core;
1794 AcpiSratMemoryAffinity *numamem;
1795
1796 int i;
1797 uint64_t curnode;
1798 int srat_start, numa_start, slots;
1799 uint64_t mem_len, mem_base, next_base;
1800 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1801 ram_addr_t hotplugabble_address_space_size =
1802 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1803 NULL);
1804
1805 srat_start = table_data->len;
1806
1807 srat = acpi_data_push(table_data, sizeof *srat);
1808 srat->reserved1 = cpu_to_le32(1);
1809 core = (void *)(srat + 1);
1810
1811 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1812 core = acpi_data_push(table_data, sizeof *core);
1813 core->type = ACPI_SRAT_PROCESSOR;
1814 core->length = sizeof(*core);
1815 core->local_apic_id = i;
1816 curnode = guest_info->node_cpu[i];
1817 core->proximity_lo = curnode;
1818 memset(core->proximity_hi, 0, 3);
1819 core->local_sapic_eid = 0;
1820 core->flags = cpu_to_le32(1);
1821 }
1822
1823
1824 /* the memory map is a bit tricky, it contains at least one hole
1825 * from 640k-1M and possibly another one from 3.5G-4G.
1826 */
1827 next_base = 0;
1828 numa_start = table_data->len;
1829
1830 numamem = acpi_data_push(table_data, sizeof *numamem);
1831 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1832 next_base = 1024 * 1024;
1833 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1834 mem_base = next_base;
1835 mem_len = guest_info->node_mem[i - 1];
1836 if (i == 1) {
1837 mem_len -= 1024 * 1024;
1838 }
1839 next_base = mem_base + mem_len;
1840
1841 /* Cut out the ACPI_PCI hole */
1842 if (mem_base <= guest_info->ram_size_below_4g &&
1843 next_base > guest_info->ram_size_below_4g) {
1844 mem_len -= next_base - guest_info->ram_size_below_4g;
1845 if (mem_len > 0) {
1846 numamem = acpi_data_push(table_data, sizeof *numamem);
1847 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1848 MEM_AFFINITY_ENABLED);
1849 }
1850 mem_base = 1ULL << 32;
1851 mem_len = next_base - guest_info->ram_size_below_4g;
1852 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1853 }
1854 numamem = acpi_data_push(table_data, sizeof *numamem);
1855 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1856 MEM_AFFINITY_ENABLED);
1857 }
1858 slots = (table_data->len - numa_start) / sizeof *numamem;
1859 for (; slots < guest_info->numa_nodes + 2; slots++) {
1860 numamem = acpi_data_push(table_data, sizeof *numamem);
1861 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1862 }
1863
1864 /*
1865 * Entry is required for Windows to enable memory hotplug in OS.
1866 * Memory devices may override proximity set by this entry,
1867 * providing _PXM method if necessary.
1868 */
1869 if (hotplugabble_address_space_size) {
1870 numamem = acpi_data_push(table_data, sizeof *numamem);
1871 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
1872 hotplugabble_address_space_size, 0,
1873 MEM_AFFINITY_HOTPLUGGABLE |
1874 MEM_AFFINITY_ENABLED);
1875 }
1876
1877 build_header(linker, table_data,
1878 (void *)(table_data->data + srat_start),
1879 "SRAT",
1880 table_data->len - srat_start, 1, NULL);
1881 }
1882
1883 static void
1884 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1885 {
1886 AcpiTableMcfg *mcfg;
1887 const char *sig;
1888 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1889
1890 mcfg = acpi_data_push(table_data, len);
1891 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1892 /* Only a single allocation so no need to play with segments */
1893 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1894 mcfg->allocation[0].start_bus_number = 0;
1895 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1896
1897 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1898 * To avoid table size changes (which create migration issues),
1899 * always create the table even if there are no allocations,
1900 * but set the signature to a reserved value in this case.
1901 * ACPI spec requires OSPMs to ignore such tables.
1902 */
1903 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1904 /* Reserved signature: ignored by OSPM */
1905 sig = "QEMU";
1906 } else {
1907 sig = "MCFG";
1908 }
1909 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL);
1910 }
1911
1912 static void
1913 build_dmar_q35(GArray *table_data, GArray *linker)
1914 {
1915 int dmar_start = table_data->len;
1916
1917 AcpiTableDmar *dmar;
1918 AcpiDmarHardwareUnit *drhd;
1919
1920 dmar = acpi_data_push(table_data, sizeof(*dmar));
1921 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1922 dmar->flags = 0; /* No intr_remap for now */
1923
1924 /* DMAR Remapping Hardware Unit Definition structure */
1925 drhd = acpi_data_push(table_data, sizeof(*drhd));
1926 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1927 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1928 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1929 drhd->pci_segment = cpu_to_le16(0);
1930 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1931
1932 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1933 "DMAR", table_data->len - dmar_start, 1, NULL);
1934 }
1935
1936 static void
1937 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1938 {
1939 AcpiTableHeader *dsdt;
1940
1941 assert(misc->dsdt_code && misc->dsdt_size);
1942
1943 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1944 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1945
1946 memset(dsdt, 0, sizeof *dsdt);
1947 build_header(linker, table_data, dsdt, "DSDT",
1948 misc->dsdt_size, 1, NULL);
1949 }
1950
1951 static GArray *
1952 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1953 {
1954 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1955
1956 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1957 true /* fseg memory */);
1958
1959 memcpy(&rsdp->signature, "RSD PTR ", 8);
1960 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1961 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1962 /* Address to be filled by Guest linker */
1963 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1964 ACPI_BUILD_TABLE_FILE,
1965 rsdp_table, &rsdp->rsdt_physical_address,
1966 sizeof rsdp->rsdt_physical_address);
1967 rsdp->checksum = 0;
1968 /* Checksum to be filled by Guest linker */
1969 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1970 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1971
1972 return rsdp_table;
1973 }
1974
1975 typedef
1976 struct AcpiBuildState {
1977 /* Copy of table in RAM (for patching). */
1978 MemoryRegion *table_mr;
1979 /* Is table patched? */
1980 uint8_t patched;
1981 PcGuestInfo *guest_info;
1982 void *rsdp;
1983 MemoryRegion *rsdp_mr;
1984 MemoryRegion *linker_mr;
1985 } AcpiBuildState;
1986
1987 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1988 {
1989 Object *pci_host;
1990 QObject *o;
1991
1992 pci_host = acpi_get_i386_pci_host();
1993 g_assert(pci_host);
1994
1995 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1996 if (!o) {
1997 return false;
1998 }
1999 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2000 qobject_decref(o);
2001
2002 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2003 assert(o);
2004 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2005 qobject_decref(o);
2006 return true;
2007 }
2008
2009 static bool acpi_has_iommu(void)
2010 {
2011 bool ambiguous;
2012 Object *intel_iommu;
2013
2014 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2015 &ambiguous);
2016 return intel_iommu && !ambiguous;
2017 }
2018
2019 static bool acpi_has_nvdimm(void)
2020 {
2021 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2022
2023 return pcms->nvdimm;
2024 }
2025
2026 static
2027 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
2028 {
2029 GArray *table_offsets;
2030 unsigned facs, ssdt, dsdt, rsdt;
2031 AcpiCpuInfo cpu;
2032 AcpiPmInfo pm;
2033 AcpiMiscInfo misc;
2034 AcpiMcfgInfo mcfg;
2035 PcPciInfo pci;
2036 uint8_t *u;
2037 size_t aml_len = 0;
2038 GArray *tables_blob = tables->table_data;
2039
2040 acpi_get_cpu_info(&cpu);
2041 acpi_get_pm_info(&pm);
2042 acpi_get_dsdt(&misc);
2043 acpi_get_misc_info(&misc);
2044 acpi_get_pci_info(&pci);
2045
2046 table_offsets = g_array_new(false, true /* clear */,
2047 sizeof(uint32_t));
2048 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2049
2050 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2051 64 /* Ensure FACS is aligned */,
2052 false /* high memory */);
2053
2054 /*
2055 * FACS is pointed to by FADT.
2056 * We place it first since it's the only table that has alignment
2057 * requirements.
2058 */
2059 facs = tables_blob->len;
2060 build_facs(tables_blob, tables->linker, guest_info);
2061
2062 /* DSDT is pointed to by FADT */
2063 dsdt = tables_blob->len;
2064 build_dsdt(tables_blob, tables->linker, &misc);
2065
2066 /* Count the size of the DSDT and SSDT, we will need it for legacy
2067 * sizing of ACPI tables.
2068 */
2069 aml_len += tables_blob->len - dsdt;
2070
2071 /* ACPI tables pointed to by RSDT */
2072 acpi_add_table(table_offsets, tables_blob);
2073 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
2074
2075 ssdt = tables_blob->len;
2076 acpi_add_table(table_offsets, tables_blob);
2077 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
2078 guest_info);
2079 aml_len += tables_blob->len - ssdt;
2080
2081 acpi_add_table(table_offsets, tables_blob);
2082 build_madt(tables_blob, tables->linker, &cpu, guest_info);
2083
2084 if (misc.has_hpet) {
2085 acpi_add_table(table_offsets, tables_blob);
2086 build_hpet(tables_blob, tables->linker);
2087 }
2088 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2089 acpi_add_table(table_offsets, tables_blob);
2090 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2091
2092 if (misc.tpm_version == TPM_VERSION_2_0) {
2093 acpi_add_table(table_offsets, tables_blob);
2094 build_tpm2(tables_blob, tables->linker);
2095 }
2096 }
2097 if (guest_info->numa_nodes) {
2098 acpi_add_table(table_offsets, tables_blob);
2099 build_srat(tables_blob, tables->linker, guest_info);
2100 }
2101 if (acpi_get_mcfg(&mcfg)) {
2102 acpi_add_table(table_offsets, tables_blob);
2103 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2104 }
2105 if (acpi_has_iommu()) {
2106 acpi_add_table(table_offsets, tables_blob);
2107 build_dmar_q35(tables_blob, tables->linker);
2108 }
2109
2110 if (acpi_has_nvdimm()) {
2111 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2112 }
2113
2114 /* Add tables supplied by user (if any) */
2115 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2116 unsigned len = acpi_table_len(u);
2117
2118 acpi_add_table(table_offsets, tables_blob);
2119 g_array_append_vals(tables_blob, u, len);
2120 }
2121
2122 /* RSDT is pointed to by RSDP */
2123 rsdt = tables_blob->len;
2124 build_rsdt(tables_blob, tables->linker, table_offsets);
2125
2126 /* RSDP is in FSEG memory, so allocate it separately */
2127 build_rsdp(tables->rsdp, tables->linker, rsdt);
2128
2129 /* We'll expose it all to Guest so we want to reduce
2130 * chance of size changes.
2131 *
2132 * We used to align the tables to 4k, but of course this would
2133 * too simple to be enough. 4k turned out to be too small an
2134 * alignment very soon, and in fact it is almost impossible to
2135 * keep the table size stable for all (max_cpus, max_memory_slots)
2136 * combinations. So the table size is always 64k for pc-i440fx-2.1
2137 * and we give an error if the table grows beyond that limit.
2138 *
2139 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2140 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2141 * than 2.0 and we can always pad the smaller tables with zeros. We can
2142 * then use the exact size of the 2.0 tables.
2143 *
2144 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2145 */
2146 if (guest_info->legacy_acpi_table_size) {
2147 /* Subtracting aml_len gives the size of fixed tables. Then add the
2148 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2149 */
2150 int legacy_aml_len =
2151 guest_info->legacy_acpi_table_size +
2152 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2153 int legacy_table_size =
2154 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2155 ACPI_BUILD_ALIGN_SIZE);
2156 if (tables_blob->len > legacy_table_size) {
2157 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2158 error_report("Warning: migration may not work.");
2159 }
2160 g_array_set_size(tables_blob, legacy_table_size);
2161 } else {
2162 /* Make sure we have a buffer in case we need to resize the tables. */
2163 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2164 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2165 error_report("Warning: ACPI tables are larger than 64k.");
2166 error_report("Warning: migration may not work.");
2167 error_report("Warning: please remove CPUs, NUMA nodes, "
2168 "memory slots or PCI bridges.");
2169 }
2170 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2171 }
2172
2173 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
2174
2175 /* Cleanup memory that's no longer used. */
2176 g_array_free(table_offsets, true);
2177 }
2178
2179 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2180 {
2181 uint32_t size = acpi_data_len(data);
2182
2183 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2184 memory_region_ram_resize(mr, size, &error_abort);
2185
2186 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2187 memory_region_set_dirty(mr, 0, size);
2188 }
2189
2190 static void acpi_build_update(void *build_opaque)
2191 {
2192 AcpiBuildState *build_state = build_opaque;
2193 AcpiBuildTables tables;
2194
2195 /* No state to update or already patched? Nothing to do. */
2196 if (!build_state || build_state->patched) {
2197 return;
2198 }
2199 build_state->patched = 1;
2200
2201 acpi_build_tables_init(&tables);
2202
2203 acpi_build(build_state->guest_info, &tables);
2204
2205 acpi_ram_update(build_state->table_mr, tables.table_data);
2206
2207 if (build_state->rsdp) {
2208 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2209 } else {
2210 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2211 }
2212
2213 acpi_ram_update(build_state->linker_mr, tables.linker);
2214 acpi_build_tables_cleanup(&tables, true);
2215 }
2216
2217 static void acpi_build_reset(void *build_opaque)
2218 {
2219 AcpiBuildState *build_state = build_opaque;
2220 build_state->patched = 0;
2221 }
2222
2223 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2224 GArray *blob, const char *name,
2225 uint64_t max_size)
2226 {
2227 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2228 name, acpi_build_update, build_state);
2229 }
2230
2231 static const VMStateDescription vmstate_acpi_build = {
2232 .name = "acpi_build",
2233 .version_id = 1,
2234 .minimum_version_id = 1,
2235 .fields = (VMStateField[]) {
2236 VMSTATE_UINT8(patched, AcpiBuildState),
2237 VMSTATE_END_OF_LIST()
2238 },
2239 };
2240
2241 void acpi_setup(PcGuestInfo *guest_info)
2242 {
2243 AcpiBuildTables tables;
2244 AcpiBuildState *build_state;
2245
2246 if (!guest_info->fw_cfg) {
2247 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2248 return;
2249 }
2250
2251 if (!guest_info->has_acpi_build) {
2252 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2253 return;
2254 }
2255
2256 if (!acpi_enabled) {
2257 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2258 return;
2259 }
2260
2261 build_state = g_malloc0(sizeof *build_state);
2262
2263 build_state->guest_info = guest_info;
2264
2265 acpi_set_pci_info();
2266
2267 acpi_build_tables_init(&tables);
2268 acpi_build(build_state->guest_info, &tables);
2269
2270 /* Now expose it all to Guest */
2271 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2272 ACPI_BUILD_TABLE_FILE,
2273 ACPI_BUILD_TABLE_MAX_SIZE);
2274 assert(build_state->table_mr != NULL);
2275
2276 build_state->linker_mr =
2277 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
2278
2279 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2280 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2281
2282 if (!guest_info->rsdp_in_ram) {
2283 /*
2284 * Keep for compatibility with old machine types.
2285 * Though RSDP is small, its contents isn't immutable, so
2286 * we'll update it along with the rest of tables on guest access.
2287 */
2288 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2289
2290 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2291 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
2292 acpi_build_update, build_state,
2293 build_state->rsdp, rsdp_size);
2294 build_state->rsdp_mr = NULL;
2295 } else {
2296 build_state->rsdp = NULL;
2297 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2298 ACPI_BUILD_RSDP_FILE, 0);
2299 }
2300
2301 qemu_register_reset(acpi_build_reset, build_state);
2302 acpi_build_reset(build_state);
2303 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2304
2305 /* Cleanup tables but don't free the memory: we track it
2306 * in build_state.
2307 */
2308 acpi_build_tables_cleanup(&tables, false);
2309 }
CRIS target port of Qemu