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Fix regression in option parsing
[qemu/cris-port.git] / hw / ppc405_uc.c
blobbfcb79144bff9f7c1dc074b6527e183ffd13377b
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_phys(bdloc + 0x00, bd->bi_memstart);
55 stl_phys(bdloc + 0x04, bd->bi_memsize);
56 stl_phys(bdloc + 0x08, bd->bi_flashstart);
57 stl_phys(bdloc + 0x0C, bd->bi_flashsize);
58 stl_phys(bdloc + 0x10, bd->bi_flashoffset);
59 stl_phys(bdloc + 0x14, bd->bi_sramstart);
60 stl_phys(bdloc + 0x18, bd->bi_sramsize);
61 stl_phys(bdloc + 0x1C, bd->bi_bootflags);
62 stl_phys(bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++)
64 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
66 stl_phys(bdloc + 0x2C, bd->bi_intfreq);
67 stl_phys(bdloc + 0x30, bd->bi_busfreq);
68 stl_phys(bdloc + 0x34, bd->bi_baudrate);
69 for (i = 0; i < 4; i++)
70 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
71 for (i = 0; i < 32; i++)
72 stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
73 stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
74 stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
75 for (i = 0; i < 6; i++)
76 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
77 n = 0x6A;
78 if (flags & 0x00000001) {
79 for (i = 0; i < 6; i++)
80 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
81 }
82 stl_phys(bdloc + n, bd->bi_opbfreq);
83 n += 4;
84 for (i = 0; i < 2; i++) {
85 stl_phys(bdloc + n, bd->bi_iic_fast[i]);
86 n += 4;
87 }
88
89 return bdloc;
90 }
91
92 /*****************************************************************************/
93 /* Shared peripherals */
94
95 /*****************************************************************************/
96 /* Peripheral local bus arbitrer */
97 enum {
98 PLB0_BESR = 0x084,
99 PLB0_BEAR = 0x086,
100 PLB0_ACR = 0x087,
101 };
102
103 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
104 struct ppc4xx_plb_t {
105 uint32_t acr;
106 uint32_t bear;
107 uint32_t besr;
108 };
109
110 static uint32_t dcr_read_plb (void *opaque, int dcrn)
111 {
112 ppc4xx_plb_t *plb;
113 uint32_t ret;
114
115 plb = opaque;
116 switch (dcrn) {
117 case PLB0_ACR:
118 ret = plb->acr;
119 break;
120 case PLB0_BEAR:
121 ret = plb->bear;
122 break;
123 case PLB0_BESR:
124 ret = plb->besr;
125 break;
126 default:
127 /* Avoid gcc warning */
128 ret = 0;
129 break;
130 }
131
132 return ret;
133 }
134
135 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
136 {
137 ppc4xx_plb_t *plb;
138
139 plb = opaque;
140 switch (dcrn) {
141 case PLB0_ACR:
142 /* We don't care about the actual parameters written as
143 * we don't manage any priorities on the bus
144 */
145 plb->acr = val & 0xF8000000;
146 break;
147 case PLB0_BEAR:
148 /* Read only */
149 break;
150 case PLB0_BESR:
151 /* Write-clear */
152 plb->besr &= ~val;
153 break;
154 }
155 }
156
157 static void ppc4xx_plb_reset (void *opaque)
158 {
159 ppc4xx_plb_t *plb;
160
161 plb = opaque;
162 plb->acr = 0x00000000;
163 plb->bear = 0x00000000;
164 plb->besr = 0x00000000;
165 }
166
167 static void ppc4xx_plb_init(CPUState *env)
168 {
169 ppc4xx_plb_t *plb;
170
171 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
172 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
173 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
174 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
175 qemu_register_reset(ppc4xx_plb_reset, plb);
176 }
177
178 /*****************************************************************************/
179 /* PLB to OPB bridge */
180 enum {
181 POB0_BESR0 = 0x0A0,
182 POB0_BESR1 = 0x0A2,
183 POB0_BEAR = 0x0A4,
184 };
185
186 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
187 struct ppc4xx_pob_t {
188 uint32_t bear;
189 uint32_t besr[2];
190 };
191
192 static uint32_t dcr_read_pob (void *opaque, int dcrn)
193 {
194 ppc4xx_pob_t *pob;
195 uint32_t ret;
196
197 pob = opaque;
198 switch (dcrn) {
199 case POB0_BEAR:
200 ret = pob->bear;
201 break;
202 case POB0_BESR0:
203 case POB0_BESR1:
204 ret = pob->besr[dcrn - POB0_BESR0];
205 break;
206 default:
207 /* Avoid gcc warning */
208 ret = 0;
209 break;
210 }
211
212 return ret;
213 }
214
215 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
216 {
217 ppc4xx_pob_t *pob;
218
219 pob = opaque;
220 switch (dcrn) {
221 case POB0_BEAR:
222 /* Read only */
223 break;
224 case POB0_BESR0:
225 case POB0_BESR1:
226 /* Write-clear */
227 pob->besr[dcrn - POB0_BESR0] &= ~val;
228 break;
229 }
230 }
231
232 static void ppc4xx_pob_reset (void *opaque)
233 {
234 ppc4xx_pob_t *pob;
235
236 pob = opaque;
237 /* No error */
238 pob->bear = 0x00000000;
239 pob->besr[0] = 0x0000000;
240 pob->besr[1] = 0x0000000;
241 }
242
243 static void ppc4xx_pob_init(CPUState *env)
244 {
245 ppc4xx_pob_t *pob;
246
247 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
248 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
249 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
250 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
251 qemu_register_reset(ppc4xx_pob_reset, pob);
252 }
253
254 /*****************************************************************************/
255 /* OPB arbitrer */
256 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
257 struct ppc4xx_opba_t {
258 uint8_t cr;
259 uint8_t pr;
260 };
261
262 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
263 {
264 ppc4xx_opba_t *opba;
265 uint32_t ret;
266
267 #ifdef DEBUG_OPBA
268 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
269 #endif
270 opba = opaque;
271 switch (addr) {
272 case 0x00:
273 ret = opba->cr;
274 break;
275 case 0x01:
276 ret = opba->pr;
277 break;
278 default:
279 ret = 0x00;
280 break;
281 }
282
283 return ret;
284 }
285
286 static void opba_writeb (void *opaque,
287 target_phys_addr_t addr, uint32_t value)
288 {
289 ppc4xx_opba_t *opba;
290
291 #ifdef DEBUG_OPBA
292 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
293 value);
294 #endif
295 opba = opaque;
296 switch (addr) {
297 case 0x00:
298 opba->cr = value & 0xF8;
299 break;
300 case 0x01:
301 opba->pr = value & 0xFF;
302 break;
303 default:
304 break;
305 }
306 }
307
308 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
309 {
310 uint32_t ret;
311
312 #ifdef DEBUG_OPBA
313 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
314 #endif
315 ret = opba_readb(opaque, addr) << 8;
316 ret |= opba_readb(opaque, addr + 1);
317
318 return ret;
319 }
320
321 static void opba_writew (void *opaque,
322 target_phys_addr_t addr, uint32_t value)
323 {
324 #ifdef DEBUG_OPBA
325 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
326 value);
327 #endif
328 opba_writeb(opaque, addr, value >> 8);
329 opba_writeb(opaque, addr + 1, value);
330 }
331
332 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
333 {
334 uint32_t ret;
335
336 #ifdef DEBUG_OPBA
337 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
338 #endif
339 ret = opba_readb(opaque, addr) << 24;
340 ret |= opba_readb(opaque, addr + 1) << 16;
341
342 return ret;
343 }
344
345 static void opba_writel (void *opaque,
346 target_phys_addr_t addr, uint32_t value)
347 {
348 #ifdef DEBUG_OPBA
349 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
350 value);
351 #endif
352 opba_writeb(opaque, addr, value >> 24);
353 opba_writeb(opaque, addr + 1, value >> 16);
354 }
355
356 static CPUReadMemoryFunc * const opba_read[] = {
357 &opba_readb,
358 &opba_readw,
359 &opba_readl,
360 };
361
362 static CPUWriteMemoryFunc * const opba_write[] = {
363 &opba_writeb,
364 &opba_writew,
365 &opba_writel,
366 };
367
368 static void ppc4xx_opba_reset (void *opaque)
369 {
370 ppc4xx_opba_t *opba;
371
372 opba = opaque;
373 opba->cr = 0x00; /* No dynamic priorities - park disabled */
374 opba->pr = 0x11;
375 }
376
377 static void ppc4xx_opba_init(target_phys_addr_t base)
378 {
379 ppc4xx_opba_t *opba;
380 int io;
381
382 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
383 #ifdef DEBUG_OPBA
384 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
385 #endif
386 io = cpu_register_io_memory(opba_read, opba_write, opba);
387 cpu_register_physical_memory(base, 0x002, io);
388 qemu_register_reset(ppc4xx_opba_reset, opba);
389 }
390
391 /*****************************************************************************/
392 /* Code decompression controller */
393 /* XXX: TODO */
394
395 /*****************************************************************************/
396 /* Peripheral controller */
397 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
398 struct ppc4xx_ebc_t {
399 uint32_t addr;
400 uint32_t bcr[8];
401 uint32_t bap[8];
402 uint32_t bear;
403 uint32_t besr0;
404 uint32_t besr1;
405 uint32_t cfg;
406 };
407
408 enum {
409 EBC0_CFGADDR = 0x012,
410 EBC0_CFGDATA = 0x013,
411 };
412
413 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
414 {
415 ppc4xx_ebc_t *ebc;
416 uint32_t ret;
417
418 ebc = opaque;
419 switch (dcrn) {
420 case EBC0_CFGADDR:
421 ret = ebc->addr;
422 break;
423 case EBC0_CFGDATA:
424 switch (ebc->addr) {
425 case 0x00: /* B0CR */
426 ret = ebc->bcr[0];
427 break;
428 case 0x01: /* B1CR */
429 ret = ebc->bcr[1];
430 break;
431 case 0x02: /* B2CR */
432 ret = ebc->bcr[2];
433 break;
434 case 0x03: /* B3CR */
435 ret = ebc->bcr[3];
436 break;
437 case 0x04: /* B4CR */
438 ret = ebc->bcr[4];
439 break;
440 case 0x05: /* B5CR */
441 ret = ebc->bcr[5];
442 break;
443 case 0x06: /* B6CR */
444 ret = ebc->bcr[6];
445 break;
446 case 0x07: /* B7CR */
447 ret = ebc->bcr[7];
448 break;
449 case 0x10: /* B0AP */
450 ret = ebc->bap[0];
451 break;
452 case 0x11: /* B1AP */
453 ret = ebc->bap[1];
454 break;
455 case 0x12: /* B2AP */
456 ret = ebc->bap[2];
457 break;
458 case 0x13: /* B3AP */
459 ret = ebc->bap[3];
460 break;
461 case 0x14: /* B4AP */
462 ret = ebc->bap[4];
463 break;
464 case 0x15: /* B5AP */
465 ret = ebc->bap[5];
466 break;
467 case 0x16: /* B6AP */
468 ret = ebc->bap[6];
469 break;
470 case 0x17: /* B7AP */
471 ret = ebc->bap[7];
472 break;
473 case 0x20: /* BEAR */
474 ret = ebc->bear;
475 break;
476 case 0x21: /* BESR0 */
477 ret = ebc->besr0;
478 break;
479 case 0x22: /* BESR1 */
480 ret = ebc->besr1;
481 break;
482 case 0x23: /* CFG */
483 ret = ebc->cfg;
484 break;
485 default:
486 ret = 0x00000000;
487 break;
488 }
489 default:
490 ret = 0x00000000;
491 break;
492 }
493
494 return ret;
495 }
496
497 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
498 {
499 ppc4xx_ebc_t *ebc;
500
501 ebc = opaque;
502 switch (dcrn) {
503 case EBC0_CFGADDR:
504 ebc->addr = val;
505 break;
506 case EBC0_CFGDATA:
507 switch (ebc->addr) {
508 case 0x00: /* B0CR */
509 break;
510 case 0x01: /* B1CR */
511 break;
512 case 0x02: /* B2CR */
513 break;
514 case 0x03: /* B3CR */
515 break;
516 case 0x04: /* B4CR */
517 break;
518 case 0x05: /* B5CR */
519 break;
520 case 0x06: /* B6CR */
521 break;
522 case 0x07: /* B7CR */
523 break;
524 case 0x10: /* B0AP */
525 break;
526 case 0x11: /* B1AP */
527 break;
528 case 0x12: /* B2AP */
529 break;
530 case 0x13: /* B3AP */
531 break;
532 case 0x14: /* B4AP */
533 break;
534 case 0x15: /* B5AP */
535 break;
536 case 0x16: /* B6AP */
537 break;
538 case 0x17: /* B7AP */
539 break;
540 case 0x20: /* BEAR */
541 break;
542 case 0x21: /* BESR0 */
543 break;
544 case 0x22: /* BESR1 */
545 break;
546 case 0x23: /* CFG */
547 break;
548 default:
549 break;
550 }
551 break;
552 default:
553 break;
554 }
555 }
556
557 static void ebc_reset (void *opaque)
558 {
559 ppc4xx_ebc_t *ebc;
560 int i;
561
562 ebc = opaque;
563 ebc->addr = 0x00000000;
564 ebc->bap[0] = 0x7F8FFE80;
565 ebc->bcr[0] = 0xFFE28000;
566 for (i = 0; i < 8; i++) {
567 ebc->bap[i] = 0x00000000;
568 ebc->bcr[i] = 0x00000000;
569 }
570 ebc->besr0 = 0x00000000;
571 ebc->besr1 = 0x00000000;
572 ebc->cfg = 0x80400000;
573 }
574
575 static void ppc405_ebc_init(CPUState *env)
576 {
577 ppc4xx_ebc_t *ebc;
578
579 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
580 qemu_register_reset(&ebc_reset, ebc);
581 ppc_dcr_register(env, EBC0_CFGADDR,
582 ebc, &dcr_read_ebc, &dcr_write_ebc);
583 ppc_dcr_register(env, EBC0_CFGDATA,
584 ebc, &dcr_read_ebc, &dcr_write_ebc);
585 }
586
587 /*****************************************************************************/
588 /* DMA controller */
589 enum {
590 DMA0_CR0 = 0x100,
591 DMA0_CT0 = 0x101,
592 DMA0_DA0 = 0x102,
593 DMA0_SA0 = 0x103,
594 DMA0_SG0 = 0x104,
595 DMA0_CR1 = 0x108,
596 DMA0_CT1 = 0x109,
597 DMA0_DA1 = 0x10A,
598 DMA0_SA1 = 0x10B,
599 DMA0_SG1 = 0x10C,
600 DMA0_CR2 = 0x110,
601 DMA0_CT2 = 0x111,
602 DMA0_DA2 = 0x112,
603 DMA0_SA2 = 0x113,
604 DMA0_SG2 = 0x114,
605 DMA0_CR3 = 0x118,
606 DMA0_CT3 = 0x119,
607 DMA0_DA3 = 0x11A,
608 DMA0_SA3 = 0x11B,
609 DMA0_SG3 = 0x11C,
610 DMA0_SR = 0x120,
611 DMA0_SGC = 0x123,
612 DMA0_SLP = 0x125,
613 DMA0_POL = 0x126,
614 };
615
616 typedef struct ppc405_dma_t ppc405_dma_t;
617 struct ppc405_dma_t {
618 qemu_irq irqs[4];
619 uint32_t cr[4];
620 uint32_t ct[4];
621 uint32_t da[4];
622 uint32_t sa[4];
623 uint32_t sg[4];
624 uint32_t sr;
625 uint32_t sgc;
626 uint32_t slp;
627 uint32_t pol;
628 };
629
630 static uint32_t dcr_read_dma (void *opaque, int dcrn)
631 {
632 ppc405_dma_t *dma;
633
634 dma = opaque;
635
636 return 0;
637 }
638
639 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
640 {
641 ppc405_dma_t *dma;
642
643 dma = opaque;
644 }
645
646 static void ppc405_dma_reset (void *opaque)
647 {
648 ppc405_dma_t *dma;
649 int i;
650
651 dma = opaque;
652 for (i = 0; i < 4; i++) {
653 dma->cr[i] = 0x00000000;
654 dma->ct[i] = 0x00000000;
655 dma->da[i] = 0x00000000;
656 dma->sa[i] = 0x00000000;
657 dma->sg[i] = 0x00000000;
658 }
659 dma->sr = 0x00000000;
660 dma->sgc = 0x00000000;
661 dma->slp = 0x7C000000;
662 dma->pol = 0x00000000;
663 }
664
665 static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
666 {
667 ppc405_dma_t *dma;
668
669 dma = qemu_mallocz(sizeof(ppc405_dma_t));
670 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
671 qemu_register_reset(&ppc405_dma_reset, dma);
672 ppc_dcr_register(env, DMA0_CR0,
673 dma, &dcr_read_dma, &dcr_write_dma);
674 ppc_dcr_register(env, DMA0_CT0,
675 dma, &dcr_read_dma, &dcr_write_dma);
676 ppc_dcr_register(env, DMA0_DA0,
677 dma, &dcr_read_dma, &dcr_write_dma);
678 ppc_dcr_register(env, DMA0_SA0,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_SG0,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_CR1,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_CT1,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_DA1,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_SA1,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_SG1,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_CR2,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_CT2,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_DA2,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_SA2,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_SG2,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_CR3,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_CT3,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_DA3,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_SA3,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_SG3,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 ppc_dcr_register(env, DMA0_SR,
713 dma, &dcr_read_dma, &dcr_write_dma);
714 ppc_dcr_register(env, DMA0_SGC,
715 dma, &dcr_read_dma, &dcr_write_dma);
716 ppc_dcr_register(env, DMA0_SLP,
717 dma, &dcr_read_dma, &dcr_write_dma);
718 ppc_dcr_register(env, DMA0_POL,
719 dma, &dcr_read_dma, &dcr_write_dma);
720 }
721
722 /*****************************************************************************/
723 /* GPIO */
724 typedef struct ppc405_gpio_t ppc405_gpio_t;
725 struct ppc405_gpio_t {
726 uint32_t or;
727 uint32_t tcr;
728 uint32_t osrh;
729 uint32_t osrl;
730 uint32_t tsrh;
731 uint32_t tsrl;
732 uint32_t odr;
733 uint32_t ir;
734 uint32_t rr1;
735 uint32_t isr1h;
736 uint32_t isr1l;
737 };
738
739 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
740 {
741 ppc405_gpio_t *gpio;
742
743 gpio = opaque;
744 #ifdef DEBUG_GPIO
745 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
746 #endif
747
748 return 0;
749 }
750
751 static void ppc405_gpio_writeb (void *opaque,
752 target_phys_addr_t addr, uint32_t value)
753 {
754 ppc405_gpio_t *gpio;
755
756 gpio = opaque;
757 #ifdef DEBUG_GPIO
758 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
759 value);
760 #endif
761 }
762
763 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
764 {
765 ppc405_gpio_t *gpio;
766
767 gpio = opaque;
768 #ifdef DEBUG_GPIO
769 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
770 #endif
771
772 return 0;
773 }
774
775 static void ppc405_gpio_writew (void *opaque,
776 target_phys_addr_t addr, uint32_t value)
777 {
778 ppc405_gpio_t *gpio;
779
780 gpio = opaque;
781 #ifdef DEBUG_GPIO
782 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
783 value);
784 #endif
785 }
786
787 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
788 {
789 ppc405_gpio_t *gpio;
790
791 gpio = opaque;
792 #ifdef DEBUG_GPIO
793 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
794 #endif
795
796 return 0;
797 }
798
799 static void ppc405_gpio_writel (void *opaque,
800 target_phys_addr_t addr, uint32_t value)
801 {
802 ppc405_gpio_t *gpio;
803
804 gpio = opaque;
805 #ifdef DEBUG_GPIO
806 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
807 value);
808 #endif
809 }
810
811 static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
812 &ppc405_gpio_readb,
813 &ppc405_gpio_readw,
814 &ppc405_gpio_readl,
815 };
816
817 static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
818 &ppc405_gpio_writeb,
819 &ppc405_gpio_writew,
820 &ppc405_gpio_writel,
821 };
822
823 static void ppc405_gpio_reset (void *opaque)
824 {
825 ppc405_gpio_t *gpio;
826
827 gpio = opaque;
828 }
829
830 static void ppc405_gpio_init(target_phys_addr_t base)
831 {
832 ppc405_gpio_t *gpio;
833 int io;
834
835 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
836 #ifdef DEBUG_GPIO
837 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
838 #endif
839 io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
840 cpu_register_physical_memory(base, 0x038, io);
841 qemu_register_reset(&ppc405_gpio_reset, gpio);
842 }
843
844 /*****************************************************************************/
845 /* On Chip Memory */
846 enum {
847 OCM0_ISARC = 0x018,
848 OCM0_ISACNTL = 0x019,
849 OCM0_DSARC = 0x01A,
850 OCM0_DSACNTL = 0x01B,
851 };
852
853 typedef struct ppc405_ocm_t ppc405_ocm_t;
854 struct ppc405_ocm_t {
855 target_ulong offset;
856 uint32_t isarc;
857 uint32_t isacntl;
858 uint32_t dsarc;
859 uint32_t dsacntl;
860 };
861
862 static void ocm_update_mappings (ppc405_ocm_t *ocm,
863 uint32_t isarc, uint32_t isacntl,
864 uint32_t dsarc, uint32_t dsacntl)
865 {
866 #ifdef DEBUG_OCM
867 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
868 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
869 " (%08" PRIx32 " %08" PRIx32 ")\n",
870 isarc, isacntl, dsarc, dsacntl,
871 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
872 #endif
873 if (ocm->isarc != isarc ||
874 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
875 if (ocm->isacntl & 0x80000000) {
876 /* Unmap previously assigned memory region */
877 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
878 cpu_register_physical_memory(ocm->isarc, 0x04000000,
879 IO_MEM_UNASSIGNED);
880 }
881 if (isacntl & 0x80000000) {
882 /* Map new instruction memory region */
883 #ifdef DEBUG_OCM
884 printf("OCM map ISA %08" PRIx32 "\n", isarc);
885 #endif
886 cpu_register_physical_memory(isarc, 0x04000000,
887 ocm->offset | IO_MEM_RAM);
888 }
889 }
890 if (ocm->dsarc != dsarc ||
891 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
892 if (ocm->dsacntl & 0x80000000) {
893 /* Beware not to unmap the region we just mapped */
894 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
895 /* Unmap previously assigned memory region */
896 #ifdef DEBUG_OCM
897 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
898 #endif
899 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
900 IO_MEM_UNASSIGNED);
901 }
902 }
903 if (dsacntl & 0x80000000) {
904 /* Beware not to remap the region we just mapped */
905 if (!(isacntl & 0x80000000) || dsarc != isarc) {
906 /* Map new data memory region */
907 #ifdef DEBUG_OCM
908 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
909 #endif
910 cpu_register_physical_memory(dsarc, 0x04000000,
911 ocm->offset | IO_MEM_RAM);
912 }
913 }
914 }
915 }
916
917 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
918 {
919 ppc405_ocm_t *ocm;
920 uint32_t ret;
921
922 ocm = opaque;
923 switch (dcrn) {
924 case OCM0_ISARC:
925 ret = ocm->isarc;
926 break;
927 case OCM0_ISACNTL:
928 ret = ocm->isacntl;
929 break;
930 case OCM0_DSARC:
931 ret = ocm->dsarc;
932 break;
933 case OCM0_DSACNTL:
934 ret = ocm->dsacntl;
935 break;
936 default:
937 ret = 0;
938 break;
939 }
940
941 return ret;
942 }
943
944 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
945 {
946 ppc405_ocm_t *ocm;
947 uint32_t isarc, dsarc, isacntl, dsacntl;
948
949 ocm = opaque;
950 isarc = ocm->isarc;
951 dsarc = ocm->dsarc;
952 isacntl = ocm->isacntl;
953 dsacntl = ocm->dsacntl;
954 switch (dcrn) {
955 case OCM0_ISARC:
956 isarc = val & 0xFC000000;
957 break;
958 case OCM0_ISACNTL:
959 isacntl = val & 0xC0000000;
960 break;
961 case OCM0_DSARC:
962 isarc = val & 0xFC000000;
963 break;
964 case OCM0_DSACNTL:
965 isacntl = val & 0xC0000000;
966 break;
967 }
968 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
969 ocm->isarc = isarc;
970 ocm->dsarc = dsarc;
971 ocm->isacntl = isacntl;
972 ocm->dsacntl = dsacntl;
973 }
974
975 static void ocm_reset (void *opaque)
976 {
977 ppc405_ocm_t *ocm;
978 uint32_t isarc, dsarc, isacntl, dsacntl;
979
980 ocm = opaque;
981 isarc = 0x00000000;
982 isacntl = 0x00000000;
983 dsarc = 0x00000000;
984 dsacntl = 0x00000000;
985 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
986 ocm->isarc = isarc;
987 ocm->dsarc = dsarc;
988 ocm->isacntl = isacntl;
989 ocm->dsacntl = dsacntl;
990 }
991
992 static void ppc405_ocm_init(CPUState *env)
993 {
994 ppc405_ocm_t *ocm;
995
996 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
997 ocm->offset = qemu_ram_alloc(4096);
998 qemu_register_reset(&ocm_reset, ocm);
999 ppc_dcr_register(env, OCM0_ISARC,
1000 ocm, &dcr_read_ocm, &dcr_write_ocm);
1001 ppc_dcr_register(env, OCM0_ISACNTL,
1002 ocm, &dcr_read_ocm, &dcr_write_ocm);
1003 ppc_dcr_register(env, OCM0_DSARC,
1004 ocm, &dcr_read_ocm, &dcr_write_ocm);
1005 ppc_dcr_register(env, OCM0_DSACNTL,
1006 ocm, &dcr_read_ocm, &dcr_write_ocm);
1007 }
1008
1009 /*****************************************************************************/
1010 /* I2C controller */
1011 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1012 struct ppc4xx_i2c_t {
1013 qemu_irq irq;
1014 uint8_t mdata;
1015 uint8_t lmadr;
1016 uint8_t hmadr;
1017 uint8_t cntl;
1018 uint8_t mdcntl;
1019 uint8_t sts;
1020 uint8_t extsts;
1021 uint8_t sdata;
1022 uint8_t lsadr;
1023 uint8_t hsadr;
1024 uint8_t clkdiv;
1025 uint8_t intrmsk;
1026 uint8_t xfrcnt;
1027 uint8_t xtcntlss;
1028 uint8_t directcntl;
1029 };
1030
1031 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1032 {
1033 ppc4xx_i2c_t *i2c;
1034 uint32_t ret;
1035
1036 #ifdef DEBUG_I2C
1037 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1038 #endif
1039 i2c = opaque;
1040 switch (addr) {
1041 case 0x00:
1042 // i2c_readbyte(&i2c->mdata);
1043 ret = i2c->mdata;
1044 break;
1045 case 0x02:
1046 ret = i2c->sdata;
1047 break;
1048 case 0x04:
1049 ret = i2c->lmadr;
1050 break;
1051 case 0x05:
1052 ret = i2c->hmadr;
1053 break;
1054 case 0x06:
1055 ret = i2c->cntl;
1056 break;
1057 case 0x07:
1058 ret = i2c->mdcntl;
1059 break;
1060 case 0x08:
1061 ret = i2c->sts;
1062 break;
1063 case 0x09:
1064 ret = i2c->extsts;
1065 break;
1066 case 0x0A:
1067 ret = i2c->lsadr;
1068 break;
1069 case 0x0B:
1070 ret = i2c->hsadr;
1071 break;
1072 case 0x0C:
1073 ret = i2c->clkdiv;
1074 break;
1075 case 0x0D:
1076 ret = i2c->intrmsk;
1077 break;
1078 case 0x0E:
1079 ret = i2c->xfrcnt;
1080 break;
1081 case 0x0F:
1082 ret = i2c->xtcntlss;
1083 break;
1084 case 0x10:
1085 ret = i2c->directcntl;
1086 break;
1087 default:
1088 ret = 0x00;
1089 break;
1090 }
1091 #ifdef DEBUG_I2C
1092 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1093 #endif
1094
1095 return ret;
1096 }
1097
1098 static void ppc4xx_i2c_writeb (void *opaque,
1099 target_phys_addr_t addr, uint32_t value)
1100 {
1101 ppc4xx_i2c_t *i2c;
1102
1103 #ifdef DEBUG_I2C
1104 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1105 value);
1106 #endif
1107 i2c = opaque;
1108 switch (addr) {
1109 case 0x00:
1110 i2c->mdata = value;
1111 // i2c_sendbyte(&i2c->mdata);
1112 break;
1113 case 0x02:
1114 i2c->sdata = value;
1115 break;
1116 case 0x04:
1117 i2c->lmadr = value;
1118 break;
1119 case 0x05:
1120 i2c->hmadr = value;
1121 break;
1122 case 0x06:
1123 i2c->cntl = value;
1124 break;
1125 case 0x07:
1126 i2c->mdcntl = value & 0xDF;
1127 break;
1128 case 0x08:
1129 i2c->sts &= ~(value & 0x0A);
1130 break;
1131 case 0x09:
1132 i2c->extsts &= ~(value & 0x8F);
1133 break;
1134 case 0x0A:
1135 i2c->lsadr = value;
1136 break;
1137 case 0x0B:
1138 i2c->hsadr = value;
1139 break;
1140 case 0x0C:
1141 i2c->clkdiv = value;
1142 break;
1143 case 0x0D:
1144 i2c->intrmsk = value;
1145 break;
1146 case 0x0E:
1147 i2c->xfrcnt = value & 0x77;
1148 break;
1149 case 0x0F:
1150 i2c->xtcntlss = value;
1151 break;
1152 case 0x10:
1153 i2c->directcntl = value & 0x7;
1154 break;
1155 }
1156 }
1157
1158 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1159 {
1160 uint32_t ret;
1161
1162 #ifdef DEBUG_I2C
1163 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1164 #endif
1165 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1166 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1167
1168 return ret;
1169 }
1170
1171 static void ppc4xx_i2c_writew (void *opaque,
1172 target_phys_addr_t addr, uint32_t value)
1173 {
1174 #ifdef DEBUG_I2C
1175 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1176 value);
1177 #endif
1178 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1179 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1180 }
1181
1182 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1183 {
1184 uint32_t ret;
1185
1186 #ifdef DEBUG_I2C
1187 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1188 #endif
1189 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1190 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1191 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1192 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1193
1194 return ret;
1195 }
1196
1197 static void ppc4xx_i2c_writel (void *opaque,
1198 target_phys_addr_t addr, uint32_t value)
1199 {
1200 #ifdef DEBUG_I2C
1201 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1202 value);
1203 #endif
1204 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1205 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1206 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1207 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1208 }
1209
1210 static CPUReadMemoryFunc * const i2c_read[] = {
1211 &ppc4xx_i2c_readb,
1212 &ppc4xx_i2c_readw,
1213 &ppc4xx_i2c_readl,
1214 };
1215
1216 static CPUWriteMemoryFunc * const i2c_write[] = {
1217 &ppc4xx_i2c_writeb,
1218 &ppc4xx_i2c_writew,
1219 &ppc4xx_i2c_writel,
1220 };
1221
1222 static void ppc4xx_i2c_reset (void *opaque)
1223 {
1224 ppc4xx_i2c_t *i2c;
1225
1226 i2c = opaque;
1227 i2c->mdata = 0x00;
1228 i2c->sdata = 0x00;
1229 i2c->cntl = 0x00;
1230 i2c->mdcntl = 0x00;
1231 i2c->sts = 0x00;
1232 i2c->extsts = 0x00;
1233 i2c->clkdiv = 0x00;
1234 i2c->xfrcnt = 0x00;
1235 i2c->directcntl = 0x0F;
1236 }
1237
1238 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1239 {
1240 ppc4xx_i2c_t *i2c;
1241 int io;
1242
1243 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1244 i2c->irq = irq;
1245 #ifdef DEBUG_I2C
1246 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1247 #endif
1248 io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
1249 cpu_register_physical_memory(base, 0x011, io);
1250 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1251 }
1252
1253 /*****************************************************************************/
1254 /* General purpose timers */
1255 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1256 struct ppc4xx_gpt_t {
1257 int64_t tb_offset;
1258 uint32_t tb_freq;
1259 struct QEMUTimer *timer;
1260 qemu_irq irqs[5];
1261 uint32_t oe;
1262 uint32_t ol;
1263 uint32_t im;
1264 uint32_t is;
1265 uint32_t ie;
1266 uint32_t comp[5];
1267 uint32_t mask[5];
1268 };
1269
1270 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1271 {
1272 #ifdef DEBUG_GPT
1273 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1274 #endif
1275 /* XXX: generate a bus fault */
1276 return -1;
1277 }
1278
1279 static void ppc4xx_gpt_writeb (void *opaque,
1280 target_phys_addr_t addr, uint32_t value)
1281 {
1282 #ifdef DEBUG_I2C
1283 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1284 value);
1285 #endif
1286 /* XXX: generate a bus fault */
1287 }
1288
1289 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1290 {
1291 #ifdef DEBUG_GPT
1292 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1293 #endif
1294 /* XXX: generate a bus fault */
1295 return -1;
1296 }
1297
1298 static void ppc4xx_gpt_writew (void *opaque,
1299 target_phys_addr_t addr, uint32_t value)
1300 {
1301 #ifdef DEBUG_I2C
1302 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1303 value);
1304 #endif
1305 /* XXX: generate a bus fault */
1306 }
1307
1308 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1309 {
1310 /* XXX: TODO */
1311 return 0;
1312 }
1313
1314 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1315 {
1316 /* XXX: TODO */
1317 }
1318
1319 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1320 {
1321 uint32_t mask;
1322 int i;
1323
1324 mask = 0x80000000;
1325 for (i = 0; i < 5; i++) {
1326 if (gpt->oe & mask) {
1327 /* Output is enabled */
1328 if (ppc4xx_gpt_compare(gpt, i)) {
1329 /* Comparison is OK */
1330 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1331 } else {
1332 /* Comparison is KO */
1333 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1334 }
1335 }
1336 mask = mask >> 1;
1337 }
1338 }
1339
1340 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1341 {
1342 uint32_t mask;
1343 int i;
1344
1345 mask = 0x00008000;
1346 for (i = 0; i < 5; i++) {
1347 if (gpt->is & gpt->im & mask)
1348 qemu_irq_raise(gpt->irqs[i]);
1349 else
1350 qemu_irq_lower(gpt->irqs[i]);
1351 mask = mask >> 1;
1352 }
1353 }
1354
1355 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1356 {
1357 /* XXX: TODO */
1358 }
1359
1360 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1361 {
1362 ppc4xx_gpt_t *gpt;
1363 uint32_t ret;
1364 int idx;
1365
1366 #ifdef DEBUG_GPT
1367 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1368 #endif
1369 gpt = opaque;
1370 switch (addr) {
1371 case 0x00:
1372 /* Time base counter */
1373 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1374 gpt->tb_freq, get_ticks_per_sec());
1375 break;
1376 case 0x10:
1377 /* Output enable */
1378 ret = gpt->oe;
1379 break;
1380 case 0x14:
1381 /* Output level */
1382 ret = gpt->ol;
1383 break;
1384 case 0x18:
1385 /* Interrupt mask */
1386 ret = gpt->im;
1387 break;
1388 case 0x1C:
1389 case 0x20:
1390 /* Interrupt status */
1391 ret = gpt->is;
1392 break;
1393 case 0x24:
1394 /* Interrupt enable */
1395 ret = gpt->ie;
1396 break;
1397 case 0x80 ... 0x90:
1398 /* Compare timer */
1399 idx = (addr - 0x80) >> 2;
1400 ret = gpt->comp[idx];
1401 break;
1402 case 0xC0 ... 0xD0:
1403 /* Compare mask */
1404 idx = (addr - 0xC0) >> 2;
1405 ret = gpt->mask[idx];
1406 break;
1407 default:
1408 ret = -1;
1409 break;
1410 }
1411
1412 return ret;
1413 }
1414
1415 static void ppc4xx_gpt_writel (void *opaque,
1416 target_phys_addr_t addr, uint32_t value)
1417 {
1418 ppc4xx_gpt_t *gpt;
1419 int idx;
1420
1421 #ifdef DEBUG_I2C
1422 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1423 value);
1424 #endif
1425 gpt = opaque;
1426 switch (addr) {
1427 case 0x00:
1428 /* Time base counter */
1429 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1430 - qemu_get_clock(vm_clock);
1431 ppc4xx_gpt_compute_timer(gpt);
1432 break;
1433 case 0x10:
1434 /* Output enable */
1435 gpt->oe = value & 0xF8000000;
1436 ppc4xx_gpt_set_outputs(gpt);
1437 break;
1438 case 0x14:
1439 /* Output level */
1440 gpt->ol = value & 0xF8000000;
1441 ppc4xx_gpt_set_outputs(gpt);
1442 break;
1443 case 0x18:
1444 /* Interrupt mask */
1445 gpt->im = value & 0x0000F800;
1446 break;
1447 case 0x1C:
1448 /* Interrupt status set */
1449 gpt->is |= value & 0x0000F800;
1450 ppc4xx_gpt_set_irqs(gpt);
1451 break;
1452 case 0x20:
1453 /* Interrupt status clear */
1454 gpt->is &= ~(value & 0x0000F800);
1455 ppc4xx_gpt_set_irqs(gpt);
1456 break;
1457 case 0x24:
1458 /* Interrupt enable */
1459 gpt->ie = value & 0x0000F800;
1460 ppc4xx_gpt_set_irqs(gpt);
1461 break;
1462 case 0x80 ... 0x90:
1463 /* Compare timer */
1464 idx = (addr - 0x80) >> 2;
1465 gpt->comp[idx] = value & 0xF8000000;
1466 ppc4xx_gpt_compute_timer(gpt);
1467 break;
1468 case 0xC0 ... 0xD0:
1469 /* Compare mask */
1470 idx = (addr - 0xC0) >> 2;
1471 gpt->mask[idx] = value & 0xF8000000;
1472 ppc4xx_gpt_compute_timer(gpt);
1473 break;
1474 }
1475 }
1476
1477 static CPUReadMemoryFunc * const gpt_read[] = {
1478 &ppc4xx_gpt_readb,
1479 &ppc4xx_gpt_readw,
1480 &ppc4xx_gpt_readl,
1481 };
1482
1483 static CPUWriteMemoryFunc * const gpt_write[] = {
1484 &ppc4xx_gpt_writeb,
1485 &ppc4xx_gpt_writew,
1486 &ppc4xx_gpt_writel,
1487 };
1488
1489 static void ppc4xx_gpt_cb (void *opaque)
1490 {
1491 ppc4xx_gpt_t *gpt;
1492
1493 gpt = opaque;
1494 ppc4xx_gpt_set_irqs(gpt);
1495 ppc4xx_gpt_set_outputs(gpt);
1496 ppc4xx_gpt_compute_timer(gpt);
1497 }
1498
1499 static void ppc4xx_gpt_reset (void *opaque)
1500 {
1501 ppc4xx_gpt_t *gpt;
1502 int i;
1503
1504 gpt = opaque;
1505 qemu_del_timer(gpt->timer);
1506 gpt->oe = 0x00000000;
1507 gpt->ol = 0x00000000;
1508 gpt->im = 0x00000000;
1509 gpt->is = 0x00000000;
1510 gpt->ie = 0x00000000;
1511 for (i = 0; i < 5; i++) {
1512 gpt->comp[i] = 0x00000000;
1513 gpt->mask[i] = 0x00000000;
1514 }
1515 }
1516
1517 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1518 {
1519 ppc4xx_gpt_t *gpt;
1520 int i;
1521 int io;
1522
1523 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1524 for (i = 0; i < 5; i++) {
1525 gpt->irqs[i] = irqs[i];
1526 }
1527 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1528 #ifdef DEBUG_GPT
1529 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1530 #endif
1531 io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
1532 cpu_register_physical_memory(base, 0x0d4, io);
1533 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1534 }
1535
1536 /*****************************************************************************/
1537 /* MAL */
1538 enum {
1539 MAL0_CFG = 0x180,
1540 MAL0_ESR = 0x181,
1541 MAL0_IER = 0x182,
1542 MAL0_TXCASR = 0x184,
1543 MAL0_TXCARR = 0x185,
1544 MAL0_TXEOBISR = 0x186,
1545 MAL0_TXDEIR = 0x187,
1546 MAL0_RXCASR = 0x190,
1547 MAL0_RXCARR = 0x191,
1548 MAL0_RXEOBISR = 0x192,
1549 MAL0_RXDEIR = 0x193,
1550 MAL0_TXCTP0R = 0x1A0,
1551 MAL0_TXCTP1R = 0x1A1,
1552 MAL0_TXCTP2R = 0x1A2,
1553 MAL0_TXCTP3R = 0x1A3,
1554 MAL0_RXCTP0R = 0x1C0,
1555 MAL0_RXCTP1R = 0x1C1,
1556 MAL0_RCBS0 = 0x1E0,
1557 MAL0_RCBS1 = 0x1E1,
1558 };
1559
1560 typedef struct ppc40x_mal_t ppc40x_mal_t;
1561 struct ppc40x_mal_t {
1562 qemu_irq irqs[4];
1563 uint32_t cfg;
1564 uint32_t esr;
1565 uint32_t ier;
1566 uint32_t txcasr;
1567 uint32_t txcarr;
1568 uint32_t txeobisr;
1569 uint32_t txdeir;
1570 uint32_t rxcasr;
1571 uint32_t rxcarr;
1572 uint32_t rxeobisr;
1573 uint32_t rxdeir;
1574 uint32_t txctpr[4];
1575 uint32_t rxctpr[2];
1576 uint32_t rcbs[2];
1577 };
1578
1579 static void ppc40x_mal_reset (void *opaque);
1580
1581 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1582 {
1583 ppc40x_mal_t *mal;
1584 uint32_t ret;
1585
1586 mal = opaque;
1587 switch (dcrn) {
1588 case MAL0_CFG:
1589 ret = mal->cfg;
1590 break;
1591 case MAL0_ESR:
1592 ret = mal->esr;
1593 break;
1594 case MAL0_IER:
1595 ret = mal->ier;
1596 break;
1597 case MAL0_TXCASR:
1598 ret = mal->txcasr;
1599 break;
1600 case MAL0_TXCARR:
1601 ret = mal->txcarr;
1602 break;
1603 case MAL0_TXEOBISR:
1604 ret = mal->txeobisr;
1605 break;
1606 case MAL0_TXDEIR:
1607 ret = mal->txdeir;
1608 break;
1609 case MAL0_RXCASR:
1610 ret = mal->rxcasr;
1611 break;
1612 case MAL0_RXCARR:
1613 ret = mal->rxcarr;
1614 break;
1615 case MAL0_RXEOBISR:
1616 ret = mal->rxeobisr;
1617 break;
1618 case MAL0_RXDEIR:
1619 ret = mal->rxdeir;
1620 break;
1621 case MAL0_TXCTP0R:
1622 ret = mal->txctpr[0];
1623 break;
1624 case MAL0_TXCTP1R:
1625 ret = mal->txctpr[1];
1626 break;
1627 case MAL0_TXCTP2R:
1628 ret = mal->txctpr[2];
1629 break;
1630 case MAL0_TXCTP3R:
1631 ret = mal->txctpr[3];
1632 break;
1633 case MAL0_RXCTP0R:
1634 ret = mal->rxctpr[0];
1635 break;
1636 case MAL0_RXCTP1R:
1637 ret = mal->rxctpr[1];
1638 break;
1639 case MAL0_RCBS0:
1640 ret = mal->rcbs[0];
1641 break;
1642 case MAL0_RCBS1:
1643 ret = mal->rcbs[1];
1644 break;
1645 default:
1646 ret = 0;
1647 break;
1648 }
1649
1650 return ret;
1651 }
1652
1653 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1654 {
1655 ppc40x_mal_t *mal;
1656 int idx;
1657
1658 mal = opaque;
1659 switch (dcrn) {
1660 case MAL0_CFG:
1661 if (val & 0x80000000)
1662 ppc40x_mal_reset(mal);
1663 mal->cfg = val & 0x00FFC087;
1664 break;
1665 case MAL0_ESR:
1666 /* Read/clear */
1667 mal->esr &= ~val;
1668 break;
1669 case MAL0_IER:
1670 mal->ier = val & 0x0000001F;
1671 break;
1672 case MAL0_TXCASR:
1673 mal->txcasr = val & 0xF0000000;
1674 break;
1675 case MAL0_TXCARR:
1676 mal->txcarr = val & 0xF0000000;
1677 break;
1678 case MAL0_TXEOBISR:
1679 /* Read/clear */
1680 mal->txeobisr &= ~val;
1681 break;
1682 case MAL0_TXDEIR:
1683 /* Read/clear */
1684 mal->txdeir &= ~val;
1685 break;
1686 case MAL0_RXCASR:
1687 mal->rxcasr = val & 0xC0000000;
1688 break;
1689 case MAL0_RXCARR:
1690 mal->rxcarr = val & 0xC0000000;
1691 break;
1692 case MAL0_RXEOBISR:
1693 /* Read/clear */
1694 mal->rxeobisr &= ~val;
1695 break;
1696 case MAL0_RXDEIR:
1697 /* Read/clear */
1698 mal->rxdeir &= ~val;
1699 break;
1700 case MAL0_TXCTP0R:
1701 idx = 0;
1702 goto update_tx_ptr;
1703 case MAL0_TXCTP1R:
1704 idx = 1;
1705 goto update_tx_ptr;
1706 case MAL0_TXCTP2R:
1707 idx = 2;
1708 goto update_tx_ptr;
1709 case MAL0_TXCTP3R:
1710 idx = 3;
1711 update_tx_ptr:
1712 mal->txctpr[idx] = val;
1713 break;
1714 case MAL0_RXCTP0R:
1715 idx = 0;
1716 goto update_rx_ptr;
1717 case MAL0_RXCTP1R:
1718 idx = 1;
1719 update_rx_ptr:
1720 mal->rxctpr[idx] = val;
1721 break;
1722 case MAL0_RCBS0:
1723 idx = 0;
1724 goto update_rx_size;
1725 case MAL0_RCBS1:
1726 idx = 1;
1727 update_rx_size:
1728 mal->rcbs[idx] = val & 0x000000FF;
1729 break;
1730 }
1731 }
1732
1733 static void ppc40x_mal_reset (void *opaque)
1734 {
1735 ppc40x_mal_t *mal;
1736
1737 mal = opaque;
1738 mal->cfg = 0x0007C000;
1739 mal->esr = 0x00000000;
1740 mal->ier = 0x00000000;
1741 mal->rxcasr = 0x00000000;
1742 mal->rxdeir = 0x00000000;
1743 mal->rxeobisr = 0x00000000;
1744 mal->txcasr = 0x00000000;
1745 mal->txdeir = 0x00000000;
1746 mal->txeobisr = 0x00000000;
1747 }
1748
1749 static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
1750 {
1751 ppc40x_mal_t *mal;
1752 int i;
1753
1754 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
1755 for (i = 0; i < 4; i++)
1756 mal->irqs[i] = irqs[i];
1757 qemu_register_reset(&ppc40x_mal_reset, mal);
1758 ppc_dcr_register(env, MAL0_CFG,
1759 mal, &dcr_read_mal, &dcr_write_mal);
1760 ppc_dcr_register(env, MAL0_ESR,
1761 mal, &dcr_read_mal, &dcr_write_mal);
1762 ppc_dcr_register(env, MAL0_IER,
1763 mal, &dcr_read_mal, &dcr_write_mal);
1764 ppc_dcr_register(env, MAL0_TXCASR,
1765 mal, &dcr_read_mal, &dcr_write_mal);
1766 ppc_dcr_register(env, MAL0_TXCARR,
1767 mal, &dcr_read_mal, &dcr_write_mal);
1768 ppc_dcr_register(env, MAL0_TXEOBISR,
1769 mal, &dcr_read_mal, &dcr_write_mal);
1770 ppc_dcr_register(env, MAL0_TXDEIR,
1771 mal, &dcr_read_mal, &dcr_write_mal);
1772 ppc_dcr_register(env, MAL0_RXCASR,
1773 mal, &dcr_read_mal, &dcr_write_mal);
1774 ppc_dcr_register(env, MAL0_RXCARR,
1775 mal, &dcr_read_mal, &dcr_write_mal);
1776 ppc_dcr_register(env, MAL0_RXEOBISR,
1777 mal, &dcr_read_mal, &dcr_write_mal);
1778 ppc_dcr_register(env, MAL0_RXDEIR,
1779 mal, &dcr_read_mal, &dcr_write_mal);
1780 ppc_dcr_register(env, MAL0_TXCTP0R,
1781 mal, &dcr_read_mal, &dcr_write_mal);
1782 ppc_dcr_register(env, MAL0_TXCTP1R,
1783 mal, &dcr_read_mal, &dcr_write_mal);
1784 ppc_dcr_register(env, MAL0_TXCTP2R,
1785 mal, &dcr_read_mal, &dcr_write_mal);
1786 ppc_dcr_register(env, MAL0_TXCTP3R,
1787 mal, &dcr_read_mal, &dcr_write_mal);
1788 ppc_dcr_register(env, MAL0_RXCTP0R,
1789 mal, &dcr_read_mal, &dcr_write_mal);
1790 ppc_dcr_register(env, MAL0_RXCTP1R,
1791 mal, &dcr_read_mal, &dcr_write_mal);
1792 ppc_dcr_register(env, MAL0_RCBS0,
1793 mal, &dcr_read_mal, &dcr_write_mal);
1794 ppc_dcr_register(env, MAL0_RCBS1,
1795 mal, &dcr_read_mal, &dcr_write_mal);
1796 }
1797
1798 /*****************************************************************************/
1799 /* SPR */
1800 void ppc40x_core_reset (CPUState *env)
1801 {
1802 target_ulong dbsr;
1803
1804 printf("Reset PowerPC core\n");
1805 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1806 /* XXX: TOFIX */
1807 #if 0
1808 cpu_reset(env);
1809 #else
1810 qemu_system_reset_request();
1811 #endif
1812 dbsr = env->spr[SPR_40x_DBSR];
1813 dbsr &= ~0x00000300;
1814 dbsr |= 0x00000100;
1815 env->spr[SPR_40x_DBSR] = dbsr;
1816 }
1817
1818 void ppc40x_chip_reset (CPUState *env)
1819 {
1820 target_ulong dbsr;
1821
1822 printf("Reset PowerPC chip\n");
1823 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1824 /* XXX: TOFIX */
1825 #if 0
1826 cpu_reset(env);
1827 #else
1828 qemu_system_reset_request();
1829 #endif
1830 /* XXX: TODO reset all internal peripherals */
1831 dbsr = env->spr[SPR_40x_DBSR];
1832 dbsr &= ~0x00000300;
1833 dbsr |= 0x00000200;
1834 env->spr[SPR_40x_DBSR] = dbsr;
1835 }
1836
1837 void ppc40x_system_reset (CPUState *env)
1838 {
1839 printf("Reset PowerPC system\n");
1840 qemu_system_reset_request();
1841 }
1842
1843 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1844 {
1845 switch ((val >> 28) & 0x3) {
1846 case 0x0:
1847 /* No action */
1848 break;
1849 case 0x1:
1850 /* Core reset */
1851 ppc40x_core_reset(env);
1852 break;
1853 case 0x2:
1854 /* Chip reset */
1855 ppc40x_chip_reset(env);
1856 break;
1857 case 0x3:
1858 /* System reset */
1859 ppc40x_system_reset(env);
1860 break;
1861 }
1862 }
1863
1864 /*****************************************************************************/
1865 /* PowerPC 405CR */
1866 enum {
1867 PPC405CR_CPC0_PLLMR = 0x0B0,
1868 PPC405CR_CPC0_CR0 = 0x0B1,
1869 PPC405CR_CPC0_CR1 = 0x0B2,
1870 PPC405CR_CPC0_PSR = 0x0B4,
1871 PPC405CR_CPC0_JTAGID = 0x0B5,
1872 PPC405CR_CPC0_ER = 0x0B9,
1873 PPC405CR_CPC0_FR = 0x0BA,
1874 PPC405CR_CPC0_SR = 0x0BB,
1875 };
1876
1877 enum {
1878 PPC405CR_CPU_CLK = 0,
1879 PPC405CR_TMR_CLK = 1,
1880 PPC405CR_PLB_CLK = 2,
1881 PPC405CR_SDRAM_CLK = 3,
1882 PPC405CR_OPB_CLK = 4,
1883 PPC405CR_EXT_CLK = 5,
1884 PPC405CR_UART_CLK = 6,
1885 PPC405CR_CLK_NB = 7,
1886 };
1887
1888 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1889 struct ppc405cr_cpc_t {
1890 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1891 uint32_t sysclk;
1892 uint32_t psr;
1893 uint32_t cr0;
1894 uint32_t cr1;
1895 uint32_t jtagid;
1896 uint32_t pllmr;
1897 uint32_t er;
1898 uint32_t fr;
1899 };
1900
1901 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1902 {
1903 uint64_t VCO_out, PLL_out;
1904 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1905 int M, D0, D1, D2;
1906
1907 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1908 if (cpc->pllmr & 0x80000000) {
1909 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1910 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1911 M = D0 * D1 * D2;
1912 VCO_out = cpc->sysclk * M;
1913 if (VCO_out < 400000000 || VCO_out > 800000000) {
1914 /* PLL cannot lock */
1915 cpc->pllmr &= ~0x80000000;
1916 goto bypass_pll;
1917 }
1918 PLL_out = VCO_out / D2;
1919 } else {
1920 /* Bypass PLL */
1921 bypass_pll:
1922 M = D0;
1923 PLL_out = cpc->sysclk * M;
1924 }
1925 CPU_clk = PLL_out;
1926 if (cpc->cr1 & 0x00800000)
1927 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1928 else
1929 TMR_clk = CPU_clk;
1930 PLB_clk = CPU_clk / D0;
1931 SDRAM_clk = PLB_clk;
1932 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1933 OPB_clk = PLB_clk / D0;
1934 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1935 EXT_clk = PLB_clk / D0;
1936 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1937 UART_clk = CPU_clk / D0;
1938 /* Setup CPU clocks */
1939 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1940 /* Setup time-base clock */
1941 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1942 /* Setup PLB clock */
1943 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1944 /* Setup SDRAM clock */
1945 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1946 /* Setup OPB clock */
1947 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1948 /* Setup external clock */
1949 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1950 /* Setup UART clock */
1951 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1952 }
1953
1954 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1955 {
1956 ppc405cr_cpc_t *cpc;
1957 uint32_t ret;
1958
1959 cpc = opaque;
1960 switch (dcrn) {
1961 case PPC405CR_CPC0_PLLMR:
1962 ret = cpc->pllmr;
1963 break;
1964 case PPC405CR_CPC0_CR0:
1965 ret = cpc->cr0;
1966 break;
1967 case PPC405CR_CPC0_CR1:
1968 ret = cpc->cr1;
1969 break;
1970 case PPC405CR_CPC0_PSR:
1971 ret = cpc->psr;
1972 break;
1973 case PPC405CR_CPC0_JTAGID:
1974 ret = cpc->jtagid;
1975 break;
1976 case PPC405CR_CPC0_ER:
1977 ret = cpc->er;
1978 break;
1979 case PPC405CR_CPC0_FR:
1980 ret = cpc->fr;
1981 break;
1982 case PPC405CR_CPC0_SR:
1983 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1984 break;
1985 default:
1986 /* Avoid gcc warning */
1987 ret = 0;
1988 break;
1989 }
1990
1991 return ret;
1992 }
1993
1994 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1995 {
1996 ppc405cr_cpc_t *cpc;
1997
1998 cpc = opaque;
1999 switch (dcrn) {
2000 case PPC405CR_CPC0_PLLMR:
2001 cpc->pllmr = val & 0xFFF77C3F;
2002 break;
2003 case PPC405CR_CPC0_CR0:
2004 cpc->cr0 = val & 0x0FFFFFFE;
2005 break;
2006 case PPC405CR_CPC0_CR1:
2007 cpc->cr1 = val & 0x00800000;
2008 break;
2009 case PPC405CR_CPC0_PSR:
2010 /* Read-only */
2011 break;
2012 case PPC405CR_CPC0_JTAGID:
2013 /* Read-only */
2014 break;
2015 case PPC405CR_CPC0_ER:
2016 cpc->er = val & 0xBFFC0000;
2017 break;
2018 case PPC405CR_CPC0_FR:
2019 cpc->fr = val & 0xBFFC0000;
2020 break;
2021 case PPC405CR_CPC0_SR:
2022 /* Read-only */
2023 break;
2024 }
2025 }
2026
2027 static void ppc405cr_cpc_reset (void *opaque)
2028 {
2029 ppc405cr_cpc_t *cpc;
2030 int D;
2031
2032 cpc = opaque;
2033 /* Compute PLLMR value from PSR settings */
2034 cpc->pllmr = 0x80000000;
2035 /* PFWD */
2036 switch ((cpc->psr >> 30) & 3) {
2037 case 0:
2038 /* Bypass */
2039 cpc->pllmr &= ~0x80000000;
2040 break;
2041 case 1:
2042 /* Divide by 3 */
2043 cpc->pllmr |= 5 << 16;
2044 break;
2045 case 2:
2046 /* Divide by 4 */
2047 cpc->pllmr |= 4 << 16;
2048 break;
2049 case 3:
2050 /* Divide by 6 */
2051 cpc->pllmr |= 2 << 16;
2052 break;
2053 }
2054 /* PFBD */
2055 D = (cpc->psr >> 28) & 3;
2056 cpc->pllmr |= (D + 1) << 20;
2057 /* PT */
2058 D = (cpc->psr >> 25) & 7;
2059 switch (D) {
2060 case 0x2:
2061 cpc->pllmr |= 0x13;
2062 break;
2063 case 0x4:
2064 cpc->pllmr |= 0x15;
2065 break;
2066 case 0x5:
2067 cpc->pllmr |= 0x16;
2068 break;
2069 default:
2070 break;
2071 }
2072 /* PDC */
2073 D = (cpc->psr >> 23) & 3;
2074 cpc->pllmr |= D << 26;
2075 /* ODP */
2076 D = (cpc->psr >> 21) & 3;
2077 cpc->pllmr |= D << 10;
2078 /* EBPD */
2079 D = (cpc->psr >> 17) & 3;
2080 cpc->pllmr |= D << 24;
2081 cpc->cr0 = 0x0000003C;
2082 cpc->cr1 = 0x2B0D8800;
2083 cpc->er = 0x00000000;
2084 cpc->fr = 0x00000000;
2085 ppc405cr_clk_setup(cpc);
2086 }
2087
2088 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2089 {
2090 int D;
2091
2092 /* XXX: this should be read from IO pins */
2093 cpc->psr = 0x00000000; /* 8 bits ROM */
2094 /* PFWD */
2095 D = 0x2; /* Divide by 4 */
2096 cpc->psr |= D << 30;
2097 /* PFBD */
2098 D = 0x1; /* Divide by 2 */
2099 cpc->psr |= D << 28;
2100 /* PDC */
2101 D = 0x1; /* Divide by 2 */
2102 cpc->psr |= D << 23;
2103 /* PT */
2104 D = 0x5; /* M = 16 */
2105 cpc->psr |= D << 25;
2106 /* ODP */
2107 D = 0x1; /* Divide by 2 */
2108 cpc->psr |= D << 21;
2109 /* EBDP */
2110 D = 0x2; /* Divide by 4 */
2111 cpc->psr |= D << 17;
2112 }
2113
2114 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2115 uint32_t sysclk)
2116 {
2117 ppc405cr_cpc_t *cpc;
2118
2119 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2120 memcpy(cpc->clk_setup, clk_setup,
2121 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2122 cpc->sysclk = sysclk;
2123 cpc->jtagid = 0x42051049;
2124 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2125 &dcr_read_crcpc, &dcr_write_crcpc);
2126 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2127 &dcr_read_crcpc, &dcr_write_crcpc);
2128 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2129 &dcr_read_crcpc, &dcr_write_crcpc);
2130 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2131 &dcr_read_crcpc, &dcr_write_crcpc);
2132 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2133 &dcr_read_crcpc, &dcr_write_crcpc);
2134 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2135 &dcr_read_crcpc, &dcr_write_crcpc);
2136 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2137 &dcr_read_crcpc, &dcr_write_crcpc);
2138 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2139 &dcr_read_crcpc, &dcr_write_crcpc);
2140 ppc405cr_clk_init(cpc);
2141 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2142 }
2143
2144 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2145 target_phys_addr_t ram_sizes[4],
2146 uint32_t sysclk, qemu_irq **picp,
2147 int do_init)
2148 {
2149 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2150 qemu_irq dma_irqs[4];
2151 CPUState *env;
2152 qemu_irq *pic, *irqs;
2153
2154 memset(clk_setup, 0, sizeof(clk_setup));
2155 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2156 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2157 /* Memory mapped devices registers */
2158 /* PLB arbitrer */
2159 ppc4xx_plb_init(env);
2160 /* PLB to OPB bridge */
2161 ppc4xx_pob_init(env);
2162 /* OBP arbitrer */
2163 ppc4xx_opba_init(0xef600600);
2164 /* Universal interrupt controller */
2165 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2166 irqs[PPCUIC_OUTPUT_INT] =
2167 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2168 irqs[PPCUIC_OUTPUT_CINT] =
2169 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2170 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2171 *picp = pic;
2172 /* SDRAM controller */
2173 ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2174 /* External bus controller */
2175 ppc405_ebc_init(env);
2176 /* DMA controller */
2177 dma_irqs[0] = pic[26];
2178 dma_irqs[1] = pic[25];
2179 dma_irqs[2] = pic[24];
2180 dma_irqs[3] = pic[23];
2181 ppc405_dma_init(env, dma_irqs);
2182 /* Serial ports */
2183 if (serial_hds[0] != NULL) {
2184 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2185 serial_hds[0], 1);
2186 }
2187 if (serial_hds[1] != NULL) {
2188 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2189 serial_hds[1], 1);
2190 }
2191 /* IIC controller */
2192 ppc405_i2c_init(0xef600500, pic[2]);
2193 /* GPIO */
2194 ppc405_gpio_init(0xef600700);
2195 /* CPU control */
2196 ppc405cr_cpc_init(env, clk_setup, sysclk);
2197
2198 return env;
2199 }
2200
2201 /*****************************************************************************/
2202 /* PowerPC 405EP */
2203 /* CPU control */
2204 enum {
2205 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2206 PPC405EP_CPC0_BOOT = 0x0F1,
2207 PPC405EP_CPC0_EPCTL = 0x0F3,
2208 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2209 PPC405EP_CPC0_UCR = 0x0F5,
2210 PPC405EP_CPC0_SRR = 0x0F6,
2211 PPC405EP_CPC0_JTAGID = 0x0F7,
2212 PPC405EP_CPC0_PCI = 0x0F9,
2213 #if 0
2214 PPC405EP_CPC0_ER = xxx,
2215 PPC405EP_CPC0_FR = xxx,
2216 PPC405EP_CPC0_SR = xxx,
2217 #endif
2218 };
2219
2220 enum {
2221 PPC405EP_CPU_CLK = 0,
2222 PPC405EP_PLB_CLK = 1,
2223 PPC405EP_OPB_CLK = 2,
2224 PPC405EP_EBC_CLK = 3,
2225 PPC405EP_MAL_CLK = 4,
2226 PPC405EP_PCI_CLK = 5,
2227 PPC405EP_UART0_CLK = 6,
2228 PPC405EP_UART1_CLK = 7,
2229 PPC405EP_CLK_NB = 8,
2230 };
2231
2232 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2233 struct ppc405ep_cpc_t {
2234 uint32_t sysclk;
2235 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2236 uint32_t boot;
2237 uint32_t epctl;
2238 uint32_t pllmr[2];
2239 uint32_t ucr;
2240 uint32_t srr;
2241 uint32_t jtagid;
2242 uint32_t pci;
2243 /* Clock and power management */
2244 uint32_t er;
2245 uint32_t fr;
2246 uint32_t sr;
2247 };
2248
2249 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2250 {
2251 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2252 uint32_t UART0_clk, UART1_clk;
2253 uint64_t VCO_out, PLL_out;
2254 int M, D;
2255
2256 VCO_out = 0;
2257 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2258 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2259 #ifdef DEBUG_CLOCKS_LL
2260 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2261 #endif
2262 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2263 #ifdef DEBUG_CLOCKS_LL
2264 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2265 #endif
2266 VCO_out = cpc->sysclk * M * D;
2267 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2268 /* Error - unlock the PLL */
2269 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2270 #if 0
2271 cpc->pllmr[1] &= ~0x80000000;
2272 goto pll_bypass;
2273 #endif
2274 }
2275 PLL_out = VCO_out / D;
2276 /* Pretend the PLL is locked */
2277 cpc->boot |= 0x00000001;
2278 } else {
2279 #if 0
2280 pll_bypass:
2281 #endif
2282 PLL_out = cpc->sysclk;
2283 if (cpc->pllmr[1] & 0x40000000) {
2284 /* Pretend the PLL is not locked */
2285 cpc->boot &= ~0x00000001;
2286 }
2287 }
2288 /* Now, compute all other clocks */
2289 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2290 #ifdef DEBUG_CLOCKS_LL
2291 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2292 #endif
2293 CPU_clk = PLL_out / D;
2294 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2295 #ifdef DEBUG_CLOCKS_LL
2296 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2297 #endif
2298 PLB_clk = CPU_clk / D;
2299 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2300 #ifdef DEBUG_CLOCKS_LL
2301 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2302 #endif
2303 OPB_clk = PLB_clk / D;
2304 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2305 #ifdef DEBUG_CLOCKS_LL
2306 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2307 #endif
2308 EBC_clk = PLB_clk / D;
2309 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2310 #ifdef DEBUG_CLOCKS_LL
2311 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2312 #endif
2313 MAL_clk = PLB_clk / D;
2314 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2315 #ifdef DEBUG_CLOCKS_LL
2316 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2317 #endif
2318 PCI_clk = PLB_clk / D;
2319 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2320 #ifdef DEBUG_CLOCKS_LL
2321 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2322 #endif
2323 UART0_clk = PLL_out / D;
2324 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2325 #ifdef DEBUG_CLOCKS_LL
2326 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2327 #endif
2328 UART1_clk = PLL_out / D;
2329 #ifdef DEBUG_CLOCKS
2330 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2331 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2332 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2333 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2334 " UART1 %" PRIu32 "\n",
2335 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2336 UART0_clk, UART1_clk);
2337 #endif
2338 /* Setup CPU clocks */
2339 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2340 /* Setup PLB clock */
2341 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2342 /* Setup OPB clock */
2343 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2344 /* Setup external clock */
2345 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2346 /* Setup MAL clock */
2347 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2348 /* Setup PCI clock */
2349 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2350 /* Setup UART0 clock */
2351 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2352 /* Setup UART1 clock */
2353 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2354 }
2355
2356 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2357 {
2358 ppc405ep_cpc_t *cpc;
2359 uint32_t ret;
2360
2361 cpc = opaque;
2362 switch (dcrn) {
2363 case PPC405EP_CPC0_BOOT:
2364 ret = cpc->boot;
2365 break;
2366 case PPC405EP_CPC0_EPCTL:
2367 ret = cpc->epctl;
2368 break;
2369 case PPC405EP_CPC0_PLLMR0:
2370 ret = cpc->pllmr[0];
2371 break;
2372 case PPC405EP_CPC0_PLLMR1:
2373 ret = cpc->pllmr[1];
2374 break;
2375 case PPC405EP_CPC0_UCR:
2376 ret = cpc->ucr;
2377 break;
2378 case PPC405EP_CPC0_SRR:
2379 ret = cpc->srr;
2380 break;
2381 case PPC405EP_CPC0_JTAGID:
2382 ret = cpc->jtagid;
2383 break;
2384 case PPC405EP_CPC0_PCI:
2385 ret = cpc->pci;
2386 break;
2387 default:
2388 /* Avoid gcc warning */
2389 ret = 0;
2390 break;
2391 }
2392
2393 return ret;
2394 }
2395
2396 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2397 {
2398 ppc405ep_cpc_t *cpc;
2399
2400 cpc = opaque;
2401 switch (dcrn) {
2402 case PPC405EP_CPC0_BOOT:
2403 /* Read-only register */
2404 break;
2405 case PPC405EP_CPC0_EPCTL:
2406 /* Don't care for now */
2407 cpc->epctl = val & 0xC00000F3;
2408 break;
2409 case PPC405EP_CPC0_PLLMR0:
2410 cpc->pllmr[0] = val & 0x00633333;
2411 ppc405ep_compute_clocks(cpc);
2412 break;
2413 case PPC405EP_CPC0_PLLMR1:
2414 cpc->pllmr[1] = val & 0xC0F73FFF;
2415 ppc405ep_compute_clocks(cpc);
2416 break;
2417 case PPC405EP_CPC0_UCR:
2418 /* UART control - don't care for now */
2419 cpc->ucr = val & 0x003F7F7F;
2420 break;
2421 case PPC405EP_CPC0_SRR:
2422 cpc->srr = val;
2423 break;
2424 case PPC405EP_CPC0_JTAGID:
2425 /* Read-only */
2426 break;
2427 case PPC405EP_CPC0_PCI:
2428 cpc->pci = val;
2429 break;
2430 }
2431 }
2432
2433 static void ppc405ep_cpc_reset (void *opaque)
2434 {
2435 ppc405ep_cpc_t *cpc = opaque;
2436
2437 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2438 cpc->epctl = 0x00000000;
2439 cpc->pllmr[0] = 0x00011010;
2440 cpc->pllmr[1] = 0x40000000;
2441 cpc->ucr = 0x00000000;
2442 cpc->srr = 0x00040000;
2443 cpc->pci = 0x00000000;
2444 cpc->er = 0x00000000;
2445 cpc->fr = 0x00000000;
2446 cpc->sr = 0x00000000;
2447 ppc405ep_compute_clocks(cpc);
2448 }
2449
2450 /* XXX: sysclk should be between 25 and 100 MHz */
2451 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2452 uint32_t sysclk)
2453 {
2454 ppc405ep_cpc_t *cpc;
2455
2456 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2457 memcpy(cpc->clk_setup, clk_setup,
2458 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2459 cpc->jtagid = 0x20267049;
2460 cpc->sysclk = sysclk;
2461 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2462 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2463 &dcr_read_epcpc, &dcr_write_epcpc);
2464 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2465 &dcr_read_epcpc, &dcr_write_epcpc);
2466 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2467 &dcr_read_epcpc, &dcr_write_epcpc);
2468 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2469 &dcr_read_epcpc, &dcr_write_epcpc);
2470 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2471 &dcr_read_epcpc, &dcr_write_epcpc);
2472 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2473 &dcr_read_epcpc, &dcr_write_epcpc);
2474 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2475 &dcr_read_epcpc, &dcr_write_epcpc);
2476 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2477 &dcr_read_epcpc, &dcr_write_epcpc);
2478 #if 0
2479 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2480 &dcr_read_epcpc, &dcr_write_epcpc);
2481 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2482 &dcr_read_epcpc, &dcr_write_epcpc);
2483 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2484 &dcr_read_epcpc, &dcr_write_epcpc);
2485 #endif
2486 }
2487
2488 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2489 target_phys_addr_t ram_sizes[2],
2490 uint32_t sysclk, qemu_irq **picp,
2491 int do_init)
2492 {
2493 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2494 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2495 CPUState *env;
2496 qemu_irq *pic, *irqs;
2497
2498 memset(clk_setup, 0, sizeof(clk_setup));
2499 /* init CPUs */
2500 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2501 &tlb_clk_setup, sysclk);
2502 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2503 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2504 /* Internal devices init */
2505 /* Memory mapped devices registers */
2506 /* PLB arbitrer */
2507 ppc4xx_plb_init(env);
2508 /* PLB to OPB bridge */
2509 ppc4xx_pob_init(env);
2510 /* OBP arbitrer */
2511 ppc4xx_opba_init(0xef600600);
2512 /* Universal interrupt controller */
2513 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2514 irqs[PPCUIC_OUTPUT_INT] =
2515 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2516 irqs[PPCUIC_OUTPUT_CINT] =
2517 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2518 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2519 *picp = pic;
2520 /* SDRAM controller */
2521 /* XXX 405EP has no ECC interrupt */
2522 ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2523 /* External bus controller */
2524 ppc405_ebc_init(env);
2525 /* DMA controller */
2526 dma_irqs[0] = pic[5];
2527 dma_irqs[1] = pic[6];
2528 dma_irqs[2] = pic[7];
2529 dma_irqs[3] = pic[8];
2530 ppc405_dma_init(env, dma_irqs);
2531 /* IIC controller */
2532 ppc405_i2c_init(0xef600500, pic[2]);
2533 /* GPIO */
2534 ppc405_gpio_init(0xef600700);
2535 /* Serial ports */
2536 if (serial_hds[0] != NULL) {
2537 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2538 serial_hds[0], 1);
2539 }
2540 if (serial_hds[1] != NULL) {
2541 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2542 serial_hds[1], 1);
2543 }
2544 /* OCM */
2545 ppc405_ocm_init(env);
2546 /* GPT */
2547 gpt_irqs[0] = pic[19];
2548 gpt_irqs[1] = pic[20];
2549 gpt_irqs[2] = pic[21];
2550 gpt_irqs[3] = pic[22];
2551 gpt_irqs[4] = pic[23];
2552 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2553 /* PCI */
2554 /* Uses pic[3], pic[16], pic[18] */
2555 /* MAL */
2556 mal_irqs[0] = pic[11];
2557 mal_irqs[1] = pic[12];
2558 mal_irqs[2] = pic[13];
2559 mal_irqs[3] = pic[14];
2560 ppc405_mal_init(env, mal_irqs);
2561 /* Ethernet */
2562 /* Uses pic[9], pic[15], pic[17] */
2563 /* CPU control */
2564 ppc405ep_cpc_init(env, clk_setup, sysclk);
2565
2566 return env;
2567 }
CRIS target port of Qemu