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block: rename BlockAcctType members to start with BLOCK_ instead of BDRV_
[qemu/cris-port.git] / hw / ide / core.c
blob43b4c1bd9845329ac0729f4eb710bbfdd1220801
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/isa/isa.h>
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "hw/block/block.h"
34 #include "sysemu/blockdev.h"
35
36 #include <hw/ide/internal.h>
37
38 /* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40 static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
56 };
57
58 static int ide_handle_rw_error(IDEState *s, int error, int op);
59 static void ide_dummy_transfer_stop(IDEState *s);
60
61 static void padstr(char *str, const char *src, int len)
62 {
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71 }
72
73 static void put_le16(uint16_t *p, unsigned int v)
74 {
75 *p = cpu_to_le16(v);
76 }
77
78 static void ide_identify_size(IDEState *s)
79 {
80 uint16_t *p = (uint16_t *)s->identify_data;
81 put_le16(p + 60, s->nb_sectors);
82 put_le16(p + 61, s->nb_sectors >> 16);
83 put_le16(p + 100, s->nb_sectors);
84 put_le16(p + 101, s->nb_sectors >> 16);
85 put_le16(p + 102, s->nb_sectors >> 32);
86 put_le16(p + 103, s->nb_sectors >> 48);
87 }
88
89 static void ide_identify(IDEState *s)
90 {
91 uint16_t *p;
92 unsigned int oldsize;
93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
94
95 p = (uint16_t *)s->identify_data;
96 if (s->identify_set) {
97 goto fill_buffer;
98 }
99 memset(p, 0, sizeof(s->identify_data));
100
101 put_le16(p + 0, 0x0040);
102 put_le16(p + 1, s->cylinders);
103 put_le16(p + 3, s->heads);
104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
105 put_le16(p + 5, 512); /* XXX: retired, remove ? */
106 put_le16(p + 6, s->sectors);
107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
108 put_le16(p + 20, 3); /* XXX: retired, remove ? */
109 put_le16(p + 21, 512); /* cache size in sectors */
110 put_le16(p + 22, 4); /* ecc bytes */
111 padstr((char *)(p + 23), s->version, 8); /* firmware version */
112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
113 #if MAX_MULT_SECTORS > 1
114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
115 #endif
116 put_le16(p + 48, 1); /* dword I/O */
117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
118 put_le16(p + 51, 0x200); /* PIO transfer cycle */
119 put_le16(p + 52, 0x200); /* DMA transfer cycle */
120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
121 put_le16(p + 54, s->cylinders);
122 put_le16(p + 55, s->heads);
123 put_le16(p + 56, s->sectors);
124 oldsize = s->cylinders * s->heads * s->sectors;
125 put_le16(p + 57, oldsize);
126 put_le16(p + 58, oldsize >> 16);
127 if (s->mult_sectors)
128 put_le16(p + 59, 0x100 | s->mult_sectors);
129 /* *(p + 60) := nb_sectors -- see ide_identify_size */
130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
132 put_le16(p + 63, 0x07); /* mdma0-2 supported */
133 put_le16(p + 64, 0x03); /* pio3-4 supported */
134 put_le16(p + 65, 120);
135 put_le16(p + 66, 120);
136 put_le16(p + 67, 120);
137 put_le16(p + 68, 120);
138 if (dev && dev->conf.discard_granularity) {
139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
140 }
141
142 if (s->ncq_queues) {
143 put_le16(p + 75, s->ncq_queues - 1);
144 /* NCQ supported */
145 put_le16(p + 76, (1 << 8));
146 }
147
148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
149 put_le16(p + 81, 0x16); /* conforms to ata5 */
150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
155 if (s->wwn) {
156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
157 } else {
158 put_le16(p + 84, (1 << 14) | 0);
159 }
160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
161 if (bdrv_enable_write_cache(s->bs))
162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
163 else
164 put_le16(p + 85, (1 << 14) | 1);
165 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
166 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
167 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
168 if (s->wwn) {
169 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
170 } else {
171 put_le16(p + 87, (1 << 14) | 0);
172 }
173 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
174 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
175 /* *(p + 100) := nb_sectors -- see ide_identify_size */
176 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
177 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
178 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
179
180 if (dev && dev->conf.physical_block_size)
181 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
182 if (s->wwn) {
183 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
184 put_le16(p + 108, s->wwn >> 48);
185 put_le16(p + 109, s->wwn >> 32);
186 put_le16(p + 110, s->wwn >> 16);
187 put_le16(p + 111, s->wwn);
188 }
189 if (dev && dev->conf.discard_granularity) {
190 put_le16(p + 169, 1); /* TRIM support */
191 }
192
193 ide_identify_size(s);
194 s->identify_set = 1;
195
196 fill_buffer:
197 memcpy(s->io_buffer, p, sizeof(s->identify_data));
198 }
199
200 static void ide_atapi_identify(IDEState *s)
201 {
202 uint16_t *p;
203
204 p = (uint16_t *)s->identify_data;
205 if (s->identify_set) {
206 goto fill_buffer;
207 }
208 memset(p, 0, sizeof(s->identify_data));
209
210 /* Removable CDROM, 50us response, 12 byte packets */
211 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
212 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
213 put_le16(p + 20, 3); /* buffer type */
214 put_le16(p + 21, 512); /* cache size in sectors */
215 put_le16(p + 22, 4); /* ecc bytes */
216 padstr((char *)(p + 23), s->version, 8); /* firmware version */
217 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
218 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
219 #ifdef USE_DMA_CDROM
220 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
221 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
222 put_le16(p + 62, 7); /* single word dma0-2 supported */
223 put_le16(p + 63, 7); /* mdma0-2 supported */
224 #else
225 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
226 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
227 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
228 #endif
229 put_le16(p + 64, 3); /* pio3-4 supported */
230 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
231 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
232 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
233 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
234
235 put_le16(p + 71, 30); /* in ns */
236 put_le16(p + 72, 30); /* in ns */
237
238 if (s->ncq_queues) {
239 put_le16(p + 75, s->ncq_queues - 1);
240 /* NCQ supported */
241 put_le16(p + 76, (1 << 8));
242 }
243
244 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
245 if (s->wwn) {
246 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
247 put_le16(p + 87, (1 << 8)); /* WWN enabled */
248 }
249
250 #ifdef USE_DMA_CDROM
251 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
252 #endif
253
254 if (s->wwn) {
255 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
256 put_le16(p + 108, s->wwn >> 48);
257 put_le16(p + 109, s->wwn >> 32);
258 put_le16(p + 110, s->wwn >> 16);
259 put_le16(p + 111, s->wwn);
260 }
261
262 s->identify_set = 1;
263
264 fill_buffer:
265 memcpy(s->io_buffer, p, sizeof(s->identify_data));
266 }
267
268 static void ide_cfata_identify_size(IDEState *s)
269 {
270 uint16_t *p = (uint16_t *)s->identify_data;
271 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
272 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
273 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
274 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
275 }
276
277 static void ide_cfata_identify(IDEState *s)
278 {
279 uint16_t *p;
280 uint32_t cur_sec;
281
282 p = (uint16_t *)s->identify_data;
283 if (s->identify_set) {
284 goto fill_buffer;
285 }
286 memset(p, 0, sizeof(s->identify_data));
287
288 cur_sec = s->cylinders * s->heads * s->sectors;
289
290 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
291 put_le16(p + 1, s->cylinders); /* Default cylinders */
292 put_le16(p + 3, s->heads); /* Default heads */
293 put_le16(p + 6, s->sectors); /* Default sectors per track */
294 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
295 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
296 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
297 put_le16(p + 22, 0x0004); /* ECC bytes */
298 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
299 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
300 #if MAX_MULT_SECTORS > 1
301 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
302 #else
303 put_le16(p + 47, 0x0000);
304 #endif
305 put_le16(p + 49, 0x0f00); /* Capabilities */
306 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
307 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
308 put_le16(p + 53, 0x0003); /* Translation params valid */
309 put_le16(p + 54, s->cylinders); /* Current cylinders */
310 put_le16(p + 55, s->heads); /* Current heads */
311 put_le16(p + 56, s->sectors); /* Current sectors */
312 put_le16(p + 57, cur_sec); /* Current capacity */
313 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
314 if (s->mult_sectors) /* Multiple sector setting */
315 put_le16(p + 59, 0x100 | s->mult_sectors);
316 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
317 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
318 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
319 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
320 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
321 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
322 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
323 put_le16(p + 82, 0x400c); /* Command Set supported */
324 put_le16(p + 83, 0x7068); /* Command Set supported */
325 put_le16(p + 84, 0x4000); /* Features supported */
326 put_le16(p + 85, 0x000c); /* Command Set enabled */
327 put_le16(p + 86, 0x7044); /* Command Set enabled */
328 put_le16(p + 87, 0x4000); /* Features enabled */
329 put_le16(p + 91, 0x4060); /* Current APM level */
330 put_le16(p + 129, 0x0002); /* Current features option */
331 put_le16(p + 130, 0x0005); /* Reassigned sectors */
332 put_le16(p + 131, 0x0001); /* Initial power mode */
333 put_le16(p + 132, 0x0000); /* User signature */
334 put_le16(p + 160, 0x8100); /* Power requirement */
335 put_le16(p + 161, 0x8001); /* CF command set */
336
337 ide_cfata_identify_size(s);
338 s->identify_set = 1;
339
340 fill_buffer:
341 memcpy(s->io_buffer, p, sizeof(s->identify_data));
342 }
343
344 static void ide_set_signature(IDEState *s)
345 {
346 s->select &= 0xf0; /* clear head */
347 /* put signature */
348 s->nsector = 1;
349 s->sector = 1;
350 if (s->drive_kind == IDE_CD) {
351 s->lcyl = 0x14;
352 s->hcyl = 0xeb;
353 } else if (s->bs) {
354 s->lcyl = 0;
355 s->hcyl = 0;
356 } else {
357 s->lcyl = 0xff;
358 s->hcyl = 0xff;
359 }
360 }
361
362 typedef struct TrimAIOCB {
363 BlockDriverAIOCB common;
364 QEMUBH *bh;
365 int ret;
366 QEMUIOVector *qiov;
367 BlockDriverAIOCB *aiocb;
368 int i, j;
369 } TrimAIOCB;
370
371 static void trim_aio_cancel(BlockDriverAIOCB *acb)
372 {
373 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
374
375 /* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */
376 iocb->j = iocb->qiov->niov - 1;
377 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
378
379 /* Tell ide_issue_trim_cb not to trigger the completion, too. */
380 qemu_bh_delete(iocb->bh);
381 iocb->bh = NULL;
382
383 if (iocb->aiocb) {
384 bdrv_aio_cancel(iocb->aiocb);
385 }
386 qemu_aio_release(iocb);
387 }
388
389 static const AIOCBInfo trim_aiocb_info = {
390 .aiocb_size = sizeof(TrimAIOCB),
391 .cancel = trim_aio_cancel,
392 };
393
394 static void ide_trim_bh_cb(void *opaque)
395 {
396 TrimAIOCB *iocb = opaque;
397
398 iocb->common.cb(iocb->common.opaque, iocb->ret);
399
400 qemu_bh_delete(iocb->bh);
401 iocb->bh = NULL;
402 qemu_aio_release(iocb);
403 }
404
405 static void ide_issue_trim_cb(void *opaque, int ret)
406 {
407 TrimAIOCB *iocb = opaque;
408 if (ret >= 0) {
409 while (iocb->j < iocb->qiov->niov) {
410 int j = iocb->j;
411 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
412 int i = iocb->i;
413 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
414
415 /* 6-byte LBA + 2-byte range per entry */
416 uint64_t entry = le64_to_cpu(buffer[i]);
417 uint64_t sector = entry & 0x0000ffffffffffffULL;
418 uint16_t count = entry >> 48;
419
420 if (count == 0) {
421 continue;
422 }
423
424 /* Got an entry! Submit and exit. */
425 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
426 ide_issue_trim_cb, opaque);
427 return;
428 }
429
430 iocb->j++;
431 iocb->i = -1;
432 }
433 } else {
434 iocb->ret = ret;
435 }
436
437 iocb->aiocb = NULL;
438 if (iocb->bh) {
439 qemu_bh_schedule(iocb->bh);
440 }
441 }
442
443 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
444 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
445 BlockDriverCompletionFunc *cb, void *opaque)
446 {
447 TrimAIOCB *iocb;
448
449 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
450 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
451 iocb->ret = 0;
452 iocb->qiov = qiov;
453 iocb->i = -1;
454 iocb->j = 0;
455 ide_issue_trim_cb(iocb, 0);
456 return &iocb->common;
457 }
458
459 static inline void ide_abort_command(IDEState *s)
460 {
461 ide_transfer_stop(s);
462 s->status = READY_STAT | ERR_STAT;
463 s->error = ABRT_ERR;
464 }
465
466 /* prepare data transfer and tell what to do after */
467 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
468 EndTransferFunc *end_transfer_func)
469 {
470 s->end_transfer_func = end_transfer_func;
471 s->data_ptr = buf;
472 s->data_end = buf + size;
473 if (!(s->status & ERR_STAT)) {
474 s->status |= DRQ_STAT;
475 }
476 if (s->bus->dma->ops->start_transfer) {
477 s->bus->dma->ops->start_transfer(s->bus->dma);
478 }
479 }
480
481 static void ide_cmd_done(IDEState *s)
482 {
483 if (s->bus->dma->ops->cmd_done) {
484 s->bus->dma->ops->cmd_done(s->bus->dma);
485 }
486 }
487
488 void ide_transfer_stop(IDEState *s)
489 {
490 s->end_transfer_func = ide_transfer_stop;
491 s->data_ptr = s->io_buffer;
492 s->data_end = s->io_buffer;
493 s->status &= ~DRQ_STAT;
494 ide_cmd_done(s);
495 }
496
497 int64_t ide_get_sector(IDEState *s)
498 {
499 int64_t sector_num;
500 if (s->select & 0x40) {
501 /* lba */
502 if (!s->lba48) {
503 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
504 (s->lcyl << 8) | s->sector;
505 } else {
506 sector_num = ((int64_t)s->hob_hcyl << 40) |
507 ((int64_t) s->hob_lcyl << 32) |
508 ((int64_t) s->hob_sector << 24) |
509 ((int64_t) s->hcyl << 16) |
510 ((int64_t) s->lcyl << 8) | s->sector;
511 }
512 } else {
513 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
514 (s->select & 0x0f) * s->sectors + (s->sector - 1);
515 }
516 return sector_num;
517 }
518
519 void ide_set_sector(IDEState *s, int64_t sector_num)
520 {
521 unsigned int cyl, r;
522 if (s->select & 0x40) {
523 if (!s->lba48) {
524 s->select = (s->select & 0xf0) | (sector_num >> 24);
525 s->hcyl = (sector_num >> 16);
526 s->lcyl = (sector_num >> 8);
527 s->sector = (sector_num);
528 } else {
529 s->sector = sector_num;
530 s->lcyl = sector_num >> 8;
531 s->hcyl = sector_num >> 16;
532 s->hob_sector = sector_num >> 24;
533 s->hob_lcyl = sector_num >> 32;
534 s->hob_hcyl = sector_num >> 40;
535 }
536 } else {
537 cyl = sector_num / (s->heads * s->sectors);
538 r = sector_num % (s->heads * s->sectors);
539 s->hcyl = cyl >> 8;
540 s->lcyl = cyl;
541 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
542 s->sector = (r % s->sectors) + 1;
543 }
544 }
545
546 static void ide_rw_error(IDEState *s) {
547 ide_abort_command(s);
548 ide_set_irq(s->bus);
549 }
550
551 static bool ide_sect_range_ok(IDEState *s,
552 uint64_t sector, uint64_t nb_sectors)
553 {
554 uint64_t total_sectors;
555
556 bdrv_get_geometry(s->bs, &total_sectors);
557 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
558 return false;
559 }
560 return true;
561 }
562
563 static void ide_sector_read_cb(void *opaque, int ret)
564 {
565 IDEState *s = opaque;
566 int n;
567
568 s->pio_aiocb = NULL;
569 s->status &= ~BUSY_STAT;
570
571 bdrv_acct_done(s->bs, &s->acct);
572 if (ret != 0) {
573 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
574 IDE_RETRY_READ)) {
575 return;
576 }
577 }
578
579 n = s->nsector;
580 if (n > s->req_nb_sectors) {
581 n = s->req_nb_sectors;
582 }
583
584 /* Allow the guest to read the io_buffer */
585 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
586
587 ide_set_irq(s->bus);
588
589 ide_set_sector(s, ide_get_sector(s) + n);
590 s->nsector -= n;
591 }
592
593 void ide_sector_read(IDEState *s)
594 {
595 int64_t sector_num;
596 int n;
597
598 s->status = READY_STAT | SEEK_STAT;
599 s->error = 0; /* not needed by IDE spec, but needed by Windows */
600 sector_num = ide_get_sector(s);
601 n = s->nsector;
602
603 if (n == 0) {
604 ide_transfer_stop(s);
605 return;
606 }
607
608 s->status |= BUSY_STAT;
609
610 if (n > s->req_nb_sectors) {
611 n = s->req_nb_sectors;
612 }
613
614 #if defined(DEBUG_IDE)
615 printf("sector=%" PRId64 "\n", sector_num);
616 #endif
617
618 if (!ide_sect_range_ok(s, sector_num, n)) {
619 ide_rw_error(s);
620 return;
621 }
622
623 s->iov.iov_base = s->io_buffer;
624 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
625 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
626
627 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
628 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
629 ide_sector_read_cb, s);
630 }
631
632 static void dma_buf_commit(IDEState *s)
633 {
634 qemu_sglist_destroy(&s->sg);
635 }
636
637 void ide_set_inactive(IDEState *s, bool more)
638 {
639 s->bus->dma->aiocb = NULL;
640 if (s->bus->dma->ops->set_inactive) {
641 s->bus->dma->ops->set_inactive(s->bus->dma, more);
642 }
643 ide_cmd_done(s);
644 }
645
646 void ide_dma_error(IDEState *s)
647 {
648 ide_abort_command(s);
649 ide_set_inactive(s, false);
650 ide_set_irq(s->bus);
651 }
652
653 static int ide_handle_rw_error(IDEState *s, int error, int op)
654 {
655 bool is_read = (op & IDE_RETRY_READ) != 0;
656 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
657
658 if (action == BLOCK_ERROR_ACTION_STOP) {
659 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
660 s->bus->error_status = op;
661 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
662 if (op & IDE_RETRY_DMA) {
663 dma_buf_commit(s);
664 ide_dma_error(s);
665 } else {
666 ide_rw_error(s);
667 }
668 }
669 bdrv_error_action(s->bs, action, is_read, error);
670 return action != BLOCK_ERROR_ACTION_IGNORE;
671 }
672
673 void ide_dma_cb(void *opaque, int ret)
674 {
675 IDEState *s = opaque;
676 int n;
677 int64_t sector_num;
678 bool stay_active = false;
679
680 if (ret < 0) {
681 int op = IDE_RETRY_DMA;
682
683 if (s->dma_cmd == IDE_DMA_READ)
684 op |= IDE_RETRY_READ;
685 else if (s->dma_cmd == IDE_DMA_TRIM)
686 op |= IDE_RETRY_TRIM;
687
688 if (ide_handle_rw_error(s, -ret, op)) {
689 return;
690 }
691 }
692
693 n = s->io_buffer_size >> 9;
694 if (n > s->nsector) {
695 /* The PRDs were longer than needed for this request. Shorten them so
696 * we don't get a negative remainder. The Active bit must remain set
697 * after the request completes. */
698 n = s->nsector;
699 stay_active = true;
700 }
701
702 sector_num = ide_get_sector(s);
703 if (n > 0) {
704 dma_buf_commit(s);
705 sector_num += n;
706 ide_set_sector(s, sector_num);
707 s->nsector -= n;
708 }
709
710 /* end of transfer ? */
711 if (s->nsector == 0) {
712 s->status = READY_STAT | SEEK_STAT;
713 ide_set_irq(s->bus);
714 goto eot;
715 }
716
717 /* launch next transfer */
718 n = s->nsector;
719 s->io_buffer_index = 0;
720 s->io_buffer_size = n * 512;
721 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
722 /* The PRDs were too short. Reset the Active bit, but don't raise an
723 * interrupt. */
724 s->status = READY_STAT | SEEK_STAT;
725 goto eot;
726 }
727
728 #ifdef DEBUG_AIO
729 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
730 sector_num, n, s->dma_cmd);
731 #endif
732
733 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
734 !ide_sect_range_ok(s, sector_num, n)) {
735 dma_buf_commit(s);
736 ide_dma_error(s);
737 return;
738 }
739
740 switch (s->dma_cmd) {
741 case IDE_DMA_READ:
742 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
743 ide_dma_cb, s);
744 break;
745 case IDE_DMA_WRITE:
746 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
747 ide_dma_cb, s);
748 break;
749 case IDE_DMA_TRIM:
750 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
751 ide_issue_trim, ide_dma_cb, s,
752 DMA_DIRECTION_TO_DEVICE);
753 break;
754 }
755 return;
756
757 eot:
758 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
759 bdrv_acct_done(s->bs, &s->acct);
760 }
761 ide_set_inactive(s, stay_active);
762 }
763
764 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
765 {
766 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
767 s->io_buffer_index = 0;
768 s->io_buffer_size = 0;
769 s->dma_cmd = dma_cmd;
770
771 switch (dma_cmd) {
772 case IDE_DMA_READ:
773 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
774 BLOCK_ACCT_READ);
775 break;
776 case IDE_DMA_WRITE:
777 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
778 BLOCK_ACCT_WRITE);
779 break;
780 default:
781 break;
782 }
783
784 ide_start_dma(s, ide_dma_cb);
785 }
786
787 void ide_start_dma(IDEState *s, BlockDriverCompletionFunc *cb)
788 {
789 if (s->bus->dma->ops->start_dma) {
790 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
791 }
792 }
793
794 static void ide_sector_write_timer_cb(void *opaque)
795 {
796 IDEState *s = opaque;
797 ide_set_irq(s->bus);
798 }
799
800 static void ide_sector_write_cb(void *opaque, int ret)
801 {
802 IDEState *s = opaque;
803 int n;
804
805 bdrv_acct_done(s->bs, &s->acct);
806
807 s->pio_aiocb = NULL;
808 s->status &= ~BUSY_STAT;
809
810 if (ret != 0) {
811 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
812 return;
813 }
814 }
815
816 n = s->nsector;
817 if (n > s->req_nb_sectors) {
818 n = s->req_nb_sectors;
819 }
820 s->nsector -= n;
821 if (s->nsector == 0) {
822 /* no more sectors to write */
823 ide_transfer_stop(s);
824 } else {
825 int n1 = s->nsector;
826 if (n1 > s->req_nb_sectors) {
827 n1 = s->req_nb_sectors;
828 }
829 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
830 ide_sector_write);
831 }
832 ide_set_sector(s, ide_get_sector(s) + n);
833
834 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
835 /* It seems there is a bug in the Windows 2000 installer HDD
836 IDE driver which fills the disk with empty logs when the
837 IDE write IRQ comes too early. This hack tries to correct
838 that at the expense of slower write performances. Use this
839 option _only_ to install Windows 2000. You must disable it
840 for normal use. */
841 timer_mod(s->sector_write_timer,
842 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
843 } else {
844 ide_set_irq(s->bus);
845 }
846 }
847
848 void ide_sector_write(IDEState *s)
849 {
850 int64_t sector_num;
851 int n;
852
853 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
854 sector_num = ide_get_sector(s);
855 #if defined(DEBUG_IDE)
856 printf("sector=%" PRId64 "\n", sector_num);
857 #endif
858 n = s->nsector;
859 if (n > s->req_nb_sectors) {
860 n = s->req_nb_sectors;
861 }
862
863 if (!ide_sect_range_ok(s, sector_num, n)) {
864 ide_rw_error(s);
865 return;
866 }
867
868 s->iov.iov_base = s->io_buffer;
869 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
870 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
871
872 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
873 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
874 ide_sector_write_cb, s);
875 }
876
877 static void ide_flush_cb(void *opaque, int ret)
878 {
879 IDEState *s = opaque;
880
881 s->pio_aiocb = NULL;
882
883 if (ret < 0) {
884 /* XXX: What sector number to set here? */
885 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
886 return;
887 }
888 }
889
890 if (s->bs) {
891 bdrv_acct_done(s->bs, &s->acct);
892 }
893 s->status = READY_STAT | SEEK_STAT;
894 ide_cmd_done(s);
895 ide_set_irq(s->bus);
896 }
897
898 void ide_flush_cache(IDEState *s)
899 {
900 if (s->bs == NULL) {
901 ide_flush_cb(s, 0);
902 return;
903 }
904
905 s->status |= BUSY_STAT;
906 bdrv_acct_start(s->bs, &s->acct, 0, BLOCK_ACCT_FLUSH);
907 s->pio_aiocb = bdrv_aio_flush(s->bs, ide_flush_cb, s);
908 }
909
910 static void ide_cfata_metadata_inquiry(IDEState *s)
911 {
912 uint16_t *p;
913 uint32_t spd;
914
915 p = (uint16_t *) s->io_buffer;
916 memset(p, 0, 0x200);
917 spd = ((s->mdata_size - 1) >> 9) + 1;
918
919 put_le16(p + 0, 0x0001); /* Data format revision */
920 put_le16(p + 1, 0x0000); /* Media property: silicon */
921 put_le16(p + 2, s->media_changed); /* Media status */
922 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
923 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
924 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
925 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
926 }
927
928 static void ide_cfata_metadata_read(IDEState *s)
929 {
930 uint16_t *p;
931
932 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
933 s->status = ERR_STAT;
934 s->error = ABRT_ERR;
935 return;
936 }
937
938 p = (uint16_t *) s->io_buffer;
939 memset(p, 0, 0x200);
940
941 put_le16(p + 0, s->media_changed); /* Media status */
942 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
943 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
944 s->nsector << 9), 0x200 - 2));
945 }
946
947 static void ide_cfata_metadata_write(IDEState *s)
948 {
949 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
950 s->status = ERR_STAT;
951 s->error = ABRT_ERR;
952 return;
953 }
954
955 s->media_changed = 0;
956
957 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
958 s->io_buffer + 2,
959 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
960 s->nsector << 9), 0x200 - 2));
961 }
962
963 /* called when the inserted state of the media has changed */
964 static void ide_cd_change_cb(void *opaque, bool load)
965 {
966 IDEState *s = opaque;
967 uint64_t nb_sectors;
968
969 s->tray_open = !load;
970 bdrv_get_geometry(s->bs, &nb_sectors);
971 s->nb_sectors = nb_sectors;
972
973 /*
974 * First indicate to the guest that a CD has been removed. That's
975 * done on the next command the guest sends us.
976 *
977 * Then we set UNIT_ATTENTION, by which the guest will
978 * detect a new CD in the drive. See ide_atapi_cmd() for details.
979 */
980 s->cdrom_changed = 1;
981 s->events.new_media = true;
982 s->events.eject_request = false;
983 ide_set_irq(s->bus);
984 }
985
986 static void ide_cd_eject_request_cb(void *opaque, bool force)
987 {
988 IDEState *s = opaque;
989
990 s->events.eject_request = true;
991 if (force) {
992 s->tray_locked = false;
993 }
994 ide_set_irq(s->bus);
995 }
996
997 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
998 {
999 s->lba48 = lba48;
1000
1001 /* handle the 'magic' 0 nsector count conversion here. to avoid
1002 * fiddling with the rest of the read logic, we just store the
1003 * full sector count in ->nsector and ignore ->hob_nsector from now
1004 */
1005 if (!s->lba48) {
1006 if (!s->nsector)
1007 s->nsector = 256;
1008 } else {
1009 if (!s->nsector && !s->hob_nsector)
1010 s->nsector = 65536;
1011 else {
1012 int lo = s->nsector;
1013 int hi = s->hob_nsector;
1014
1015 s->nsector = (hi << 8) | lo;
1016 }
1017 }
1018 }
1019
1020 static void ide_clear_hob(IDEBus *bus)
1021 {
1022 /* any write clears HOB high bit of device control register */
1023 bus->ifs[0].select &= ~(1 << 7);
1024 bus->ifs[1].select &= ~(1 << 7);
1025 }
1026
1027 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1028 {
1029 IDEBus *bus = opaque;
1030
1031 #ifdef DEBUG_IDE
1032 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1033 #endif
1034
1035 addr &= 7;
1036
1037 /* ignore writes to command block while busy with previous command */
1038 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1039 return;
1040
1041 switch(addr) {
1042 case 0:
1043 break;
1044 case 1:
1045 ide_clear_hob(bus);
1046 /* NOTE: data is written to the two drives */
1047 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1048 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1049 bus->ifs[0].feature = val;
1050 bus->ifs[1].feature = val;
1051 break;
1052 case 2:
1053 ide_clear_hob(bus);
1054 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1055 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1056 bus->ifs[0].nsector = val;
1057 bus->ifs[1].nsector = val;
1058 break;
1059 case 3:
1060 ide_clear_hob(bus);
1061 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1062 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1063 bus->ifs[0].sector = val;
1064 bus->ifs[1].sector = val;
1065 break;
1066 case 4:
1067 ide_clear_hob(bus);
1068 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1069 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1070 bus->ifs[0].lcyl = val;
1071 bus->ifs[1].lcyl = val;
1072 break;
1073 case 5:
1074 ide_clear_hob(bus);
1075 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1076 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1077 bus->ifs[0].hcyl = val;
1078 bus->ifs[1].hcyl = val;
1079 break;
1080 case 6:
1081 /* FIXME: HOB readback uses bit 7 */
1082 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1083 bus->ifs[1].select = (val | 0x10) | 0xa0;
1084 /* select drive */
1085 bus->unit = (val >> 4) & 1;
1086 break;
1087 default:
1088 case 7:
1089 /* command */
1090 ide_exec_cmd(bus, val);
1091 break;
1092 }
1093 }
1094
1095 static bool cmd_nop(IDEState *s, uint8_t cmd)
1096 {
1097 return true;
1098 }
1099
1100 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1101 {
1102 switch (s->feature) {
1103 case DSM_TRIM:
1104 if (s->bs) {
1105 ide_sector_start_dma(s, IDE_DMA_TRIM);
1106 return false;
1107 }
1108 break;
1109 }
1110
1111 ide_abort_command(s);
1112 return true;
1113 }
1114
1115 static bool cmd_identify(IDEState *s, uint8_t cmd)
1116 {
1117 if (s->bs && s->drive_kind != IDE_CD) {
1118 if (s->drive_kind != IDE_CFATA) {
1119 ide_identify(s);
1120 } else {
1121 ide_cfata_identify(s);
1122 }
1123 s->status = READY_STAT | SEEK_STAT;
1124 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1125 ide_set_irq(s->bus);
1126 return false;
1127 } else {
1128 if (s->drive_kind == IDE_CD) {
1129 ide_set_signature(s);
1130 }
1131 ide_abort_command(s);
1132 }
1133
1134 return true;
1135 }
1136
1137 static bool cmd_verify(IDEState *s, uint8_t cmd)
1138 {
1139 bool lba48 = (cmd == WIN_VERIFY_EXT);
1140
1141 /* do sector number check ? */
1142 ide_cmd_lba48_transform(s, lba48);
1143
1144 return true;
1145 }
1146
1147 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1148 {
1149 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1150 /* Disable Read and Write Multiple */
1151 s->mult_sectors = 0;
1152 } else if ((s->nsector & 0xff) != 0 &&
1153 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1154 (s->nsector & (s->nsector - 1)) != 0)) {
1155 ide_abort_command(s);
1156 } else {
1157 s->mult_sectors = s->nsector & 0xff;
1158 }
1159
1160 return true;
1161 }
1162
1163 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1164 {
1165 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1166
1167 if (!s->bs || !s->mult_sectors) {
1168 ide_abort_command(s);
1169 return true;
1170 }
1171
1172 ide_cmd_lba48_transform(s, lba48);
1173 s->req_nb_sectors = s->mult_sectors;
1174 ide_sector_read(s);
1175 return false;
1176 }
1177
1178 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1179 {
1180 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1181 int n;
1182
1183 if (!s->bs || !s->mult_sectors) {
1184 ide_abort_command(s);
1185 return true;
1186 }
1187
1188 ide_cmd_lba48_transform(s, lba48);
1189
1190 s->req_nb_sectors = s->mult_sectors;
1191 n = MIN(s->nsector, s->req_nb_sectors);
1192
1193 s->status = SEEK_STAT | READY_STAT;
1194 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1195
1196 s->media_changed = 1;
1197
1198 return false;
1199 }
1200
1201 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1202 {
1203 bool lba48 = (cmd == WIN_READ_EXT);
1204
1205 if (s->drive_kind == IDE_CD) {
1206 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1207 ide_abort_command(s);
1208 return true;
1209 }
1210
1211 if (!s->bs) {
1212 ide_abort_command(s);
1213 return true;
1214 }
1215
1216 ide_cmd_lba48_transform(s, lba48);
1217 s->req_nb_sectors = 1;
1218 ide_sector_read(s);
1219
1220 return false;
1221 }
1222
1223 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1224 {
1225 bool lba48 = (cmd == WIN_WRITE_EXT);
1226
1227 if (!s->bs) {
1228 ide_abort_command(s);
1229 return true;
1230 }
1231
1232 ide_cmd_lba48_transform(s, lba48);
1233
1234 s->req_nb_sectors = 1;
1235 s->status = SEEK_STAT | READY_STAT;
1236 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1237
1238 s->media_changed = 1;
1239
1240 return false;
1241 }
1242
1243 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1244 {
1245 bool lba48 = (cmd == WIN_READDMA_EXT);
1246
1247 if (!s->bs) {
1248 ide_abort_command(s);
1249 return true;
1250 }
1251
1252 ide_cmd_lba48_transform(s, lba48);
1253 ide_sector_start_dma(s, IDE_DMA_READ);
1254
1255 return false;
1256 }
1257
1258 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1259 {
1260 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1261
1262 if (!s->bs) {
1263 ide_abort_command(s);
1264 return true;
1265 }
1266
1267 ide_cmd_lba48_transform(s, lba48);
1268 ide_sector_start_dma(s, IDE_DMA_WRITE);
1269
1270 s->media_changed = 1;
1271
1272 return false;
1273 }
1274
1275 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1276 {
1277 ide_flush_cache(s);
1278 return false;
1279 }
1280
1281 static bool cmd_seek(IDEState *s, uint8_t cmd)
1282 {
1283 /* XXX: Check that seek is within bounds */
1284 return true;
1285 }
1286
1287 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1288 {
1289 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1290
1291 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1292 if (s->nb_sectors == 0) {
1293 ide_abort_command(s);
1294 return true;
1295 }
1296
1297 ide_cmd_lba48_transform(s, lba48);
1298 ide_set_sector(s, s->nb_sectors - 1);
1299
1300 return true;
1301 }
1302
1303 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1304 {
1305 s->nsector = 0xff; /* device active or idle */
1306 return true;
1307 }
1308
1309 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1310 {
1311 uint16_t *identify_data;
1312
1313 if (!s->bs) {
1314 ide_abort_command(s);
1315 return true;
1316 }
1317
1318 /* XXX: valid for CDROM ? */
1319 switch (s->feature) {
1320 case 0x02: /* write cache enable */
1321 bdrv_set_enable_write_cache(s->bs, true);
1322 identify_data = (uint16_t *)s->identify_data;
1323 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1324 return true;
1325 case 0x82: /* write cache disable */
1326 bdrv_set_enable_write_cache(s->bs, false);
1327 identify_data = (uint16_t *)s->identify_data;
1328 put_le16(identify_data + 85, (1 << 14) | 1);
1329 ide_flush_cache(s);
1330 return false;
1331 case 0xcc: /* reverting to power-on defaults enable */
1332 case 0x66: /* reverting to power-on defaults disable */
1333 case 0xaa: /* read look-ahead enable */
1334 case 0x55: /* read look-ahead disable */
1335 case 0x05: /* set advanced power management mode */
1336 case 0x85: /* disable advanced power management mode */
1337 case 0x69: /* NOP */
1338 case 0x67: /* NOP */
1339 case 0x96: /* NOP */
1340 case 0x9a: /* NOP */
1341 case 0x42: /* enable Automatic Acoustic Mode */
1342 case 0xc2: /* disable Automatic Acoustic Mode */
1343 return true;
1344 case 0x03: /* set transfer mode */
1345 {
1346 uint8_t val = s->nsector & 0x07;
1347 identify_data = (uint16_t *)s->identify_data;
1348
1349 switch (s->nsector >> 3) {
1350 case 0x00: /* pio default */
1351 case 0x01: /* pio mode */
1352 put_le16(identify_data + 62, 0x07);
1353 put_le16(identify_data + 63, 0x07);
1354 put_le16(identify_data + 88, 0x3f);
1355 break;
1356 case 0x02: /* sigle word dma mode*/
1357 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1358 put_le16(identify_data + 63, 0x07);
1359 put_le16(identify_data + 88, 0x3f);
1360 break;
1361 case 0x04: /* mdma mode */
1362 put_le16(identify_data + 62, 0x07);
1363 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1364 put_le16(identify_data + 88, 0x3f);
1365 break;
1366 case 0x08: /* udma mode */
1367 put_le16(identify_data + 62, 0x07);
1368 put_le16(identify_data + 63, 0x07);
1369 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1370 break;
1371 default:
1372 goto abort_cmd;
1373 }
1374 return true;
1375 }
1376 }
1377
1378 abort_cmd:
1379 ide_abort_command(s);
1380 return true;
1381 }
1382
1383
1384 /*** ATAPI commands ***/
1385
1386 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1387 {
1388 ide_atapi_identify(s);
1389 s->status = READY_STAT | SEEK_STAT;
1390 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1391 ide_set_irq(s->bus);
1392 return false;
1393 }
1394
1395 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1396 {
1397 ide_set_signature(s);
1398
1399 if (s->drive_kind == IDE_CD) {
1400 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1401 * devices to return a clear status register
1402 * with READY_STAT *not* set. */
1403 s->error = 0x01;
1404 } else {
1405 s->status = READY_STAT | SEEK_STAT;
1406 /* The bits of the error register are not as usual for this command!
1407 * They are part of the regular output (this is why ERR_STAT isn't set)
1408 * Device 0 passed, Device 1 passed or not present. */
1409 s->error = 0x01;
1410 ide_set_irq(s->bus);
1411 }
1412
1413 return false;
1414 }
1415
1416 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1417 {
1418 ide_set_signature(s);
1419 s->status = 0x00; /* NOTE: READY is _not_ set */
1420 s->error = 0x01;
1421
1422 return false;
1423 }
1424
1425 static bool cmd_packet(IDEState *s, uint8_t cmd)
1426 {
1427 /* overlapping commands not supported */
1428 if (s->feature & 0x02) {
1429 ide_abort_command(s);
1430 return true;
1431 }
1432
1433 s->status = READY_STAT | SEEK_STAT;
1434 s->atapi_dma = s->feature & 1;
1435 s->nsector = 1;
1436 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1437 ide_atapi_cmd);
1438 return false;
1439 }
1440
1441
1442 /*** CF-ATA commands ***/
1443
1444 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1445 {
1446 s->error = 0x09; /* miscellaneous error */
1447 s->status = READY_STAT | SEEK_STAT;
1448 ide_set_irq(s->bus);
1449
1450 return false;
1451 }
1452
1453 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1454 {
1455 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1456 * required for Windows 8 to work with AHCI */
1457
1458 if (cmd == CFA_WEAR_LEVEL) {
1459 s->nsector = 0;
1460 }
1461
1462 if (cmd == CFA_ERASE_SECTORS) {
1463 s->media_changed = 1;
1464 }
1465
1466 return true;
1467 }
1468
1469 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1470 {
1471 s->status = READY_STAT | SEEK_STAT;
1472
1473 memset(s->io_buffer, 0, 0x200);
1474 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1475 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1476 s->io_buffer[0x02] = s->select; /* Head */
1477 s->io_buffer[0x03] = s->sector; /* Sector */
1478 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1479 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1480 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1481 s->io_buffer[0x13] = 0x00; /* Erase flag */
1482 s->io_buffer[0x18] = 0x00; /* Hot count */
1483 s->io_buffer[0x19] = 0x00; /* Hot count */
1484 s->io_buffer[0x1a] = 0x01; /* Hot count */
1485
1486 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1487 ide_set_irq(s->bus);
1488
1489 return false;
1490 }
1491
1492 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1493 {
1494 switch (s->feature) {
1495 case 0x02: /* Inquiry Metadata Storage */
1496 ide_cfata_metadata_inquiry(s);
1497 break;
1498 case 0x03: /* Read Metadata Storage */
1499 ide_cfata_metadata_read(s);
1500 break;
1501 case 0x04: /* Write Metadata Storage */
1502 ide_cfata_metadata_write(s);
1503 break;
1504 default:
1505 ide_abort_command(s);
1506 return true;
1507 }
1508
1509 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1510 s->status = 0x00; /* NOTE: READY is _not_ set */
1511 ide_set_irq(s->bus);
1512
1513 return false;
1514 }
1515
1516 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1517 {
1518 switch (s->feature) {
1519 case 0x01: /* sense temperature in device */
1520 s->nsector = 0x50; /* +20 C */
1521 break;
1522 default:
1523 ide_abort_command(s);
1524 return true;
1525 }
1526
1527 return true;
1528 }
1529
1530
1531 /*** SMART commands ***/
1532
1533 static bool cmd_smart(IDEState *s, uint8_t cmd)
1534 {
1535 int n;
1536
1537 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1538 goto abort_cmd;
1539 }
1540
1541 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1542 goto abort_cmd;
1543 }
1544
1545 switch (s->feature) {
1546 case SMART_DISABLE:
1547 s->smart_enabled = 0;
1548 return true;
1549
1550 case SMART_ENABLE:
1551 s->smart_enabled = 1;
1552 return true;
1553
1554 case SMART_ATTR_AUTOSAVE:
1555 switch (s->sector) {
1556 case 0x00:
1557 s->smart_autosave = 0;
1558 break;
1559 case 0xf1:
1560 s->smart_autosave = 1;
1561 break;
1562 default:
1563 goto abort_cmd;
1564 }
1565 return true;
1566
1567 case SMART_STATUS:
1568 if (!s->smart_errors) {
1569 s->hcyl = 0xc2;
1570 s->lcyl = 0x4f;
1571 } else {
1572 s->hcyl = 0x2c;
1573 s->lcyl = 0xf4;
1574 }
1575 return true;
1576
1577 case SMART_READ_THRESH:
1578 memset(s->io_buffer, 0, 0x200);
1579 s->io_buffer[0] = 0x01; /* smart struct version */
1580
1581 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1582 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1583 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1584 }
1585
1586 /* checksum */
1587 for (n = 0; n < 511; n++) {
1588 s->io_buffer[511] += s->io_buffer[n];
1589 }
1590 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1591
1592 s->status = READY_STAT | SEEK_STAT;
1593 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1594 ide_set_irq(s->bus);
1595 return false;
1596
1597 case SMART_READ_DATA:
1598 memset(s->io_buffer, 0, 0x200);
1599 s->io_buffer[0] = 0x01; /* smart struct version */
1600
1601 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1602 int i;
1603 for (i = 0; i < 11; i++) {
1604 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1605 }
1606 }
1607
1608 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1609 if (s->smart_selftest_count == 0) {
1610 s->io_buffer[363] = 0;
1611 } else {
1612 s->io_buffer[363] =
1613 s->smart_selftest_data[3 +
1614 (s->smart_selftest_count - 1) *
1615 24];
1616 }
1617 s->io_buffer[364] = 0x20;
1618 s->io_buffer[365] = 0x01;
1619 /* offline data collection capacity: execute + self-test*/
1620 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1621 s->io_buffer[368] = 0x03; /* smart capability (1) */
1622 s->io_buffer[369] = 0x00; /* smart capability (2) */
1623 s->io_buffer[370] = 0x01; /* error logging supported */
1624 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1625 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1626 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1627
1628 for (n = 0; n < 511; n++) {
1629 s->io_buffer[511] += s->io_buffer[n];
1630 }
1631 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1632
1633 s->status = READY_STAT | SEEK_STAT;
1634 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1635 ide_set_irq(s->bus);
1636 return false;
1637
1638 case SMART_READ_LOG:
1639 switch (s->sector) {
1640 case 0x01: /* summary smart error log */
1641 memset(s->io_buffer, 0, 0x200);
1642 s->io_buffer[0] = 0x01;
1643 s->io_buffer[1] = 0x00; /* no error entries */
1644 s->io_buffer[452] = s->smart_errors & 0xff;
1645 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1646
1647 for (n = 0; n < 511; n++) {
1648 s->io_buffer[511] += s->io_buffer[n];
1649 }
1650 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1651 break;
1652 case 0x06: /* smart self test log */
1653 memset(s->io_buffer, 0, 0x200);
1654 s->io_buffer[0] = 0x01;
1655 if (s->smart_selftest_count == 0) {
1656 s->io_buffer[508] = 0;
1657 } else {
1658 s->io_buffer[508] = s->smart_selftest_count;
1659 for (n = 2; n < 506; n++) {
1660 s->io_buffer[n] = s->smart_selftest_data[n];
1661 }
1662 }
1663
1664 for (n = 0; n < 511; n++) {
1665 s->io_buffer[511] += s->io_buffer[n];
1666 }
1667 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1668 break;
1669 default:
1670 goto abort_cmd;
1671 }
1672 s->status = READY_STAT | SEEK_STAT;
1673 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1674 ide_set_irq(s->bus);
1675 return false;
1676
1677 case SMART_EXECUTE_OFFLINE:
1678 switch (s->sector) {
1679 case 0: /* off-line routine */
1680 case 1: /* short self test */
1681 case 2: /* extended self test */
1682 s->smart_selftest_count++;
1683 if (s->smart_selftest_count > 21) {
1684 s->smart_selftest_count = 1;
1685 }
1686 n = 2 + (s->smart_selftest_count - 1) * 24;
1687 s->smart_selftest_data[n] = s->sector;
1688 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1689 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1690 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1691 break;
1692 default:
1693 goto abort_cmd;
1694 }
1695 return true;
1696 }
1697
1698 abort_cmd:
1699 ide_abort_command(s);
1700 return true;
1701 }
1702
1703 #define HD_OK (1u << IDE_HD)
1704 #define CD_OK (1u << IDE_CD)
1705 #define CFA_OK (1u << IDE_CFATA)
1706 #define HD_CFA_OK (HD_OK | CFA_OK)
1707 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1708
1709 /* Set the Disk Seek Completed status bit during completion */
1710 #define SET_DSC (1u << 8)
1711
1712 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1713 static const struct {
1714 /* Returns true if the completion code should be run */
1715 bool (*handler)(IDEState *s, uint8_t cmd);
1716 int flags;
1717 } ide_cmd_table[0x100] = {
1718 /* NOP not implemented, mandatory for CD */
1719 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1720 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
1721 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1722 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1723 [WIN_READ] = { cmd_read_pio, ALL_OK },
1724 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1725 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1726 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1727 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1728 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1729 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1730 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1731 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1732 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1733 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1734 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1735 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1736 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1737 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1738 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1739 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1740 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1741 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1742 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1743 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1744 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1745 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1746 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
1747 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1748 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
1749 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1750 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1751 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1752 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1753 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1754 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1755 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1756 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1757 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1758 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1759 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1760 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1761 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1762 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1763 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1764 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1765 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
1766 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1767 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
1768 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1769 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1770 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1771 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1772 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1773 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1774 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
1775 };
1776
1777 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1778 {
1779 return cmd < ARRAY_SIZE(ide_cmd_table)
1780 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1781 }
1782
1783 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1784 {
1785 IDEState *s;
1786 bool complete;
1787
1788 #if defined(DEBUG_IDE)
1789 printf("ide: CMD=%02x\n", val);
1790 #endif
1791 s = idebus_active_if(bus);
1792 /* ignore commands to non existent slave */
1793 if (s != bus->ifs && !s->bs)
1794 return;
1795
1796 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1797 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1798 return;
1799
1800 if (!ide_cmd_permitted(s, val)) {
1801 ide_abort_command(s);
1802 ide_set_irq(s->bus);
1803 return;
1804 }
1805
1806 s->status = READY_STAT | BUSY_STAT;
1807 s->error = 0;
1808
1809 complete = ide_cmd_table[val].handler(s, val);
1810 if (complete) {
1811 s->status &= ~BUSY_STAT;
1812 assert(!!s->error == !!(s->status & ERR_STAT));
1813
1814 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1815 s->status |= SEEK_STAT;
1816 }
1817
1818 ide_cmd_done(s);
1819 ide_set_irq(s->bus);
1820 }
1821 }
1822
1823 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1824 {
1825 IDEBus *bus = opaque;
1826 IDEState *s = idebus_active_if(bus);
1827 uint32_t addr;
1828 int ret, hob;
1829
1830 addr = addr1 & 7;
1831 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1832 //hob = s->select & (1 << 7);
1833 hob = 0;
1834 switch(addr) {
1835 case 0:
1836 ret = 0xff;
1837 break;
1838 case 1:
1839 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1840 (s != bus->ifs && !s->bs))
1841 ret = 0;
1842 else if (!hob)
1843 ret = s->error;
1844 else
1845 ret = s->hob_feature;
1846 break;
1847 case 2:
1848 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1849 ret = 0;
1850 else if (!hob)
1851 ret = s->nsector & 0xff;
1852 else
1853 ret = s->hob_nsector;
1854 break;
1855 case 3:
1856 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1857 ret = 0;
1858 else if (!hob)
1859 ret = s->sector;
1860 else
1861 ret = s->hob_sector;
1862 break;
1863 case 4:
1864 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1865 ret = 0;
1866 else if (!hob)
1867 ret = s->lcyl;
1868 else
1869 ret = s->hob_lcyl;
1870 break;
1871 case 5:
1872 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1873 ret = 0;
1874 else if (!hob)
1875 ret = s->hcyl;
1876 else
1877 ret = s->hob_hcyl;
1878 break;
1879 case 6:
1880 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1881 ret = 0;
1882 else
1883 ret = s->select;
1884 break;
1885 default:
1886 case 7:
1887 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1888 (s != bus->ifs && !s->bs))
1889 ret = 0;
1890 else
1891 ret = s->status;
1892 qemu_irq_lower(bus->irq);
1893 break;
1894 }
1895 #ifdef DEBUG_IDE
1896 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1897 #endif
1898 return ret;
1899 }
1900
1901 uint32_t ide_status_read(void *opaque, uint32_t addr)
1902 {
1903 IDEBus *bus = opaque;
1904 IDEState *s = idebus_active_if(bus);
1905 int ret;
1906
1907 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1908 (s != bus->ifs && !s->bs))
1909 ret = 0;
1910 else
1911 ret = s->status;
1912 #ifdef DEBUG_IDE
1913 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1914 #endif
1915 return ret;
1916 }
1917
1918 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1919 {
1920 IDEBus *bus = opaque;
1921 IDEState *s;
1922 int i;
1923
1924 #ifdef DEBUG_IDE
1925 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1926 #endif
1927 /* common for both drives */
1928 if (!(bus->cmd & IDE_CMD_RESET) &&
1929 (val & IDE_CMD_RESET)) {
1930 /* reset low to high */
1931 for(i = 0;i < 2; i++) {
1932 s = &bus->ifs[i];
1933 s->status = BUSY_STAT | SEEK_STAT;
1934 s->error = 0x01;
1935 }
1936 } else if ((bus->cmd & IDE_CMD_RESET) &&
1937 !(val & IDE_CMD_RESET)) {
1938 /* high to low */
1939 for(i = 0;i < 2; i++) {
1940 s = &bus->ifs[i];
1941 if (s->drive_kind == IDE_CD)
1942 s->status = 0x00; /* NOTE: READY is _not_ set */
1943 else
1944 s->status = READY_STAT | SEEK_STAT;
1945 ide_set_signature(s);
1946 }
1947 }
1948
1949 bus->cmd = val;
1950 }
1951
1952 /*
1953 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1954 * transferred from the device to the guest), false if it's a PIO in
1955 */
1956 static bool ide_is_pio_out(IDEState *s)
1957 {
1958 if (s->end_transfer_func == ide_sector_write ||
1959 s->end_transfer_func == ide_atapi_cmd) {
1960 return false;
1961 } else if (s->end_transfer_func == ide_sector_read ||
1962 s->end_transfer_func == ide_transfer_stop ||
1963 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1964 s->end_transfer_func == ide_dummy_transfer_stop) {
1965 return true;
1966 }
1967
1968 abort();
1969 }
1970
1971 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1972 {
1973 IDEBus *bus = opaque;
1974 IDEState *s = idebus_active_if(bus);
1975 uint8_t *p;
1976
1977 /* PIO data access allowed only when DRQ bit is set. The result of a write
1978 * during PIO out is indeterminate, just ignore it. */
1979 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1980 return;
1981 }
1982
1983 p = s->data_ptr;
1984 *(uint16_t *)p = le16_to_cpu(val);
1985 p += 2;
1986 s->data_ptr = p;
1987 if (p >= s->data_end)
1988 s->end_transfer_func(s);
1989 }
1990
1991 uint32_t ide_data_readw(void *opaque, uint32_t addr)
1992 {
1993 IDEBus *bus = opaque;
1994 IDEState *s = idebus_active_if(bus);
1995 uint8_t *p;
1996 int ret;
1997
1998 /* PIO data access allowed only when DRQ bit is set. The result of a read
1999 * during PIO in is indeterminate, return 0 and don't move forward. */
2000 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2001 return 0;
2002 }
2003
2004 p = s->data_ptr;
2005 ret = cpu_to_le16(*(uint16_t *)p);
2006 p += 2;
2007 s->data_ptr = p;
2008 if (p >= s->data_end)
2009 s->end_transfer_func(s);
2010 return ret;
2011 }
2012
2013 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2014 {
2015 IDEBus *bus = opaque;
2016 IDEState *s = idebus_active_if(bus);
2017 uint8_t *p;
2018
2019 /* PIO data access allowed only when DRQ bit is set. The result of a write
2020 * during PIO out is indeterminate, just ignore it. */
2021 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2022 return;
2023 }
2024
2025 p = s->data_ptr;
2026 *(uint32_t *)p = le32_to_cpu(val);
2027 p += 4;
2028 s->data_ptr = p;
2029 if (p >= s->data_end)
2030 s->end_transfer_func(s);
2031 }
2032
2033 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2034 {
2035 IDEBus *bus = opaque;
2036 IDEState *s = idebus_active_if(bus);
2037 uint8_t *p;
2038 int ret;
2039
2040 /* PIO data access allowed only when DRQ bit is set. The result of a read
2041 * during PIO in is indeterminate, return 0 and don't move forward. */
2042 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2043 return 0;
2044 }
2045
2046 p = s->data_ptr;
2047 ret = cpu_to_le32(*(uint32_t *)p);
2048 p += 4;
2049 s->data_ptr = p;
2050 if (p >= s->data_end)
2051 s->end_transfer_func(s);
2052 return ret;
2053 }
2054
2055 static void ide_dummy_transfer_stop(IDEState *s)
2056 {
2057 s->data_ptr = s->io_buffer;
2058 s->data_end = s->io_buffer;
2059 s->io_buffer[0] = 0xff;
2060 s->io_buffer[1] = 0xff;
2061 s->io_buffer[2] = 0xff;
2062 s->io_buffer[3] = 0xff;
2063 }
2064
2065 static void ide_reset(IDEState *s)
2066 {
2067 #ifdef DEBUG_IDE
2068 printf("ide: reset\n");
2069 #endif
2070
2071 if (s->pio_aiocb) {
2072 bdrv_aio_cancel(s->pio_aiocb);
2073 s->pio_aiocb = NULL;
2074 }
2075
2076 if (s->drive_kind == IDE_CFATA)
2077 s->mult_sectors = 0;
2078 else
2079 s->mult_sectors = MAX_MULT_SECTORS;
2080 /* ide regs */
2081 s->feature = 0;
2082 s->error = 0;
2083 s->nsector = 0;
2084 s->sector = 0;
2085 s->lcyl = 0;
2086 s->hcyl = 0;
2087
2088 /* lba48 */
2089 s->hob_feature = 0;
2090 s->hob_sector = 0;
2091 s->hob_nsector = 0;
2092 s->hob_lcyl = 0;
2093 s->hob_hcyl = 0;
2094
2095 s->select = 0xa0;
2096 s->status = READY_STAT | SEEK_STAT;
2097
2098 s->lba48 = 0;
2099
2100 /* ATAPI specific */
2101 s->sense_key = 0;
2102 s->asc = 0;
2103 s->cdrom_changed = 0;
2104 s->packet_transfer_size = 0;
2105 s->elementary_transfer_size = 0;
2106 s->io_buffer_index = 0;
2107 s->cd_sector_size = 0;
2108 s->atapi_dma = 0;
2109 s->tray_locked = 0;
2110 s->tray_open = 0;
2111 /* ATA DMA state */
2112 s->io_buffer_size = 0;
2113 s->req_nb_sectors = 0;
2114
2115 ide_set_signature(s);
2116 /* init the transfer handler so that 0xffff is returned on data
2117 accesses */
2118 s->end_transfer_func = ide_dummy_transfer_stop;
2119 ide_dummy_transfer_stop(s);
2120 s->media_changed = 0;
2121 }
2122
2123 void ide_bus_reset(IDEBus *bus)
2124 {
2125 bus->unit = 0;
2126 bus->cmd = 0;
2127 ide_reset(&bus->ifs[0]);
2128 ide_reset(&bus->ifs[1]);
2129 ide_clear_hob(bus);
2130
2131 /* pending async DMA */
2132 if (bus->dma->aiocb) {
2133 #ifdef DEBUG_AIO
2134 printf("aio_cancel\n");
2135 #endif
2136 bdrv_aio_cancel(bus->dma->aiocb);
2137 bus->dma->aiocb = NULL;
2138 }
2139
2140 /* reset dma provider too */
2141 if (bus->dma->ops->reset) {
2142 bus->dma->ops->reset(bus->dma);
2143 }
2144 }
2145
2146 static bool ide_cd_is_tray_open(void *opaque)
2147 {
2148 return ((IDEState *)opaque)->tray_open;
2149 }
2150
2151 static bool ide_cd_is_medium_locked(void *opaque)
2152 {
2153 return ((IDEState *)opaque)->tray_locked;
2154 }
2155
2156 static void ide_resize_cb(void *opaque)
2157 {
2158 IDEState *s = opaque;
2159 uint64_t nb_sectors;
2160
2161 if (!s->identify_set) {
2162 return;
2163 }
2164
2165 bdrv_get_geometry(s->bs, &nb_sectors);
2166 s->nb_sectors = nb_sectors;
2167
2168 /* Update the identify data buffer. */
2169 if (s->drive_kind == IDE_CFATA) {
2170 ide_cfata_identify_size(s);
2171 } else {
2172 /* IDE_CD uses a different set of callbacks entirely. */
2173 assert(s->drive_kind != IDE_CD);
2174 ide_identify_size(s);
2175 }
2176 }
2177
2178 static const BlockDevOps ide_cd_block_ops = {
2179 .change_media_cb = ide_cd_change_cb,
2180 .eject_request_cb = ide_cd_eject_request_cb,
2181 .is_tray_open = ide_cd_is_tray_open,
2182 .is_medium_locked = ide_cd_is_medium_locked,
2183 };
2184
2185 static const BlockDevOps ide_hd_block_ops = {
2186 .resize_cb = ide_resize_cb,
2187 };
2188
2189 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
2190 const char *version, const char *serial, const char *model,
2191 uint64_t wwn,
2192 uint32_t cylinders, uint32_t heads, uint32_t secs,
2193 int chs_trans)
2194 {
2195 uint64_t nb_sectors;
2196
2197 s->bs = bs;
2198 s->drive_kind = kind;
2199
2200 bdrv_get_geometry(bs, &nb_sectors);
2201 s->cylinders = cylinders;
2202 s->heads = heads;
2203 s->sectors = secs;
2204 s->chs_trans = chs_trans;
2205 s->nb_sectors = nb_sectors;
2206 s->wwn = wwn;
2207 /* The SMART values should be preserved across power cycles
2208 but they aren't. */
2209 s->smart_enabled = 1;
2210 s->smart_autosave = 1;
2211 s->smart_errors = 0;
2212 s->smart_selftest_count = 0;
2213 if (kind == IDE_CD) {
2214 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
2215 bdrv_set_guest_block_size(bs, 2048);
2216 } else {
2217 if (!bdrv_is_inserted(s->bs)) {
2218 error_report("Device needs media, but drive is empty");
2219 return -1;
2220 }
2221 if (bdrv_is_read_only(bs)) {
2222 error_report("Can't use a read-only drive");
2223 return -1;
2224 }
2225 bdrv_set_dev_ops(bs, &ide_hd_block_ops, s);
2226 }
2227 if (serial) {
2228 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2229 } else {
2230 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2231 "QM%05d", s->drive_serial);
2232 }
2233 if (model) {
2234 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2235 } else {
2236 switch (kind) {
2237 case IDE_CD:
2238 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2239 break;
2240 case IDE_CFATA:
2241 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2242 break;
2243 default:
2244 strcpy(s->drive_model_str, "QEMU HARDDISK");
2245 break;
2246 }
2247 }
2248
2249 if (version) {
2250 pstrcpy(s->version, sizeof(s->version), version);
2251 } else {
2252 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
2253 }
2254
2255 ide_reset(s);
2256 bdrv_iostatus_enable(bs);
2257 return 0;
2258 }
2259
2260 static void ide_init1(IDEBus *bus, int unit)
2261 {
2262 static int drive_serial = 1;
2263 IDEState *s = &bus->ifs[unit];
2264
2265 s->bus = bus;
2266 s->unit = unit;
2267 s->drive_serial = drive_serial++;
2268 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2269 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2270 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2271 memset(s->io_buffer, 0, s->io_buffer_total_len);
2272
2273 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
2274 memset(s->smart_selftest_data, 0, 512);
2275
2276 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2277 ide_sector_write_timer_cb, s);
2278 }
2279
2280 static int ide_nop_int(IDEDMA *dma, int x)
2281 {
2282 return 0;
2283 }
2284
2285 static void ide_nop_restart(void *opaque, int x, RunState y)
2286 {
2287 }
2288
2289 static const IDEDMAOps ide_dma_nop_ops = {
2290 .prepare_buf = ide_nop_int,
2291 .rw_buf = ide_nop_int,
2292 .set_unit = ide_nop_int,
2293 .restart_cb = ide_nop_restart,
2294 };
2295
2296 static IDEDMA ide_dma_nop = {
2297 .ops = &ide_dma_nop_ops,
2298 .aiocb = NULL,
2299 };
2300
2301 void ide_init2(IDEBus *bus, qemu_irq irq)
2302 {
2303 int i;
2304
2305 for(i = 0; i < 2; i++) {
2306 ide_init1(bus, i);
2307 ide_reset(&bus->ifs[i]);
2308 }
2309 bus->irq = irq;
2310 bus->dma = &ide_dma_nop;
2311 }
2312
2313 static const MemoryRegionPortio ide_portio_list[] = {
2314 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2315 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2316 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2317 PORTIO_END_OF_LIST(),
2318 };
2319
2320 static const MemoryRegionPortio ide_portio2_list[] = {
2321 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2322 PORTIO_END_OF_LIST(),
2323 };
2324
2325 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2326 {
2327 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2328 bridge has been setup properly to always register with ISA. */
2329 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2330
2331 if (iobase2) {
2332 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2333 }
2334 }
2335
2336 static bool is_identify_set(void *opaque, int version_id)
2337 {
2338 IDEState *s = opaque;
2339
2340 return s->identify_set != 0;
2341 }
2342
2343 static EndTransferFunc* transfer_end_table[] = {
2344 ide_sector_read,
2345 ide_sector_write,
2346 ide_transfer_stop,
2347 ide_atapi_cmd_reply_end,
2348 ide_atapi_cmd,
2349 ide_dummy_transfer_stop,
2350 };
2351
2352 static int transfer_end_table_idx(EndTransferFunc *fn)
2353 {
2354 int i;
2355
2356 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2357 if (transfer_end_table[i] == fn)
2358 return i;
2359
2360 return -1;
2361 }
2362
2363 static int ide_drive_post_load(void *opaque, int version_id)
2364 {
2365 IDEState *s = opaque;
2366
2367 if (s->identify_set) {
2368 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2369 }
2370 return 0;
2371 }
2372
2373 static int ide_drive_pio_post_load(void *opaque, int version_id)
2374 {
2375 IDEState *s = opaque;
2376
2377 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2378 return -EINVAL;
2379 }
2380 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2381 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2382 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2383
2384 return 0;
2385 }
2386
2387 static void ide_drive_pio_pre_save(void *opaque)
2388 {
2389 IDEState *s = opaque;
2390 int idx;
2391
2392 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2393 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2394
2395 idx = transfer_end_table_idx(s->end_transfer_func);
2396 if (idx == -1) {
2397 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2398 __func__);
2399 s->end_transfer_fn_idx = 2;
2400 } else {
2401 s->end_transfer_fn_idx = idx;
2402 }
2403 }
2404
2405 static bool ide_drive_pio_state_needed(void *opaque)
2406 {
2407 IDEState *s = opaque;
2408
2409 return ((s->status & DRQ_STAT) != 0)
2410 || (s->bus->error_status & IDE_RETRY_PIO);
2411 }
2412
2413 static bool ide_tray_state_needed(void *opaque)
2414 {
2415 IDEState *s = opaque;
2416
2417 return s->tray_open || s->tray_locked;
2418 }
2419
2420 static bool ide_atapi_gesn_needed(void *opaque)
2421 {
2422 IDEState *s = opaque;
2423
2424 return s->events.new_media || s->events.eject_request;
2425 }
2426
2427 static bool ide_error_needed(void *opaque)
2428 {
2429 IDEBus *bus = opaque;
2430
2431 return (bus->error_status != 0);
2432 }
2433
2434 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2435 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2436 .name ="ide_drive/atapi/gesn_state",
2437 .version_id = 1,
2438 .minimum_version_id = 1,
2439 .fields = (VMStateField[]) {
2440 VMSTATE_BOOL(events.new_media, IDEState),
2441 VMSTATE_BOOL(events.eject_request, IDEState),
2442 VMSTATE_END_OF_LIST()
2443 }
2444 };
2445
2446 static const VMStateDescription vmstate_ide_tray_state = {
2447 .name = "ide_drive/tray_state",
2448 .version_id = 1,
2449 .minimum_version_id = 1,
2450 .fields = (VMStateField[]) {
2451 VMSTATE_BOOL(tray_open, IDEState),
2452 VMSTATE_BOOL(tray_locked, IDEState),
2453 VMSTATE_END_OF_LIST()
2454 }
2455 };
2456
2457 static const VMStateDescription vmstate_ide_drive_pio_state = {
2458 .name = "ide_drive/pio_state",
2459 .version_id = 1,
2460 .minimum_version_id = 1,
2461 .pre_save = ide_drive_pio_pre_save,
2462 .post_load = ide_drive_pio_post_load,
2463 .fields = (VMStateField[]) {
2464 VMSTATE_INT32(req_nb_sectors, IDEState),
2465 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2466 vmstate_info_uint8, uint8_t),
2467 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2468 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2469 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2470 VMSTATE_INT32(elementary_transfer_size, IDEState),
2471 VMSTATE_INT32(packet_transfer_size, IDEState),
2472 VMSTATE_END_OF_LIST()
2473 }
2474 };
2475
2476 const VMStateDescription vmstate_ide_drive = {
2477 .name = "ide_drive",
2478 .version_id = 3,
2479 .minimum_version_id = 0,
2480 .post_load = ide_drive_post_load,
2481 .fields = (VMStateField[]) {
2482 VMSTATE_INT32(mult_sectors, IDEState),
2483 VMSTATE_INT32(identify_set, IDEState),
2484 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2485 VMSTATE_UINT8(feature, IDEState),
2486 VMSTATE_UINT8(error, IDEState),
2487 VMSTATE_UINT32(nsector, IDEState),
2488 VMSTATE_UINT8(sector, IDEState),
2489 VMSTATE_UINT8(lcyl, IDEState),
2490 VMSTATE_UINT8(hcyl, IDEState),
2491 VMSTATE_UINT8(hob_feature, IDEState),
2492 VMSTATE_UINT8(hob_sector, IDEState),
2493 VMSTATE_UINT8(hob_nsector, IDEState),
2494 VMSTATE_UINT8(hob_lcyl, IDEState),
2495 VMSTATE_UINT8(hob_hcyl, IDEState),
2496 VMSTATE_UINT8(select, IDEState),
2497 VMSTATE_UINT8(status, IDEState),
2498 VMSTATE_UINT8(lba48, IDEState),
2499 VMSTATE_UINT8(sense_key, IDEState),
2500 VMSTATE_UINT8(asc, IDEState),
2501 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2502 VMSTATE_END_OF_LIST()
2503 },
2504 .subsections = (VMStateSubsection []) {
2505 {
2506 .vmsd = &vmstate_ide_drive_pio_state,
2507 .needed = ide_drive_pio_state_needed,
2508 }, {
2509 .vmsd = &vmstate_ide_tray_state,
2510 .needed = ide_tray_state_needed,
2511 }, {
2512 .vmsd = &vmstate_ide_atapi_gesn_state,
2513 .needed = ide_atapi_gesn_needed,
2514 }, {
2515 /* empty */
2516 }
2517 }
2518 };
2519
2520 static const VMStateDescription vmstate_ide_error_status = {
2521 .name ="ide_bus/error",
2522 .version_id = 1,
2523 .minimum_version_id = 1,
2524 .fields = (VMStateField[]) {
2525 VMSTATE_INT32(error_status, IDEBus),
2526 VMSTATE_END_OF_LIST()
2527 }
2528 };
2529
2530 const VMStateDescription vmstate_ide_bus = {
2531 .name = "ide_bus",
2532 .version_id = 1,
2533 .minimum_version_id = 1,
2534 .fields = (VMStateField[]) {
2535 VMSTATE_UINT8(cmd, IDEBus),
2536 VMSTATE_UINT8(unit, IDEBus),
2537 VMSTATE_END_OF_LIST()
2538 },
2539 .subsections = (VMStateSubsection []) {
2540 {
2541 .vmsd = &vmstate_ide_error_status,
2542 .needed = ide_error_needed,
2543 }, {
2544 /* empty */
2545 }
2546 }
2547 };
2548
2549 void ide_drive_get(DriveInfo **hd, int max_bus)
2550 {
2551 int i;
2552
2553 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2554 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2555 exit(1);
2556 }
2557
2558 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2559 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2560 }
2561 }
CRIS target port of Qemu