hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "i8254.h"
  40 #include "pcspk.h"
  41 #include "msi.h"
  42 #include "sysbus.h"
  43 #include "sysemu.h"
  44 #include "kvm.h"
  45 #include "xen.h"
  46 #include "blockdev.h"
  47 #include "ui/qemu-spice.h"
  48 #include "memory.h"
  49 #include "exec-memory.h"
  50 #include "arch_init.h"
  51
  52 /* output Bochs bios info messages */
  53 //#define DEBUG_BIOS
  54
  55 /* debug PC/ISA interrupts */
  56 //#define DEBUG_IRQ
  57
  58 #ifdef DEBUG_IRQ
  59 #define DPRINTF(fmt, ...)                                       \
  60     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  61 #else
  62 #define DPRINTF(fmt, ...)
  63 #endif
  64
  65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  66 #define ACPI_DATA_SIZE       0x10000
  67 #define BIOS_CFG_IOPORT 0x510
  68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  73
  74 #define MSI_ADDR_BASE 0xfee00000
  75
  76 #define E820_NR_ENTRIES         16
  77
  78 struct e820_entry {
  79     uint64_t address;
  80     uint64_t length;
  81     uint32_t type;
  82 } QEMU_PACKED __attribute((__aligned__(4)));
  83
  84 struct e820_table {
  85     uint32_t count;
  86     struct e820_entry entry[E820_NR_ENTRIES];
  87 } QEMU_PACKED __attribute((__aligned__(4)));
  88
  89 static struct e820_table e820_table;
  90 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  91
  92 void gsi_handler(void *opaque, int n, int level)
  93 {
  94     GSIState *s = opaque;
  95
  96     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  97     if (n < ISA_NUM_IRQS) {
  98         qemu_set_irq(s->i8259_irq[n], level);
  99     }
 100     qemu_set_irq(s->ioapic_irq[n], level);
 101 }
 102
 103 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 104 {
 105 }
 106
 107 /* MSDOS compatibility mode FPU exception support */
 108 static qemu_irq ferr_irq;
 109
 110 void pc_register_ferr_irq(qemu_irq irq)
 111 {
 112     ferr_irq = irq;
 113 }
 114
 115 /* XXX: add IGNNE support */
 116 void cpu_set_ferr(CPUX86State *s)
 117 {
 118     qemu_irq_raise(ferr_irq);
 119 }
 120
 121 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 122 {
 123     qemu_irq_lower(ferr_irq);
 124 }
 125
 126 /* TSC handling */
 127 uint64_t cpu_get_tsc(CPUX86State *env)
 128 {
 129     return cpu_get_ticks();
 130 }
 131
 132 /* SMM support */
 133
 134 static cpu_set_smm_t smm_set;
 135 static void *smm_arg;
 136
 137 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 138 {
 139     assert(smm_set == NULL);
 140     assert(smm_arg == NULL);
 141     smm_set = callback;
 142     smm_arg = arg;
 143 }
 144
 145 void cpu_smm_update(CPUX86State *env)
 146 {
 147     if (smm_set && smm_arg && env == first_cpu)
 148         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 149 }
 150
 151
 152 /* IRQ handling */
 153 int cpu_get_pic_interrupt(CPUX86State *env)
 154 {
 155     int intno;
 156
 157     intno = apic_get_interrupt(env->apic_state);
 158     if (intno >= 0) {
 159         return intno;
 160     }
 161     /* read the irq from the PIC */
 162     if (!apic_accept_pic_intr(env->apic_state)) {
 163         return -1;
 164     }
 165
 166     intno = pic_read_irq(isa_pic);
 167     return intno;
 168 }
 169
 170 static void pic_irq_request(void *opaque, int irq, int level)
 171 {
 172     CPUX86State *env = first_cpu;
 173
 174     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 175     if (env->apic_state) {
 176         while (env) {
 177             if (apic_accept_pic_intr(env->apic_state)) {
 178                 apic_deliver_pic_intr(env->apic_state, level);
 179             }
 180             env = env->next_cpu;
 181         }
 182     } else {
 183         if (level)
 184             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 185         else
 186             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 187     }
 188 }
 189
 190 /* PC cmos mappings */
 191
 192 #define REG_EQUIPMENT_BYTE          0x14
 193
 194 static int cmos_get_fd_drive_type(FDriveType fd0)
 195 {
 196     int val;
 197
 198     switch (fd0) {
 199     case FDRIVE_DRV_144:
 200         /* 1.44 Mb 3"5 drive */
 201         val = 4;
 202         break;
 203     case FDRIVE_DRV_288:
 204         /* 2.88 Mb 3"5 drive */
 205         val = 5;
 206         break;
 207     case FDRIVE_DRV_120:
 208         /* 1.2 Mb 5"5 drive */
 209         val = 2;
 210         break;
 211     case FDRIVE_DRV_NONE:
 212     default:
 213         val = 0;
 214         break;
 215     }
 216     return val;
 217 }
 218
 219 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 220                          ISADevice *s)
 221 {
 222     int cylinders, heads, sectors;
 223     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 224     rtc_set_memory(s, type_ofs, 47);
 225     rtc_set_memory(s, info_ofs, cylinders);
 226     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 227     rtc_set_memory(s, info_ofs + 2, heads);
 228     rtc_set_memory(s, info_ofs + 3, 0xff);
 229     rtc_set_memory(s, info_ofs + 4, 0xff);
 230     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 231     rtc_set_memory(s, info_ofs + 6, cylinders);
 232     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 233     rtc_set_memory(s, info_ofs + 8, sectors);
 234 }
 235
 236 /* convert boot_device letter to something recognizable by the bios */
 237 static int boot_device2nibble(char boot_device)
 238 {
 239     switch(boot_device) {
 240     case 'a':
 241     case 'b':
 242         return 0x01; /* floppy boot */
 243     case 'c':
 244         return 0x02; /* hard drive boot */
 245     case 'd':
 246         return 0x03; /* CD-ROM boot */
 247     case 'n':
 248         return 0x04; /* Network boot */
 249     }
 250     return 0;
 251 }
 252
 253 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 254 {
 255 #define PC_MAX_BOOT_DEVICES 3
 256     int nbds, bds[3] = { 0, };
 257     int i;
 258
 259     nbds = strlen(boot_device);
 260     if (nbds > PC_MAX_BOOT_DEVICES) {
 261         error_report("Too many boot devices for PC");
 262         return(1);
 263     }
 264     for (i = 0; i < nbds; i++) {
 265         bds[i] = boot_device2nibble(boot_device[i]);
 266         if (bds[i] == 0) {
 267             error_report("Invalid boot device for PC: '%c'",
 268                          boot_device[i]);
 269             return(1);
 270         }
 271     }
 272     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 273     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 274     return(0);
 275 }
 276
 277 static int pc_boot_set(void *opaque, const char *boot_device)
 278 {
 279     return set_boot_dev(opaque, boot_device, 0);
 280 }
 281
 282 typedef struct pc_cmos_init_late_arg {
 283     ISADevice *rtc_state;
 284     BusState *idebus0, *idebus1;
 285 } pc_cmos_init_late_arg;
 286
 287 static void pc_cmos_init_late(void *opaque)
 288 {
 289     pc_cmos_init_late_arg *arg = opaque;
 290     ISADevice *s = arg->rtc_state;
 291     int val;
 292     BlockDriverState *hd_table[4];
 293     int i;
 294
 295     ide_get_bs(hd_table, arg->idebus0);
 296     ide_get_bs(hd_table + 2, arg->idebus1);
 297
 298     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 299     if (hd_table[0])
 300         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 301     if (hd_table[1])
 302         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 303
 304     val = 0;
 305     for (i = 0; i < 4; i++) {
 306         if (hd_table[i]) {
 307             int cylinders, heads, sectors, translation;
 308             /* NOTE: bdrv_get_geometry_hint() returns the physical
 309                 geometry.  It is always such that: 1 <= sects <= 63, 1
 310                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 311                 geometry can be different if a translation is done. */
 312             translation = bdrv_get_translation_hint(hd_table[i]);
 313             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 314                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 315                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 316                     /* No translation. */
 317                     translation = 0;
 318                 } else {
 319                     /* LBA translation. */
 320                     translation = 1;
 321                 }
 322             } else {
 323                 translation--;
 324             }
 325             val |= translation << (i * 2);
 326         }
 327     }
 328     rtc_set_memory(s, 0x39, val);
 329
 330     qemu_unregister_reset(pc_cmos_init_late, opaque);
 331 }
 332
 333 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 334                   const char *boot_device,
 335                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 336                   ISADevice *s)
 337 {
 338     int val, nb, nb_heads, max_track, last_sect, i;
 339     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 340     FDriveRate rate;
 341     BlockDriverState *fd[MAX_FD];
 342     static pc_cmos_init_late_arg arg;
 343
 344     /* various important CMOS locations needed by PC/Bochs bios */
 345
 346     /* memory size */
 347     val = 640; /* base memory in K */
 348     rtc_set_memory(s, 0x15, val);
 349     rtc_set_memory(s, 0x16, val >> 8);
 350
 351     val = (ram_size / 1024) - 1024;
 352     if (val > 65535)
 353         val = 65535;
 354     rtc_set_memory(s, 0x17, val);
 355     rtc_set_memory(s, 0x18, val >> 8);
 356     rtc_set_memory(s, 0x30, val);
 357     rtc_set_memory(s, 0x31, val >> 8);
 358
 359     if (above_4g_mem_size) {
 360         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 361         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 362         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 363     }
 364
 365     if (ram_size > (16 * 1024 * 1024))
 366         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 367     else
 368         val = 0;
 369     if (val > 65535)
 370         val = 65535;
 371     rtc_set_memory(s, 0x34, val);
 372     rtc_set_memory(s, 0x35, val >> 8);
 373
 374     /* set the number of CPU */
 375     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 376
 377     /* set boot devices, and disable floppy signature check if requested */
 378     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 379         exit(1);
 380     }
 381
 382     /* floppy type */
 383     if (floppy) {
 384         fdc_get_bs(fd, floppy);
 385         for (i = 0; i < 2; i++) {
 386             if (fd[i]) {
 387                 bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
 388                                               &last_sect, FDRIVE_DRV_NONE,
 389                                               &fd_type[i], &rate);
 390             }
 391         }
 392     }
 393     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 394         cmos_get_fd_drive_type(fd_type[1]);
 395     rtc_set_memory(s, 0x10, val);
 396
 397     val = 0;
 398     nb = 0;
 399     if (fd_type[0] < FDRIVE_DRV_NONE) {
 400         nb++;
 401     }
 402     if (fd_type[1] < FDRIVE_DRV_NONE) {
 403         nb++;
 404     }
 405     switch (nb) {
 406     case 0:
 407         break;
 408     case 1:
 409         val |= 0x01; /* 1 drive, ready for boot */
 410         break;
 411     case 2:
 412         val |= 0x41; /* 2 drives, ready for boot */
 413         break;
 414     }
 415     val |= 0x02; /* FPU is there */
 416     val |= 0x04; /* PS/2 mouse installed */
 417     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 418
 419     /* hard drives */
 420     arg.rtc_state = s;
 421     arg.idebus0 = idebus0;
 422     arg.idebus1 = idebus1;
 423     qemu_register_reset(pc_cmos_init_late, &arg);
 424 }
 425
 426 /* port 92 stuff: could be split off */
 427 typedef struct Port92State {
 428     ISADevice dev;
 429     MemoryRegion io;
 430     uint8_t outport;
 431     qemu_irq *a20_out;
 432 } Port92State;
 433
 434 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 435 {
 436     Port92State *s = opaque;
 437
 438     DPRINTF("port92: write 0x%02x\n", val);
 439     s->outport = val;
 440     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 441     if (val & 1) {
 442         qemu_system_reset_request();
 443     }
 444 }
 445
 446 static uint32_t port92_read(void *opaque, uint32_t addr)
 447 {
 448     Port92State *s = opaque;
 449     uint32_t ret;
 450
 451     ret = s->outport;
 452     DPRINTF("port92: read 0x%02x\n", ret);
 453     return ret;
 454 }
 455
 456 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 457 {
 458     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 459
 460     s->a20_out = a20_out;
 461 }
 462
 463 static const VMStateDescription vmstate_port92_isa = {
 464     .name = "port92",
 465     .version_id = 1,
 466     .minimum_version_id = 1,
 467     .minimum_version_id_old = 1,
 468     .fields      = (VMStateField []) {
 469         VMSTATE_UINT8(outport, Port92State),
 470         VMSTATE_END_OF_LIST()
 471     }
 472 };
 473
 474 static void port92_reset(DeviceState *d)
 475 {
 476     Port92State *s = container_of(d, Port92State, dev.qdev);
 477
 478     s->outport &= ~1;
 479 }
 480
 481 static const MemoryRegionPortio port92_portio[] = {
 482     { 0, 1, 1, .read = port92_read, .write = port92_write },
 483     PORTIO_END_OF_LIST(),
 484 };
 485
 486 static const MemoryRegionOps port92_ops = {
 487     .old_portio = port92_portio
 488 };
 489
 490 static int port92_initfn(ISADevice *dev)
 491 {
 492     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 493
 494     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 495     isa_register_ioport(dev, &s->io, 0x92);
 496
 497     s->outport = 0;
 498     return 0;
 499 }
 500
 501 static void port92_class_initfn(ObjectClass *klass, void *data)
 502 {
 503     DeviceClass *dc = DEVICE_CLASS(klass);
 504     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 505     ic->init = port92_initfn;
 506     dc->no_user = 1;
 507     dc->reset = port92_reset;
 508     dc->vmsd = &vmstate_port92_isa;
 509 }
 510
 511 static TypeInfo port92_info = {
 512     .name          = "port92",
 513     .parent        = TYPE_ISA_DEVICE,
 514     .instance_size = sizeof(Port92State),
 515     .class_init    = port92_class_initfn,
 516 };
 517
 518 static void port92_register_types(void)
 519 {
 520     type_register_static(&port92_info);
 521 }
 522
 523 type_init(port92_register_types)
 524
 525 static void handle_a20_line_change(void *opaque, int irq, int level)
 526 {
 527     CPUX86State *cpu = opaque;
 528
 529     /* XXX: send to all CPUs ? */
 530     /* XXX: add logic to handle multiple A20 line sources */
 531     cpu_x86_set_a20(cpu, level);
 532 }
 533
 534 /***********************************************************/
 535 /* Bochs BIOS debug ports */
 536
 537 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 538 {
 539     static const char shutdown_str[8] = "Shutdown";
 540     static int shutdown_index = 0;
 541
 542     switch(addr) {
 543         /* Bochs BIOS messages */
 544     case 0x400:
 545     case 0x401:
 546         /* used to be panic, now unused */
 547         break;
 548     case 0x402:
 549     case 0x403:
 550 #ifdef DEBUG_BIOS
 551         fprintf(stderr, "%c", val);
 552 #endif
 553         break;
 554     case 0x8900:
 555         /* same as Bochs power off */
 556         if (val == shutdown_str[shutdown_index]) {
 557             shutdown_index++;
 558             if (shutdown_index == 8) {
 559                 shutdown_index = 0;
 560                 qemu_system_shutdown_request();
 561             }
 562         } else {
 563             shutdown_index = 0;
 564         }
 565         break;
 566
 567         /* LGPL'ed VGA BIOS messages */
 568     case 0x501:
 569     case 0x502:
 570         exit((val << 1) | 1);
 571     case 0x500:
 572     case 0x503:
 573 #ifdef DEBUG_BIOS
 574         fprintf(stderr, "%c", val);
 575 #endif
 576         break;
 577     }
 578 }
 579
 580 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 581 {
 582     int index = le32_to_cpu(e820_table.count);
 583     struct e820_entry *entry;
 584
 585     if (index >= E820_NR_ENTRIES)
 586         return -EBUSY;
 587     entry = &e820_table.entry[index++];
 588
 589     entry->address = cpu_to_le64(address);
 590     entry->length = cpu_to_le64(length);
 591     entry->type = cpu_to_le32(type);
 592
 593     e820_table.count = cpu_to_le32(index);
 594     return index;
 595 }
 596
 597 static void *bochs_bios_init(void)
 598 {
 599     void *fw_cfg;
 600     uint8_t *smbios_table;
 601     size_t smbios_len;
 602     uint64_t *numa_fw_cfg;
 603     int i, j;
 604
 605     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 606     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 607     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 608     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 609     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 610
 611     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 612     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 613     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 614     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 615     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 616
 617     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 618
 619     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 620     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 621     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 622                      acpi_tables_len);
 623     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 624
 625     smbios_table = smbios_get_table(&smbios_len);
 626     if (smbios_table)
 627         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 628                          smbios_table, smbios_len);
 629     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 630                      sizeof(struct e820_table));
 631
 632     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 633                      sizeof(struct hpet_fw_config));
 634     /* allocate memory for the NUMA channel: one (64bit) word for the number
 635      * of nodes, one word for each VCPU->node and one word for each node to
 636      * hold the amount of memory.
 637      */
 638     numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
 639     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 640     for (i = 0; i < max_cpus; i++) {
 641         for (j = 0; j < nb_numa_nodes; j++) {
 642             if (node_cpumask[j] & (1 << i)) {
 643                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 644                 break;
 645             }
 646         }
 647     }
 648     for (i = 0; i < nb_numa_nodes; i++) {
 649         numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 650     }
 651     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 652                      (1 + max_cpus + nb_numa_nodes) * 8);
 653
 654     return fw_cfg;
 655 }
 656
 657 static long get_file_size(FILE *f)
 658 {
 659     long where, size;
 660
 661     /* XXX: on Unix systems, using fstat() probably makes more sense */
 662
 663     where = ftell(f);
 664     fseek(f, 0, SEEK_END);
 665     size = ftell(f);
 666     fseek(f, where, SEEK_SET);
 667
 668     return size;
 669 }
 670
 671 static void load_linux(void *fw_cfg,
 672                        const char *kernel_filename,
 673                        const char *initrd_filename,
 674                        const char *kernel_cmdline,
 675                        target_phys_addr_t max_ram_size)
 676 {
 677     uint16_t protocol;
 678     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 679     uint32_t initrd_max;
 680     uint8_t header[8192], *setup, *kernel, *initrd_data;
 681     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 682     FILE *f;
 683     char *vmode;
 684
 685     /* Align to 16 bytes as a paranoia measure */
 686     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 687
 688     /* load the kernel header */
 689     f = fopen(kernel_filename, "rb");
 690     if (!f || !(kernel_size = get_file_size(f)) ||
 691         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 692         MIN(ARRAY_SIZE(header), kernel_size)) {
 693         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 694                 kernel_filename, strerror(errno));
 695         exit(1);
 696     }
 697
 698     /* kernel protocol version */
 699 #if 0
 700     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 701 #endif
 702     if (ldl_p(header+0x202) == 0x53726448)
 703         protocol = lduw_p(header+0x206);
 704     else {
 705         /* This looks like a multiboot kernel. If it is, let's stop
 706            treating it like a Linux kernel. */
 707         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 708                            kernel_cmdline, kernel_size, header))
 709             return;
 710         protocol = 0;
 711     }
 712
 713     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 714         /* Low kernel */
 715         real_addr    = 0x90000;
 716         cmdline_addr = 0x9a000 - cmdline_size;
 717         prot_addr    = 0x10000;
 718     } else if (protocol < 0x202) {
 719         /* High but ancient kernel */
 720         real_addr    = 0x90000;
 721         cmdline_addr = 0x9a000 - cmdline_size;
 722         prot_addr    = 0x100000;
 723     } else {
 724         /* High and recent kernel */
 725         real_addr    = 0x10000;
 726         cmdline_addr = 0x20000;
 727         prot_addr    = 0x100000;
 728     }
 729
 730 #if 0
 731     fprintf(stderr,
 732             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 733             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 734             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 735             real_addr,
 736             cmdline_addr,
 737             prot_addr);
 738 #endif
 739
 740     /* highest address for loading the initrd */
 741     if (protocol >= 0x203)
 742         initrd_max = ldl_p(header+0x22c);
 743     else
 744         initrd_max = 0x37ffffff;
 745
 746     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 747         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 748
 749     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 750     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 751     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 752                      (uint8_t*)strdup(kernel_cmdline),
 753                      strlen(kernel_cmdline)+1);
 754
 755     if (protocol >= 0x202) {
 756         stl_p(header+0x228, cmdline_addr);
 757     } else {
 758         stw_p(header+0x20, 0xA33F);
 759         stw_p(header+0x22, cmdline_addr-real_addr);
 760     }
 761
 762     /* handle vga= parameter */
 763     vmode = strstr(kernel_cmdline, "vga=");
 764     if (vmode) {
 765         unsigned int video_mode;
 766         /* skip "vga=" */
 767         vmode += 4;
 768         if (!strncmp(vmode, "normal", 6)) {
 769             video_mode = 0xffff;
 770         } else if (!strncmp(vmode, "ext", 3)) {
 771             video_mode = 0xfffe;
 772         } else if (!strncmp(vmode, "ask", 3)) {
 773             video_mode = 0xfffd;
 774         } else {
 775             video_mode = strtol(vmode, NULL, 0);
 776         }
 777         stw_p(header+0x1fa, video_mode);
 778     }
 779
 780     /* loader type */
 781     /* High nybble = B reserved for QEMU; low nybble is revision number.
 782        If this code is substantially changed, you may want to consider
 783        incrementing the revision. */
 784     if (protocol >= 0x200)
 785         header[0x210] = 0xB0;
 786
 787     /* heap */
 788     if (protocol >= 0x201) {
 789         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 790         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 791     }
 792
 793     /* load initrd */
 794     if (initrd_filename) {
 795         if (protocol < 0x200) {
 796             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 797             exit(1);
 798         }
 799
 800         initrd_size = get_image_size(initrd_filename);
 801         if (initrd_size < 0) {
 802             fprintf(stderr, "qemu: error reading initrd %s\n",
 803                     initrd_filename);
 804             exit(1);
 805         }
 806
 807         initrd_addr = (initrd_max-initrd_size) & ~4095;
 808
 809         initrd_data = g_malloc(initrd_size);
 810         load_image(initrd_filename, initrd_data);
 811
 812         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 813         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 814         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 815
 816         stl_p(header+0x218, initrd_addr);
 817         stl_p(header+0x21c, initrd_size);
 818     }
 819
 820     /* load kernel and setup */
 821     setup_size = header[0x1f1];
 822     if (setup_size == 0)
 823         setup_size = 4;
 824     setup_size = (setup_size+1)*512;
 825     kernel_size -= setup_size;
 826
 827     setup  = g_malloc(setup_size);
 828     kernel = g_malloc(kernel_size);
 829     fseek(f, 0, SEEK_SET);
 830     if (fread(setup, 1, setup_size, f) != setup_size) {
 831         fprintf(stderr, "fread() failed\n");
 832         exit(1);
 833     }
 834     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 835         fprintf(stderr, "fread() failed\n");
 836         exit(1);
 837     }
 838     fclose(f);
 839     memcpy(setup, header, MIN(sizeof(header), setup_size));
 840
 841     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 842     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 843     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 844
 845     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 846     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 847     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 848
 849     option_rom[nb_option_roms].name = "linuxboot.bin";
 850     option_rom[nb_option_roms].bootindex = 0;
 851     nb_option_roms++;
 852 }
 853
 854 #define NE2000_NB_MAX 6
 855
 856 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 857                                               0x280, 0x380 };
 858 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 859
 860 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 861 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 862
 863 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 864 {
 865     static int nb_ne2k = 0;
 866
 867     if (nb_ne2k == NE2000_NB_MAX)
 868         return;
 869     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 870                     ne2000_irq[nb_ne2k], nd);
 871     nb_ne2k++;
 872 }
 873
 874 int cpu_is_bsp(CPUX86State *env)
 875 {
 876     /* We hard-wire the BSP to the first CPU. */
 877     return env->cpu_index == 0;
 878 }
 879
 880 DeviceState *cpu_get_current_apic(void)
 881 {
 882     if (cpu_single_env) {
 883         return cpu_single_env->apic_state;
 884     } else {
 885         return NULL;
 886     }
 887 }
 888
 889 static DeviceState *apic_init(void *env, uint8_t apic_id)
 890 {
 891     DeviceState *dev;
 892     static int apic_mapped;
 893
 894     if (kvm_irqchip_in_kernel()) {
 895         dev = qdev_create(NULL, "kvm-apic");
 896     } else if (xen_enabled()) {
 897         dev = qdev_create(NULL, "xen-apic");
 898     } else {
 899         dev = qdev_create(NULL, "apic");
 900     }
 901
 902     qdev_prop_set_uint8(dev, "id", apic_id);
 903     qdev_prop_set_ptr(dev, "cpu_env", env);
 904     qdev_init_nofail(dev);
 905
 906     /* XXX: mapping more APICs at the same memory location */
 907     if (apic_mapped == 0) {
 908         /* NOTE: the APIC is directly connected to the CPU - it is not
 909            on the global memory bus. */
 910         /* XXX: what if the base changes? */
 911         sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
 912         apic_mapped = 1;
 913     }
 914
 915     return dev;
 916 }
 917
 918 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 919 {
 920     CPUX86State *s = opaque;
 921
 922     if (level) {
 923         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 924     }
 925 }
 926
 927 static void pc_cpu_reset(void *opaque)
 928 {
 929     X86CPU *cpu = opaque;
 930     CPUX86State *env = &cpu->env;
 931
 932     cpu_reset(CPU(cpu));
 933     env->halted = !cpu_is_bsp(env);
 934 }
 935
 936 static X86CPU *pc_new_cpu(const char *cpu_model)
 937 {
 938     X86CPU *cpu;
 939     CPUX86State *env;
 940
 941     cpu = cpu_x86_init(cpu_model);
 942     if (cpu == NULL) {
 943         fprintf(stderr, "Unable to find x86 CPU definition\n");
 944         exit(1);
 945     }
 946     env = &cpu->env;
 947     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 948         env->apic_state = apic_init(env, env->cpuid_apic_id);
 949     }
 950     qemu_register_reset(pc_cpu_reset, cpu);
 951     pc_cpu_reset(cpu);
 952     return cpu;
 953 }
 954
 955 void pc_cpus_init(const char *cpu_model)
 956 {
 957     int i;
 958
 959     /* init CPUs */
 960     if (cpu_model == NULL) {
 961 #ifdef TARGET_X86_64
 962         cpu_model = "qemu64";
 963 #else
 964         cpu_model = "qemu32";
 965 #endif
 966     }
 967
 968     for(i = 0; i < smp_cpus; i++) {
 969         pc_new_cpu(cpu_model);
 970     }
 971 }
 972
 973 void *pc_memory_init(MemoryRegion *system_memory,
 974                     const char *kernel_filename,
 975                     const char *kernel_cmdline,
 976                     const char *initrd_filename,
 977                     ram_addr_t below_4g_mem_size,
 978                     ram_addr_t above_4g_mem_size,
 979                     MemoryRegion *rom_memory,
 980                     MemoryRegion **ram_memory)
 981 {
 982     int linux_boot, i;
 983     MemoryRegion *ram, *option_rom_mr;
 984     MemoryRegion *ram_below_4g, *ram_above_4g;
 985     void *fw_cfg;
 986
 987     linux_boot = (kernel_filename != NULL);
 988
 989     /* Allocate RAM.  We allocate it as a single memory region and use
 990      * aliases to address portions of it, mostly for backwards compatibility
 991      * with older qemus that used qemu_ram_alloc().
 992      */
 993     ram = g_malloc(sizeof(*ram));
 994     memory_region_init_ram(ram, "pc.ram",
 995                            below_4g_mem_size + above_4g_mem_size);
 996     vmstate_register_ram_global(ram);
 997     *ram_memory = ram;
 998     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 999     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
1000                              0, below_4g_mem_size);
1001     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1002     if (above_4g_mem_size > 0) {
1003         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1004         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1005                                  below_4g_mem_size, above_4g_mem_size);
1006         memory_region_add_subregion(system_memory, 0x100000000ULL,
1007                                     ram_above_4g);
1008     }
1009
1010
1011     /* Initialize PC system firmware */
1012     pc_system_firmware_init(rom_memory);
1013
1014     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1015     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
1016     vmstate_register_ram_global(option_rom_mr);
1017     memory_region_add_subregion_overlap(rom_memory,
1018                                         PC_ROM_MIN_VGA,
1019                                         option_rom_mr,
1020                                         1);
1021
1022     fw_cfg = bochs_bios_init();
1023     rom_set_fw(fw_cfg);
1024
1025     if (linux_boot) {
1026         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1027     }
1028
1029     for (i = 0; i < nb_option_roms; i++) {
1030         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1031     }
1032     return fw_cfg;
1033 }
1034
1035 qemu_irq *pc_allocate_cpu_irq(void)
1036 {
1037     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1038 }
1039
1040 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1041 {
1042     DeviceState *dev = NULL;
1043
1044     if (cirrus_vga_enabled) {
1045         if (pci_bus) {
1046             dev = pci_cirrus_vga_init(pci_bus);
1047         } else {
1048             dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
1049         }
1050     } else if (vmsvga_enabled) {
1051         if (pci_bus) {
1052             dev = pci_vmsvga_init(pci_bus);
1053         } else {
1054             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1055         }
1056 #ifdef CONFIG_SPICE
1057     } else if (qxl_enabled) {
1058         if (pci_bus) {
1059             dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
1060         } else {
1061             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1062         }
1063 #endif
1064     } else if (std_vga_enabled) {
1065         if (pci_bus) {
1066             dev = pci_vga_init(pci_bus);
1067         } else {
1068             dev = isa_vga_init(isa_bus);
1069         }
1070     }
1071
1072     return dev;
1073 }
1074
1075 static void cpu_request_exit(void *opaque, int irq, int level)
1076 {
1077     CPUX86State *env = cpu_single_env;
1078
1079     if (env && level) {
1080         cpu_exit(env);
1081     }
1082 }
1083
1084 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1085                           ISADevice **rtc_state,
1086                           ISADevice **floppy,
1087                           bool no_vmport)
1088 {
1089     int i;
1090     DriveInfo *fd[MAX_FD];
1091     DeviceState *hpet = NULL;
1092     int pit_isa_irq = 0;
1093     qemu_irq pit_alt_irq = NULL;
1094     qemu_irq rtc_irq = NULL;
1095     qemu_irq *a20_line;
1096     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1097     qemu_irq *cpu_exit_irq;
1098
1099     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1100
1101     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1102
1103     /*
1104      * Check if an HPET shall be created.
1105      *
1106      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1107      * when the HPET wants to take over. Thus we have to disable the latter.
1108      */
1109     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1110         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1111
1112         if (hpet) {
1113             for (i = 0; i < GSI_NUM_PINS; i++) {
1114                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1115             }
1116             pit_isa_irq = -1;
1117             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1118             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1119         }
1120     }
1121     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1122
1123     qemu_register_boot_set(pc_boot_set, *rtc_state);
1124
1125     if (!xen_enabled()) {
1126         if (kvm_irqchip_in_kernel()) {
1127             pit = kvm_pit_init(isa_bus, 0x40);
1128         } else {
1129             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1130         }
1131         if (hpet) {
1132             /* connect PIT to output control line of the HPET */
1133             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1134         }
1135         pcspk_init(isa_bus, pit);
1136     }
1137
1138     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1139         if (serial_hds[i]) {
1140             serial_isa_init(isa_bus, i, serial_hds[i]);
1141         }
1142     }
1143
1144     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1145         if (parallel_hds[i]) {
1146             parallel_init(isa_bus, i, parallel_hds[i]);
1147         }
1148     }
1149
1150     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1151     i8042 = isa_create_simple(isa_bus, "i8042");
1152     i8042_setup_a20_line(i8042, &a20_line[0]);
1153     if (!no_vmport) {
1154         vmport_init(isa_bus);
1155         vmmouse = isa_try_create(isa_bus, "vmmouse");
1156     } else {
1157         vmmouse = NULL;
1158     }
1159     if (vmmouse) {
1160         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1161         qdev_init_nofail(&vmmouse->qdev);
1162     }
1163     port92 = isa_create_simple(isa_bus, "port92");
1164     port92_init(port92, &a20_line[1]);
1165
1166     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1167     DMA_init(0, cpu_exit_irq);
1168
1169     for(i = 0; i < MAX_FD; i++) {
1170         fd[i] = drive_get(IF_FLOPPY, 0, i);
1171     }
1172     *floppy = fdctrl_init_isa(isa_bus, fd);
1173 }
1174
1175 void pc_pci_device_init(PCIBus *pci_bus)
1176 {
1177     int max_bus;
1178     int bus;
1179
1180     max_bus = drive_get_max_bus(IF_SCSI);
1181     for (bus = 0; bus <= max_bus; bus++) {
1182         pci_create_simple(pci_bus, -1, "lsi53c895a");
1183     }
1184 }