hw/s390x/s390-pci-bus.c

   1 /*
   2  * s390 PCI BUS
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "s390-pci-bus.h"
  15 #include <hw/pci/pci_bus.h>
  16 #include <hw/pci/msi.h>
  17 #include <qemu/error-report.h>
  18
  19 /* #define DEBUG_S390PCI_BUS */
  20 #ifdef DEBUG_S390PCI_BUS
  21 #define DPRINTF(fmt, ...) \
  22     do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
  23 #else
  24 #define DPRINTF(fmt, ...) \
  25     do { } while (0)
  26 #endif
  27
  28 int chsc_sei_nt2_get_event(void *res)
  29 {
  30     ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
  31     PciCcdfAvail *accdf;
  32     PciCcdfErr *eccdf;
  33     int rc = 1;
  34     SeiContainer *sei_cont;
  35     S390pciState *s = S390_PCI_HOST_BRIDGE(
  36         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  37
  38     if (!s) {
  39         return rc;
  40     }
  41
  42     sei_cont = QTAILQ_FIRST(&s->pending_sei);
  43     if (sei_cont) {
  44         QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
  45         nt2_res->nt = 2;
  46         nt2_res->cc = sei_cont->cc;
  47         nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
  48         switch (sei_cont->cc) {
  49         case 1: /* error event */
  50             eccdf = (PciCcdfErr *)nt2_res->ccdf;
  51             eccdf->fid = cpu_to_be32(sei_cont->fid);
  52             eccdf->fh = cpu_to_be32(sei_cont->fh);
  53             eccdf->e = cpu_to_be32(sei_cont->e);
  54             eccdf->faddr = cpu_to_be64(sei_cont->faddr);
  55             eccdf->pec = cpu_to_be16(sei_cont->pec);
  56             break;
  57         case 2: /* availability event */
  58             accdf = (PciCcdfAvail *)nt2_res->ccdf;
  59             accdf->fid = cpu_to_be32(sei_cont->fid);
  60             accdf->fh = cpu_to_be32(sei_cont->fh);
  61             accdf->pec = cpu_to_be16(sei_cont->pec);
  62             break;
  63         default:
  64             abort();
  65         }
  66         g_free(sei_cont);
  67         rc = 0;
  68     }
  69
  70     return rc;
  71 }
  72
  73 int chsc_sei_nt2_have_event(void)
  74 {
  75     S390pciState *s = S390_PCI_HOST_BRIDGE(
  76         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  77
  78     if (!s) {
  79         return 0;
  80     }
  81
  82     return !QTAILQ_EMPTY(&s->pending_sei);
  83 }
  84
  85 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
  86 {
  87     S390PCIBusDevice *pbdev;
  88     int i;
  89     S390pciState *s = S390_PCI_HOST_BRIDGE(
  90         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  91
  92     if (!s) {
  93         return NULL;
  94     }
  95
  96     for (i = 0; i < PCI_SLOT_MAX; i++) {
  97         pbdev = &s->pbdev[i];
  98         if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
  99             return pbdev;
 100         }
 101     }
 102
 103     return NULL;
 104 }
 105
 106 void s390_pci_sclp_configure(int configure, SCCB *sccb)
 107 {
 108     PciCfgSccb *psccb = (PciCfgSccb *)sccb;
 109     S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
 110     uint16_t rc;
 111
 112     if (pbdev) {
 113         if ((configure == 1 && pbdev->configured == true) ||
 114             (configure == 0 && pbdev->configured == false)) {
 115             rc = SCLP_RC_NO_ACTION_REQUIRED;
 116         } else {
 117             pbdev->configured = !pbdev->configured;
 118             rc = SCLP_RC_NORMAL_COMPLETION;
 119         }
 120     } else {
 121         DPRINTF("sclp config %d no dev found\n", configure);
 122         rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
 123     }
 124
 125     psccb->header.response_code = cpu_to_be16(rc);
 126     return;
 127 }
 128
 129 static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
 130 {
 131     return PCI_SLOT(pdev->devfn);
 132 }
 133
 134 static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
 135 {
 136     return PCI_SLOT(pdev->devfn) | FH_VIRT;
 137 }
 138
 139 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
 140 {
 141     S390PCIBusDevice *pbdev;
 142     int i;
 143     int j = 0;
 144     S390pciState *s = S390_PCI_HOST_BRIDGE(
 145         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 146
 147     if (!s) {
 148         return NULL;
 149     }
 150
 151     for (i = 0; i < PCI_SLOT_MAX; i++) {
 152         pbdev = &s->pbdev[i];
 153
 154         if (pbdev->fh == 0) {
 155             continue;
 156         }
 157
 158         if (j == idx) {
 159             return pbdev;
 160         }
 161         j++;
 162     }
 163
 164     return NULL;
 165 }
 166
 167 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
 168 {
 169     S390PCIBusDevice *pbdev;
 170     int i;
 171     S390pciState *s = S390_PCI_HOST_BRIDGE(
 172         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 173
 174     if (!s || !fh) {
 175         return NULL;
 176     }
 177
 178     for (i = 0; i < PCI_SLOT_MAX; i++) {
 179         pbdev = &s->pbdev[i];
 180         if (pbdev->fh == fh) {
 181             return pbdev;
 182         }
 183     }
 184
 185     return NULL;
 186 }
 187
 188 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
 189                                     uint32_t fid, uint64_t faddr, uint32_t e)
 190 {
 191     SeiContainer *sei_cont;
 192     S390pciState *s = S390_PCI_HOST_BRIDGE(
 193         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 194
 195     if (!s) {
 196         return;
 197     }
 198
 199     sei_cont = g_malloc0(sizeof(SeiContainer));
 200     sei_cont->fh = fh;
 201     sei_cont->fid = fid;
 202     sei_cont->cc = cc;
 203     sei_cont->pec = pec;
 204     sei_cont->faddr = faddr;
 205     sei_cont->e = e;
 206
 207     QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
 208     css_generate_css_crws(0);
 209 }
 210
 211 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
 212                                          uint32_t fid)
 213 {
 214     s390_pci_generate_event(2, pec, fh, fid, 0, 0);
 215 }
 216
 217 static void s390_pci_generate_error_event(uint16_t pec, uint32_t fh,
 218                                           uint32_t fid, uint64_t faddr,
 219                                           uint32_t e)
 220 {
 221     s390_pci_generate_event(1, pec, fh, fid, faddr, e);
 222 }
 223
 224 static void s390_pci_set_irq(void *opaque, int irq, int level)
 225 {
 226     /* nothing to do */
 227 }
 228
 229 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 230 {
 231     /* nothing to do */
 232     return 0;
 233 }
 234
 235 static uint64_t s390_pci_get_table_origin(uint64_t iota)
 236 {
 237     return iota & ~ZPCI_IOTA_RTTO_FLAG;
 238 }
 239
 240 static unsigned int calc_rtx(dma_addr_t ptr)
 241 {
 242     return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
 243 }
 244
 245 static unsigned int calc_sx(dma_addr_t ptr)
 246 {
 247     return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
 248 }
 249
 250 static unsigned int calc_px(dma_addr_t ptr)
 251 {
 252     return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
 253 }
 254
 255 static uint64_t get_rt_sto(uint64_t entry)
 256 {
 257     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
 258                 ? (entry & ZPCI_RTE_ADDR_MASK)
 259                 : 0;
 260 }
 261
 262 static uint64_t get_st_pto(uint64_t entry)
 263 {
 264     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
 265             ? (entry & ZPCI_STE_ADDR_MASK)
 266             : 0;
 267 }
 268
 269 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
 270                                   uint64_t guest_dma_address)
 271 {
 272     uint64_t sto_a, pto_a, px_a;
 273     uint64_t sto, pto, pte;
 274     uint32_t rtx, sx, px;
 275
 276     rtx = calc_rtx(guest_dma_address);
 277     sx = calc_sx(guest_dma_address);
 278     px = calc_px(guest_dma_address);
 279
 280     sto_a = guest_iota + rtx * sizeof(uint64_t);
 281     sto = address_space_ldq(&address_space_memory, sto_a,
 282                             MEMTXATTRS_UNSPECIFIED, NULL);
 283     sto = get_rt_sto(sto);
 284     if (!sto) {
 285         pte = 0;
 286         goto out;
 287     }
 288
 289     pto_a = sto + sx * sizeof(uint64_t);
 290     pto = address_space_ldq(&address_space_memory, pto_a,
 291                             MEMTXATTRS_UNSPECIFIED, NULL);
 292     pto = get_st_pto(pto);
 293     if (!pto) {
 294         pte = 0;
 295         goto out;
 296     }
 297
 298     px_a = pto + px * sizeof(uint64_t);
 299     pte = address_space_ldq(&address_space_memory, px_a,
 300                             MEMTXATTRS_UNSPECIFIED, NULL);
 301
 302 out:
 303     return pte;
 304 }
 305
 306 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
 307                                           bool is_write)
 308 {
 309     uint64_t pte;
 310     uint32_t flags;
 311     S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, mr);
 312     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)
 313                                            ->qbus.parent);
 314     IOMMUTLBEntry ret = {
 315         .target_as = &address_space_memory,
 316         .iova = 0,
 317         .translated_addr = 0,
 318         .addr_mask = ~(hwaddr)0,
 319         .perm = IOMMU_NONE,
 320     };
 321
 322     DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
 323
 324     /* s390 does not have an APIC mapped to main storage so we use
 325      * a separate AddressSpace only for msix notifications
 326      */
 327     if (addr == ZPCI_MSI_ADDR) {
 328         ret.target_as = &s->msix_notify_as;
 329         ret.iova = addr;
 330         ret.translated_addr = addr;
 331         ret.addr_mask = 0xfff;
 332         ret.perm = IOMMU_RW;
 333         return ret;
 334     }
 335
 336     if (!pbdev->g_iota) {
 337         pbdev->error_state = true;
 338         pbdev->lgstg_blocked = true;
 339         s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
 340                                       addr, 0);
 341         return ret;
 342     }
 343
 344     if (addr < pbdev->pba || addr > pbdev->pal) {
 345         pbdev->error_state = true;
 346         pbdev->lgstg_blocked = true;
 347         s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
 348                                       addr, 0);
 349         return ret;
 350     }
 351
 352     pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
 353                                    addr);
 354
 355     if (!pte) {
 356         pbdev->error_state = true;
 357         pbdev->lgstg_blocked = true;
 358         s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
 359                                       addr, ERR_EVENT_Q_BIT);
 360         return ret;
 361     }
 362
 363     flags = pte & ZPCI_PTE_FLAG_MASK;
 364     ret.iova = addr;
 365     ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
 366     ret.addr_mask = 0xfff;
 367
 368     if (flags & ZPCI_PTE_INVALID) {
 369         ret.perm = IOMMU_NONE;
 370     } else {
 371         ret.perm = IOMMU_RW;
 372     }
 373
 374     return ret;
 375 }
 376
 377 static const MemoryRegionIOMMUOps s390_iommu_ops = {
 378     .translate = s390_translate_iommu,
 379 };
 380
 381 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 382 {
 383     S390pciState *s = opaque;
 384
 385     return &s->pbdev[PCI_SLOT(devfn)].as;
 386 }
 387
 388 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
 389 {
 390     uint8_t ind_old, ind_new;
 391     hwaddr len = 1;
 392     uint8_t *ind_addr;
 393
 394     ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
 395     if (!ind_addr) {
 396         s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
 397         return -1;
 398     }
 399     do {
 400         ind_old = *ind_addr;
 401         ind_new = ind_old | to_be_set;
 402     } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
 403     cpu_physical_memory_unmap(ind_addr, len, 1, len);
 404
 405     return ind_old;
 406 }
 407
 408 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
 409                                 unsigned int size)
 410 {
 411     S390PCIBusDevice *pbdev;
 412     uint32_t io_int_word;
 413     uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
 414     uint32_t vec = data & ZPCI_MSI_VEC_MASK;
 415     uint64_t ind_bit;
 416     uint32_t sum_bit;
 417     uint32_t e = 0;
 418
 419     DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
 420
 421     pbdev = s390_pci_find_dev_by_fid(fid);
 422     if (!pbdev) {
 423         e |= (vec << ERR_EVENT_MVN_OFFSET);
 424         s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
 425         return;
 426     }
 427
 428     ind_bit = pbdev->routes.adapter.ind_offset;
 429     sum_bit = pbdev->routes.adapter.summary_offset;
 430
 431     set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
 432                    0x80 >> ((ind_bit + vec) % 8));
 433     if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
 434                                        0x80 >> (sum_bit % 8))) {
 435         io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
 436         s390_io_interrupt(0, 0, 0, io_int_word);
 437     }
 438
 439     return;
 440 }
 441
 442 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
 443 {
 444     return 0xffffffff;
 445 }
 446
 447 static const MemoryRegionOps s390_msi_ctrl_ops = {
 448     .write = s390_msi_ctrl_write,
 449     .read = s390_msi_ctrl_read,
 450     .endianness = DEVICE_LITTLE_ENDIAN,
 451 };
 452
 453 static void s390_pcihost_init_as(S390pciState *s)
 454 {
 455     int i;
 456
 457     for (i = 0; i < PCI_SLOT_MAX; i++) {
 458         memory_region_init_iommu(&s->pbdev[i].mr, OBJECT(s),
 459                                  &s390_iommu_ops, "iommu-s390", UINT64_MAX);
 460         address_space_init(&s->pbdev[i].as, &s->pbdev[i].mr, "iommu-pci");
 461     }
 462
 463     memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
 464                           &s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
 465     address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
 466 }
 467
 468 static int s390_pcihost_init(SysBusDevice *dev)
 469 {
 470     PCIBus *b;
 471     BusState *bus;
 472     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 473     S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
 474
 475     DPRINTF("host_init\n");
 476
 477     b = pci_register_bus(DEVICE(dev), NULL,
 478                          s390_pci_set_irq, s390_pci_map_irq, NULL,
 479                          get_system_memory(), get_system_io(), 0, 64,
 480                          TYPE_PCI_BUS);
 481     s390_pcihost_init_as(s);
 482     pci_setup_iommu(b, s390_pci_dma_iommu, s);
 483
 484     bus = BUS(b);
 485     qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
 486     phb->bus = b;
 487     QTAILQ_INIT(&s->pending_sei);
 488     return 0;
 489 }
 490
 491 static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
 492 {
 493     uint8_t pos;
 494     uint16_t ctrl;
 495     uint32_t table, pba;
 496
 497     pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
 498     if (!pos) {
 499         pbdev->msix.available = false;
 500         return 0;
 501     }
 502
 503     ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_CAP_FLAGS,
 504              pci_config_size(pbdev->pdev), sizeof(ctrl));
 505     table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
 506              pci_config_size(pbdev->pdev), sizeof(table));
 507     pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
 508              pci_config_size(pbdev->pdev), sizeof(pba));
 509
 510     pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
 511     pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
 512     pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
 513     pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
 514     pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
 515     pbdev->msix.available = true;
 516     return 0;
 517 }
 518
 519 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
 520                                   DeviceState *dev, Error **errp)
 521 {
 522     PCIDevice *pci_dev = PCI_DEVICE(dev);
 523     S390PCIBusDevice *pbdev;
 524     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 525                                            ->qbus.parent);
 526
 527     pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 528
 529     pbdev->fid = s390_pci_get_pfid(pci_dev);
 530     pbdev->pdev = pci_dev;
 531     pbdev->configured = true;
 532     pbdev->fh = s390_pci_get_pfh(pci_dev);
 533
 534     s390_pcihost_setup_msix(pbdev);
 535
 536     if (dev->hotplugged) {
 537         s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
 538                                      pbdev->fh, pbdev->fid);
 539         s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
 540                                      pbdev->fh, pbdev->fid);
 541     }
 542     return;
 543 }
 544
 545 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
 546                                     DeviceState *dev, Error **errp)
 547 {
 548     PCIDevice *pci_dev = PCI_DEVICE(dev);
 549     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 550                                            ->qbus.parent);
 551     S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 552
 553     if (pbdev->configured) {
 554         pbdev->configured = false;
 555         s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
 556                                      pbdev->fh, pbdev->fid);
 557     }
 558
 559     s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
 560                                  pbdev->fh, pbdev->fid);
 561     pbdev->fh = 0;
 562     pbdev->fid = 0;
 563     pbdev->pdev = NULL;
 564     object_unparent(OBJECT(pci_dev));
 565 }
 566
 567 static void s390_pcihost_class_init(ObjectClass *klass, void *data)
 568 {
 569     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 570     DeviceClass *dc = DEVICE_CLASS(klass);
 571     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 572
 573     dc->cannot_instantiate_with_device_add_yet = true;
 574     k->init = s390_pcihost_init;
 575     hc->plug = s390_pcihost_hot_plug;
 576     hc->unplug = s390_pcihost_hot_unplug;
 577     msi_supported = true;
 578 }
 579
 580 static const TypeInfo s390_pcihost_info = {
 581     .name          = TYPE_S390_PCI_HOST_BRIDGE,
 582     .parent        = TYPE_PCI_HOST_BRIDGE,
 583     .instance_size = sizeof(S390pciState),
 584     .class_init    = s390_pcihost_class_init,
 585     .interfaces = (InterfaceInfo[]) {
 586         { TYPE_HOTPLUG_HANDLER },
 587         { }
 588     }
 589 };
 590
 591 static void s390_pci_register_types(void)
 592 {
 593     type_register_static(&s390_pcihost_info);
 594 }
 595
 596 type_init(s390_pci_register_types)