arm_mptimer: Respect IT bit state
[qemu/cris-port.git] / hw / cpu / icc_bus.c
blob6646ea2b34d46144f688429687a92f2fd754607b
1 /* icc_bus.c
2 * emulate x86 ICC (Interrupt Controller Communications) bus
4 * Copyright (c) 2013 Red Hat, Inc
6 * Authors:
7 * Igor Mammedov <imammedo@redhat.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>
22 #include "hw/cpu/icc_bus.h"
23 #include "hw/sysbus.h"
25 /* icc-bridge implementation */
27 static const TypeInfo icc_bus_info = {
28 .name = TYPE_ICC_BUS,
29 .parent = TYPE_BUS,
30 .instance_size = sizeof(ICCBus),
34 /* icc-device implementation */
36 static void icc_device_realize(DeviceState *dev, Error **errp)
38 ICCDeviceClass *idc = ICC_DEVICE_GET_CLASS(dev);
40 /* convert to QOM */
41 if (idc->realize) {
42 idc->realize(dev, errp);
47 static void icc_device_class_init(ObjectClass *oc, void *data)
49 DeviceClass *dc = DEVICE_CLASS(oc);
51 dc->realize = icc_device_realize;
52 dc->bus_type = TYPE_ICC_BUS;
55 static const TypeInfo icc_device_info = {
56 .name = TYPE_ICC_DEVICE,
57 .parent = TYPE_DEVICE,
58 .abstract = true,
59 .instance_size = sizeof(ICCDevice),
60 .class_size = sizeof(ICCDeviceClass),
61 .class_init = icc_device_class_init,
65 /* icc-bridge implementation */
67 typedef struct ICCBridgeState {
68 /*< private >*/
69 SysBusDevice parent_obj;
70 /*< public >*/
72 ICCBus icc_bus;
73 MemoryRegion apic_container;
74 } ICCBridgeState;
76 #define ICC_BRIDGE(obj) OBJECT_CHECK(ICCBridgeState, (obj), TYPE_ICC_BRIDGE)
78 static void icc_bridge_init(Object *obj)
80 ICCBridgeState *s = ICC_BRIDGE(obj);
81 SysBusDevice *sb = SYS_BUS_DEVICE(obj);
83 qbus_create_inplace(&s->icc_bus, sizeof(s->icc_bus), TYPE_ICC_BUS,
84 DEVICE(s), "icc");
86 /* Do not change order of registering regions,
87 * APIC must be first registered region, board maps it by 0 index
89 memory_region_init(&s->apic_container, obj, "icc-apic-container",
90 APIC_SPACE_SIZE);
91 sysbus_init_mmio(sb, &s->apic_container);
92 s->icc_bus.apic_address_space = &s->apic_container;
95 static void icc_bridge_class_init(ObjectClass *oc, void *data)
97 DeviceClass *dc = DEVICE_CLASS(oc);
99 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
102 static const TypeInfo icc_bridge_info = {
103 .name = TYPE_ICC_BRIDGE,
104 .parent = TYPE_SYS_BUS_DEVICE,
105 .instance_init = icc_bridge_init,
106 .instance_size = sizeof(ICCBridgeState),
107 .class_init = icc_bridge_class_init,
111 static void icc_bus_register_types(void)
113 type_register_static(&icc_bus_info);
114 type_register_static(&icc_device_info);
115 type_register_static(&icc_bridge_info);
118 type_init(icc_bus_register_types)