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arm_mptimer: Respect IT bit state
[qemu/cris-port.git] / hw / audio / ac97.c
blobb17383555ee00a7f2f74ca8067aebd9c71297a92
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 */
19
20 #include "hw/hw.h"
21 #include "hw/audio/audio.h"
22 #include "audio/audio.h"
23 #include "hw/pci/pci.h"
24 #include "sysemu/dma.h"
25
26 enum {
27 AC97_Reset = 0x00,
28 AC97_Master_Volume_Mute = 0x02,
29 AC97_Headphone_Volume_Mute = 0x04,
30 AC97_Master_Volume_Mono_Mute = 0x06,
31 AC97_Master_Tone_RL = 0x08,
32 AC97_PC_BEEP_Volume_Mute = 0x0A,
33 AC97_Phone_Volume_Mute = 0x0C,
34 AC97_Mic_Volume_Mute = 0x0E,
35 AC97_Line_In_Volume_Mute = 0x10,
36 AC97_CD_Volume_Mute = 0x12,
37 AC97_Video_Volume_Mute = 0x14,
38 AC97_Aux_Volume_Mute = 0x16,
39 AC97_PCM_Out_Volume_Mute = 0x18,
40 AC97_Record_Select = 0x1A,
41 AC97_Record_Gain_Mute = 0x1C,
42 AC97_Record_Gain_Mic_Mute = 0x1E,
43 AC97_General_Purpose = 0x20,
44 AC97_3D_Control = 0x22,
45 AC97_AC_97_RESERVED = 0x24,
46 AC97_Powerdown_Ctrl_Stat = 0x26,
47 AC97_Extended_Audio_ID = 0x28,
48 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
49 AC97_PCM_Front_DAC_Rate = 0x2C,
50 AC97_PCM_Surround_DAC_Rate = 0x2E,
51 AC97_PCM_LFE_DAC_Rate = 0x30,
52 AC97_PCM_LR_ADC_Rate = 0x32,
53 AC97_MIC_ADC_Rate = 0x34,
54 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
55 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
56 AC97_Vendor_Reserved = 0x58,
57 AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
58 AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
59 AC97_Vendor_ID1 = 0x7c,
60 AC97_Vendor_ID2 = 0x7e
61 };
62
63 #define SOFT_VOLUME
64 #define SR_FIFOE 16 /* rwc */
65 #define SR_BCIS 8 /* rwc */
66 #define SR_LVBCI 4 /* rwc */
67 #define SR_CELV 2 /* ro */
68 #define SR_DCH 1 /* ro */
69 #define SR_VALID_MASK ((1 << 5) - 1)
70 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
71 #define SR_RO_MASK (SR_DCH | SR_CELV)
72 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
73
74 #define CR_IOCE 16 /* rw */
75 #define CR_FEIE 8 /* rw */
76 #define CR_LVBIE 4 /* rw */
77 #define CR_RR 2 /* rw */
78 #define CR_RPBM 1 /* rw */
79 #define CR_VALID_MASK ((1 << 5) - 1)
80 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
81
82 #define GC_WR 4 /* rw */
83 #define GC_CR 2 /* rw */
84 #define GC_VALID_MASK ((1 << 6) - 1)
85
86 #define GS_MD3 (1<<17) /* rw */
87 #define GS_AD3 (1<<16) /* rw */
88 #define GS_RCS (1<<15) /* rwc */
89 #define GS_B3S12 (1<<14) /* ro */
90 #define GS_B2S12 (1<<13) /* ro */
91 #define GS_B1S12 (1<<12) /* ro */
92 #define GS_S1R1 (1<<11) /* rwc */
93 #define GS_S0R1 (1<<10) /* rwc */
94 #define GS_S1CR (1<<9) /* ro */
95 #define GS_S0CR (1<<8) /* ro */
96 #define GS_MINT (1<<7) /* ro */
97 #define GS_POINT (1<<6) /* ro */
98 #define GS_PIINT (1<<5) /* ro */
99 #define GS_RSRVD ((1<<4)|(1<<3))
100 #define GS_MOINT (1<<2) /* ro */
101 #define GS_MIINT (1<<1) /* ro */
102 #define GS_GSCI 1 /* rwc */
103 #define GS_RO_MASK (GS_B3S12| \
104 GS_B2S12| \
105 GS_B1S12| \
106 GS_S1CR| \
107 GS_S0CR| \
108 GS_MINT| \
109 GS_POINT| \
110 GS_PIINT| \
111 GS_RSRVD| \
112 GS_MOINT| \
113 GS_MIINT)
114 #define GS_VALID_MASK ((1 << 18) - 1)
115 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
116
117 #define BD_IOC (1<<31)
118 #define BD_BUP (1<<30)
119
120 #define EACS_VRA 1
121 #define EACS_VRM 8
122
123 #define MUTE_SHIFT 15
124
125 #define REC_MASK 7
126 enum {
127 REC_MIC = 0,
128 REC_CD,
129 REC_VIDEO,
130 REC_AUX,
131 REC_LINE_IN,
132 REC_STEREO_MIX,
133 REC_MONO_MIX,
134 REC_PHONE
135 };
136
137 typedef struct BD {
138 uint32_t addr;
139 uint32_t ctl_len;
140 } BD;
141
142 typedef struct AC97BusMasterRegs {
143 uint32_t bdbar; /* rw 0 */
144 uint8_t civ; /* ro 0 */
145 uint8_t lvi; /* rw 0 */
146 uint16_t sr; /* rw 1 */
147 uint16_t picb; /* ro 0 */
148 uint8_t piv; /* ro 0 */
149 uint8_t cr; /* rw 0 */
150 unsigned int bd_valid;
151 BD bd;
152 } AC97BusMasterRegs;
153
154 typedef struct AC97LinkState {
155 PCIDevice dev;
156 QEMUSoundCard card;
157 uint32_t use_broken_id;
158 uint32_t glob_cnt;
159 uint32_t glob_sta;
160 uint32_t cas;
161 uint32_t last_samp;
162 AC97BusMasterRegs bm_regs[3];
163 uint8_t mixer_data[256];
164 SWVoiceIn *voice_pi;
165 SWVoiceOut *voice_po;
166 SWVoiceIn *voice_mc;
167 int invalid_freq[3];
168 uint8_t silence[128];
169 int bup_flag;
170 MemoryRegion io_nam;
171 MemoryRegion io_nabm;
172 } AC97LinkState;
173
174 enum {
175 BUP_SET = 1,
176 BUP_LAST = 2
177 };
178
179 #ifdef DEBUG_AC97
180 #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
181 #else
182 #define dolog(...)
183 #endif
184
185 #define MKREGS(prefix, start) \
186 enum { \
187 prefix ## _BDBAR = start, \
188 prefix ## _CIV = start + 4, \
189 prefix ## _LVI = start + 5, \
190 prefix ## _SR = start + 6, \
191 prefix ## _PICB = start + 8, \
192 prefix ## _PIV = start + 10, \
193 prefix ## _CR = start + 11 \
194 }
195
196 enum {
197 PI_INDEX = 0,
198 PO_INDEX,
199 MC_INDEX,
200 LAST_INDEX
201 };
202
203 MKREGS (PI, PI_INDEX * 16);
204 MKREGS (PO, PO_INDEX * 16);
205 MKREGS (MC, MC_INDEX * 16);
206
207 enum {
208 GLOB_CNT = 0x2c,
209 GLOB_STA = 0x30,
210 CAS = 0x34
211 };
212
213 #define GET_BM(index) (((index) >> 4) & 3)
214
215 static void po_callback (void *opaque, int free);
216 static void pi_callback (void *opaque, int avail);
217 static void mc_callback (void *opaque, int avail);
218
219 static void warm_reset (AC97LinkState *s)
220 {
221 (void) s;
222 }
223
224 static void cold_reset (AC97LinkState * s)
225 {
226 (void) s;
227 }
228
229 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
230 {
231 uint8_t b[8];
232
233 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
234 r->bd_valid = 1;
235 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
236 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
237 r->picb = r->bd.ctl_len & 0xffff;
238 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
239 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
240 r->bd.ctl_len & 0xffff,
241 (r->bd.ctl_len & 0xffff) << 1);
242 }
243
244 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
245 {
246 int event = 0;
247 int level = 0;
248 uint32_t new_mask = new_sr & SR_INT_MASK;
249 uint32_t old_mask = r->sr & SR_INT_MASK;
250 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
251
252 if (new_mask ^ old_mask) {
253 /** @todo is IRQ deasserted when only one of status bits is cleared? */
254 if (!new_mask) {
255 event = 1;
256 level = 0;
257 }
258 else {
259 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
260 event = 1;
261 level = 1;
262 }
263 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
264 event = 1;
265 level = 1;
266 }
267 }
268 }
269
270 r->sr = new_sr;
271
272 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
273 r->sr & SR_BCIS, r->sr & SR_LVBCI,
274 r->sr,
275 event, level);
276
277 if (!event)
278 return;
279
280 if (level) {
281 s->glob_sta |= masks[r - s->bm_regs];
282 dolog ("set irq level=1\n");
283 pci_irq_assert(&s->dev);
284 }
285 else {
286 s->glob_sta &= ~masks[r - s->bm_regs];
287 dolog ("set irq level=0\n");
288 pci_irq_deassert(&s->dev);
289 }
290 }
291
292 static void voice_set_active (AC97LinkState *s, int bm_index, int on)
293 {
294 switch (bm_index) {
295 case PI_INDEX:
296 AUD_set_active_in (s->voice_pi, on);
297 break;
298
299 case PO_INDEX:
300 AUD_set_active_out (s->voice_po, on);
301 break;
302
303 case MC_INDEX:
304 AUD_set_active_in (s->voice_mc, on);
305 break;
306
307 default:
308 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
309 break;
310 }
311 }
312
313 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
314 {
315 dolog ("reset_bm_regs\n");
316 r->bdbar = 0;
317 r->civ = 0;
318 r->lvi = 0;
319 /** todo do we need to do that? */
320 update_sr (s, r, SR_DCH);
321 r->picb = 0;
322 r->piv = 0;
323 r->cr = r->cr & CR_DONT_CLEAR_MASK;
324 r->bd_valid = 0;
325
326 voice_set_active (s, r - s->bm_regs, 0);
327 memset (s->silence, 0, sizeof (s->silence));
328 }
329
330 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
331 {
332 if (i + 2 > sizeof (s->mixer_data)) {
333 dolog ("mixer_store: index %d out of bounds %zd\n",
334 i, sizeof (s->mixer_data));
335 return;
336 }
337
338 s->mixer_data[i + 0] = v & 0xff;
339 s->mixer_data[i + 1] = v >> 8;
340 }
341
342 static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
343 {
344 uint16_t val = 0xffff;
345
346 if (i + 2 > sizeof (s->mixer_data)) {
347 dolog ("mixer_load: index %d out of bounds %zd\n",
348 i, sizeof (s->mixer_data));
349 }
350 else {
351 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
352 }
353
354 return val;
355 }
356
357 static void open_voice (AC97LinkState *s, int index, int freq)
358 {
359 struct audsettings as;
360
361 as.freq = freq;
362 as.nchannels = 2;
363 as.fmt = AUD_FMT_S16;
364 as.endianness = 0;
365
366 if (freq > 0) {
367 s->invalid_freq[index] = 0;
368 switch (index) {
369 case PI_INDEX:
370 s->voice_pi = AUD_open_in (
371 &s->card,
372 s->voice_pi,
373 "ac97.pi",
374 s,
375 pi_callback,
376 &as
377 );
378 break;
379
380 case PO_INDEX:
381 s->voice_po = AUD_open_out (
382 &s->card,
383 s->voice_po,
384 "ac97.po",
385 s,
386 po_callback,
387 &as
388 );
389 break;
390
391 case MC_INDEX:
392 s->voice_mc = AUD_open_in (
393 &s->card,
394 s->voice_mc,
395 "ac97.mc",
396 s,
397 mc_callback,
398 &as
399 );
400 break;
401 }
402 }
403 else {
404 s->invalid_freq[index] = freq;
405 switch (index) {
406 case PI_INDEX:
407 AUD_close_in (&s->card, s->voice_pi);
408 s->voice_pi = NULL;
409 break;
410
411 case PO_INDEX:
412 AUD_close_out (&s->card, s->voice_po);
413 s->voice_po = NULL;
414 break;
415
416 case MC_INDEX:
417 AUD_close_in (&s->card, s->voice_mc);
418 s->voice_mc = NULL;
419 break;
420 }
421 }
422 }
423
424 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
425 {
426 uint16_t freq;
427
428 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
429 open_voice (s, PI_INDEX, freq);
430 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
431
432 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
433 open_voice (s, PO_INDEX, freq);
434 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
435
436 freq = mixer_load (s, AC97_MIC_ADC_Rate);
437 open_voice (s, MC_INDEX, freq);
438 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
439 }
440
441 static void get_volume (uint16_t vol, uint16_t mask, int inverse,
442 int *mute, uint8_t *lvol, uint8_t *rvol)
443 {
444 *mute = (vol >> MUTE_SHIFT) & 1;
445 *rvol = (255 * (vol & mask)) / mask;
446 *lvol = (255 * ((vol >> 8) & mask)) / mask;
447
448 if (inverse) {
449 *rvol = 255 - *rvol;
450 *lvol = 255 - *lvol;
451 }
452 }
453
454 static void update_combined_volume_out (AC97LinkState *s)
455 {
456 uint8_t lvol, rvol, plvol, prvol;
457 int mute, pmute;
458
459 get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1,
460 &mute, &lvol, &rvol);
461 get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x1f, 1,
462 &pmute, &plvol, &prvol);
463
464 mute = mute | pmute;
465 lvol = (lvol * plvol) / 255;
466 rvol = (rvol * prvol) / 255;
467
468 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
469 }
470
471 static void update_volume_in (AC97LinkState *s)
472 {
473 uint8_t lvol, rvol;
474 int mute;
475
476 get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0,
477 &mute, &lvol, &rvol);
478
479 AUD_set_volume_in (s->voice_pi, mute, lvol, rvol);
480 }
481
482 static void set_volume (AC97LinkState *s, int index, uint32_t val)
483 {
484 switch (index) {
485 case AC97_Master_Volume_Mute:
486 val &= 0xbf3f;
487 mixer_store (s, index, val);
488 update_combined_volume_out (s);
489 break;
490 case AC97_PCM_Out_Volume_Mute:
491 val &= 0x9f1f;
492 mixer_store (s, index, val);
493 update_combined_volume_out (s);
494 break;
495 case AC97_Record_Gain_Mute:
496 val &= 0x8f0f;
497 mixer_store (s, index, val);
498 update_volume_in (s);
499 break;
500 }
501 }
502
503 static void record_select (AC97LinkState *s, uint32_t val)
504 {
505 uint8_t rs = val & REC_MASK;
506 uint8_t ls = (val >> 8) & REC_MASK;
507 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
508 }
509
510 static void mixer_reset (AC97LinkState *s)
511 {
512 uint8_t active[LAST_INDEX];
513
514 dolog ("mixer_reset\n");
515 memset (s->mixer_data, 0, sizeof (s->mixer_data));
516 memset (active, 0, sizeof (active));
517 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
518 mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000);
519 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000);
520 mixer_store (s, AC97_Master_Tone_RL, 0x0000);
521 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
522 mixer_store (s, AC97_Phone_Volume_Mute , 0x0000);
523 mixer_store (s, AC97_Mic_Volume_Mute , 0x0000);
524 mixer_store (s, AC97_Line_In_Volume_Mute , 0x0000);
525 mixer_store (s, AC97_CD_Volume_Mute , 0x0000);
526 mixer_store (s, AC97_Video_Volume_Mute , 0x0000);
527 mixer_store (s, AC97_Aux_Volume_Mute , 0x0000);
528 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000);
529 mixer_store (s, AC97_General_Purpose , 0x0000);
530 mixer_store (s, AC97_3D_Control , 0x0000);
531 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
532
533 /*
534 * Sigmatel 9700 (STAC9700)
535 */
536 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
537 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
538
539 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
540 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
541 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
542 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
543 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
544 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
545 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
546
547 record_select (s, 0);
548 set_volume (s, AC97_Master_Volume_Mute, 0x8000);
549 set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808);
550 set_volume (s, AC97_Record_Gain_Mute, 0x8808);
551
552 reset_voices (s, active);
553 }
554
555 /**
556 * Native audio mixer
557 * I/O Reads
558 */
559 static uint32_t nam_readb (void *opaque, uint32_t addr)
560 {
561 AC97LinkState *s = opaque;
562 dolog ("U nam readb %#x\n", addr);
563 s->cas = 0;
564 return ~0U;
565 }
566
567 static uint32_t nam_readw (void *opaque, uint32_t addr)
568 {
569 AC97LinkState *s = opaque;
570 uint32_t val = ~0U;
571 uint32_t index = addr;
572 s->cas = 0;
573 val = mixer_load (s, index);
574 return val;
575 }
576
577 static uint32_t nam_readl (void *opaque, uint32_t addr)
578 {
579 AC97LinkState *s = opaque;
580 dolog ("U nam readl %#x\n", addr);
581 s->cas = 0;
582 return ~0U;
583 }
584
585 /**
586 * Native audio mixer
587 * I/O Writes
588 */
589 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
590 {
591 AC97LinkState *s = opaque;
592 dolog ("U nam writeb %#x <- %#x\n", addr, val);
593 s->cas = 0;
594 }
595
596 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
597 {
598 AC97LinkState *s = opaque;
599 uint32_t index = addr;
600 s->cas = 0;
601 switch (index) {
602 case AC97_Reset:
603 mixer_reset (s);
604 break;
605 case AC97_Powerdown_Ctrl_Stat:
606 val &= ~0x800f;
607 val |= mixer_load (s, index) & 0xf;
608 mixer_store (s, index, val);
609 break;
610 case AC97_PCM_Out_Volume_Mute:
611 case AC97_Master_Volume_Mute:
612 case AC97_Record_Gain_Mute:
613 set_volume (s, index, val);
614 break;
615 case AC97_Record_Select:
616 record_select (s, val);
617 break;
618 case AC97_Vendor_ID1:
619 case AC97_Vendor_ID2:
620 dolog ("Attempt to write vendor ID to %#x\n", val);
621 break;
622 case AC97_Extended_Audio_ID:
623 dolog ("Attempt to write extended audio ID to %#x\n", val);
624 break;
625 case AC97_Extended_Audio_Ctrl_Stat:
626 if (!(val & EACS_VRA)) {
627 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
628 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
629 open_voice (s, PI_INDEX, 48000);
630 open_voice (s, PO_INDEX, 48000);
631 }
632 if (!(val & EACS_VRM)) {
633 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
634 open_voice (s, MC_INDEX, 48000);
635 }
636 dolog ("Setting extended audio control to %#x\n", val);
637 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
638 break;
639 case AC97_PCM_Front_DAC_Rate:
640 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
641 mixer_store (s, index, val);
642 dolog ("Set front DAC rate to %d\n", val);
643 open_voice (s, PO_INDEX, val);
644 }
645 else {
646 dolog ("Attempt to set front DAC rate to %d, "
647 "but VRA is not set\n",
648 val);
649 }
650 break;
651 case AC97_MIC_ADC_Rate:
652 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
653 mixer_store (s, index, val);
654 dolog ("Set MIC ADC rate to %d\n", val);
655 open_voice (s, MC_INDEX, val);
656 }
657 else {
658 dolog ("Attempt to set MIC ADC rate to %d, "
659 "but VRM is not set\n",
660 val);
661 }
662 break;
663 case AC97_PCM_LR_ADC_Rate:
664 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
665 mixer_store (s, index, val);
666 dolog ("Set front LR ADC rate to %d\n", val);
667 open_voice (s, PI_INDEX, val);
668 }
669 else {
670 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
671 val);
672 }
673 break;
674 case AC97_Headphone_Volume_Mute:
675 case AC97_Master_Volume_Mono_Mute:
676 case AC97_Master_Tone_RL:
677 case AC97_PC_BEEP_Volume_Mute:
678 case AC97_Phone_Volume_Mute:
679 case AC97_Mic_Volume_Mute:
680 case AC97_Line_In_Volume_Mute:
681 case AC97_CD_Volume_Mute:
682 case AC97_Video_Volume_Mute:
683 case AC97_Aux_Volume_Mute:
684 case AC97_Record_Gain_Mic_Mute:
685 case AC97_General_Purpose:
686 case AC97_3D_Control:
687 case AC97_Sigmatel_Analog:
688 case AC97_Sigmatel_Dac2Invert:
689 /* None of the features in these regs are emulated, so they are RO */
690 break;
691 default:
692 dolog ("U nam writew %#x <- %#x\n", addr, val);
693 mixer_store (s, index, val);
694 break;
695 }
696 }
697
698 static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
699 {
700 AC97LinkState *s = opaque;
701 dolog ("U nam writel %#x <- %#x\n", addr, val);
702 s->cas = 0;
703 }
704
705 /**
706 * Native audio bus master
707 * I/O Reads
708 */
709 static uint32_t nabm_readb (void *opaque, uint32_t addr)
710 {
711 AC97LinkState *s = opaque;
712 AC97BusMasterRegs *r = NULL;
713 uint32_t index = addr;
714 uint32_t val = ~0U;
715
716 switch (index) {
717 case CAS:
718 dolog ("CAS %d\n", s->cas);
719 val = s->cas;
720 s->cas = 1;
721 break;
722 case PI_CIV:
723 case PO_CIV:
724 case MC_CIV:
725 r = &s->bm_regs[GET_BM (index)];
726 val = r->civ;
727 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
728 break;
729 case PI_LVI:
730 case PO_LVI:
731 case MC_LVI:
732 r = &s->bm_regs[GET_BM (index)];
733 val = r->lvi;
734 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
735 break;
736 case PI_PIV:
737 case PO_PIV:
738 case MC_PIV:
739 r = &s->bm_regs[GET_BM (index)];
740 val = r->piv;
741 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
742 break;
743 case PI_CR:
744 case PO_CR:
745 case MC_CR:
746 r = &s->bm_regs[GET_BM (index)];
747 val = r->cr;
748 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
749 break;
750 case PI_SR:
751 case PO_SR:
752 case MC_SR:
753 r = &s->bm_regs[GET_BM (index)];
754 val = r->sr & 0xff;
755 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
756 break;
757 default:
758 dolog ("U nabm readb %#x -> %#x\n", addr, val);
759 break;
760 }
761 return val;
762 }
763
764 static uint32_t nabm_readw (void *opaque, uint32_t addr)
765 {
766 AC97LinkState *s = opaque;
767 AC97BusMasterRegs *r = NULL;
768 uint32_t index = addr;
769 uint32_t val = ~0U;
770
771 switch (index) {
772 case PI_SR:
773 case PO_SR:
774 case MC_SR:
775 r = &s->bm_regs[GET_BM (index)];
776 val = r->sr;
777 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
778 break;
779 case PI_PICB:
780 case PO_PICB:
781 case MC_PICB:
782 r = &s->bm_regs[GET_BM (index)];
783 val = r->picb;
784 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
785 break;
786 default:
787 dolog ("U nabm readw %#x -> %#x\n", addr, val);
788 break;
789 }
790 return val;
791 }
792
793 static uint32_t nabm_readl (void *opaque, uint32_t addr)
794 {
795 AC97LinkState *s = opaque;
796 AC97BusMasterRegs *r = NULL;
797 uint32_t index = addr;
798 uint32_t val = ~0U;
799
800 switch (index) {
801 case PI_BDBAR:
802 case PO_BDBAR:
803 case MC_BDBAR:
804 r = &s->bm_regs[GET_BM (index)];
805 val = r->bdbar;
806 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
807 break;
808 case PI_CIV:
809 case PO_CIV:
810 case MC_CIV:
811 r = &s->bm_regs[GET_BM (index)];
812 val = r->civ | (r->lvi << 8) | (r->sr << 16);
813 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
814 r->civ, r->lvi, r->sr);
815 break;
816 case PI_PICB:
817 case PO_PICB:
818 case MC_PICB:
819 r = &s->bm_regs[GET_BM (index)];
820 val = r->picb | (r->piv << 16) | (r->cr << 24);
821 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
822 val, r->picb, r->piv, r->cr);
823 break;
824 case GLOB_CNT:
825 val = s->glob_cnt;
826 dolog ("glob_cnt -> %#x\n", val);
827 break;
828 case GLOB_STA:
829 val = s->glob_sta | GS_S0CR;
830 dolog ("glob_sta -> %#x\n", val);
831 break;
832 default:
833 dolog ("U nabm readl %#x -> %#x\n", addr, val);
834 break;
835 }
836 return val;
837 }
838
839 /**
840 * Native audio bus master
841 * I/O Writes
842 */
843 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
844 {
845 AC97LinkState *s = opaque;
846 AC97BusMasterRegs *r = NULL;
847 uint32_t index = addr;
848 switch (index) {
849 case PI_LVI:
850 case PO_LVI:
851 case MC_LVI:
852 r = &s->bm_regs[GET_BM (index)];
853 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
854 r->sr &= ~(SR_DCH | SR_CELV);
855 r->civ = r->piv;
856 r->piv = (r->piv + 1) % 32;
857 fetch_bd (s, r);
858 }
859 r->lvi = val % 32;
860 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
861 break;
862 case PI_CR:
863 case PO_CR:
864 case MC_CR:
865 r = &s->bm_regs[GET_BM (index)];
866 if (val & CR_RR) {
867 reset_bm_regs (s, r);
868 }
869 else {
870 r->cr = val & CR_VALID_MASK;
871 if (!(r->cr & CR_RPBM)) {
872 voice_set_active (s, r - s->bm_regs, 0);
873 r->sr |= SR_DCH;
874 }
875 else {
876 r->civ = r->piv;
877 r->piv = (r->piv + 1) % 32;
878 fetch_bd (s, r);
879 r->sr &= ~SR_DCH;
880 voice_set_active (s, r - s->bm_regs, 1);
881 }
882 }
883 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
884 break;
885 case PI_SR:
886 case PO_SR:
887 case MC_SR:
888 r = &s->bm_regs[GET_BM (index)];
889 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
890 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
891 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
892 break;
893 default:
894 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
895 break;
896 }
897 }
898
899 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
900 {
901 AC97LinkState *s = opaque;
902 AC97BusMasterRegs *r = NULL;
903 uint32_t index = addr;
904 switch (index) {
905 case PI_SR:
906 case PO_SR:
907 case MC_SR:
908 r = &s->bm_regs[GET_BM (index)];
909 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
910 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
911 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
912 break;
913 default:
914 dolog ("U nabm writew %#x <- %#x\n", addr, val);
915 break;
916 }
917 }
918
919 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
920 {
921 AC97LinkState *s = opaque;
922 AC97BusMasterRegs *r = NULL;
923 uint32_t index = addr;
924 switch (index) {
925 case PI_BDBAR:
926 case PO_BDBAR:
927 case MC_BDBAR:
928 r = &s->bm_regs[GET_BM (index)];
929 r->bdbar = val & ~3;
930 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
931 GET_BM (index), val, r->bdbar);
932 break;
933 case GLOB_CNT:
934 if (val & GC_WR)
935 warm_reset (s);
936 if (val & GC_CR)
937 cold_reset (s);
938 if (!(val & (GC_WR | GC_CR)))
939 s->glob_cnt = val & GC_VALID_MASK;
940 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
941 break;
942 case GLOB_STA:
943 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
944 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
945 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
946 break;
947 default:
948 dolog ("U nabm writel %#x <- %#x\n", addr, val);
949 break;
950 }
951 }
952
953 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
954 int max, int *stop)
955 {
956 uint8_t tmpbuf[4096];
957 uint32_t addr = r->bd.addr;
958 uint32_t temp = r->picb << 1;
959 uint32_t written = 0;
960 int to_copy = 0;
961 temp = audio_MIN (temp, max);
962
963 if (!temp) {
964 *stop = 1;
965 return 0;
966 }
967
968 while (temp) {
969 int copied;
970 to_copy = audio_MIN (temp, sizeof (tmpbuf));
971 pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
972 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
973 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
974 max, to_copy, copied);
975 if (!copied) {
976 *stop = 1;
977 break;
978 }
979 temp -= copied;
980 addr += copied;
981 written += copied;
982 }
983
984 if (!temp) {
985 if (to_copy < 4) {
986 dolog ("whoops\n");
987 s->last_samp = 0;
988 }
989 else {
990 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
991 }
992 }
993
994 r->bd.addr = addr;
995 return written;
996 }
997
998 static void write_bup (AC97LinkState *s, int elapsed)
999 {
1000 dolog ("write_bup\n");
1001 if (!(s->bup_flag & BUP_SET)) {
1002 if (s->bup_flag & BUP_LAST) {
1003 int i;
1004 uint8_t *p = s->silence;
1005 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
1006 *(uint32_t *) p = s->last_samp;
1007 }
1008 }
1009 else {
1010 memset (s->silence, 0, sizeof (s->silence));
1011 }
1012 s->bup_flag |= BUP_SET;
1013 }
1014
1015 while (elapsed) {
1016 int temp = audio_MIN (elapsed, sizeof (s->silence));
1017 while (temp) {
1018 int copied = AUD_write (s->voice_po, s->silence, temp);
1019 if (!copied)
1020 return;
1021 temp -= copied;
1022 elapsed -= copied;
1023 }
1024 }
1025 }
1026
1027 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1028 int max, int *stop)
1029 {
1030 uint8_t tmpbuf[4096];
1031 uint32_t addr = r->bd.addr;
1032 uint32_t temp = r->picb << 1;
1033 uint32_t nread = 0;
1034 int to_copy = 0;
1035 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1036
1037 temp = audio_MIN (temp, max);
1038
1039 if (!temp) {
1040 *stop = 1;
1041 return 0;
1042 }
1043
1044 while (temp) {
1045 int acquired;
1046 to_copy = audio_MIN (temp, sizeof (tmpbuf));
1047 acquired = AUD_read (voice, tmpbuf, to_copy);
1048 if (!acquired) {
1049 *stop = 1;
1050 break;
1051 }
1052 pci_dma_write (&s->dev, addr, tmpbuf, acquired);
1053 temp -= acquired;
1054 addr += acquired;
1055 nread += acquired;
1056 }
1057
1058 r->bd.addr = addr;
1059 return nread;
1060 }
1061
1062 static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1063 {
1064 AC97BusMasterRegs *r = &s->bm_regs[index];
1065 int stop = 0;
1066
1067 if (s->invalid_freq[index]) {
1068 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1069 index, s->invalid_freq[index]);
1070 return;
1071 }
1072
1073 if (r->sr & SR_DCH) {
1074 if (r->cr & CR_RPBM) {
1075 switch (index) {
1076 case PO_INDEX:
1077 write_bup (s, elapsed);
1078 break;
1079 }
1080 }
1081 return;
1082 }
1083
1084 while ((elapsed >> 1) && !stop) {
1085 int temp;
1086
1087 if (!r->bd_valid) {
1088 dolog ("invalid bd\n");
1089 fetch_bd (s, r);
1090 }
1091
1092 if (!r->picb) {
1093 dolog ("fresh bd %d is empty %#x %#x\n",
1094 r->civ, r->bd.addr, r->bd.ctl_len);
1095 if (r->civ == r->lvi) {
1096 r->sr |= SR_DCH; /* CELV? */
1097 s->bup_flag = 0;
1098 break;
1099 }
1100 r->sr &= ~SR_CELV;
1101 r->civ = r->piv;
1102 r->piv = (r->piv + 1) % 32;
1103 fetch_bd (s, r);
1104 return;
1105 }
1106
1107 switch (index) {
1108 case PO_INDEX:
1109 temp = write_audio (s, r, elapsed, &stop);
1110 elapsed -= temp;
1111 r->picb -= (temp >> 1);
1112 break;
1113
1114 case PI_INDEX:
1115 case MC_INDEX:
1116 temp = read_audio (s, r, elapsed, &stop);
1117 elapsed -= temp;
1118 r->picb -= (temp >> 1);
1119 break;
1120 }
1121
1122 if (!r->picb) {
1123 uint32_t new_sr = r->sr & ~SR_CELV;
1124
1125 if (r->bd.ctl_len & BD_IOC) {
1126 new_sr |= SR_BCIS;
1127 }
1128
1129 if (r->civ == r->lvi) {
1130 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1131
1132 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1133 stop = 1;
1134 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1135 }
1136 else {
1137 r->civ = r->piv;
1138 r->piv = (r->piv + 1) % 32;
1139 fetch_bd (s, r);
1140 }
1141
1142 update_sr (s, r, new_sr);
1143 }
1144 }
1145 }
1146
1147 static void pi_callback (void *opaque, int avail)
1148 {
1149 transfer_audio (opaque, PI_INDEX, avail);
1150 }
1151
1152 static void mc_callback (void *opaque, int avail)
1153 {
1154 transfer_audio (opaque, MC_INDEX, avail);
1155 }
1156
1157 static void po_callback (void *opaque, int free)
1158 {
1159 transfer_audio (opaque, PO_INDEX, free);
1160 }
1161
1162 static const VMStateDescription vmstate_ac97_bm_regs = {
1163 .name = "ac97_bm_regs",
1164 .version_id = 1,
1165 .minimum_version_id = 1,
1166 .fields = (VMStateField[]) {
1167 VMSTATE_UINT32 (bdbar, AC97BusMasterRegs),
1168 VMSTATE_UINT8 (civ, AC97BusMasterRegs),
1169 VMSTATE_UINT8 (lvi, AC97BusMasterRegs),
1170 VMSTATE_UINT16 (sr, AC97BusMasterRegs),
1171 VMSTATE_UINT16 (picb, AC97BusMasterRegs),
1172 VMSTATE_UINT8 (piv, AC97BusMasterRegs),
1173 VMSTATE_UINT8 (cr, AC97BusMasterRegs),
1174 VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs),
1175 VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs),
1176 VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs),
1177 VMSTATE_END_OF_LIST ()
1178 }
1179 };
1180
1181 static int ac97_post_load (void *opaque, int version_id)
1182 {
1183 uint8_t active[LAST_INDEX];
1184 AC97LinkState *s = opaque;
1185
1186 record_select (s, mixer_load (s, AC97_Record_Select));
1187 set_volume (s, AC97_Master_Volume_Mute,
1188 mixer_load (s, AC97_Master_Volume_Mute));
1189 set_volume (s, AC97_PCM_Out_Volume_Mute,
1190 mixer_load (s, AC97_PCM_Out_Volume_Mute));
1191 set_volume (s, AC97_Record_Gain_Mute,
1192 mixer_load (s, AC97_Record_Gain_Mute));
1193
1194 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1195 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1196 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1197 reset_voices (s, active);
1198
1199 s->bup_flag = 0;
1200 s->last_samp = 0;
1201 return 0;
1202 }
1203
1204 static bool is_version_2 (void *opaque, int version_id)
1205 {
1206 return version_id == 2;
1207 }
1208
1209 static const VMStateDescription vmstate_ac97 = {
1210 .name = "ac97",
1211 .version_id = 3,
1212 .minimum_version_id = 2,
1213 .post_load = ac97_post_load,
1214 .fields = (VMStateField[]) {
1215 VMSTATE_PCI_DEVICE (dev, AC97LinkState),
1216 VMSTATE_UINT32 (glob_cnt, AC97LinkState),
1217 VMSTATE_UINT32 (glob_sta, AC97LinkState),
1218 VMSTATE_UINT32 (cas, AC97LinkState),
1219 VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1,
1220 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1221 VMSTATE_BUFFER (mixer_data, AC97LinkState),
1222 VMSTATE_UNUSED_TEST (is_version_2, 3),
1223 VMSTATE_END_OF_LIST ()
1224 }
1225 };
1226
1227 static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size)
1228 {
1229 if ((addr / size) > 256) {
1230 return -1;
1231 }
1232
1233 switch (size) {
1234 case 1:
1235 return nam_readb(opaque, addr);
1236 case 2:
1237 return nam_readw(opaque, addr);
1238 case 4:
1239 return nam_readl(opaque, addr);
1240 default:
1241 return -1;
1242 }
1243 }
1244
1245 static void nam_write(void *opaque, hwaddr addr, uint64_t val,
1246 unsigned size)
1247 {
1248 if ((addr / size) > 256) {
1249 return;
1250 }
1251
1252 switch (size) {
1253 case 1:
1254 nam_writeb(opaque, addr, val);
1255 break;
1256 case 2:
1257 nam_writew(opaque, addr, val);
1258 break;
1259 case 4:
1260 nam_writel(opaque, addr, val);
1261 break;
1262 }
1263 }
1264
1265 static const MemoryRegionOps ac97_io_nam_ops = {
1266 .read = nam_read,
1267 .write = nam_write,
1268 .impl = {
1269 .min_access_size = 1,
1270 .max_access_size = 4,
1271 },
1272 .endianness = DEVICE_LITTLE_ENDIAN,
1273 };
1274
1275 static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size)
1276 {
1277 if ((addr / size) > 64) {
1278 return -1;
1279 }
1280
1281 switch (size) {
1282 case 1:
1283 return nabm_readb(opaque, addr);
1284 case 2:
1285 return nabm_readw(opaque, addr);
1286 case 4:
1287 return nabm_readl(opaque, addr);
1288 default:
1289 return -1;
1290 }
1291 }
1292
1293 static void nabm_write(void *opaque, hwaddr addr, uint64_t val,
1294 unsigned size)
1295 {
1296 if ((addr / size) > 64) {
1297 return;
1298 }
1299
1300 switch (size) {
1301 case 1:
1302 nabm_writeb(opaque, addr, val);
1303 break;
1304 case 2:
1305 nabm_writew(opaque, addr, val);
1306 break;
1307 case 4:
1308 nabm_writel(opaque, addr, val);
1309 break;
1310 }
1311 }
1312
1313
1314 static const MemoryRegionOps ac97_io_nabm_ops = {
1315 .read = nabm_read,
1316 .write = nabm_write,
1317 .impl = {
1318 .min_access_size = 1,
1319 .max_access_size = 4,
1320 },
1321 .endianness = DEVICE_LITTLE_ENDIAN,
1322 };
1323
1324 static void ac97_on_reset (DeviceState *dev)
1325 {
1326 AC97LinkState *s = container_of(dev, AC97LinkState, dev.qdev);
1327
1328 reset_bm_regs (s, &s->bm_regs[0]);
1329 reset_bm_regs (s, &s->bm_regs[1]);
1330 reset_bm_regs (s, &s->bm_regs[2]);
1331
1332 /*
1333 * Reset the mixer too. The Windows XP driver seems to rely on
1334 * this. At least it wants to read the vendor id before it resets
1335 * the codec manually.
1336 */
1337 mixer_reset (s);
1338 }
1339
1340 static void ac97_realize(PCIDevice *dev, Error **errp)
1341 {
1342 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1343 uint8_t *c = s->dev.config;
1344
1345 /* TODO: no need to override */
1346 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1347 c[PCI_COMMAND + 1] = 0x00;
1348
1349 /* TODO: */
1350 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1351 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1352
1353 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1354
1355 /* TODO set when bar is registered. no need to override. */
1356 /* nabmar native audio mixer base address rw */
1357 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1358 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1359 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1360 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1361
1362 /* TODO set when bar is registered. no need to override. */
1363 /* nabmbar native audio bus mastering base address rw */
1364 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1365 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1366 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1367 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1368
1369 if (s->use_broken_id) {
1370 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86;
1371 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
1372 c[PCI_SUBSYSTEM_ID] = 0x00;
1373 c[PCI_SUBSYSTEM_ID + 1] = 0x00;
1374 }
1375
1376 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1377 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1378
1379 memory_region_init_io (&s->io_nam, OBJECT(s), &ac97_io_nam_ops, s,
1380 "ac97-nam", 1024);
1381 memory_region_init_io (&s->io_nabm, OBJECT(s), &ac97_io_nabm_ops, s,
1382 "ac97-nabm", 256);
1383 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1384 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1385 AUD_register_card ("ac97", &s->card);
1386 ac97_on_reset (&s->dev.qdev);
1387 }
1388
1389 static int ac97_init (PCIBus *bus)
1390 {
1391 pci_create_simple (bus, -1, "AC97");
1392 return 0;
1393 }
1394
1395 static Property ac97_properties[] = {
1396 DEFINE_PROP_UINT32 ("use_broken_id", AC97LinkState, use_broken_id, 0),
1397 DEFINE_PROP_END_OF_LIST (),
1398 };
1399
1400 static void ac97_class_init (ObjectClass *klass, void *data)
1401 {
1402 DeviceClass *dc = DEVICE_CLASS (klass);
1403 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
1404
1405 k->realize = ac97_realize;
1406 k->vendor_id = PCI_VENDOR_ID_INTEL;
1407 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
1408 k->revision = 0x01;
1409 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
1410 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1411 dc->desc = "Intel 82801AA AC97 Audio";
1412 dc->vmsd = &vmstate_ac97;
1413 dc->props = ac97_properties;
1414 dc->reset = ac97_on_reset;
1415 }
1416
1417 static const TypeInfo ac97_info = {
1418 .name = "AC97",
1419 .parent = TYPE_PCI_DEVICE,
1420 .instance_size = sizeof (AC97LinkState),
1421 .class_init = ac97_class_init,
1422 };
1423
1424 static void ac97_register_types (void)
1425 {
1426 type_register_static (&ac97_info);
1427 pci_register_soundhw("ac97", "Intel 82801AA AC97 Audio", ac97_init);
1428 }
1429
1430 type_init (ac97_register_types)
CRIS target port of Qemu