target-microblaze/cpu.h

   1 /*
   2  *  MicroBlaze virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_MICROBLAZE_H
  20 #define CPU_MICROBLAZE_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #define TARGET_LONG_BITS 32
  26
  27 #define CPUArchState struct CPUMBState
  28
  29 #include "exec/cpu-defs.h"
  30 #include "fpu/softfloat.h"
  31 struct CPUMBState;
  32 typedef struct CPUMBState CPUMBState;
  33 #if !defined(CONFIG_USER_ONLY)
  34 #include "mmu.h"
  35 #endif
  36
  37 #define ELF_MACHINE     EM_MICROBLAZE
  38
  39 #define EXCP_MMU        1
  40 #define EXCP_IRQ        2
  41 #define EXCP_BREAK      3
  42 #define EXCP_HW_BREAK   4
  43 #define EXCP_HW_EXCP    5
  44
  45 /* MicroBlaze-specific interrupt pending bits.  */
  46 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  47
  48 /* Meanings of the MBCPU object's two inbound GPIO lines */
  49 #define MB_CPU_IRQ 0
  50 #define MB_CPU_FIR 1
  51
  52 /* Register aliases. R0 - R15 */
  53 #define R_SP     1
  54 #define SR_PC    0
  55 #define SR_MSR   1
  56 #define SR_EAR   3
  57 #define SR_ESR   5
  58 #define SR_FSR   7
  59 #define SR_BTR   0xb
  60 #define SR_EDR   0xd
  61
  62 /* MSR flags.  */
  63 #define MSR_BE  (1<<0) /* 0x001 */
  64 #define MSR_IE  (1<<1) /* 0x002 */
  65 #define MSR_C   (1<<2) /* 0x004 */
  66 #define MSR_BIP (1<<3) /* 0x008 */
  67 #define MSR_FSL (1<<4) /* 0x010 */
  68 #define MSR_ICE (1<<5) /* 0x020 */
  69 #define MSR_DZ  (1<<6) /* 0x040 */
  70 #define MSR_DCE (1<<7) /* 0x080 */
  71 #define MSR_EE  (1<<8) /* 0x100 */
  72 #define MSR_EIP (1<<9) /* 0x200 */
  73 #define MSR_PVR (1<<10) /* 0x400 */
  74 #define MSR_CC  (1<<31)
  75
  76 /* Machine State Register (MSR) Fields */
  77 #define MSR_UM (1<<11) /* User Mode */
  78 #define MSR_UMS        (1<<12) /* User Mode Save */
  79 #define MSR_VM (1<<13) /* Virtual Mode */
  80 #define MSR_VMS        (1<<14) /* Virtual Mode Save */
  81
  82 #define MSR_KERNEL      MSR_EE|MSR_VM
  83 //#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
  84 #define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
  85 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
  86
  87 /* Exception State Register (ESR) Fields */
  88 #define          ESR_DIZ       (1<<11) /* Zone Protection */
  89 #define          ESR_S         (1<<10) /* Store instruction */
  90
  91 #define          ESR_ESS_FSL_OFFSET     5
  92
  93 #define          ESR_EC_FSL             0
  94 #define          ESR_EC_UNALIGNED_DATA  1
  95 #define          ESR_EC_ILLEGAL_OP      2
  96 #define          ESR_EC_INSN_BUS        3
  97 #define          ESR_EC_DATA_BUS        4
  98 #define          ESR_EC_DIVZERO         5
  99 #define          ESR_EC_FPU             6
 100 #define          ESR_EC_PRIVINSN        7
 101 #define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
 102 #define          ESR_EC_DATA_STORAGE    8
 103 #define          ESR_EC_INSN_STORAGE    9
 104 #define          ESR_EC_DATA_TLB        10
 105 #define          ESR_EC_INSN_TLB        11
 106 #define          ESR_EC_MASK            31
 107
 108 /* Floating Point Status Register (FSR) Bits */
 109 #define FSR_IO          (1<<4) /* Invalid operation */
 110 #define FSR_DZ          (1<<3) /* Divide-by-zero */
 111 #define FSR_OF          (1<<2) /* Overflow */
 112 #define FSR_UF          (1<<1) /* Underflow */
 113 #define FSR_DO          (1<<0) /* Denormalized operand error */
 114
 115 /* Version reg.  */
 116 /* Basic PVR mask */
 117 #define PVR0_PVR_FULL_MASK              0x80000000
 118 #define PVR0_USE_BARREL_MASK            0x40000000
 119 #define PVR0_USE_DIV_MASK               0x20000000
 120 #define PVR0_USE_HW_MUL_MASK            0x10000000
 121 #define PVR0_USE_FPU_MASK               0x08000000
 122 #define PVR0_USE_EXC_MASK               0x04000000
 123 #define PVR0_USE_ICACHE_MASK            0x02000000
 124 #define PVR0_USE_DCACHE_MASK            0x01000000
 125 #define PVR0_USE_MMU                    0x00800000      /* new */
 126 #define PVR0_USE_BTC                    0x00400000
 127 #define PVR0_ENDI                       0x00200000
 128 #define PVR0_FAULT                      0x00100000
 129 #define PVR0_VERSION_MASK               0x0000FF00
 130 #define PVR0_USER1_MASK                 0x000000FF
 131
 132 /* User 2 PVR mask */
 133 #define PVR1_USER2_MASK                 0xFFFFFFFF
 134
 135 /* Configuration PVR masks */
 136 #define PVR2_D_OPB_MASK                 0x80000000
 137 #define PVR2_D_LMB_MASK                 0x40000000
 138 #define PVR2_I_OPB_MASK                 0x20000000
 139 #define PVR2_I_LMB_MASK                 0x10000000
 140 #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 141 #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
 142 #define PVR2_D_PLB_MASK                 0x02000000      /* new */
 143 #define PVR2_I_PLB_MASK                 0x01000000      /* new */
 144 #define PVR2_INTERCONNECT               0x00800000      /* new */
 145 #define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
 146 #define PVR2_USE_FSL_EXC                0x00040000      /* new */
 147 #define PVR2_USE_MSR_INSTR              0x00020000
 148 #define PVR2_USE_PCMP_INSTR             0x00010000
 149 #define PVR2_AREA_OPTIMISED             0x00008000
 150 #define PVR2_USE_BARREL_MASK            0x00004000
 151 #define PVR2_USE_DIV_MASK               0x00002000
 152 #define PVR2_USE_HW_MUL_MASK            0x00001000
 153 #define PVR2_USE_FPU_MASK               0x00000800
 154 #define PVR2_USE_MUL64_MASK             0x00000400
 155 #define PVR2_USE_FPU2_MASK              0x00000200      /* new */
 156 #define PVR2_USE_IPLBEXC                0x00000100
 157 #define PVR2_USE_DPLBEXC                0x00000080
 158 #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
 159 #define PVR2_UNALIGNED_EXC_MASK         0x00000020
 160 #define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
 161 #define PVR2_IOPB_BUS_EXC_MASK          0x00000008
 162 #define PVR2_DOPB_BUS_EXC_MASK          0x00000004
 163 #define PVR2_DIV_ZERO_EXC_MASK          0x00000002
 164 #define PVR2_FPU_EXC_MASK               0x00000001
 165
 166 /* Debug and exception PVR masks */
 167 #define PVR3_DEBUG_ENABLED_MASK         0x80000000
 168 #define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
 169 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
 170 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
 171 #define PVR3_FSL_LINKS_MASK             0x00000380
 172
 173 /* ICache config PVR masks */
 174 #define PVR4_USE_ICACHE_MASK            0x80000000
 175 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
 176 #define PVR4_ICACHE_USE_FSL_MASK        0x02000000
 177 #define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
 178 #define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
 179 #define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
 180
 181 /* DCache config PVR masks */
 182 #define PVR5_USE_DCACHE_MASK            0x80000000
 183 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
 184 #define PVR5_DCACHE_USE_FSL_MASK        0x02000000
 185 #define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
 186 #define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
 187 #define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
 188 #define PVR5_DCACHE_WRITEBACK_MASK      0x00004000
 189
 190 /* ICache base address PVR mask */
 191 #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
 192
 193 /* ICache high address PVR mask */
 194 #define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 195
 196 /* DCache base address PVR mask */
 197 #define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 198
 199 /* DCache high address PVR mask */
 200 #define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 201
 202 /* Target family PVR mask */
 203 #define PVR10_TARGET_FAMILY_MASK        0xFF000000
 204
 205 /* MMU descrtiption */
 206 #define PVR11_USE_MMU                   0xC0000000
 207 #define PVR11_MMU_ITLB_SIZE             0x38000000
 208 #define PVR11_MMU_DTLB_SIZE             0x07000000
 209 #define PVR11_MMU_TLB_ACCESS            0x00C00000
 210 #define PVR11_MMU_ZONES                 0x003E0000
 211 /* MSR Reset value PVR mask */
 212 #define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 213
 214
 215
 216 /* CPU flags.  */
 217
 218 /* Condition codes.  */
 219 #define CC_GE  5
 220 #define CC_GT  4
 221 #define CC_LE  3
 222 #define CC_LT  2
 223 #define CC_NE  1
 224 #define CC_EQ  0
 225
 226 #define NB_MMU_MODES    3
 227
 228 #define STREAM_EXCEPTION (1 << 0)
 229 #define STREAM_ATOMIC    (1 << 1)
 230 #define STREAM_TEST      (1 << 2)
 231 #define STREAM_CONTROL   (1 << 3)
 232 #define STREAM_NONBLOCK  (1 << 4)
 233
 234 struct CPUMBState {
 235     uint32_t debug;
 236     uint32_t btaken;
 237     uint32_t btarget;
 238     uint32_t bimm;
 239
 240     uint32_t imm;
 241     uint32_t regs[33];
 242     uint32_t sregs[24];
 243     float_status fp_status;
 244     /* Stack protectors. Yes, it's a hw feature.  */
 245     uint32_t slr, shr;
 246
 247     /* lwx/swx reserved address */
 248 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
 249     uint32_t res_addr;
 250     uint32_t res_val;
 251
 252     /* Internal flags.  */
 253 #define IMM_FLAG        4
 254 #define MSR_EE_FLAG     (1 << 8)
 255 #define DRTI_FLAG       (1 << 16)
 256 #define DRTE_FLAG       (1 << 17)
 257 #define DRTB_FLAG       (1 << 18)
 258 #define D_FLAG          (1 << 19)  /* Bit in ESR.  */
 259 /* TB dependent CPUMBState.  */
 260 #define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
 261     uint32_t iflags;
 262
 263     struct {
 264         uint32_t regs[16];
 265     } pvr;
 266
 267 #if !defined(CONFIG_USER_ONLY)
 268     /* Unified MMU.  */
 269     struct microblaze_mmu mmu;
 270 #endif
 271
 272     CPU_COMMON
 273 };
 274
 275 #include "cpu-qom.h"
 276
 277 void mb_tcg_init(void);
 278 MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
 279 int cpu_mb_exec(CPUMBState *s);
 280 /* you can call this signal handler from your SIGBUS and SIGSEGV
 281    signal handlers to inform the virtual CPU of exceptions. non zero
 282    is returned if the signal was handled by the virtual CPU.  */
 283 int cpu_mb_signal_handler(int host_signum, void *pinfo,
 284                           void *puc);
 285
 286 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 287 #define TARGET_PAGE_BITS 12
 288 #define MMAP_SHIFT TARGET_PAGE_BITS
 289
 290 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 291 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 292
 293 #define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
 294
 295 #define cpu_exec cpu_mb_exec
 296 #define cpu_gen_code cpu_mb_gen_code
 297 #define cpu_signal_handler cpu_mb_signal_handler
 298
 299 /* MMU modes definitions */
 300 #define MMU_MODE0_SUFFIX _nommu
 301 #define MMU_MODE1_SUFFIX _kernel
 302 #define MMU_MODE2_SUFFIX _user
 303 #define MMU_NOMMU_IDX   0
 304 #define MMU_KERNEL_IDX  1
 305 #define MMU_USER_IDX    2
 306 /* See NB_MMU_MODES further up the file.  */
 307
 308 static inline int cpu_mmu_index (CPUMBState *env)
 309 {
 310         /* Are we in nommu mode?.  */
 311         if (!(env->sregs[SR_MSR] & MSR_VM))
 312             return MMU_NOMMU_IDX;
 313
 314         if (env->sregs[SR_MSR] & MSR_UM)
 315             return MMU_USER_IDX;
 316         return MMU_KERNEL_IDX;
 317 }
 318
 319 int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 320                             int mmu_idx);
 321
 322 #include "exec/cpu-all.h"
 323
 324 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
 325                                         target_ulong *cs_base, int *flags)
 326 {
 327     *pc = env->sregs[SR_PC];
 328     *cs_base = 0;
 329     *flags = (env->iflags & IFLAGS_TB_MASK) |
 330                  (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
 331 }
 332
 333 #if !defined(CONFIG_USER_ONLY)
 334 void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 335                               bool is_write, bool is_exec, int is_asi,
 336                               unsigned size);
 337 #endif
 338
 339 #include "exec/exec-all.h"
 340
 341 #endif