hw/arm_sysctl.c

   1 /*
   2  * Status and system control registers for ARM RealView/Versatile boards.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw.h"
  11 #include "qemu-timer.h"
  12 #include "sysbus.h"
  13 #include "primecell.h"
  14 #include "sysemu.h"
  15
  16 #define LOCK_VALUE 0xa05f
  17
  18 typedef struct {
  19     SysBusDevice busdev;
  20     qemu_irq pl110_mux_ctrl;
  21
  22     uint32_t sys_id;
  23     uint32_t leds;
  24     uint16_t lockval;
  25     uint32_t cfgdata1;
  26     uint32_t cfgdata2;
  27     uint32_t flags;
  28     uint32_t nvflags;
  29     uint32_t resetlevel;
  30     uint32_t proc_id;
  31     uint32_t sys_mci;
  32     uint32_t sys_cfgdata;
  33     uint32_t sys_cfgctrl;
  34     uint32_t sys_cfgstat;
  35     uint32_t sys_clcd;
  36 } arm_sysctl_state;
  37
  38 static const VMStateDescription vmstate_arm_sysctl = {
  39     .name = "realview_sysctl",
  40     .version_id = 3,
  41     .minimum_version_id = 1,
  42     .fields = (VMStateField[]) {
  43         VMSTATE_UINT32(leds, arm_sysctl_state),
  44         VMSTATE_UINT16(lockval, arm_sysctl_state),
  45         VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
  46         VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
  47         VMSTATE_UINT32(flags, arm_sysctl_state),
  48         VMSTATE_UINT32(nvflags, arm_sysctl_state),
  49         VMSTATE_UINT32(resetlevel, arm_sysctl_state),
  50         VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
  51         VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
  52         VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
  53         VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
  54         VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
  55         VMSTATE_END_OF_LIST()
  56     }
  57 };
  58
  59 /* The PB926 actually uses a different format for
  60  * its SYS_ID register. Fortunately the bits which are
  61  * board type on later boards are distinct.
  62  */
  63 #define BOARD_ID_PB926 0x100
  64 #define BOARD_ID_EB 0x140
  65 #define BOARD_ID_PBA8 0x178
  66 #define BOARD_ID_PBX 0x182
  67 #define BOARD_ID_VEXPRESS 0x190
  68
  69 static int board_id(arm_sysctl_state *s)
  70 {
  71     /* Extract the board ID field from the SYS_ID register value */
  72     return (s->sys_id >> 16) & 0xfff;
  73 }
  74
  75 static void arm_sysctl_reset(DeviceState *d)
  76 {
  77     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
  78
  79     s->leds = 0;
  80     s->lockval = 0;
  81     s->cfgdata1 = 0;
  82     s->cfgdata2 = 0;
  83     s->flags = 0;
  84     s->resetlevel = 0;
  85     if (board_id(s) == BOARD_ID_VEXPRESS) {
  86         /* On VExpress this register will RAZ/WI */
  87         s->sys_clcd = 0;
  88     } else {
  89         /* All others: CLCDID 0x1f, indicating VGA */
  90         s->sys_clcd = 0x1f00;
  91     }
  92 }
  93
  94 static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
  95 {
  96     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
  97
  98     switch (offset) {
  99     case 0x00: /* ID */
 100         return s->sys_id;
 101     case 0x04: /* SW */
 102         /* General purpose hardware switches.
 103            We don't have a useful way of exposing these to the user.  */
 104         return 0;
 105     case 0x08: /* LED */
 106         return s->leds;
 107     case 0x20: /* LOCK */
 108         return s->lockval;
 109     case 0x0c: /* OSC0 */
 110     case 0x10: /* OSC1 */
 111     case 0x14: /* OSC2 */
 112     case 0x18: /* OSC3 */
 113     case 0x1c: /* OSC4 */
 114     case 0x24: /* 100HZ */
 115         /* ??? Implement these.  */
 116         return 0;
 117     case 0x28: /* CFGDATA1 */
 118         return s->cfgdata1;
 119     case 0x2c: /* CFGDATA2 */
 120         return s->cfgdata2;
 121     case 0x30: /* FLAGS */
 122         return s->flags;
 123     case 0x38: /* NVFLAGS */
 124         return s->nvflags;
 125     case 0x40: /* RESETCTL */
 126         if (board_id(s) == BOARD_ID_VEXPRESS) {
 127             /* reserved: RAZ/WI */
 128             return 0;
 129         }
 130         return s->resetlevel;
 131     case 0x44: /* PCICTL */
 132         return 1;
 133     case 0x48: /* MCI */
 134         return s->sys_mci;
 135     case 0x4c: /* FLASH */
 136         return 0;
 137     case 0x50: /* CLCD */
 138         return s->sys_clcd;
 139     case 0x54: /* CLCDSER */
 140         return 0;
 141     case 0x58: /* BOOTCS */
 142         return 0;
 143     case 0x5c: /* 24MHz */
 144         return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
 145     case 0x60: /* MISC */
 146         return 0;
 147     case 0x84: /* PROCID0 */
 148         return s->proc_id;
 149     case 0x88: /* PROCID1 */
 150         return 0xff000000;
 151     case 0x64: /* DMAPSR0 */
 152     case 0x68: /* DMAPSR1 */
 153     case 0x6c: /* DMAPSR2 */
 154     case 0x70: /* IOSEL */
 155     case 0x74: /* PLDCTL */
 156     case 0x80: /* BUSID */
 157     case 0x8c: /* OSCRESET0 */
 158     case 0x90: /* OSCRESET1 */
 159     case 0x94: /* OSCRESET2 */
 160     case 0x98: /* OSCRESET3 */
 161     case 0x9c: /* OSCRESET4 */
 162     case 0xc0: /* SYS_TEST_OSC0 */
 163     case 0xc4: /* SYS_TEST_OSC1 */
 164     case 0xc8: /* SYS_TEST_OSC2 */
 165     case 0xcc: /* SYS_TEST_OSC3 */
 166     case 0xd0: /* SYS_TEST_OSC4 */
 167         return 0;
 168     case 0xa0: /* SYS_CFGDATA */
 169         if (board_id(s) != BOARD_ID_VEXPRESS) {
 170             goto bad_reg;
 171         }
 172         return s->sys_cfgdata;
 173     case 0xa4: /* SYS_CFGCTRL */
 174         if (board_id(s) != BOARD_ID_VEXPRESS) {
 175             goto bad_reg;
 176         }
 177         return s->sys_cfgctrl;
 178     case 0xa8: /* SYS_CFGSTAT */
 179         if (board_id(s) != BOARD_ID_VEXPRESS) {
 180             goto bad_reg;
 181         }
 182         return s->sys_cfgstat;
 183     default:
 184     bad_reg:
 185         printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
 186         return 0;
 187     }
 188 }
 189
 190 static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
 191                           uint32_t val)
 192 {
 193     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 194
 195     switch (offset) {
 196     case 0x08: /* LED */
 197         s->leds = val;
 198     case 0x0c: /* OSC0 */
 199     case 0x10: /* OSC1 */
 200     case 0x14: /* OSC2 */
 201     case 0x18: /* OSC3 */
 202     case 0x1c: /* OSC4 */
 203         /* ??? */
 204         break;
 205     case 0x20: /* LOCK */
 206         if (val == LOCK_VALUE)
 207             s->lockval = val;
 208         else
 209             s->lockval = val & 0x7fff;
 210         break;
 211     case 0x28: /* CFGDATA1 */
 212         /* ??? Need to implement this.  */
 213         s->cfgdata1 = val;
 214         break;
 215     case 0x2c: /* CFGDATA2 */
 216         /* ??? Need to implement this.  */
 217         s->cfgdata2 = val;
 218         break;
 219     case 0x30: /* FLAGSSET */
 220         s->flags |= val;
 221         break;
 222     case 0x34: /* FLAGSCLR */
 223         s->flags &= ~val;
 224         break;
 225     case 0x38: /* NVFLAGSSET */
 226         s->nvflags |= val;
 227         break;
 228     case 0x3c: /* NVFLAGSCLR */
 229         s->nvflags &= ~val;
 230         break;
 231     case 0x40: /* RESETCTL */
 232         if (board_id(s) == BOARD_ID_VEXPRESS) {
 233             /* reserved: RAZ/WI */
 234             break;
 235         }
 236         if (s->lockval == LOCK_VALUE) {
 237             s->resetlevel = val;
 238             if (val & 0x100)
 239                 qemu_system_reset_request ();
 240         }
 241         break;
 242     case 0x44: /* PCICTL */
 243         /* nothing to do.  */
 244         break;
 245     case 0x4c: /* FLASH */
 246         break;
 247     case 0x50: /* CLCD */
 248         switch (board_id(s)) {
 249         case BOARD_ID_PB926:
 250             /* On 926 bits 13:8 are R/O, bits 1:0 control
 251              * the mux that defines how to interpret the PL110
 252              * graphics format, and other bits are r/w but we
 253              * don't implement them to do anything.
 254              */
 255             s->sys_clcd &= 0x3f00;
 256             s->sys_clcd |= val & ~0x3f00;
 257             qemu_set_irq(s->pl110_mux_ctrl, val & 3);
 258             break;
 259         case BOARD_ID_EB:
 260             /* The EB is the same except that there is no mux since
 261              * the EB has a PL111.
 262              */
 263             s->sys_clcd &= 0x3f00;
 264             s->sys_clcd |= val & ~0x3f00;
 265             break;
 266         case BOARD_ID_PBA8:
 267         case BOARD_ID_PBX:
 268             /* On PBA8 and PBX bit 7 is r/w and all other bits
 269              * are either r/o or RAZ/WI.
 270              */
 271             s->sys_clcd &= (1 << 7);
 272             s->sys_clcd |= val & ~(1 << 7);
 273             break;
 274         case BOARD_ID_VEXPRESS:
 275         default:
 276             /* On VExpress this register is unimplemented and will RAZ/WI */
 277             break;
 278         }
 279     case 0x54: /* CLCDSER */
 280     case 0x64: /* DMAPSR0 */
 281     case 0x68: /* DMAPSR1 */
 282     case 0x6c: /* DMAPSR2 */
 283     case 0x70: /* IOSEL */
 284     case 0x74: /* PLDCTL */
 285     case 0x80: /* BUSID */
 286     case 0x84: /* PROCID0 */
 287     case 0x88: /* PROCID1 */
 288     case 0x8c: /* OSCRESET0 */
 289     case 0x90: /* OSCRESET1 */
 290     case 0x94: /* OSCRESET2 */
 291     case 0x98: /* OSCRESET3 */
 292     case 0x9c: /* OSCRESET4 */
 293         break;
 294     case 0xa0: /* SYS_CFGDATA */
 295         if (board_id(s) != BOARD_ID_VEXPRESS) {
 296             goto bad_reg;
 297         }
 298         s->sys_cfgdata = val;
 299         return;
 300     case 0xa4: /* SYS_CFGCTRL */
 301         if (board_id(s) != BOARD_ID_VEXPRESS) {
 302             goto bad_reg;
 303         }
 304         s->sys_cfgctrl = val & ~(3 << 18);
 305         s->sys_cfgstat = 1;            /* complete */
 306         switch (s->sys_cfgctrl) {
 307         case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
 308             qemu_system_shutdown_request();
 309             break;
 310         case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
 311             qemu_system_reset_request();
 312             break;
 313         default:
 314             s->sys_cfgstat |= 2;        /* error */
 315         }
 316         return;
 317     case 0xa8: /* SYS_CFGSTAT */
 318         if (board_id(s) != BOARD_ID_VEXPRESS) {
 319             goto bad_reg;
 320         }
 321         s->sys_cfgstat = val & 3;
 322         return;
 323     default:
 324     bad_reg:
 325         printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
 326         return;
 327     }
 328 }
 329
 330 static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
 331    arm_sysctl_read,
 332    arm_sysctl_read,
 333    arm_sysctl_read
 334 };
 335
 336 static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
 337    arm_sysctl_write,
 338    arm_sysctl_write,
 339    arm_sysctl_write
 340 };
 341
 342 static void arm_sysctl_gpio_set(void *opaque, int line, int level)
 343 {
 344     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 345     switch (line) {
 346     case ARM_SYSCTL_GPIO_MMC_WPROT:
 347     {
 348         /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
 349          * for all later boards it is bit 1.
 350          */
 351         int bit = 2;
 352         if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
 353             bit = 4;
 354         }
 355         s->sys_mci &= ~bit;
 356         if (level) {
 357             s->sys_mci |= bit;
 358         }
 359         break;
 360     }
 361     case ARM_SYSCTL_GPIO_MMC_CARDIN:
 362         s->sys_mci &= ~1;
 363         if (level) {
 364             s->sys_mci |= 1;
 365         }
 366         break;
 367     }
 368 }
 369
 370 static int arm_sysctl_init1(SysBusDevice *dev)
 371 {
 372     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
 373     int iomemtype;
 374
 375     iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
 376                                        arm_sysctl_writefn, s,
 377                                        DEVICE_NATIVE_ENDIAN);
 378     sysbus_init_mmio(dev, 0x1000, iomemtype);
 379     qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
 380     qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
 381     return 0;
 382 }
 383
 384 /* Legacy helper function.  */
 385 void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
 386 {
 387     DeviceState *dev;
 388
 389     dev = qdev_create(NULL, "realview_sysctl");
 390     qdev_prop_set_uint32(dev, "sys_id", sys_id);
 391     qdev_init_nofail(dev);
 392     qdev_prop_set_uint32(dev, "proc_id", proc_id);
 393     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
 394 }
 395
 396 static SysBusDeviceInfo arm_sysctl_info = {
 397     .init = arm_sysctl_init1,
 398     .qdev.name  = "realview_sysctl",
 399     .qdev.size  = sizeof(arm_sysctl_state),
 400     .qdev.vmsd = &vmstate_arm_sysctl,
 401     .qdev.reset = arm_sysctl_reset,
 402     .qdev.props = (Property[]) {
 403         DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 404         DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 405         DEFINE_PROP_END_OF_LIST(),
 406     }
 407 };
 408
 409 static void arm_sysctl_register_devices(void)
 410 {
 411     sysbus_register_withprop(&arm_sysctl_info);
 412 }
 413
 414 device_init(arm_sysctl_register_devices)