target-ppc/mem_helper.c

   1 /*
   2  *  PowerPC memory access emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/exec-all.h"
  22 #include "qemu/host-utils.h"
  23 #include "exec/helper-proto.h"
  24
  25 #include "helper_regs.h"
  26 #include "exec/exec-all.h"
  27 #include "exec/cpu_ldst.h"
  28
  29 //#define DEBUG_OP
  30
  31 static inline bool needs_byteswap(const CPUPPCState *env)
  32 {
  33 #if defined(TARGET_WORDS_BIGENDIAN)
  34   return msr_le;
  35 #else
  36   return !msr_le;
  37 #endif
  38 }
  39
  40 /*****************************************************************************/
  41 /* Memory load and stores */
  42
  43 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
  44                                     target_long arg)
  45 {
  46 #if defined(TARGET_PPC64)
  47     if (!msr_is_64bit(env, env->msr)) {
  48         return (uint32_t)(addr + arg);
  49     } else
  50 #endif
  51     {
  52         return addr + arg;
  53     }
  54 }
  55
  56 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  57 {
  58     for (; reg < 32; reg++) {
  59         if (needs_byteswap(env)) {
  60             env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
  61         } else {
  62             env->gpr[reg] = cpu_ldl_data(env, addr);
  63         }
  64         addr = addr_add(env, addr, 4);
  65     }
  66 }
  67
  68 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  69 {
  70     for (; reg < 32; reg++) {
  71         if (needs_byteswap(env)) {
  72             cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
  73         } else {
  74             cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
  75         }
  76         addr = addr_add(env, addr, 4);
  77     }
  78 }
  79
  80 void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
  81 {
  82     int sh;
  83
  84     for (; nb > 3; nb -= 4) {
  85         env->gpr[reg] = cpu_ldl_data(env, addr);
  86         reg = (reg + 1) % 32;
  87         addr = addr_add(env, addr, 4);
  88     }
  89     if (unlikely(nb > 0)) {
  90         env->gpr[reg] = 0;
  91         for (sh = 24; nb > 0; nb--, sh -= 8) {
  92             env->gpr[reg] |= cpu_ldub_data(env, addr) << sh;
  93             addr = addr_add(env, addr, 1);
  94         }
  95     }
  96 }
  97 /* PPC32 specification says we must generate an exception if
  98  * rA is in the range of registers to be loaded.
  99  * In an other hand, IBM says this is valid, but rA won't be loaded.
 100  * For now, I'll follow the spec...
 101  */
 102 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 103                  uint32_t ra, uint32_t rb)
 104 {
 105     if (likely(xer_bc != 0)) {
 106         int num_used_regs = (xer_bc + 3) / 4;
 107         if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
 108                      lsw_reg_in_range(reg, num_used_regs, rb))) {
 109             env->nip += 4;     /* Compensate the "nip - 4" from gen_lswx() */
 110             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 111                                        POWERPC_EXCP_INVAL |
 112                                        POWERPC_EXCP_INVAL_LSWX);
 113         } else {
 114             helper_lsw(env, addr, xer_bc, reg);
 115         }
 116     }
 117 }
 118
 119 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
 120                  uint32_t reg)
 121 {
 122     int sh;
 123
 124     for (; nb > 3; nb -= 4) {
 125         cpu_stl_data(env, addr, env->gpr[reg]);
 126         reg = (reg + 1) % 32;
 127         addr = addr_add(env, addr, 4);
 128     }
 129     if (unlikely(nb > 0)) {
 130         for (sh = 24; nb > 0; nb--, sh -= 8) {
 131             cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF);
 132             addr = addr_add(env, addr, 1);
 133         }
 134     }
 135 }
 136
 137 static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
 138 {
 139     int i;
 140
 141     addr &= ~(dcache_line_size - 1);
 142     for (i = 0; i < dcache_line_size; i += 4) {
 143         cpu_stl_data(env, addr + i, 0);
 144     }
 145     if (env->reserve_addr == addr) {
 146         env->reserve_addr = (target_ulong)-1ULL;
 147     }
 148 }
 149
 150 void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
 151 {
 152     int dcbz_size = env->dcache_line_size;
 153
 154 #if defined(TARGET_PPC64)
 155     if (!is_dcbzl &&
 156         (env->excp_model == POWERPC_EXCP_970) &&
 157         ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
 158         dcbz_size = 32;
 159     }
 160 #endif
 161
 162     /* XXX add e500mc support */
 163
 164     do_dcbz(env, addr, dcbz_size);
 165 }
 166
 167 void helper_icbi(CPUPPCState *env, target_ulong addr)
 168 {
 169     addr &= ~(env->dcache_line_size - 1);
 170     /* Invalidate one cache line :
 171      * PowerPC specification says this is to be treated like a load
 172      * (not a fetch) by the MMU. To be sure it will be so,
 173      * do the load "by hand".
 174      */
 175     cpu_ldl_data(env, addr);
 176 }
 177
 178 /* XXX: to be tested */
 179 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 180                           uint32_t ra, uint32_t rb)
 181 {
 182     int i, c, d;
 183
 184     d = 24;
 185     for (i = 0; i < xer_bc; i++) {
 186         c = cpu_ldub_data(env, addr);
 187         addr = addr_add(env, addr, 1);
 188         /* ra (if not 0) and rb are never modified */
 189         if (likely(reg != rb && (ra == 0 || reg != ra))) {
 190             env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
 191         }
 192         if (unlikely(c == xer_cmp)) {
 193             break;
 194         }
 195         if (likely(d != 0)) {
 196             d -= 8;
 197         } else {
 198             d = 24;
 199             reg++;
 200             reg = reg & 0x1F;
 201         }
 202     }
 203     return i;
 204 }
 205
 206 /*****************************************************************************/
 207 /* Altivec extension helpers */
 208 #if defined(HOST_WORDS_BIGENDIAN)
 209 #define HI_IDX 0
 210 #define LO_IDX 1
 211 #else
 212 #define HI_IDX 1
 213 #define LO_IDX 0
 214 #endif
 215
 216 /* We use msr_le to determine index ordering in a vector.  However,
 217    byteswapping is not simply controlled by msr_le.  We also need to take
 218    into account endianness of the target.  This is done for the little-endian
 219    PPC64 user-mode target. */
 220
 221 #define LVE(name, access, swap, element)                        \
 222     void helper_##name(CPUPPCState *env, ppc_avr_t *r,          \
 223                        target_ulong addr)                       \
 224     {                                                           \
 225         size_t n_elems = ARRAY_SIZE(r->element);                \
 226         int adjust = HI_IDX*(n_elems - 1);                      \
 227         int sh = sizeof(r->element[0]) >> 1;                    \
 228         int index = (addr & 0xf) >> sh;                         \
 229         if (msr_le) {                                           \
 230             index = n_elems - index - 1;                        \
 231         }                                                       \
 232                                                                 \
 233         if (needs_byteswap(env)) {                              \
 234             r->element[LO_IDX ? index : (adjust - index)] =     \
 235                 swap(access(env, addr));                        \
 236         } else {                                                \
 237             r->element[LO_IDX ? index : (adjust - index)] =     \
 238                 access(env, addr);                              \
 239         }                                                       \
 240     }
 241 #define I(x) (x)
 242 LVE(lvebx, cpu_ldub_data, I, u8)
 243 LVE(lvehx, cpu_lduw_data, bswap16, u16)
 244 LVE(lvewx, cpu_ldl_data, bswap32, u32)
 245 #undef I
 246 #undef LVE
 247
 248 #define STVE(name, access, swap, element)                               \
 249     void helper_##name(CPUPPCState *env, ppc_avr_t *r,                  \
 250                        target_ulong addr)                               \
 251     {                                                                   \
 252         size_t n_elems = ARRAY_SIZE(r->element);                        \
 253         int adjust = HI_IDX * (n_elems - 1);                            \
 254         int sh = sizeof(r->element[0]) >> 1;                            \
 255         int index = (addr & 0xf) >> sh;                                 \
 256         if (msr_le) {                                                   \
 257             index = n_elems - index - 1;                                \
 258         }                                                               \
 259                                                                         \
 260         if (needs_byteswap(env)) {                                      \
 261             access(env, addr, swap(r->element[LO_IDX ? index :          \
 262                                               (adjust - index)]));      \
 263         } else {                                                        \
 264             access(env, addr, r->element[LO_IDX ? index :               \
 265                                          (adjust - index)]);            \
 266         }                                                               \
 267     }
 268 #define I(x) (x)
 269 STVE(stvebx, cpu_stb_data, I, u8)
 270 STVE(stvehx, cpu_stw_data, bswap16, u16)
 271 STVE(stvewx, cpu_stl_data, bswap32, u32)
 272 #undef I
 273 #undef LVE
 274
 275 #undef HI_IDX
 276 #undef LO_IDX
 277
 278 void helper_tbegin(CPUPPCState *env)
 279 {
 280     /* As a degenerate implementation, always fail tbegin.  The reason
 281      * given is "Nesting overflow".  The "persistent" bit is set,
 282      * providing a hint to the error handler to not retry.  The TFIAR
 283      * captures the address of the failure, which is this tbegin
 284      * instruction.  Instruction execution will continue with the
 285      * next instruction in memory, which is precisely what we want.
 286      */
 287
 288     env->spr[SPR_TEXASR] =
 289         (1ULL << TEXASR_FAILURE_PERSISTENT) |
 290         (1ULL << TEXASR_NESTING_OVERFLOW) |
 291         (msr_hv << TEXASR_PRIVILEGE_HV) |
 292         (msr_pr << TEXASR_PRIVILEGE_PR) |
 293         (1ULL << TEXASR_FAILURE_SUMMARY) |
 294         (1ULL << TEXASR_TFIAR_EXACT);
 295     env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
 296     env->spr[SPR_TFHAR] = env->nip + 4;
 297     env->crf[0] = 0xB; /* 0b1010 = transaction failure */
 298 }