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microblaze: avoid "naked" qemu_log
[qemu/cris-port.git] / target-i386 / kvm.c
blob7b01328ffec62c68c46236a11abf6af6eee4e3b5
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm_int.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38
39 #include "exec/ioport.h"
40 #include "standard-headers/asm-x86/hyperv.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci/msi.h"
43 #include "migration/migration.h"
44 #include "exec/memattrs.h"
45
46 //#define DEBUG_KVM
47
48 #ifdef DEBUG_KVM
49 #define DPRINTF(fmt, ...) \
50 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
51 #else
52 #define DPRINTF(fmt, ...) \
53 do { } while (0)
54 #endif
55
56 #define MSR_KVM_WALL_CLOCK 0x11
57 #define MSR_KVM_SYSTEM_TIME 0x12
58
59 #ifndef BUS_MCEERR_AR
60 #define BUS_MCEERR_AR 4
61 #endif
62 #ifndef BUS_MCEERR_AO
63 #define BUS_MCEERR_AO 5
64 #endif
65
66 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71 };
72
73 static bool has_msr_star;
74 static bool has_msr_hsave_pa;
75 static bool has_msr_tsc_aux;
76 static bool has_msr_tsc_adjust;
77 static bool has_msr_tsc_deadline;
78 static bool has_msr_feature_control;
79 static bool has_msr_async_pf_en;
80 static bool has_msr_pv_eoi_en;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static bool has_msr_kvm_steal_time;
85 static int lm_capable_kernel;
86 static bool has_msr_hv_hypercall;
87 static bool has_msr_hv_vapic;
88 static bool has_msr_hv_tsc;
89 static bool has_msr_hv_crash;
90 static bool has_msr_hv_reset;
91 static bool has_msr_hv_vpindex;
92 static bool has_msr_hv_runtime;
93 static bool has_msr_hv_synic;
94 static bool has_msr_hv_stimer;
95 static bool has_msr_mtrr;
96 static bool has_msr_xss;
97
98 static bool has_msr_architectural_pmu;
99 static uint32_t num_architectural_pmu_counters;
100
101 static int has_xsave;
102 static int has_xcrs;
103 static int has_pit_state2;
104
105 int kvm_has_pit_state2(void)
106 {
107 return has_pit_state2;
108 }
109
110 bool kvm_has_smm(void)
111 {
112 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
113 }
114
115 bool kvm_allows_irq0_override(void)
116 {
117 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
118 }
119
120 static int kvm_get_tsc(CPUState *cs)
121 {
122 X86CPU *cpu = X86_CPU(cs);
123 CPUX86State *env = &cpu->env;
124 struct {
125 struct kvm_msrs info;
126 struct kvm_msr_entry entries[1];
127 } msr_data;
128 int ret;
129
130 if (env->tsc_valid) {
131 return 0;
132 }
133
134 msr_data.info.nmsrs = 1;
135 msr_data.entries[0].index = MSR_IA32_TSC;
136 env->tsc_valid = !runstate_is_running();
137
138 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
139 if (ret < 0) {
140 return ret;
141 }
142
143 env->tsc = msr_data.entries[0].data;
144 return 0;
145 }
146
147 static inline void do_kvm_synchronize_tsc(void *arg)
148 {
149 CPUState *cpu = arg;
150
151 kvm_get_tsc(cpu);
152 }
153
154 void kvm_synchronize_all_tsc(void)
155 {
156 CPUState *cpu;
157
158 if (kvm_enabled()) {
159 CPU_FOREACH(cpu) {
160 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
161 }
162 }
163 }
164
165 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
166 {
167 struct kvm_cpuid2 *cpuid;
168 int r, size;
169
170 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
171 cpuid = g_malloc0(size);
172 cpuid->nent = max;
173 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
174 if (r == 0 && cpuid->nent >= max) {
175 r = -E2BIG;
176 }
177 if (r < 0) {
178 if (r == -E2BIG) {
179 g_free(cpuid);
180 return NULL;
181 } else {
182 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
183 strerror(-r));
184 exit(1);
185 }
186 }
187 return cpuid;
188 }
189
190 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
191 * for all entries.
192 */
193 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
194 {
195 struct kvm_cpuid2 *cpuid;
196 int max = 1;
197 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
198 max *= 2;
199 }
200 return cpuid;
201 }
202
203 static const struct kvm_para_features {
204 int cap;
205 int feature;
206 } para_features[] = {
207 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
208 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
209 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
210 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
211 };
212
213 static int get_para_features(KVMState *s)
214 {
215 int i, features = 0;
216
217 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
218 if (kvm_check_extension(s, para_features[i].cap)) {
219 features |= (1 << para_features[i].feature);
220 }
221 }
222
223 return features;
224 }
225
226
227 /* Returns the value for a specific register on the cpuid entry
228 */
229 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
230 {
231 uint32_t ret = 0;
232 switch (reg) {
233 case R_EAX:
234 ret = entry->eax;
235 break;
236 case R_EBX:
237 ret = entry->ebx;
238 break;
239 case R_ECX:
240 ret = entry->ecx;
241 break;
242 case R_EDX:
243 ret = entry->edx;
244 break;
245 }
246 return ret;
247 }
248
249 /* Find matching entry for function/index on kvm_cpuid2 struct
250 */
251 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
252 uint32_t function,
253 uint32_t index)
254 {
255 int i;
256 for (i = 0; i < cpuid->nent; ++i) {
257 if (cpuid->entries[i].function == function &&
258 cpuid->entries[i].index == index) {
259 return &cpuid->entries[i];
260 }
261 }
262 /* not found: */
263 return NULL;
264 }
265
266 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
267 uint32_t index, int reg)
268 {
269 struct kvm_cpuid2 *cpuid;
270 uint32_t ret = 0;
271 uint32_t cpuid_1_edx;
272 bool found = false;
273
274 cpuid = get_supported_cpuid(s);
275
276 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
277 if (entry) {
278 found = true;
279 ret = cpuid_entry_get_reg(entry, reg);
280 }
281
282 /* Fixups for the data returned by KVM, below */
283
284 if (function == 1 && reg == R_EDX) {
285 /* KVM before 2.6.30 misreports the following features */
286 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
287 } else if (function == 1 && reg == R_ECX) {
288 /* We can set the hypervisor flag, even if KVM does not return it on
289 * GET_SUPPORTED_CPUID
290 */
291 ret |= CPUID_EXT_HYPERVISOR;
292 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
293 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
294 * and the irqchip is in the kernel.
295 */
296 if (kvm_irqchip_in_kernel() &&
297 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
298 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
299 }
300
301 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
302 * without the in-kernel irqchip
303 */
304 if (!kvm_irqchip_in_kernel()) {
305 ret &= ~CPUID_EXT_X2APIC;
306 }
307 } else if (function == 6 && reg == R_EAX) {
308 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
309 } else if (function == 0x80000001 && reg == R_EDX) {
310 /* On Intel, kvm returns cpuid according to the Intel spec,
311 * so add missing bits according to the AMD spec:
312 */
313 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
314 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
315 }
316
317 g_free(cpuid);
318
319 /* fallback for older kernels */
320 if ((function == KVM_CPUID_FEATURES) && !found) {
321 ret = get_para_features(s);
322 }
323
324 return ret;
325 }
326
327 typedef struct HWPoisonPage {
328 ram_addr_t ram_addr;
329 QLIST_ENTRY(HWPoisonPage) list;
330 } HWPoisonPage;
331
332 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
333 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
334
335 static void kvm_unpoison_all(void *param)
336 {
337 HWPoisonPage *page, *next_page;
338
339 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
340 QLIST_REMOVE(page, list);
341 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
342 g_free(page);
343 }
344 }
345
346 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
347 {
348 HWPoisonPage *page;
349
350 QLIST_FOREACH(page, &hwpoison_page_list, list) {
351 if (page->ram_addr == ram_addr) {
352 return;
353 }
354 }
355 page = g_new(HWPoisonPage, 1);
356 page->ram_addr = ram_addr;
357 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
358 }
359
360 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
361 int *max_banks)
362 {
363 int r;
364
365 r = kvm_check_extension(s, KVM_CAP_MCE);
366 if (r > 0) {
367 *max_banks = r;
368 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
369 }
370 return -ENOSYS;
371 }
372
373 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
374 {
375 CPUX86State *env = &cpu->env;
376 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
377 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
378 uint64_t mcg_status = MCG_STATUS_MCIP;
379
380 if (code == BUS_MCEERR_AR) {
381 status |= MCI_STATUS_AR | 0x134;
382 mcg_status |= MCG_STATUS_EIPV;
383 } else {
384 status |= 0xc0;
385 mcg_status |= MCG_STATUS_RIPV;
386 }
387 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
388 (MCM_ADDR_PHYS << 6) | 0xc,
389 cpu_x86_support_mca_broadcast(env) ?
390 MCE_INJECT_BROADCAST : 0);
391 }
392
393 static void hardware_memory_error(void)
394 {
395 fprintf(stderr, "Hardware memory error!\n");
396 exit(1);
397 }
398
399 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
400 {
401 X86CPU *cpu = X86_CPU(c);
402 CPUX86State *env = &cpu->env;
403 ram_addr_t ram_addr;
404 hwaddr paddr;
405
406 if ((env->mcg_cap & MCG_SER_P) && addr
407 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
408 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
409 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
410 fprintf(stderr, "Hardware memory error for memory used by "
411 "QEMU itself instead of guest system!\n");
412 /* Hope we are lucky for AO MCE */
413 if (code == BUS_MCEERR_AO) {
414 return 0;
415 } else {
416 hardware_memory_error();
417 }
418 }
419 kvm_hwpoison_page_add(ram_addr);
420 kvm_mce_inject(cpu, paddr, code);
421 } else {
422 if (code == BUS_MCEERR_AO) {
423 return 0;
424 } else if (code == BUS_MCEERR_AR) {
425 hardware_memory_error();
426 } else {
427 return 1;
428 }
429 }
430 return 0;
431 }
432
433 int kvm_arch_on_sigbus(int code, void *addr)
434 {
435 X86CPU *cpu = X86_CPU(first_cpu);
436
437 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
438 ram_addr_t ram_addr;
439 hwaddr paddr;
440
441 /* Hope we are lucky for AO MCE */
442 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
443 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
444 addr, &paddr)) {
445 fprintf(stderr, "Hardware memory error for memory used by "
446 "QEMU itself instead of guest system!: %p\n", addr);
447 return 0;
448 }
449 kvm_hwpoison_page_add(ram_addr);
450 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
451 } else {
452 if (code == BUS_MCEERR_AO) {
453 return 0;
454 } else if (code == BUS_MCEERR_AR) {
455 hardware_memory_error();
456 } else {
457 return 1;
458 }
459 }
460 return 0;
461 }
462
463 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
464 {
465 CPUX86State *env = &cpu->env;
466
467 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
468 unsigned int bank, bank_num = env->mcg_cap & 0xff;
469 struct kvm_x86_mce mce;
470
471 env->exception_injected = -1;
472
473 /*
474 * There must be at least one bank in use if an MCE is pending.
475 * Find it and use its values for the event injection.
476 */
477 for (bank = 0; bank < bank_num; bank++) {
478 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
479 break;
480 }
481 }
482 assert(bank < bank_num);
483
484 mce.bank = bank;
485 mce.status = env->mce_banks[bank * 4 + 1];
486 mce.mcg_status = env->mcg_status;
487 mce.addr = env->mce_banks[bank * 4 + 2];
488 mce.misc = env->mce_banks[bank * 4 + 3];
489
490 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
491 }
492 return 0;
493 }
494
495 static void cpu_update_state(void *opaque, int running, RunState state)
496 {
497 CPUX86State *env = opaque;
498
499 if (running) {
500 env->tsc_valid = false;
501 }
502 }
503
504 unsigned long kvm_arch_vcpu_id(CPUState *cs)
505 {
506 X86CPU *cpu = X86_CPU(cs);
507 return cpu->apic_id;
508 }
509
510 #ifndef KVM_CPUID_SIGNATURE_NEXT
511 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
512 #endif
513
514 static bool hyperv_hypercall_available(X86CPU *cpu)
515 {
516 return cpu->hyperv_vapic ||
517 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
518 }
519
520 static bool hyperv_enabled(X86CPU *cpu)
521 {
522 CPUState *cs = CPU(cpu);
523 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
524 (hyperv_hypercall_available(cpu) ||
525 cpu->hyperv_time ||
526 cpu->hyperv_relaxed_timing ||
527 cpu->hyperv_crash ||
528 cpu->hyperv_reset ||
529 cpu->hyperv_vpindex ||
530 cpu->hyperv_runtime ||
531 cpu->hyperv_synic ||
532 cpu->hyperv_stimer);
533 }
534
535 static Error *invtsc_mig_blocker;
536
537 #define KVM_MAX_CPUID_ENTRIES 100
538
539 int kvm_arch_init_vcpu(CPUState *cs)
540 {
541 struct {
542 struct kvm_cpuid2 cpuid;
543 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
544 } QEMU_PACKED cpuid_data;
545 X86CPU *cpu = X86_CPU(cs);
546 CPUX86State *env = &cpu->env;
547 uint32_t limit, i, j, cpuid_i;
548 uint32_t unused;
549 struct kvm_cpuid_entry2 *c;
550 uint32_t signature[3];
551 int kvm_base = KVM_CPUID_SIGNATURE;
552 int r;
553
554 memset(&cpuid_data, 0, sizeof(cpuid_data));
555
556 cpuid_i = 0;
557
558 /* Paravirtualization CPUIDs */
559 if (hyperv_enabled(cpu)) {
560 c = &cpuid_data.entries[cpuid_i++];
561 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
562 if (!cpu->hyperv_vendor_id) {
563 memcpy(signature, "Microsoft Hv", 12);
564 } else {
565 size_t len = strlen(cpu->hyperv_vendor_id);
566
567 if (len > 12) {
568 error_report("hv-vendor-id truncated to 12 characters");
569 len = 12;
570 }
571 memset(signature, 0, 12);
572 memcpy(signature, cpu->hyperv_vendor_id, len);
573 }
574 c->eax = HYPERV_CPUID_MIN;
575 c->ebx = signature[0];
576 c->ecx = signature[1];
577 c->edx = signature[2];
578
579 c = &cpuid_data.entries[cpuid_i++];
580 c->function = HYPERV_CPUID_INTERFACE;
581 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
582 c->eax = signature[0];
583 c->ebx = 0;
584 c->ecx = 0;
585 c->edx = 0;
586
587 c = &cpuid_data.entries[cpuid_i++];
588 c->function = HYPERV_CPUID_VERSION;
589 c->eax = 0x00001bbc;
590 c->ebx = 0x00060001;
591
592 c = &cpuid_data.entries[cpuid_i++];
593 c->function = HYPERV_CPUID_FEATURES;
594 if (cpu->hyperv_relaxed_timing) {
595 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
596 }
597 if (cpu->hyperv_vapic) {
598 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
599 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
600 has_msr_hv_vapic = true;
601 }
602 if (cpu->hyperv_time &&
603 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
604 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
605 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
606 c->eax |= 0x200;
607 has_msr_hv_tsc = true;
608 }
609 if (cpu->hyperv_crash && has_msr_hv_crash) {
610 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
611 }
612 if (cpu->hyperv_reset && has_msr_hv_reset) {
613 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
614 }
615 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
616 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
617 }
618 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
619 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
620 }
621 if (cpu->hyperv_synic) {
622 int sint;
623
624 if (!has_msr_hv_synic ||
625 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
626 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
627 return -ENOSYS;
628 }
629
630 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
631 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
632 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
633 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
634 }
635 }
636 if (cpu->hyperv_stimer) {
637 if (!has_msr_hv_stimer) {
638 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
639 return -ENOSYS;
640 }
641 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
642 }
643 c = &cpuid_data.entries[cpuid_i++];
644 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
645 if (cpu->hyperv_relaxed_timing) {
646 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
647 }
648 if (has_msr_hv_vapic) {
649 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
650 }
651 c->ebx = cpu->hyperv_spinlock_attempts;
652
653 c = &cpuid_data.entries[cpuid_i++];
654 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
655 c->eax = 0x40;
656 c->ebx = 0x40;
657
658 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
659 has_msr_hv_hypercall = true;
660 }
661
662 if (cpu->expose_kvm) {
663 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
664 c = &cpuid_data.entries[cpuid_i++];
665 c->function = KVM_CPUID_SIGNATURE | kvm_base;
666 c->eax = KVM_CPUID_FEATURES | kvm_base;
667 c->ebx = signature[0];
668 c->ecx = signature[1];
669 c->edx = signature[2];
670
671 c = &cpuid_data.entries[cpuid_i++];
672 c->function = KVM_CPUID_FEATURES | kvm_base;
673 c->eax = env->features[FEAT_KVM];
674
675 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
676
677 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
678
679 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
680 }
681
682 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
683
684 for (i = 0; i <= limit; i++) {
685 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
686 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
687 abort();
688 }
689 c = &cpuid_data.entries[cpuid_i++];
690
691 switch (i) {
692 case 2: {
693 /* Keep reading function 2 till all the input is received */
694 int times;
695
696 c->function = i;
697 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
698 KVM_CPUID_FLAG_STATE_READ_NEXT;
699 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
700 times = c->eax & 0xff;
701
702 for (j = 1; j < times; ++j) {
703 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
704 fprintf(stderr, "cpuid_data is full, no space for "
705 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
706 abort();
707 }
708 c = &cpuid_data.entries[cpuid_i++];
709 c->function = i;
710 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
711 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
712 }
713 break;
714 }
715 case 4:
716 case 0xb:
717 case 0xd:
718 for (j = 0; ; j++) {
719 if (i == 0xd && j == 64) {
720 break;
721 }
722 c->function = i;
723 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
724 c->index = j;
725 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
726
727 if (i == 4 && c->eax == 0) {
728 break;
729 }
730 if (i == 0xb && !(c->ecx & 0xff00)) {
731 break;
732 }
733 if (i == 0xd && c->eax == 0) {
734 continue;
735 }
736 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
737 fprintf(stderr, "cpuid_data is full, no space for "
738 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
739 abort();
740 }
741 c = &cpuid_data.entries[cpuid_i++];
742 }
743 break;
744 default:
745 c->function = i;
746 c->flags = 0;
747 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
748 break;
749 }
750 }
751
752 if (limit >= 0x0a) {
753 uint32_t ver;
754
755 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
756 if ((ver & 0xff) > 0) {
757 has_msr_architectural_pmu = true;
758 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
759
760 /* Shouldn't be more than 32, since that's the number of bits
761 * available in EBX to tell us _which_ counters are available.
762 * Play it safe.
763 */
764 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
765 num_architectural_pmu_counters = MAX_GP_COUNTERS;
766 }
767 }
768 }
769
770 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
771
772 for (i = 0x80000000; i <= limit; i++) {
773 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
774 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
775 abort();
776 }
777 c = &cpuid_data.entries[cpuid_i++];
778
779 c->function = i;
780 c->flags = 0;
781 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
782 }
783
784 /* Call Centaur's CPUID instructions they are supported. */
785 if (env->cpuid_xlevel2 > 0) {
786 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
787
788 for (i = 0xC0000000; i <= limit; i++) {
789 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
790 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
791 abort();
792 }
793 c = &cpuid_data.entries[cpuid_i++];
794
795 c->function = i;
796 c->flags = 0;
797 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
798 }
799 }
800
801 cpuid_data.cpuid.nent = cpuid_i;
802
803 if (((env->cpuid_version >> 8)&0xF) >= 6
804 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
805 (CPUID_MCE | CPUID_MCA)
806 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
807 uint64_t mcg_cap, unsupported_caps;
808 int banks;
809 int ret;
810
811 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
812 if (ret < 0) {
813 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
814 return ret;
815 }
816
817 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
818 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
819 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
820 return -ENOTSUP;
821 }
822
823 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
824 if (unsupported_caps) {
825 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
826 unsupported_caps);
827 }
828
829 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
830 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
831 if (ret < 0) {
832 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
833 return ret;
834 }
835 }
836
837 qemu_add_vm_change_state_handler(cpu_update_state, env);
838
839 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
840 if (c) {
841 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
842 !!(c->ecx & CPUID_EXT_SMX);
843 }
844
845 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
846 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
847 /* for migration */
848 error_setg(&invtsc_mig_blocker,
849 "State blocked by non-migratable CPU device"
850 " (invtsc flag)");
851 migrate_add_blocker(invtsc_mig_blocker);
852 /* for savevm */
853 vmstate_x86_cpu.unmigratable = 1;
854 }
855
856 cpuid_data.cpuid.padding = 0;
857 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
858 if (r) {
859 return r;
860 }
861
862 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
863 if (r && env->tsc_khz) {
864 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
865 if (r < 0) {
866 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
867 return r;
868 }
869 }
870
871 if (has_xsave) {
872 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
873 }
874
875 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
876 has_msr_mtrr = true;
877 }
878
879 return 0;
880 }
881
882 void kvm_arch_reset_vcpu(X86CPU *cpu)
883 {
884 CPUX86State *env = &cpu->env;
885
886 env->exception_injected = -1;
887 env->interrupt_injected = -1;
888 env->xcr0 = 1;
889 if (kvm_irqchip_in_kernel()) {
890 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
891 KVM_MP_STATE_UNINITIALIZED;
892 } else {
893 env->mp_state = KVM_MP_STATE_RUNNABLE;
894 }
895 }
896
897 void kvm_arch_do_init_vcpu(X86CPU *cpu)
898 {
899 CPUX86State *env = &cpu->env;
900
901 /* APs get directly into wait-for-SIPI state. */
902 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
903 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
904 }
905 }
906
907 static int kvm_get_supported_msrs(KVMState *s)
908 {
909 static int kvm_supported_msrs;
910 int ret = 0;
911
912 /* first time */
913 if (kvm_supported_msrs == 0) {
914 struct kvm_msr_list msr_list, *kvm_msr_list;
915
916 kvm_supported_msrs = -1;
917
918 /* Obtain MSR list from KVM. These are the MSRs that we must
919 * save/restore */
920 msr_list.nmsrs = 0;
921 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
922 if (ret < 0 && ret != -E2BIG) {
923 return ret;
924 }
925 /* Old kernel modules had a bug and could write beyond the provided
926 memory. Allocate at least a safe amount of 1K. */
927 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
928 msr_list.nmsrs *
929 sizeof(msr_list.indices[0])));
930
931 kvm_msr_list->nmsrs = msr_list.nmsrs;
932 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
933 if (ret >= 0) {
934 int i;
935
936 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
937 if (kvm_msr_list->indices[i] == MSR_STAR) {
938 has_msr_star = true;
939 continue;
940 }
941 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
942 has_msr_hsave_pa = true;
943 continue;
944 }
945 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
946 has_msr_tsc_aux = true;
947 continue;
948 }
949 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
950 has_msr_tsc_adjust = true;
951 continue;
952 }
953 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
954 has_msr_tsc_deadline = true;
955 continue;
956 }
957 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
958 has_msr_smbase = true;
959 continue;
960 }
961 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
962 has_msr_misc_enable = true;
963 continue;
964 }
965 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
966 has_msr_bndcfgs = true;
967 continue;
968 }
969 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
970 has_msr_xss = true;
971 continue;
972 }
973 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
974 has_msr_hv_crash = true;
975 continue;
976 }
977 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
978 has_msr_hv_reset = true;
979 continue;
980 }
981 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
982 has_msr_hv_vpindex = true;
983 continue;
984 }
985 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
986 has_msr_hv_runtime = true;
987 continue;
988 }
989 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
990 has_msr_hv_synic = true;
991 continue;
992 }
993 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
994 has_msr_hv_stimer = true;
995 continue;
996 }
997 }
998 }
999
1000 g_free(kvm_msr_list);
1001 }
1002
1003 return ret;
1004 }
1005
1006 static Notifier smram_machine_done;
1007 static KVMMemoryListener smram_listener;
1008 static AddressSpace smram_address_space;
1009 static MemoryRegion smram_as_root;
1010 static MemoryRegion smram_as_mem;
1011
1012 static void register_smram_listener(Notifier *n, void *unused)
1013 {
1014 MemoryRegion *smram =
1015 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1016
1017 /* Outer container... */
1018 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1019 memory_region_set_enabled(&smram_as_root, true);
1020
1021 /* ... with two regions inside: normal system memory with low
1022 * priority, and...
1023 */
1024 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1025 get_system_memory(), 0, ~0ull);
1026 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1027 memory_region_set_enabled(&smram_as_mem, true);
1028
1029 if (smram) {
1030 /* ... SMRAM with higher priority */
1031 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1032 memory_region_set_enabled(smram, true);
1033 }
1034
1035 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1036 kvm_memory_listener_register(kvm_state, &smram_listener,
1037 &smram_address_space, 1);
1038 }
1039
1040 int kvm_arch_init(MachineState *ms, KVMState *s)
1041 {
1042 uint64_t identity_base = 0xfffbc000;
1043 uint64_t shadow_mem;
1044 int ret;
1045 struct utsname utsname;
1046
1047 #ifdef KVM_CAP_XSAVE
1048 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1049 #endif
1050
1051 #ifdef KVM_CAP_XCRS
1052 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1053 #endif
1054
1055 #ifdef KVM_CAP_PIT_STATE2
1056 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1057 #endif
1058
1059 ret = kvm_get_supported_msrs(s);
1060 if (ret < 0) {
1061 return ret;
1062 }
1063
1064 uname(&utsname);
1065 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1066
1067 /*
1068 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1069 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1070 * Since these must be part of guest physical memory, we need to allocate
1071 * them, both by setting their start addresses in the kernel and by
1072 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1073 *
1074 * Older KVM versions may not support setting the identity map base. In
1075 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1076 * size.
1077 */
1078 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1079 /* Allows up to 16M BIOSes. */
1080 identity_base = 0xfeffc000;
1081
1082 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1083 if (ret < 0) {
1084 return ret;
1085 }
1086 }
1087
1088 /* Set TSS base one page after EPT identity map. */
1089 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1090 if (ret < 0) {
1091 return ret;
1092 }
1093
1094 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1095 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1096 if (ret < 0) {
1097 fprintf(stderr, "e820_add_entry() table is full\n");
1098 return ret;
1099 }
1100 qemu_register_reset(kvm_unpoison_all, NULL);
1101
1102 shadow_mem = machine_kvm_shadow_mem(ms);
1103 if (shadow_mem != -1) {
1104 shadow_mem /= 4096;
1105 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1106 if (ret < 0) {
1107 return ret;
1108 }
1109 }
1110
1111 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1112 smram_machine_done.notify = register_smram_listener;
1113 qemu_add_machine_init_done_notifier(&smram_machine_done);
1114 }
1115 return 0;
1116 }
1117
1118 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1119 {
1120 lhs->selector = rhs->selector;
1121 lhs->base = rhs->base;
1122 lhs->limit = rhs->limit;
1123 lhs->type = 3;
1124 lhs->present = 1;
1125 lhs->dpl = 3;
1126 lhs->db = 0;
1127 lhs->s = 1;
1128 lhs->l = 0;
1129 lhs->g = 0;
1130 lhs->avl = 0;
1131 lhs->unusable = 0;
1132 }
1133
1134 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1135 {
1136 unsigned flags = rhs->flags;
1137 lhs->selector = rhs->selector;
1138 lhs->base = rhs->base;
1139 lhs->limit = rhs->limit;
1140 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1141 lhs->present = (flags & DESC_P_MASK) != 0;
1142 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1143 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1144 lhs->s = (flags & DESC_S_MASK) != 0;
1145 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1146 lhs->g = (flags & DESC_G_MASK) != 0;
1147 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1148 lhs->unusable = 0;
1149 lhs->padding = 0;
1150 }
1151
1152 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1153 {
1154 lhs->selector = rhs->selector;
1155 lhs->base = rhs->base;
1156 lhs->limit = rhs->limit;
1157 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1158 (rhs->present * DESC_P_MASK) |
1159 (rhs->dpl << DESC_DPL_SHIFT) |
1160 (rhs->db << DESC_B_SHIFT) |
1161 (rhs->s * DESC_S_MASK) |
1162 (rhs->l << DESC_L_SHIFT) |
1163 (rhs->g * DESC_G_MASK) |
1164 (rhs->avl * DESC_AVL_MASK);
1165 }
1166
1167 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1168 {
1169 if (set) {
1170 *kvm_reg = *qemu_reg;
1171 } else {
1172 *qemu_reg = *kvm_reg;
1173 }
1174 }
1175
1176 static int kvm_getput_regs(X86CPU *cpu, int set)
1177 {
1178 CPUX86State *env = &cpu->env;
1179 struct kvm_regs regs;
1180 int ret = 0;
1181
1182 if (!set) {
1183 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1184 if (ret < 0) {
1185 return ret;
1186 }
1187 }
1188
1189 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1190 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1191 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1192 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1193 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1194 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1195 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1196 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1197 #ifdef TARGET_X86_64
1198 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1199 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1200 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1201 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1202 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1203 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1204 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1205 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1206 #endif
1207
1208 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1209 kvm_getput_reg(&regs.rip, &env->eip, set);
1210
1211 if (set) {
1212 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1213 }
1214
1215 return ret;
1216 }
1217
1218 static int kvm_put_fpu(X86CPU *cpu)
1219 {
1220 CPUX86State *env = &cpu->env;
1221 struct kvm_fpu fpu;
1222 int i;
1223
1224 memset(&fpu, 0, sizeof fpu);
1225 fpu.fsw = env->fpus & ~(7 << 11);
1226 fpu.fsw |= (env->fpstt & 7) << 11;
1227 fpu.fcw = env->fpuc;
1228 fpu.last_opcode = env->fpop;
1229 fpu.last_ip = env->fpip;
1230 fpu.last_dp = env->fpdp;
1231 for (i = 0; i < 8; ++i) {
1232 fpu.ftwx |= (!env->fptags[i]) << i;
1233 }
1234 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1235 for (i = 0; i < CPU_NB_REGS; i++) {
1236 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1237 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1238 }
1239 fpu.mxcsr = env->mxcsr;
1240
1241 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1242 }
1243
1244 #define XSAVE_FCW_FSW 0
1245 #define XSAVE_FTW_FOP 1
1246 #define XSAVE_CWD_RIP 2
1247 #define XSAVE_CWD_RDP 4
1248 #define XSAVE_MXCSR 6
1249 #define XSAVE_ST_SPACE 8
1250 #define XSAVE_XMM_SPACE 40
1251 #define XSAVE_XSTATE_BV 128
1252 #define XSAVE_YMMH_SPACE 144
1253 #define XSAVE_BNDREGS 240
1254 #define XSAVE_BNDCSR 256
1255 #define XSAVE_OPMASK 272
1256 #define XSAVE_ZMM_Hi256 288
1257 #define XSAVE_Hi16_ZMM 416
1258
1259 static int kvm_put_xsave(X86CPU *cpu)
1260 {
1261 CPUX86State *env = &cpu->env;
1262 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1263 uint16_t cwd, swd, twd;
1264 uint8_t *xmm, *ymmh, *zmmh;
1265 int i, r;
1266
1267 if (!has_xsave) {
1268 return kvm_put_fpu(cpu);
1269 }
1270
1271 memset(xsave, 0, sizeof(struct kvm_xsave));
1272 twd = 0;
1273 swd = env->fpus & ~(7 << 11);
1274 swd |= (env->fpstt & 7) << 11;
1275 cwd = env->fpuc;
1276 for (i = 0; i < 8; ++i) {
1277 twd |= (!env->fptags[i]) << i;
1278 }
1279 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1280 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1281 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1282 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1283 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1284 sizeof env->fpregs);
1285 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1286 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1287 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1288 sizeof env->bnd_regs);
1289 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1290 sizeof(env->bndcs_regs));
1291 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1292 sizeof env->opmask_regs);
1293
1294 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1295 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1296 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1297 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1298 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1299 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1300 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1301 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1302 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1303 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1304 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1305 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1306 }
1307
1308 #ifdef TARGET_X86_64
1309 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1310 16 * sizeof env->xmm_regs[16]);
1311 #endif
1312 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1313 return r;
1314 }
1315
1316 static int kvm_put_xcrs(X86CPU *cpu)
1317 {
1318 CPUX86State *env = &cpu->env;
1319 struct kvm_xcrs xcrs = {};
1320
1321 if (!has_xcrs) {
1322 return 0;
1323 }
1324
1325 xcrs.nr_xcrs = 1;
1326 xcrs.flags = 0;
1327 xcrs.xcrs[0].xcr = 0;
1328 xcrs.xcrs[0].value = env->xcr0;
1329 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1330 }
1331
1332 static int kvm_put_sregs(X86CPU *cpu)
1333 {
1334 CPUX86State *env = &cpu->env;
1335 struct kvm_sregs sregs;
1336
1337 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1338 if (env->interrupt_injected >= 0) {
1339 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1340 (uint64_t)1 << (env->interrupt_injected % 64);
1341 }
1342
1343 if ((env->eflags & VM_MASK)) {
1344 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1345 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1346 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1347 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1348 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1349 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1350 } else {
1351 set_seg(&sregs.cs, &env->segs[R_CS]);
1352 set_seg(&sregs.ds, &env->segs[R_DS]);
1353 set_seg(&sregs.es, &env->segs[R_ES]);
1354 set_seg(&sregs.fs, &env->segs[R_FS]);
1355 set_seg(&sregs.gs, &env->segs[R_GS]);
1356 set_seg(&sregs.ss, &env->segs[R_SS]);
1357 }
1358
1359 set_seg(&sregs.tr, &env->tr);
1360 set_seg(&sregs.ldt, &env->ldt);
1361
1362 sregs.idt.limit = env->idt.limit;
1363 sregs.idt.base = env->idt.base;
1364 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1365 sregs.gdt.limit = env->gdt.limit;
1366 sregs.gdt.base = env->gdt.base;
1367 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1368
1369 sregs.cr0 = env->cr[0];
1370 sregs.cr2 = env->cr[2];
1371 sregs.cr3 = env->cr[3];
1372 sregs.cr4 = env->cr[4];
1373
1374 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1375 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1376
1377 sregs.efer = env->efer;
1378
1379 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1380 }
1381
1382 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1383 uint32_t index, uint64_t value)
1384 {
1385 entry->index = index;
1386 entry->reserved = 0;
1387 entry->data = value;
1388 }
1389
1390 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1391 {
1392 CPUX86State *env = &cpu->env;
1393 struct {
1394 struct kvm_msrs info;
1395 struct kvm_msr_entry entries[1];
1396 } msr_data;
1397 struct kvm_msr_entry *msrs = msr_data.entries;
1398
1399 if (!has_msr_tsc_deadline) {
1400 return 0;
1401 }
1402
1403 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1404
1405 msr_data.info = (struct kvm_msrs) {
1406 .nmsrs = 1,
1407 };
1408
1409 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1410 }
1411
1412 /*
1413 * Provide a separate write service for the feature control MSR in order to
1414 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1415 * before writing any other state because forcibly leaving nested mode
1416 * invalidates the VCPU state.
1417 */
1418 static int kvm_put_msr_feature_control(X86CPU *cpu)
1419 {
1420 struct {
1421 struct kvm_msrs info;
1422 struct kvm_msr_entry entry;
1423 } msr_data;
1424
1425 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1426 cpu->env.msr_ia32_feature_control);
1427
1428 msr_data.info = (struct kvm_msrs) {
1429 .nmsrs = 1,
1430 };
1431
1432 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1433 }
1434
1435 static int kvm_put_msrs(X86CPU *cpu, int level)
1436 {
1437 CPUX86State *env = &cpu->env;
1438 struct {
1439 struct kvm_msrs info;
1440 struct kvm_msr_entry entries[150];
1441 } msr_data;
1442 struct kvm_msr_entry *msrs = msr_data.entries;
1443 int n = 0, i;
1444
1445 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1446 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1447 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1448 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1449 if (has_msr_star) {
1450 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1451 }
1452 if (has_msr_hsave_pa) {
1453 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1454 }
1455 if (has_msr_tsc_aux) {
1456 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1457 }
1458 if (has_msr_tsc_adjust) {
1459 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1460 }
1461 if (has_msr_misc_enable) {
1462 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1463 env->msr_ia32_misc_enable);
1464 }
1465 if (has_msr_smbase) {
1466 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1467 }
1468 if (has_msr_bndcfgs) {
1469 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1470 }
1471 if (has_msr_xss) {
1472 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1473 }
1474 #ifdef TARGET_X86_64
1475 if (lm_capable_kernel) {
1476 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1477 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1478 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1479 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1480 }
1481 #endif
1482 /*
1483 * The following MSRs have side effects on the guest or are too heavy
1484 * for normal writeback. Limit them to reset or full state updates.
1485 */
1486 if (level >= KVM_PUT_RESET_STATE) {
1487 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1488 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1489 env->system_time_msr);
1490 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1491 if (has_msr_async_pf_en) {
1492 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1493 env->async_pf_en_msr);
1494 }
1495 if (has_msr_pv_eoi_en) {
1496 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1497 env->pv_eoi_en_msr);
1498 }
1499 if (has_msr_kvm_steal_time) {
1500 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1501 env->steal_time_msr);
1502 }
1503 if (has_msr_architectural_pmu) {
1504 /* Stop the counter. */
1505 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1506 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1507
1508 /* Set the counter values. */
1509 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1510 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1511 env->msr_fixed_counters[i]);
1512 }
1513 for (i = 0; i < num_architectural_pmu_counters; i++) {
1514 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1515 env->msr_gp_counters[i]);
1516 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1517 env->msr_gp_evtsel[i]);
1518 }
1519 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1520 env->msr_global_status);
1521 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1522 env->msr_global_ovf_ctrl);
1523
1524 /* Now start the PMU. */
1525 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1526 env->msr_fixed_ctr_ctrl);
1527 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1528 env->msr_global_ctrl);
1529 }
1530 if (has_msr_hv_hypercall) {
1531 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1532 env->msr_hv_guest_os_id);
1533 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1534 env->msr_hv_hypercall);
1535 }
1536 if (has_msr_hv_vapic) {
1537 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1538 env->msr_hv_vapic);
1539 }
1540 if (has_msr_hv_tsc) {
1541 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1542 env->msr_hv_tsc);
1543 }
1544 if (has_msr_hv_crash) {
1545 int j;
1546
1547 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1548 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1549 env->msr_hv_crash_params[j]);
1550
1551 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1552 HV_X64_MSR_CRASH_CTL_NOTIFY);
1553 }
1554 if (has_msr_hv_runtime) {
1555 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1556 env->msr_hv_runtime);
1557 }
1558 if (cpu->hyperv_synic) {
1559 int j;
1560
1561 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL,
1562 env->msr_hv_synic_control);
1563 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION,
1564 env->msr_hv_synic_version);
1565 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP,
1566 env->msr_hv_synic_evt_page);
1567 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP,
1568 env->msr_hv_synic_msg_page);
1569
1570 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1571 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j,
1572 env->msr_hv_synic_sint[j]);
1573 }
1574 }
1575 if (has_msr_hv_stimer) {
1576 int j;
1577
1578 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1579 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG + j*2,
1580 env->msr_hv_stimer_config[j]);
1581 }
1582
1583 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1584 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT + j*2,
1585 env->msr_hv_stimer_count[j]);
1586 }
1587 }
1588 if (has_msr_mtrr) {
1589 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1590 kvm_msr_entry_set(&msrs[n++],
1591 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1592 kvm_msr_entry_set(&msrs[n++],
1593 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1594 kvm_msr_entry_set(&msrs[n++],
1595 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1596 kvm_msr_entry_set(&msrs[n++],
1597 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1598 kvm_msr_entry_set(&msrs[n++],
1599 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1600 kvm_msr_entry_set(&msrs[n++],
1601 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1602 kvm_msr_entry_set(&msrs[n++],
1603 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1604 kvm_msr_entry_set(&msrs[n++],
1605 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1606 kvm_msr_entry_set(&msrs[n++],
1607 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1608 kvm_msr_entry_set(&msrs[n++],
1609 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1610 kvm_msr_entry_set(&msrs[n++],
1611 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1612 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1613 kvm_msr_entry_set(&msrs[n++],
1614 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1615 kvm_msr_entry_set(&msrs[n++],
1616 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1617 }
1618 }
1619
1620 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1621 * kvm_put_msr_feature_control. */
1622 }
1623 if (env->mcg_cap) {
1624 int i;
1625
1626 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1627 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1628 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1629 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1630 }
1631 }
1632
1633 msr_data.info = (struct kvm_msrs) {
1634 .nmsrs = n,
1635 };
1636
1637 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1638
1639 }
1640
1641
1642 static int kvm_get_fpu(X86CPU *cpu)
1643 {
1644 CPUX86State *env = &cpu->env;
1645 struct kvm_fpu fpu;
1646 int i, ret;
1647
1648 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1649 if (ret < 0) {
1650 return ret;
1651 }
1652
1653 env->fpstt = (fpu.fsw >> 11) & 7;
1654 env->fpus = fpu.fsw;
1655 env->fpuc = fpu.fcw;
1656 env->fpop = fpu.last_opcode;
1657 env->fpip = fpu.last_ip;
1658 env->fpdp = fpu.last_dp;
1659 for (i = 0; i < 8; ++i) {
1660 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1661 }
1662 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1663 for (i = 0; i < CPU_NB_REGS; i++) {
1664 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1665 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1666 }
1667 env->mxcsr = fpu.mxcsr;
1668
1669 return 0;
1670 }
1671
1672 static int kvm_get_xsave(X86CPU *cpu)
1673 {
1674 CPUX86State *env = &cpu->env;
1675 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1676 int ret, i;
1677 const uint8_t *xmm, *ymmh, *zmmh;
1678 uint16_t cwd, swd, twd;
1679
1680 if (!has_xsave) {
1681 return kvm_get_fpu(cpu);
1682 }
1683
1684 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1685 if (ret < 0) {
1686 return ret;
1687 }
1688
1689 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1690 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1691 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1692 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1693 env->fpstt = (swd >> 11) & 7;
1694 env->fpus = swd;
1695 env->fpuc = cwd;
1696 for (i = 0; i < 8; ++i) {
1697 env->fptags[i] = !((twd >> i) & 1);
1698 }
1699 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1700 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1701 env->mxcsr = xsave->region[XSAVE_MXCSR];
1702 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1703 sizeof env->fpregs);
1704 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1705 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1706 sizeof env->bnd_regs);
1707 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1708 sizeof(env->bndcs_regs));
1709 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1710 sizeof env->opmask_regs);
1711
1712 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1713 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1714 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1715 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1716 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1717 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1718 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1719 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1720 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1721 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1722 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1723 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1724 }
1725
1726 #ifdef TARGET_X86_64
1727 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1728 16 * sizeof env->xmm_regs[16]);
1729 #endif
1730 return 0;
1731 }
1732
1733 static int kvm_get_xcrs(X86CPU *cpu)
1734 {
1735 CPUX86State *env = &cpu->env;
1736 int i, ret;
1737 struct kvm_xcrs xcrs;
1738
1739 if (!has_xcrs) {
1740 return 0;
1741 }
1742
1743 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1744 if (ret < 0) {
1745 return ret;
1746 }
1747
1748 for (i = 0; i < xcrs.nr_xcrs; i++) {
1749 /* Only support xcr0 now */
1750 if (xcrs.xcrs[i].xcr == 0) {
1751 env->xcr0 = xcrs.xcrs[i].value;
1752 break;
1753 }
1754 }
1755 return 0;
1756 }
1757
1758 static int kvm_get_sregs(X86CPU *cpu)
1759 {
1760 CPUX86State *env = &cpu->env;
1761 struct kvm_sregs sregs;
1762 uint32_t hflags;
1763 int bit, i, ret;
1764
1765 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1766 if (ret < 0) {
1767 return ret;
1768 }
1769
1770 /* There can only be one pending IRQ set in the bitmap at a time, so try
1771 to find it and save its number instead (-1 for none). */
1772 env->interrupt_injected = -1;
1773 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1774 if (sregs.interrupt_bitmap[i]) {
1775 bit = ctz64(sregs.interrupt_bitmap[i]);
1776 env->interrupt_injected = i * 64 + bit;
1777 break;
1778 }
1779 }
1780
1781 get_seg(&env->segs[R_CS], &sregs.cs);
1782 get_seg(&env->segs[R_DS], &sregs.ds);
1783 get_seg(&env->segs[R_ES], &sregs.es);
1784 get_seg(&env->segs[R_FS], &sregs.fs);
1785 get_seg(&env->segs[R_GS], &sregs.gs);
1786 get_seg(&env->segs[R_SS], &sregs.ss);
1787
1788 get_seg(&env->tr, &sregs.tr);
1789 get_seg(&env->ldt, &sregs.ldt);
1790
1791 env->idt.limit = sregs.idt.limit;
1792 env->idt.base = sregs.idt.base;
1793 env->gdt.limit = sregs.gdt.limit;
1794 env->gdt.base = sregs.gdt.base;
1795
1796 env->cr[0] = sregs.cr0;
1797 env->cr[2] = sregs.cr2;
1798 env->cr[3] = sregs.cr3;
1799 env->cr[4] = sregs.cr4;
1800
1801 env->efer = sregs.efer;
1802
1803 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1804
1805 #define HFLAG_COPY_MASK \
1806 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1807 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1808 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1809 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1810
1811 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1812 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1813 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1814 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1815 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1816 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1817 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1818
1819 if (env->efer & MSR_EFER_LMA) {
1820 hflags |= HF_LMA_MASK;
1821 }
1822
1823 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1824 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1825 } else {
1826 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1827 (DESC_B_SHIFT - HF_CS32_SHIFT);
1828 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1829 (DESC_B_SHIFT - HF_SS32_SHIFT);
1830 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1831 !(hflags & HF_CS32_MASK)) {
1832 hflags |= HF_ADDSEG_MASK;
1833 } else {
1834 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1835 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1836 }
1837 }
1838 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1839
1840 return 0;
1841 }
1842
1843 static int kvm_get_msrs(X86CPU *cpu)
1844 {
1845 CPUX86State *env = &cpu->env;
1846 struct {
1847 struct kvm_msrs info;
1848 struct kvm_msr_entry entries[150];
1849 } msr_data;
1850 struct kvm_msr_entry *msrs = msr_data.entries;
1851 int ret, i, n;
1852
1853 n = 0;
1854 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1855 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1856 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1857 msrs[n++].index = MSR_PAT;
1858 if (has_msr_star) {
1859 msrs[n++].index = MSR_STAR;
1860 }
1861 if (has_msr_hsave_pa) {
1862 msrs[n++].index = MSR_VM_HSAVE_PA;
1863 }
1864 if (has_msr_tsc_aux) {
1865 msrs[n++].index = MSR_TSC_AUX;
1866 }
1867 if (has_msr_tsc_adjust) {
1868 msrs[n++].index = MSR_TSC_ADJUST;
1869 }
1870 if (has_msr_tsc_deadline) {
1871 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1872 }
1873 if (has_msr_misc_enable) {
1874 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1875 }
1876 if (has_msr_smbase) {
1877 msrs[n++].index = MSR_IA32_SMBASE;
1878 }
1879 if (has_msr_feature_control) {
1880 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1881 }
1882 if (has_msr_bndcfgs) {
1883 msrs[n++].index = MSR_IA32_BNDCFGS;
1884 }
1885 if (has_msr_xss) {
1886 msrs[n++].index = MSR_IA32_XSS;
1887 }
1888
1889
1890 if (!env->tsc_valid) {
1891 msrs[n++].index = MSR_IA32_TSC;
1892 env->tsc_valid = !runstate_is_running();
1893 }
1894
1895 #ifdef TARGET_X86_64
1896 if (lm_capable_kernel) {
1897 msrs[n++].index = MSR_CSTAR;
1898 msrs[n++].index = MSR_KERNELGSBASE;
1899 msrs[n++].index = MSR_FMASK;
1900 msrs[n++].index = MSR_LSTAR;
1901 }
1902 #endif
1903 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1904 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1905 if (has_msr_async_pf_en) {
1906 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1907 }
1908 if (has_msr_pv_eoi_en) {
1909 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1910 }
1911 if (has_msr_kvm_steal_time) {
1912 msrs[n++].index = MSR_KVM_STEAL_TIME;
1913 }
1914 if (has_msr_architectural_pmu) {
1915 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1916 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1917 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1918 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1919 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1920 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1921 }
1922 for (i = 0; i < num_architectural_pmu_counters; i++) {
1923 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1924 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1925 }
1926 }
1927
1928 if (env->mcg_cap) {
1929 msrs[n++].index = MSR_MCG_STATUS;
1930 msrs[n++].index = MSR_MCG_CTL;
1931 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1932 msrs[n++].index = MSR_MC0_CTL + i;
1933 }
1934 }
1935
1936 if (has_msr_hv_hypercall) {
1937 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1938 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1939 }
1940 if (has_msr_hv_vapic) {
1941 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1942 }
1943 if (has_msr_hv_tsc) {
1944 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1945 }
1946 if (has_msr_hv_crash) {
1947 int j;
1948
1949 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
1950 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
1951 }
1952 }
1953 if (has_msr_hv_runtime) {
1954 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
1955 }
1956 if (cpu->hyperv_synic) {
1957 uint32_t msr;
1958
1959 msrs[n++].index = HV_X64_MSR_SCONTROL;
1960 msrs[n++].index = HV_X64_MSR_SVERSION;
1961 msrs[n++].index = HV_X64_MSR_SIEFP;
1962 msrs[n++].index = HV_X64_MSR_SIMP;
1963 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
1964 msrs[n++].index = msr;
1965 }
1966 }
1967 if (has_msr_hv_stimer) {
1968 uint32_t msr;
1969
1970 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
1971 msr++) {
1972 msrs[n++].index = msr;
1973 }
1974 }
1975 if (has_msr_mtrr) {
1976 msrs[n++].index = MSR_MTRRdefType;
1977 msrs[n++].index = MSR_MTRRfix64K_00000;
1978 msrs[n++].index = MSR_MTRRfix16K_80000;
1979 msrs[n++].index = MSR_MTRRfix16K_A0000;
1980 msrs[n++].index = MSR_MTRRfix4K_C0000;
1981 msrs[n++].index = MSR_MTRRfix4K_C8000;
1982 msrs[n++].index = MSR_MTRRfix4K_D0000;
1983 msrs[n++].index = MSR_MTRRfix4K_D8000;
1984 msrs[n++].index = MSR_MTRRfix4K_E0000;
1985 msrs[n++].index = MSR_MTRRfix4K_E8000;
1986 msrs[n++].index = MSR_MTRRfix4K_F0000;
1987 msrs[n++].index = MSR_MTRRfix4K_F8000;
1988 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1989 msrs[n++].index = MSR_MTRRphysBase(i);
1990 msrs[n++].index = MSR_MTRRphysMask(i);
1991 }
1992 }
1993
1994 msr_data.info = (struct kvm_msrs) {
1995 .nmsrs = n,
1996 };
1997
1998 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1999 if (ret < 0) {
2000 return ret;
2001 }
2002
2003 for (i = 0; i < ret; i++) {
2004 uint32_t index = msrs[i].index;
2005 switch (index) {
2006 case MSR_IA32_SYSENTER_CS:
2007 env->sysenter_cs = msrs[i].data;
2008 break;
2009 case MSR_IA32_SYSENTER_ESP:
2010 env->sysenter_esp = msrs[i].data;
2011 break;
2012 case MSR_IA32_SYSENTER_EIP:
2013 env->sysenter_eip = msrs[i].data;
2014 break;
2015 case MSR_PAT:
2016 env->pat = msrs[i].data;
2017 break;
2018 case MSR_STAR:
2019 env->star = msrs[i].data;
2020 break;
2021 #ifdef TARGET_X86_64
2022 case MSR_CSTAR:
2023 env->cstar = msrs[i].data;
2024 break;
2025 case MSR_KERNELGSBASE:
2026 env->kernelgsbase = msrs[i].data;
2027 break;
2028 case MSR_FMASK:
2029 env->fmask = msrs[i].data;
2030 break;
2031 case MSR_LSTAR:
2032 env->lstar = msrs[i].data;
2033 break;
2034 #endif
2035 case MSR_IA32_TSC:
2036 env->tsc = msrs[i].data;
2037 break;
2038 case MSR_TSC_AUX:
2039 env->tsc_aux = msrs[i].data;
2040 break;
2041 case MSR_TSC_ADJUST:
2042 env->tsc_adjust = msrs[i].data;
2043 break;
2044 case MSR_IA32_TSCDEADLINE:
2045 env->tsc_deadline = msrs[i].data;
2046 break;
2047 case MSR_VM_HSAVE_PA:
2048 env->vm_hsave = msrs[i].data;
2049 break;
2050 case MSR_KVM_SYSTEM_TIME:
2051 env->system_time_msr = msrs[i].data;
2052 break;
2053 case MSR_KVM_WALL_CLOCK:
2054 env->wall_clock_msr = msrs[i].data;
2055 break;
2056 case MSR_MCG_STATUS:
2057 env->mcg_status = msrs[i].data;
2058 break;
2059 case MSR_MCG_CTL:
2060 env->mcg_ctl = msrs[i].data;
2061 break;
2062 case MSR_IA32_MISC_ENABLE:
2063 env->msr_ia32_misc_enable = msrs[i].data;
2064 break;
2065 case MSR_IA32_SMBASE:
2066 env->smbase = msrs[i].data;
2067 break;
2068 case MSR_IA32_FEATURE_CONTROL:
2069 env->msr_ia32_feature_control = msrs[i].data;
2070 break;
2071 case MSR_IA32_BNDCFGS:
2072 env->msr_bndcfgs = msrs[i].data;
2073 break;
2074 case MSR_IA32_XSS:
2075 env->xss = msrs[i].data;
2076 break;
2077 default:
2078 if (msrs[i].index >= MSR_MC0_CTL &&
2079 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2080 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2081 }
2082 break;
2083 case MSR_KVM_ASYNC_PF_EN:
2084 env->async_pf_en_msr = msrs[i].data;
2085 break;
2086 case MSR_KVM_PV_EOI_EN:
2087 env->pv_eoi_en_msr = msrs[i].data;
2088 break;
2089 case MSR_KVM_STEAL_TIME:
2090 env->steal_time_msr = msrs[i].data;
2091 break;
2092 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2093 env->msr_fixed_ctr_ctrl = msrs[i].data;
2094 break;
2095 case MSR_CORE_PERF_GLOBAL_CTRL:
2096 env->msr_global_ctrl = msrs[i].data;
2097 break;
2098 case MSR_CORE_PERF_GLOBAL_STATUS:
2099 env->msr_global_status = msrs[i].data;
2100 break;
2101 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2102 env->msr_global_ovf_ctrl = msrs[i].data;
2103 break;
2104 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2105 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2106 break;
2107 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2108 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2109 break;
2110 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2111 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2112 break;
2113 case HV_X64_MSR_HYPERCALL:
2114 env->msr_hv_hypercall = msrs[i].data;
2115 break;
2116 case HV_X64_MSR_GUEST_OS_ID:
2117 env->msr_hv_guest_os_id = msrs[i].data;
2118 break;
2119 case HV_X64_MSR_APIC_ASSIST_PAGE:
2120 env->msr_hv_vapic = msrs[i].data;
2121 break;
2122 case HV_X64_MSR_REFERENCE_TSC:
2123 env->msr_hv_tsc = msrs[i].data;
2124 break;
2125 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2126 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2127 break;
2128 case HV_X64_MSR_VP_RUNTIME:
2129 env->msr_hv_runtime = msrs[i].data;
2130 break;
2131 case HV_X64_MSR_SCONTROL:
2132 env->msr_hv_synic_control = msrs[i].data;
2133 break;
2134 case HV_X64_MSR_SVERSION:
2135 env->msr_hv_synic_version = msrs[i].data;
2136 break;
2137 case HV_X64_MSR_SIEFP:
2138 env->msr_hv_synic_evt_page = msrs[i].data;
2139 break;
2140 case HV_X64_MSR_SIMP:
2141 env->msr_hv_synic_msg_page = msrs[i].data;
2142 break;
2143 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2144 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2145 break;
2146 case HV_X64_MSR_STIMER0_CONFIG:
2147 case HV_X64_MSR_STIMER1_CONFIG:
2148 case HV_X64_MSR_STIMER2_CONFIG:
2149 case HV_X64_MSR_STIMER3_CONFIG:
2150 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2151 msrs[i].data;
2152 break;
2153 case HV_X64_MSR_STIMER0_COUNT:
2154 case HV_X64_MSR_STIMER1_COUNT:
2155 case HV_X64_MSR_STIMER2_COUNT:
2156 case HV_X64_MSR_STIMER3_COUNT:
2157 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2158 msrs[i].data;
2159 break;
2160 case MSR_MTRRdefType:
2161 env->mtrr_deftype = msrs[i].data;
2162 break;
2163 case MSR_MTRRfix64K_00000:
2164 env->mtrr_fixed[0] = msrs[i].data;
2165 break;
2166 case MSR_MTRRfix16K_80000:
2167 env->mtrr_fixed[1] = msrs[i].data;
2168 break;
2169 case MSR_MTRRfix16K_A0000:
2170 env->mtrr_fixed[2] = msrs[i].data;
2171 break;
2172 case MSR_MTRRfix4K_C0000:
2173 env->mtrr_fixed[3] = msrs[i].data;
2174 break;
2175 case MSR_MTRRfix4K_C8000:
2176 env->mtrr_fixed[4] = msrs[i].data;
2177 break;
2178 case MSR_MTRRfix4K_D0000:
2179 env->mtrr_fixed[5] = msrs[i].data;
2180 break;
2181 case MSR_MTRRfix4K_D8000:
2182 env->mtrr_fixed[6] = msrs[i].data;
2183 break;
2184 case MSR_MTRRfix4K_E0000:
2185 env->mtrr_fixed[7] = msrs[i].data;
2186 break;
2187 case MSR_MTRRfix4K_E8000:
2188 env->mtrr_fixed[8] = msrs[i].data;
2189 break;
2190 case MSR_MTRRfix4K_F0000:
2191 env->mtrr_fixed[9] = msrs[i].data;
2192 break;
2193 case MSR_MTRRfix4K_F8000:
2194 env->mtrr_fixed[10] = msrs[i].data;
2195 break;
2196 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2197 if (index & 1) {
2198 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2199 } else {
2200 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2201 }
2202 break;
2203 }
2204 }
2205
2206 return 0;
2207 }
2208
2209 static int kvm_put_mp_state(X86CPU *cpu)
2210 {
2211 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2212
2213 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2214 }
2215
2216 static int kvm_get_mp_state(X86CPU *cpu)
2217 {
2218 CPUState *cs = CPU(cpu);
2219 CPUX86State *env = &cpu->env;
2220 struct kvm_mp_state mp_state;
2221 int ret;
2222
2223 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2224 if (ret < 0) {
2225 return ret;
2226 }
2227 env->mp_state = mp_state.mp_state;
2228 if (kvm_irqchip_in_kernel()) {
2229 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2230 }
2231 return 0;
2232 }
2233
2234 static int kvm_get_apic(X86CPU *cpu)
2235 {
2236 DeviceState *apic = cpu->apic_state;
2237 struct kvm_lapic_state kapic;
2238 int ret;
2239
2240 if (apic && kvm_irqchip_in_kernel()) {
2241 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2242 if (ret < 0) {
2243 return ret;
2244 }
2245
2246 kvm_get_apic_state(apic, &kapic);
2247 }
2248 return 0;
2249 }
2250
2251 static int kvm_put_apic(X86CPU *cpu)
2252 {
2253 DeviceState *apic = cpu->apic_state;
2254 struct kvm_lapic_state kapic;
2255
2256 if (apic && kvm_irqchip_in_kernel()) {
2257 kvm_put_apic_state(apic, &kapic);
2258
2259 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2260 }
2261 return 0;
2262 }
2263
2264 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2265 {
2266 CPUState *cs = CPU(cpu);
2267 CPUX86State *env = &cpu->env;
2268 struct kvm_vcpu_events events = {};
2269
2270 if (!kvm_has_vcpu_events()) {
2271 return 0;
2272 }
2273
2274 events.exception.injected = (env->exception_injected >= 0);
2275 events.exception.nr = env->exception_injected;
2276 events.exception.has_error_code = env->has_error_code;
2277 events.exception.error_code = env->error_code;
2278 events.exception.pad = 0;
2279
2280 events.interrupt.injected = (env->interrupt_injected >= 0);
2281 events.interrupt.nr = env->interrupt_injected;
2282 events.interrupt.soft = env->soft_interrupt;
2283
2284 events.nmi.injected = env->nmi_injected;
2285 events.nmi.pending = env->nmi_pending;
2286 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2287 events.nmi.pad = 0;
2288
2289 events.sipi_vector = env->sipi_vector;
2290
2291 if (has_msr_smbase) {
2292 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2293 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2294 if (kvm_irqchip_in_kernel()) {
2295 /* As soon as these are moved to the kernel, remove them
2296 * from cs->interrupt_request.
2297 */
2298 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2299 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2300 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2301 } else {
2302 /* Keep these in cs->interrupt_request. */
2303 events.smi.pending = 0;
2304 events.smi.latched_init = 0;
2305 }
2306 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2307 }
2308
2309 events.flags = 0;
2310 if (level >= KVM_PUT_RESET_STATE) {
2311 events.flags |=
2312 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2313 }
2314
2315 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2316 }
2317
2318 static int kvm_get_vcpu_events(X86CPU *cpu)
2319 {
2320 CPUX86State *env = &cpu->env;
2321 struct kvm_vcpu_events events;
2322 int ret;
2323
2324 if (!kvm_has_vcpu_events()) {
2325 return 0;
2326 }
2327
2328 memset(&events, 0, sizeof(events));
2329 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2330 if (ret < 0) {
2331 return ret;
2332 }
2333 env->exception_injected =
2334 events.exception.injected ? events.exception.nr : -1;
2335 env->has_error_code = events.exception.has_error_code;
2336 env->error_code = events.exception.error_code;
2337
2338 env->interrupt_injected =
2339 events.interrupt.injected ? events.interrupt.nr : -1;
2340 env->soft_interrupt = events.interrupt.soft;
2341
2342 env->nmi_injected = events.nmi.injected;
2343 env->nmi_pending = events.nmi.pending;
2344 if (events.nmi.masked) {
2345 env->hflags2 |= HF2_NMI_MASK;
2346 } else {
2347 env->hflags2 &= ~HF2_NMI_MASK;
2348 }
2349
2350 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2351 if (events.smi.smm) {
2352 env->hflags |= HF_SMM_MASK;
2353 } else {
2354 env->hflags &= ~HF_SMM_MASK;
2355 }
2356 if (events.smi.pending) {
2357 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2358 } else {
2359 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2360 }
2361 if (events.smi.smm_inside_nmi) {
2362 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2363 } else {
2364 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2365 }
2366 if (events.smi.latched_init) {
2367 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2368 } else {
2369 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2370 }
2371 }
2372
2373 env->sipi_vector = events.sipi_vector;
2374
2375 return 0;
2376 }
2377
2378 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2379 {
2380 CPUState *cs = CPU(cpu);
2381 CPUX86State *env = &cpu->env;
2382 int ret = 0;
2383 unsigned long reinject_trap = 0;
2384
2385 if (!kvm_has_vcpu_events()) {
2386 if (env->exception_injected == 1) {
2387 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2388 } else if (env->exception_injected == 3) {
2389 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2390 }
2391 env->exception_injected = -1;
2392 }
2393
2394 /*
2395 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2396 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2397 * by updating the debug state once again if single-stepping is on.
2398 * Another reason to call kvm_update_guest_debug here is a pending debug
2399 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2400 * reinject them via SET_GUEST_DEBUG.
2401 */
2402 if (reinject_trap ||
2403 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2404 ret = kvm_update_guest_debug(cs, reinject_trap);
2405 }
2406 return ret;
2407 }
2408
2409 static int kvm_put_debugregs(X86CPU *cpu)
2410 {
2411 CPUX86State *env = &cpu->env;
2412 struct kvm_debugregs dbgregs;
2413 int i;
2414
2415 if (!kvm_has_debugregs()) {
2416 return 0;
2417 }
2418
2419 for (i = 0; i < 4; i++) {
2420 dbgregs.db[i] = env->dr[i];
2421 }
2422 dbgregs.dr6 = env->dr[6];
2423 dbgregs.dr7 = env->dr[7];
2424 dbgregs.flags = 0;
2425
2426 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2427 }
2428
2429 static int kvm_get_debugregs(X86CPU *cpu)
2430 {
2431 CPUX86State *env = &cpu->env;
2432 struct kvm_debugregs dbgregs;
2433 int i, ret;
2434
2435 if (!kvm_has_debugregs()) {
2436 return 0;
2437 }
2438
2439 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2440 if (ret < 0) {
2441 return ret;
2442 }
2443 for (i = 0; i < 4; i++) {
2444 env->dr[i] = dbgregs.db[i];
2445 }
2446 env->dr[4] = env->dr[6] = dbgregs.dr6;
2447 env->dr[5] = env->dr[7] = dbgregs.dr7;
2448
2449 return 0;
2450 }
2451
2452 int kvm_arch_put_registers(CPUState *cpu, int level)
2453 {
2454 X86CPU *x86_cpu = X86_CPU(cpu);
2455 int ret;
2456
2457 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2458
2459 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2460 ret = kvm_put_msr_feature_control(x86_cpu);
2461 if (ret < 0) {
2462 return ret;
2463 }
2464 }
2465
2466 ret = kvm_getput_regs(x86_cpu, 1);
2467 if (ret < 0) {
2468 return ret;
2469 }
2470 ret = kvm_put_xsave(x86_cpu);
2471 if (ret < 0) {
2472 return ret;
2473 }
2474 ret = kvm_put_xcrs(x86_cpu);
2475 if (ret < 0) {
2476 return ret;
2477 }
2478 ret = kvm_put_sregs(x86_cpu);
2479 if (ret < 0) {
2480 return ret;
2481 }
2482 /* must be before kvm_put_msrs */
2483 ret = kvm_inject_mce_oldstyle(x86_cpu);
2484 if (ret < 0) {
2485 return ret;
2486 }
2487 ret = kvm_put_msrs(x86_cpu, level);
2488 if (ret < 0) {
2489 return ret;
2490 }
2491 if (level >= KVM_PUT_RESET_STATE) {
2492 ret = kvm_put_mp_state(x86_cpu);
2493 if (ret < 0) {
2494 return ret;
2495 }
2496 ret = kvm_put_apic(x86_cpu);
2497 if (ret < 0) {
2498 return ret;
2499 }
2500 }
2501
2502 ret = kvm_put_tscdeadline_msr(x86_cpu);
2503 if (ret < 0) {
2504 return ret;
2505 }
2506
2507 ret = kvm_put_vcpu_events(x86_cpu, level);
2508 if (ret < 0) {
2509 return ret;
2510 }
2511 ret = kvm_put_debugregs(x86_cpu);
2512 if (ret < 0) {
2513 return ret;
2514 }
2515 /* must be last */
2516 ret = kvm_guest_debug_workarounds(x86_cpu);
2517 if (ret < 0) {
2518 return ret;
2519 }
2520 return 0;
2521 }
2522
2523 int kvm_arch_get_registers(CPUState *cs)
2524 {
2525 X86CPU *cpu = X86_CPU(cs);
2526 int ret;
2527
2528 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2529
2530 ret = kvm_getput_regs(cpu, 0);
2531 if (ret < 0) {
2532 return ret;
2533 }
2534 ret = kvm_get_xsave(cpu);
2535 if (ret < 0) {
2536 return ret;
2537 }
2538 ret = kvm_get_xcrs(cpu);
2539 if (ret < 0) {
2540 return ret;
2541 }
2542 ret = kvm_get_sregs(cpu);
2543 if (ret < 0) {
2544 return ret;
2545 }
2546 ret = kvm_get_msrs(cpu);
2547 if (ret < 0) {
2548 return ret;
2549 }
2550 ret = kvm_get_mp_state(cpu);
2551 if (ret < 0) {
2552 return ret;
2553 }
2554 ret = kvm_get_apic(cpu);
2555 if (ret < 0) {
2556 return ret;
2557 }
2558 ret = kvm_get_vcpu_events(cpu);
2559 if (ret < 0) {
2560 return ret;
2561 }
2562 ret = kvm_get_debugregs(cpu);
2563 if (ret < 0) {
2564 return ret;
2565 }
2566 return 0;
2567 }
2568
2569 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2570 {
2571 X86CPU *x86_cpu = X86_CPU(cpu);
2572 CPUX86State *env = &x86_cpu->env;
2573 int ret;
2574
2575 /* Inject NMI */
2576 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2577 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2578 qemu_mutex_lock_iothread();
2579 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2580 qemu_mutex_unlock_iothread();
2581 DPRINTF("injected NMI\n");
2582 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2583 if (ret < 0) {
2584 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2585 strerror(-ret));
2586 }
2587 }
2588 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2589 qemu_mutex_lock_iothread();
2590 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2591 qemu_mutex_unlock_iothread();
2592 DPRINTF("injected SMI\n");
2593 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2594 if (ret < 0) {
2595 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2596 strerror(-ret));
2597 }
2598 }
2599 }
2600
2601 if (!kvm_pic_in_kernel()) {
2602 qemu_mutex_lock_iothread();
2603 }
2604
2605 /* Force the VCPU out of its inner loop to process any INIT requests
2606 * or (for userspace APIC, but it is cheap to combine the checks here)
2607 * pending TPR access reports.
2608 */
2609 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2610 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2611 !(env->hflags & HF_SMM_MASK)) {
2612 cpu->exit_request = 1;
2613 }
2614 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2615 cpu->exit_request = 1;
2616 }
2617 }
2618
2619 if (!kvm_pic_in_kernel()) {
2620 /* Try to inject an interrupt if the guest can accept it */
2621 if (run->ready_for_interrupt_injection &&
2622 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2623 (env->eflags & IF_MASK)) {
2624 int irq;
2625
2626 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2627 irq = cpu_get_pic_interrupt(env);
2628 if (irq >= 0) {
2629 struct kvm_interrupt intr;
2630
2631 intr.irq = irq;
2632 DPRINTF("injected interrupt %d\n", irq);
2633 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2634 if (ret < 0) {
2635 fprintf(stderr,
2636 "KVM: injection failed, interrupt lost (%s)\n",
2637 strerror(-ret));
2638 }
2639 }
2640 }
2641
2642 /* If we have an interrupt but the guest is not ready to receive an
2643 * interrupt, request an interrupt window exit. This will
2644 * cause a return to userspace as soon as the guest is ready to
2645 * receive interrupts. */
2646 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2647 run->request_interrupt_window = 1;
2648 } else {
2649 run->request_interrupt_window = 0;
2650 }
2651
2652 DPRINTF("setting tpr\n");
2653 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2654
2655 qemu_mutex_unlock_iothread();
2656 }
2657 }
2658
2659 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2660 {
2661 X86CPU *x86_cpu = X86_CPU(cpu);
2662 CPUX86State *env = &x86_cpu->env;
2663
2664 if (run->flags & KVM_RUN_X86_SMM) {
2665 env->hflags |= HF_SMM_MASK;
2666 } else {
2667 env->hflags &= HF_SMM_MASK;
2668 }
2669 if (run->if_flag) {
2670 env->eflags |= IF_MASK;
2671 } else {
2672 env->eflags &= ~IF_MASK;
2673 }
2674
2675 /* We need to protect the apic state against concurrent accesses from
2676 * different threads in case the userspace irqchip is used. */
2677 if (!kvm_irqchip_in_kernel()) {
2678 qemu_mutex_lock_iothread();
2679 }
2680 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2681 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2682 if (!kvm_irqchip_in_kernel()) {
2683 qemu_mutex_unlock_iothread();
2684 }
2685 return cpu_get_mem_attrs(env);
2686 }
2687
2688 int kvm_arch_process_async_events(CPUState *cs)
2689 {
2690 X86CPU *cpu = X86_CPU(cs);
2691 CPUX86State *env = &cpu->env;
2692
2693 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2694 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2695 assert(env->mcg_cap);
2696
2697 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2698
2699 kvm_cpu_synchronize_state(cs);
2700
2701 if (env->exception_injected == EXCP08_DBLE) {
2702 /* this means triple fault */
2703 qemu_system_reset_request();
2704 cs->exit_request = 1;
2705 return 0;
2706 }
2707 env->exception_injected = EXCP12_MCHK;
2708 env->has_error_code = 0;
2709
2710 cs->halted = 0;
2711 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2712 env->mp_state = KVM_MP_STATE_RUNNABLE;
2713 }
2714 }
2715
2716 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2717 !(env->hflags & HF_SMM_MASK)) {
2718 kvm_cpu_synchronize_state(cs);
2719 do_cpu_init(cpu);
2720 }
2721
2722 if (kvm_irqchip_in_kernel()) {
2723 return 0;
2724 }
2725
2726 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2727 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2728 apic_poll_irq(cpu->apic_state);
2729 }
2730 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2731 (env->eflags & IF_MASK)) ||
2732 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2733 cs->halted = 0;
2734 }
2735 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2736 kvm_cpu_synchronize_state(cs);
2737 do_cpu_sipi(cpu);
2738 }
2739 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2740 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2741 kvm_cpu_synchronize_state(cs);
2742 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2743 env->tpr_access_type);
2744 }
2745
2746 return cs->halted;
2747 }
2748
2749 static int kvm_handle_halt(X86CPU *cpu)
2750 {
2751 CPUState *cs = CPU(cpu);
2752 CPUX86State *env = &cpu->env;
2753
2754 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2755 (env->eflags & IF_MASK)) &&
2756 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2757 cs->halted = 1;
2758 return EXCP_HLT;
2759 }
2760
2761 return 0;
2762 }
2763
2764 static int kvm_handle_tpr_access(X86CPU *cpu)
2765 {
2766 CPUState *cs = CPU(cpu);
2767 struct kvm_run *run = cs->kvm_run;
2768
2769 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2770 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2771 : TPR_ACCESS_READ);
2772 return 1;
2773 }
2774
2775 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2776 {
2777 static const uint8_t int3 = 0xcc;
2778
2779 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2780 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2781 return -EINVAL;
2782 }
2783 return 0;
2784 }
2785
2786 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2787 {
2788 uint8_t int3;
2789
2790 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2791 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2792 return -EINVAL;
2793 }
2794 return 0;
2795 }
2796
2797 static struct {
2798 target_ulong addr;
2799 int len;
2800 int type;
2801 } hw_breakpoint[4];
2802
2803 static int nb_hw_breakpoint;
2804
2805 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2806 {
2807 int n;
2808
2809 for (n = 0; n < nb_hw_breakpoint; n++) {
2810 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2811 (hw_breakpoint[n].len == len || len == -1)) {
2812 return n;
2813 }
2814 }
2815 return -1;
2816 }
2817
2818 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2819 target_ulong len, int type)
2820 {
2821 switch (type) {
2822 case GDB_BREAKPOINT_HW:
2823 len = 1;
2824 break;
2825 case GDB_WATCHPOINT_WRITE:
2826 case GDB_WATCHPOINT_ACCESS:
2827 switch (len) {
2828 case 1:
2829 break;
2830 case 2:
2831 case 4:
2832 case 8:
2833 if (addr & (len - 1)) {
2834 return -EINVAL;
2835 }
2836 break;
2837 default:
2838 return -EINVAL;
2839 }
2840 break;
2841 default:
2842 return -ENOSYS;
2843 }
2844
2845 if (nb_hw_breakpoint == 4) {
2846 return -ENOBUFS;
2847 }
2848 if (find_hw_breakpoint(addr, len, type) >= 0) {
2849 return -EEXIST;
2850 }
2851 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2852 hw_breakpoint[nb_hw_breakpoint].len = len;
2853 hw_breakpoint[nb_hw_breakpoint].type = type;
2854 nb_hw_breakpoint++;
2855
2856 return 0;
2857 }
2858
2859 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2860 target_ulong len, int type)
2861 {
2862 int n;
2863
2864 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2865 if (n < 0) {
2866 return -ENOENT;
2867 }
2868 nb_hw_breakpoint--;
2869 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2870
2871 return 0;
2872 }
2873
2874 void kvm_arch_remove_all_hw_breakpoints(void)
2875 {
2876 nb_hw_breakpoint = 0;
2877 }
2878
2879 static CPUWatchpoint hw_watchpoint;
2880
2881 static int kvm_handle_debug(X86CPU *cpu,
2882 struct kvm_debug_exit_arch *arch_info)
2883 {
2884 CPUState *cs = CPU(cpu);
2885 CPUX86State *env = &cpu->env;
2886 int ret = 0;
2887 int n;
2888
2889 if (arch_info->exception == 1) {
2890 if (arch_info->dr6 & (1 << 14)) {
2891 if (cs->singlestep_enabled) {
2892 ret = EXCP_DEBUG;
2893 }
2894 } else {
2895 for (n = 0; n < 4; n++) {
2896 if (arch_info->dr6 & (1 << n)) {
2897 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2898 case 0x0:
2899 ret = EXCP_DEBUG;
2900 break;
2901 case 0x1:
2902 ret = EXCP_DEBUG;
2903 cs->watchpoint_hit = &hw_watchpoint;
2904 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2905 hw_watchpoint.flags = BP_MEM_WRITE;
2906 break;
2907 case 0x3:
2908 ret = EXCP_DEBUG;
2909 cs->watchpoint_hit = &hw_watchpoint;
2910 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2911 hw_watchpoint.flags = BP_MEM_ACCESS;
2912 break;
2913 }
2914 }
2915 }
2916 }
2917 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2918 ret = EXCP_DEBUG;
2919 }
2920 if (ret == 0) {
2921 cpu_synchronize_state(cs);
2922 assert(env->exception_injected == -1);
2923
2924 /* pass to guest */
2925 env->exception_injected = arch_info->exception;
2926 env->has_error_code = 0;
2927 }
2928
2929 return ret;
2930 }
2931
2932 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2933 {
2934 const uint8_t type_code[] = {
2935 [GDB_BREAKPOINT_HW] = 0x0,
2936 [GDB_WATCHPOINT_WRITE] = 0x1,
2937 [GDB_WATCHPOINT_ACCESS] = 0x3
2938 };
2939 const uint8_t len_code[] = {
2940 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2941 };
2942 int n;
2943
2944 if (kvm_sw_breakpoints_active(cpu)) {
2945 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2946 }
2947 if (nb_hw_breakpoint > 0) {
2948 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2949 dbg->arch.debugreg[7] = 0x0600;
2950 for (n = 0; n < nb_hw_breakpoint; n++) {
2951 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2952 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2953 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2954 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2955 }
2956 }
2957 }
2958
2959 static bool host_supports_vmx(void)
2960 {
2961 uint32_t ecx, unused;
2962
2963 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2964 return ecx & CPUID_EXT_VMX;
2965 }
2966
2967 #define VMX_INVALID_GUEST_STATE 0x80000021
2968
2969 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2970 {
2971 X86CPU *cpu = X86_CPU(cs);
2972 uint64_t code;
2973 int ret;
2974
2975 switch (run->exit_reason) {
2976 case KVM_EXIT_HLT:
2977 DPRINTF("handle_hlt\n");
2978 qemu_mutex_lock_iothread();
2979 ret = kvm_handle_halt(cpu);
2980 qemu_mutex_unlock_iothread();
2981 break;
2982 case KVM_EXIT_SET_TPR:
2983 ret = 0;
2984 break;
2985 case KVM_EXIT_TPR_ACCESS:
2986 qemu_mutex_lock_iothread();
2987 ret = kvm_handle_tpr_access(cpu);
2988 qemu_mutex_unlock_iothread();
2989 break;
2990 case KVM_EXIT_FAIL_ENTRY:
2991 code = run->fail_entry.hardware_entry_failure_reason;
2992 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2993 code);
2994 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2995 fprintf(stderr,
2996 "\nIf you're running a guest on an Intel machine without "
2997 "unrestricted mode\n"
2998 "support, the failure can be most likely due to the guest "
2999 "entering an invalid\n"
3000 "state for Intel VT. For example, the guest maybe running "
3001 "in big real mode\n"
3002 "which is not supported on less recent Intel processors."
3003 "\n\n");
3004 }
3005 ret = -1;
3006 break;
3007 case KVM_EXIT_EXCEPTION:
3008 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3009 run->ex.exception, run->ex.error_code);
3010 ret = -1;
3011 break;
3012 case KVM_EXIT_DEBUG:
3013 DPRINTF("kvm_exit_debug\n");
3014 qemu_mutex_lock_iothread();
3015 ret = kvm_handle_debug(cpu, &run->debug.arch);
3016 qemu_mutex_unlock_iothread();
3017 break;
3018 case KVM_EXIT_HYPERV:
3019 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3020 break;
3021 case KVM_EXIT_IOAPIC_EOI:
3022 ioapic_eoi_broadcast(run->eoi.vector);
3023 ret = 0;
3024 break;
3025 default:
3026 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3027 ret = -1;
3028 break;
3029 }
3030
3031 return ret;
3032 }
3033
3034 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3035 {
3036 X86CPU *cpu = X86_CPU(cs);
3037 CPUX86State *env = &cpu->env;
3038
3039 kvm_cpu_synchronize_state(cs);
3040 return !(env->cr[0] & CR0_PE_MASK) ||
3041 ((env->segs[R_CS].selector & 3) != 3);
3042 }
3043
3044 void kvm_arch_init_irq_routing(KVMState *s)
3045 {
3046 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3047 /* If kernel can't do irq routing, interrupt source
3048 * override 0->2 cannot be set up as required by HPET.
3049 * So we have to disable it.
3050 */
3051 no_hpet = 1;
3052 }
3053 /* We know at this point that we're using the in-kernel
3054 * irqchip, so we can use irqfds, and on x86 we know
3055 * we can use msi via irqfd and GSI routing.
3056 */
3057 kvm_msi_via_irqfd_allowed = true;
3058 kvm_gsi_routing_allowed = true;
3059
3060 if (kvm_irqchip_is_split()) {
3061 int i;
3062
3063 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3064 MSI routes for signaling interrupts to the local apics. */
3065 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3066 struct MSIMessage msg = { 0x0, 0x0 };
3067 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3068 error_report("Could not enable split IRQ mode.");
3069 exit(1);
3070 }
3071 }
3072 }
3073 }
3074
3075 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3076 {
3077 int ret;
3078 if (machine_kernel_irqchip_split(ms)) {
3079 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3080 if (ret) {
3081 error_report("Could not enable split irqchip mode: %s\n",
3082 strerror(-ret));
3083 exit(1);
3084 } else {
3085 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3086 kvm_split_irqchip = true;
3087 return 1;
3088 }
3089 } else {
3090 return 0;
3091 }
3092 }
3093
3094 /* Classic KVM device assignment interface. Will remain x86 only. */
3095 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3096 uint32_t flags, uint32_t *dev_id)
3097 {
3098 struct kvm_assigned_pci_dev dev_data = {
3099 .segnr = dev_addr->domain,
3100 .busnr = dev_addr->bus,
3101 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3102 .flags = flags,
3103 };
3104 int ret;
3105
3106 dev_data.assigned_dev_id =
3107 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3108
3109 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3110 if (ret < 0) {
3111 return ret;
3112 }
3113
3114 *dev_id = dev_data.assigned_dev_id;
3115
3116 return 0;
3117 }
3118
3119 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3120 {
3121 struct kvm_assigned_pci_dev dev_data = {
3122 .assigned_dev_id = dev_id,
3123 };
3124
3125 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3126 }
3127
3128 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3129 uint32_t irq_type, uint32_t guest_irq)
3130 {
3131 struct kvm_assigned_irq assigned_irq = {
3132 .assigned_dev_id = dev_id,
3133 .guest_irq = guest_irq,
3134 .flags = irq_type,
3135 };
3136
3137 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3138 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3139 } else {
3140 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3141 }
3142 }
3143
3144 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3145 uint32_t guest_irq)
3146 {
3147 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3148 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3149
3150 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3151 }
3152
3153 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3154 {
3155 struct kvm_assigned_pci_dev dev_data = {
3156 .assigned_dev_id = dev_id,
3157 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3158 };
3159
3160 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3161 }
3162
3163 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3164 uint32_t type)
3165 {
3166 struct kvm_assigned_irq assigned_irq = {
3167 .assigned_dev_id = dev_id,
3168 .flags = type,
3169 };
3170
3171 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3172 }
3173
3174 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3175 {
3176 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3177 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3178 }
3179
3180 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3181 {
3182 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3183 KVM_DEV_IRQ_GUEST_MSI, virq);
3184 }
3185
3186 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3187 {
3188 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3189 KVM_DEV_IRQ_HOST_MSI);
3190 }
3191
3192 bool kvm_device_msix_supported(KVMState *s)
3193 {
3194 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3195 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3196 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3197 }
3198
3199 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3200 uint32_t nr_vectors)
3201 {
3202 struct kvm_assigned_msix_nr msix_nr = {
3203 .assigned_dev_id = dev_id,
3204 .entry_nr = nr_vectors,
3205 };
3206
3207 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3208 }
3209
3210 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3211 int virq)
3212 {
3213 struct kvm_assigned_msix_entry msix_entry = {
3214 .assigned_dev_id = dev_id,
3215 .gsi = virq,
3216 .entry = vector,
3217 };
3218
3219 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3220 }
3221
3222 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3223 {
3224 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3225 KVM_DEV_IRQ_GUEST_MSIX, 0);
3226 }
3227
3228 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3229 {
3230 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3231 KVM_DEV_IRQ_HOST_MSIX);
3232 }
3233
3234 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3235 uint64_t address, uint32_t data, PCIDevice *dev)
3236 {
3237 return 0;
3238 }
3239
3240 int kvm_arch_msi_data_to_gsi(uint32_t data)
3241 {
3242 abort();
3243 }
CRIS target port of Qemu