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virtio-blk: cleanup: QOM cast
[qemu/cris-port.git] / target-ppc / translate.c
blob380a884131aa765114667839054413a7651cf013
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 TCGv t0 = tcg_temp_new();
750
751 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
752 tcg_gen_xor_tl(t0, arg1, arg2);
753 if (sub) {
754 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
755 } else {
756 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
757 }
758 tcg_temp_free(t0);
759 #if defined(TARGET_PPC64)
760 if (!ctx->sf_mode) {
761 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
762 }
763 #endif
764 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
765 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
766 }
767
768 /* Common add function */
769 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
770 TCGv arg2, bool add_ca, bool compute_ca,
771 bool compute_ov, bool compute_rc0)
772 {
773 TCGv t0 = ret;
774
775 if (((compute_ca && add_ca) || compute_ov)
776 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
777 t0 = tcg_temp_new();
778 }
779
780 if (compute_ca) {
781 TCGv zero = tcg_const_tl(0);
782 if (add_ca) {
783 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
784 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
785 } else {
786 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
787 }
788 tcg_temp_free(zero);
789 } else {
790 tcg_gen_add_tl(t0, arg1, arg2);
791 if (add_ca) {
792 tcg_gen_add_tl(t0, t0, cpu_ca);
793 }
794 }
795
796 if (compute_ov) {
797 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
798 }
799 if (unlikely(compute_rc0)) {
800 gen_set_Rc0(ctx, t0);
801 }
802
803 if (!TCGV_EQUAL(t0, ret)) {
804 tcg_gen_mov_tl(ret, t0);
805 tcg_temp_free(t0);
806 }
807 }
808 /* Add functions with two operands */
809 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
810 static void glue(gen_, name)(DisasContext *ctx) \
811 { \
812 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
813 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
814 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
815 }
816 /* Add functions with one operand and one immediate */
817 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
818 add_ca, compute_ca, compute_ov) \
819 static void glue(gen_, name)(DisasContext *ctx) \
820 { \
821 TCGv t0 = tcg_const_tl(const_val); \
822 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
823 cpu_gpr[rA(ctx->opcode)], t0, \
824 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
825 tcg_temp_free(t0); \
826 }
827
828 /* add add. addo addo. */
829 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
830 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
831 /* addc addc. addco addco. */
832 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
833 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
834 /* adde adde. addeo addeo. */
835 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
836 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
837 /* addme addme. addmeo addmeo. */
838 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
839 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
840 /* addze addze. addzeo addzeo.*/
841 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
842 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
843 /* addi */
844 static void gen_addi(DisasContext *ctx)
845 {
846 target_long simm = SIMM(ctx->opcode);
847
848 if (rA(ctx->opcode) == 0) {
849 /* li case */
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
851 } else {
852 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
853 cpu_gpr[rA(ctx->opcode)], simm);
854 }
855 }
856 /* addic addic.*/
857 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
858 {
859 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
860 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
861 c, 0, 1, 0, compute_rc0);
862 tcg_temp_free(c);
863 }
864
865 static void gen_addic(DisasContext *ctx)
866 {
867 gen_op_addic(ctx, 0);
868 }
869
870 static void gen_addic_(DisasContext *ctx)
871 {
872 gen_op_addic(ctx, 1);
873 }
874
875 /* addis */
876 static void gen_addis(DisasContext *ctx)
877 {
878 target_long simm = SIMM(ctx->opcode);
879
880 if (rA(ctx->opcode) == 0) {
881 /* lis case */
882 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
883 } else {
884 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
885 cpu_gpr[rA(ctx->opcode)], simm << 16);
886 }
887 }
888
889 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
890 TCGv arg2, int sign, int compute_ov)
891 {
892 int l1 = gen_new_label();
893 int l2 = gen_new_label();
894 TCGv_i32 t0 = tcg_temp_local_new_i32();
895 TCGv_i32 t1 = tcg_temp_local_new_i32();
896
897 tcg_gen_trunc_tl_i32(t0, arg1);
898 tcg_gen_trunc_tl_i32(t1, arg2);
899 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
900 if (sign) {
901 int l3 = gen_new_label();
902 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
903 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
904 gen_set_label(l3);
905 tcg_gen_div_i32(t0, t0, t1);
906 } else {
907 tcg_gen_divu_i32(t0, t0, t1);
908 }
909 if (compute_ov) {
910 tcg_gen_movi_tl(cpu_ov, 0);
911 }
912 tcg_gen_br(l2);
913 gen_set_label(l1);
914 if (sign) {
915 tcg_gen_sari_i32(t0, t0, 31);
916 } else {
917 tcg_gen_movi_i32(t0, 0);
918 }
919 if (compute_ov) {
920 tcg_gen_movi_tl(cpu_ov, 1);
921 tcg_gen_movi_tl(cpu_so, 1);
922 }
923 gen_set_label(l2);
924 tcg_gen_extu_i32_tl(ret, t0);
925 tcg_temp_free_i32(t0);
926 tcg_temp_free_i32(t1);
927 if (unlikely(Rc(ctx->opcode) != 0))
928 gen_set_Rc0(ctx, ret);
929 }
930 /* Div functions */
931 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
932 static void glue(gen_, name)(DisasContext *ctx) \
933 { \
934 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
935 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
936 sign, compute_ov); \
937 }
938 /* divwu divwu. divwuo divwuo. */
939 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
940 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
941 /* divw divw. divwo divwo. */
942 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
943 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
944 #if defined(TARGET_PPC64)
945 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
946 TCGv arg2, int sign, int compute_ov)
947 {
948 int l1 = gen_new_label();
949 int l2 = gen_new_label();
950
951 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
952 if (sign) {
953 int l3 = gen_new_label();
954 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
955 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i64(ret, arg1, arg2);
958 } else {
959 tcg_gen_divu_i64(ret, arg1, arg2);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i64(ret, arg1, 63);
968 } else {
969 tcg_gen_movi_i64(ret, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 if (unlikely(Rc(ctx->opcode) != 0))
977 gen_set_Rc0(ctx, ret);
978 }
979 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
980 static void glue(gen_, name)(DisasContext *ctx) \
981 { \
982 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 sign, compute_ov); \
985 }
986 /* divwu divwu. divwuo divwuo. */
987 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
988 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
989 /* divw divw. divwo divwo. */
990 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
991 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
992 #endif
993
994 /* mulhw mulhw. */
995 static void gen_mulhw(DisasContext *ctx)
996 {
997 TCGv_i32 t0 = tcg_temp_new_i32();
998 TCGv_i32 t1 = tcg_temp_new_i32();
999
1000 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1001 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1002 tcg_gen_muls2_i32(t0, t1, t0, t1);
1003 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1004 tcg_temp_free_i32(t0);
1005 tcg_temp_free_i32(t1);
1006 if (unlikely(Rc(ctx->opcode) != 0))
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1008 }
1009
1010 /* mulhwu mulhwu. */
1011 static void gen_mulhwu(DisasContext *ctx)
1012 {
1013 TCGv_i32 t0 = tcg_temp_new_i32();
1014 TCGv_i32 t1 = tcg_temp_new_i32();
1015
1016 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1019 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1020 tcg_temp_free_i32(t0);
1021 tcg_temp_free_i32(t1);
1022 if (unlikely(Rc(ctx->opcode) != 0))
1023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1024 }
1025
1026 /* mullw mullw. */
1027 static void gen_mullw(DisasContext *ctx)
1028 {
1029 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1030 cpu_gpr[rB(ctx->opcode)]);
1031 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1032 if (unlikely(Rc(ctx->opcode) != 0))
1033 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034 }
1035
1036 /* mullwo mullwo. */
1037 static void gen_mullwo(DisasContext *ctx)
1038 {
1039 TCGv_i32 t0 = tcg_temp_new_i32();
1040 TCGv_i32 t1 = tcg_temp_new_i32();
1041
1042 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1043 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1044 tcg_gen_muls2_i32(t0, t1, t0, t1);
1045 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1046
1047 tcg_gen_sari_i32(t0, t0, 31);
1048 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1049 tcg_gen_extu_i32_tl(cpu_ov, t0);
1050 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1051
1052 tcg_temp_free_i32(t0);
1053 tcg_temp_free_i32(t1);
1054 if (unlikely(Rc(ctx->opcode) != 0))
1055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1056 }
1057
1058 /* mulli */
1059 static void gen_mulli(DisasContext *ctx)
1060 {
1061 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1062 SIMM(ctx->opcode));
1063 }
1064
1065 #if defined(TARGET_PPC64)
1066 /* mulhd mulhd. */
1067 static void gen_mulhd(DisasContext *ctx)
1068 {
1069 TCGv lo = tcg_temp_new();
1070 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1071 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1072 tcg_temp_free(lo);
1073 if (unlikely(Rc(ctx->opcode) != 0)) {
1074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1075 }
1076 }
1077
1078 /* mulhdu mulhdu. */
1079 static void gen_mulhdu(DisasContext *ctx)
1080 {
1081 TCGv lo = tcg_temp_new();
1082 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1083 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1084 tcg_temp_free(lo);
1085 if (unlikely(Rc(ctx->opcode) != 0)) {
1086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1087 }
1088 }
1089
1090 /* mulld mulld. */
1091 static void gen_mulld(DisasContext *ctx)
1092 {
1093 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1094 cpu_gpr[rB(ctx->opcode)]);
1095 if (unlikely(Rc(ctx->opcode) != 0))
1096 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1097 }
1098
1099 /* mulldo mulldo. */
1100 static void gen_mulldo(DisasContext *ctx)
1101 {
1102 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1103 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1104 if (unlikely(Rc(ctx->opcode) != 0)) {
1105 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1106 }
1107 }
1108 #endif
1109
1110 /* Common subf function */
1111 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1112 TCGv arg2, bool add_ca, bool compute_ca,
1113 bool compute_ov, bool compute_rc0)
1114 {
1115 TCGv t0 = ret;
1116
1117 if (((add_ca && compute_ca) || compute_ov)
1118 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1119 t0 = tcg_temp_new();
1120 }
1121
1122 if (add_ca) {
1123 /* dest = ~arg1 + arg2 + ca. */
1124 if (compute_ca) {
1125 TCGv zero, inv1 = tcg_temp_new();
1126 tcg_gen_not_tl(inv1, arg1);
1127 zero = tcg_const_tl(0);
1128 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1129 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1130 tcg_temp_free(zero);
1131 tcg_temp_free(inv1);
1132 } else {
1133 tcg_gen_sub_tl(t0, arg2, arg1);
1134 tcg_gen_add_tl(t0, t0, cpu_ca);
1135 tcg_gen_subi_tl(t0, t0, 1);
1136 }
1137 } else {
1138 if (compute_ca) {
1139 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1140 }
1141 tcg_gen_sub_tl(t0, arg2, arg1);
1142 }
1143
1144 if (compute_ov) {
1145 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1146 }
1147 if (unlikely(compute_rc0)) {
1148 gen_set_Rc0(ctx, t0);
1149 }
1150
1151 if (!TCGV_EQUAL(t0, ret)) {
1152 tcg_gen_mov_tl(ret, t0);
1153 tcg_temp_free(t0);
1154 }
1155 }
1156 /* Sub functions with Two operands functions */
1157 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1158 static void glue(gen_, name)(DisasContext *ctx) \
1159 { \
1160 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1162 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1163 }
1164 /* Sub functions with one operand and one immediate */
1165 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1166 add_ca, compute_ca, compute_ov) \
1167 static void glue(gen_, name)(DisasContext *ctx) \
1168 { \
1169 TCGv t0 = tcg_const_tl(const_val); \
1170 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1171 cpu_gpr[rA(ctx->opcode)], t0, \
1172 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1173 tcg_temp_free(t0); \
1174 }
1175 /* subf subf. subfo subfo. */
1176 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1177 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1178 /* subfc subfc. subfco subfco. */
1179 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1180 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1181 /* subfe subfe. subfeo subfo. */
1182 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1183 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1184 /* subfme subfme. subfmeo subfmeo. */
1185 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1186 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1187 /* subfze subfze. subfzeo subfzeo.*/
1188 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1189 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1190
1191 /* subfic */
1192 static void gen_subfic(DisasContext *ctx)
1193 {
1194 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1195 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1196 c, 0, 1, 0, 0);
1197 tcg_temp_free(c);
1198 }
1199
1200 /* neg neg. nego nego. */
1201 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1202 {
1203 TCGv zero = tcg_const_tl(0);
1204 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1205 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1206 tcg_temp_free(zero);
1207 }
1208
1209 static void gen_neg(DisasContext *ctx)
1210 {
1211 gen_op_arith_neg(ctx, 0);
1212 }
1213
1214 static void gen_nego(DisasContext *ctx)
1215 {
1216 gen_op_arith_neg(ctx, 1);
1217 }
1218
1219 /*** Integer logical ***/
1220 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1221 static void glue(gen_, name)(DisasContext *ctx) \
1222 { \
1223 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1224 cpu_gpr[rB(ctx->opcode)]); \
1225 if (unlikely(Rc(ctx->opcode) != 0)) \
1226 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1227 }
1228
1229 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1230 static void glue(gen_, name)(DisasContext *ctx) \
1231 { \
1232 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1233 if (unlikely(Rc(ctx->opcode) != 0)) \
1234 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1235 }
1236
1237 /* and & and. */
1238 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1239 /* andc & andc. */
1240 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1241
1242 /* andi. */
1243 static void gen_andi_(DisasContext *ctx)
1244 {
1245 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1246 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1247 }
1248
1249 /* andis. */
1250 static void gen_andis_(DisasContext *ctx)
1251 {
1252 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1253 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1254 }
1255
1256 /* cntlzw */
1257 static void gen_cntlzw(DisasContext *ctx)
1258 {
1259 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1260 if (unlikely(Rc(ctx->opcode) != 0))
1261 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1262 }
1263 /* eqv & eqv. */
1264 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1265 /* extsb & extsb. */
1266 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1267 /* extsh & extsh. */
1268 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1269 /* nand & nand. */
1270 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1271 /* nor & nor. */
1272 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1273
1274 /* or & or. */
1275 static void gen_or(DisasContext *ctx)
1276 {
1277 int rs, ra, rb;
1278
1279 rs = rS(ctx->opcode);
1280 ra = rA(ctx->opcode);
1281 rb = rB(ctx->opcode);
1282 /* Optimisation for mr. ri case */
1283 if (rs != ra || rs != rb) {
1284 if (rs != rb)
1285 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1286 else
1287 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1288 if (unlikely(Rc(ctx->opcode) != 0))
1289 gen_set_Rc0(ctx, cpu_gpr[ra]);
1290 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1291 gen_set_Rc0(ctx, cpu_gpr[rs]);
1292 #if defined(TARGET_PPC64)
1293 } else {
1294 int prio = 0;
1295
1296 switch (rs) {
1297 case 1:
1298 /* Set process priority to low */
1299 prio = 2;
1300 break;
1301 case 6:
1302 /* Set process priority to medium-low */
1303 prio = 3;
1304 break;
1305 case 2:
1306 /* Set process priority to normal */
1307 prio = 4;
1308 break;
1309 #if !defined(CONFIG_USER_ONLY)
1310 case 31:
1311 if (ctx->mem_idx > 0) {
1312 /* Set process priority to very low */
1313 prio = 1;
1314 }
1315 break;
1316 case 5:
1317 if (ctx->mem_idx > 0) {
1318 /* Set process priority to medium-hight */
1319 prio = 5;
1320 }
1321 break;
1322 case 3:
1323 if (ctx->mem_idx > 0) {
1324 /* Set process priority to high */
1325 prio = 6;
1326 }
1327 break;
1328 case 7:
1329 if (ctx->mem_idx > 1) {
1330 /* Set process priority to very high */
1331 prio = 7;
1332 }
1333 break;
1334 #endif
1335 default:
1336 /* nop */
1337 break;
1338 }
1339 if (prio) {
1340 TCGv t0 = tcg_temp_new();
1341 gen_load_spr(t0, SPR_PPR);
1342 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1343 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1344 gen_store_spr(SPR_PPR, t0);
1345 tcg_temp_free(t0);
1346 }
1347 #endif
1348 }
1349 }
1350 /* orc & orc. */
1351 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1352
1353 /* xor & xor. */
1354 static void gen_xor(DisasContext *ctx)
1355 {
1356 /* Optimisation for "set to zero" case */
1357 if (rS(ctx->opcode) != rB(ctx->opcode))
1358 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1359 else
1360 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1361 if (unlikely(Rc(ctx->opcode) != 0))
1362 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1363 }
1364
1365 /* ori */
1366 static void gen_ori(DisasContext *ctx)
1367 {
1368 target_ulong uimm = UIMM(ctx->opcode);
1369
1370 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1371 /* NOP */
1372 /* XXX: should handle special NOPs for POWER series */
1373 return;
1374 }
1375 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1376 }
1377
1378 /* oris */
1379 static void gen_oris(DisasContext *ctx)
1380 {
1381 target_ulong uimm = UIMM(ctx->opcode);
1382
1383 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1384 /* NOP */
1385 return;
1386 }
1387 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1388 }
1389
1390 /* xori */
1391 static void gen_xori(DisasContext *ctx)
1392 {
1393 target_ulong uimm = UIMM(ctx->opcode);
1394
1395 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1396 /* NOP */
1397 return;
1398 }
1399 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1400 }
1401
1402 /* xoris */
1403 static void gen_xoris(DisasContext *ctx)
1404 {
1405 target_ulong uimm = UIMM(ctx->opcode);
1406
1407 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1408 /* NOP */
1409 return;
1410 }
1411 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1412 }
1413
1414 /* popcntb : PowerPC 2.03 specification */
1415 static void gen_popcntb(DisasContext *ctx)
1416 {
1417 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1418 }
1419
1420 static void gen_popcntw(DisasContext *ctx)
1421 {
1422 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1423 }
1424
1425 #if defined(TARGET_PPC64)
1426 /* popcntd: PowerPC 2.06 specification */
1427 static void gen_popcntd(DisasContext *ctx)
1428 {
1429 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1430 }
1431 #endif
1432
1433 #if defined(TARGET_PPC64)
1434 /* extsw & extsw. */
1435 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1436
1437 /* cntlzd */
1438 static void gen_cntlzd(DisasContext *ctx)
1439 {
1440 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1441 if (unlikely(Rc(ctx->opcode) != 0))
1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1443 }
1444 #endif
1445
1446 /*** Integer rotate ***/
1447
1448 /* rlwimi & rlwimi. */
1449 static void gen_rlwimi(DisasContext *ctx)
1450 {
1451 uint32_t mb, me, sh;
1452
1453 mb = MB(ctx->opcode);
1454 me = ME(ctx->opcode);
1455 sh = SH(ctx->opcode);
1456 if (likely(sh == 0 && mb == 0 && me == 31)) {
1457 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1458 } else {
1459 target_ulong mask;
1460 TCGv t1;
1461 TCGv t0 = tcg_temp_new();
1462 #if defined(TARGET_PPC64)
1463 TCGv_i32 t2 = tcg_temp_new_i32();
1464 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1465 tcg_gen_rotli_i32(t2, t2, sh);
1466 tcg_gen_extu_i32_i64(t0, t2);
1467 tcg_temp_free_i32(t2);
1468 #else
1469 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1470 #endif
1471 #if defined(TARGET_PPC64)
1472 mb += 32;
1473 me += 32;
1474 #endif
1475 mask = MASK(mb, me);
1476 t1 = tcg_temp_new();
1477 tcg_gen_andi_tl(t0, t0, mask);
1478 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1479 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1480 tcg_temp_free(t0);
1481 tcg_temp_free(t1);
1482 }
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485 }
1486
1487 /* rlwinm & rlwinm. */
1488 static void gen_rlwinm(DisasContext *ctx)
1489 {
1490 uint32_t mb, me, sh;
1491
1492 sh = SH(ctx->opcode);
1493 mb = MB(ctx->opcode);
1494 me = ME(ctx->opcode);
1495
1496 if (likely(mb == 0 && me == (31 - sh))) {
1497 if (likely(sh == 0)) {
1498 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1499 } else {
1500 TCGv t0 = tcg_temp_new();
1501 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1502 tcg_gen_shli_tl(t0, t0, sh);
1503 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1504 tcg_temp_free(t0);
1505 }
1506 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1507 TCGv t0 = tcg_temp_new();
1508 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1509 tcg_gen_shri_tl(t0, t0, mb);
1510 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1511 tcg_temp_free(t0);
1512 } else {
1513 TCGv t0 = tcg_temp_new();
1514 #if defined(TARGET_PPC64)
1515 TCGv_i32 t1 = tcg_temp_new_i32();
1516 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1517 tcg_gen_rotli_i32(t1, t1, sh);
1518 tcg_gen_extu_i32_i64(t0, t1);
1519 tcg_temp_free_i32(t1);
1520 #else
1521 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1522 #endif
1523 #if defined(TARGET_PPC64)
1524 mb += 32;
1525 me += 32;
1526 #endif
1527 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1528 tcg_temp_free(t0);
1529 }
1530 if (unlikely(Rc(ctx->opcode) != 0))
1531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1532 }
1533
1534 /* rlwnm & rlwnm. */
1535 static void gen_rlwnm(DisasContext *ctx)
1536 {
1537 uint32_t mb, me;
1538 TCGv t0;
1539 #if defined(TARGET_PPC64)
1540 TCGv_i32 t1, t2;
1541 #endif
1542
1543 mb = MB(ctx->opcode);
1544 me = ME(ctx->opcode);
1545 t0 = tcg_temp_new();
1546 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1547 #if defined(TARGET_PPC64)
1548 t1 = tcg_temp_new_i32();
1549 t2 = tcg_temp_new_i32();
1550 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1551 tcg_gen_trunc_i64_i32(t2, t0);
1552 tcg_gen_rotl_i32(t1, t1, t2);
1553 tcg_gen_extu_i32_i64(t0, t1);
1554 tcg_temp_free_i32(t1);
1555 tcg_temp_free_i32(t2);
1556 #else
1557 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1558 #endif
1559 if (unlikely(mb != 0 || me != 31)) {
1560 #if defined(TARGET_PPC64)
1561 mb += 32;
1562 me += 32;
1563 #endif
1564 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1565 } else {
1566 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1567 }
1568 tcg_temp_free(t0);
1569 if (unlikely(Rc(ctx->opcode) != 0))
1570 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1571 }
1572
1573 #if defined(TARGET_PPC64)
1574 #define GEN_PPC64_R2(name, opc1, opc2) \
1575 static void glue(gen_, name##0)(DisasContext *ctx) \
1576 { \
1577 gen_##name(ctx, 0); \
1578 } \
1579 \
1580 static void glue(gen_, name##1)(DisasContext *ctx) \
1581 { \
1582 gen_##name(ctx, 1); \
1583 }
1584 #define GEN_PPC64_R4(name, opc1, opc2) \
1585 static void glue(gen_, name##0)(DisasContext *ctx) \
1586 { \
1587 gen_##name(ctx, 0, 0); \
1588 } \
1589 \
1590 static void glue(gen_, name##1)(DisasContext *ctx) \
1591 { \
1592 gen_##name(ctx, 0, 1); \
1593 } \
1594 \
1595 static void glue(gen_, name##2)(DisasContext *ctx) \
1596 { \
1597 gen_##name(ctx, 1, 0); \
1598 } \
1599 \
1600 static void glue(gen_, name##3)(DisasContext *ctx) \
1601 { \
1602 gen_##name(ctx, 1, 1); \
1603 }
1604
1605 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1606 uint32_t sh)
1607 {
1608 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1609 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1610 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1611 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1612 } else {
1613 TCGv t0 = tcg_temp_new();
1614 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1615 if (likely(mb == 0 && me == 63)) {
1616 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1617 } else {
1618 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1619 }
1620 tcg_temp_free(t0);
1621 }
1622 if (unlikely(Rc(ctx->opcode) != 0))
1623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1624 }
1625 /* rldicl - rldicl. */
1626 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1627 {
1628 uint32_t sh, mb;
1629
1630 sh = SH(ctx->opcode) | (shn << 5);
1631 mb = MB(ctx->opcode) | (mbn << 5);
1632 gen_rldinm(ctx, mb, 63, sh);
1633 }
1634 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1635 /* rldicr - rldicr. */
1636 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1637 {
1638 uint32_t sh, me;
1639
1640 sh = SH(ctx->opcode) | (shn << 5);
1641 me = MB(ctx->opcode) | (men << 5);
1642 gen_rldinm(ctx, 0, me, sh);
1643 }
1644 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1645 /* rldic - rldic. */
1646 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1647 {
1648 uint32_t sh, mb;
1649
1650 sh = SH(ctx->opcode) | (shn << 5);
1651 mb = MB(ctx->opcode) | (mbn << 5);
1652 gen_rldinm(ctx, mb, 63 - sh, sh);
1653 }
1654 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1655
1656 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1657 {
1658 TCGv t0;
1659
1660 mb = MB(ctx->opcode);
1661 me = ME(ctx->opcode);
1662 t0 = tcg_temp_new();
1663 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1664 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1665 if (unlikely(mb != 0 || me != 63)) {
1666 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1667 } else {
1668 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1669 }
1670 tcg_temp_free(t0);
1671 if (unlikely(Rc(ctx->opcode) != 0))
1672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1673 }
1674
1675 /* rldcl - rldcl. */
1676 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1677 {
1678 uint32_t mb;
1679
1680 mb = MB(ctx->opcode) | (mbn << 5);
1681 gen_rldnm(ctx, mb, 63);
1682 }
1683 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1684 /* rldcr - rldcr. */
1685 static inline void gen_rldcr(DisasContext *ctx, int men)
1686 {
1687 uint32_t me;
1688
1689 me = MB(ctx->opcode) | (men << 5);
1690 gen_rldnm(ctx, 0, me);
1691 }
1692 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1693 /* rldimi - rldimi. */
1694 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1695 {
1696 uint32_t sh, mb, me;
1697
1698 sh = SH(ctx->opcode) | (shn << 5);
1699 mb = MB(ctx->opcode) | (mbn << 5);
1700 me = 63 - sh;
1701 if (unlikely(sh == 0 && mb == 0)) {
1702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1703 } else {
1704 TCGv t0, t1;
1705 target_ulong mask;
1706
1707 t0 = tcg_temp_new();
1708 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1709 t1 = tcg_temp_new();
1710 mask = MASK(mb, me);
1711 tcg_gen_andi_tl(t0, t0, mask);
1712 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1713 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1714 tcg_temp_free(t0);
1715 tcg_temp_free(t1);
1716 }
1717 if (unlikely(Rc(ctx->opcode) != 0))
1718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1719 }
1720 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1721 #endif
1722
1723 /*** Integer shift ***/
1724
1725 /* slw & slw. */
1726 static void gen_slw(DisasContext *ctx)
1727 {
1728 TCGv t0, t1;
1729
1730 t0 = tcg_temp_new();
1731 /* AND rS with a mask that is 0 when rB >= 0x20 */
1732 #if defined(TARGET_PPC64)
1733 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1734 tcg_gen_sari_tl(t0, t0, 0x3f);
1735 #else
1736 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1737 tcg_gen_sari_tl(t0, t0, 0x1f);
1738 #endif
1739 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1740 t1 = tcg_temp_new();
1741 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1742 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1743 tcg_temp_free(t1);
1744 tcg_temp_free(t0);
1745 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1746 if (unlikely(Rc(ctx->opcode) != 0))
1747 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1748 }
1749
1750 /* sraw & sraw. */
1751 static void gen_sraw(DisasContext *ctx)
1752 {
1753 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1754 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1755 if (unlikely(Rc(ctx->opcode) != 0))
1756 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1757 }
1758
1759 /* srawi & srawi. */
1760 static void gen_srawi(DisasContext *ctx)
1761 {
1762 int sh = SH(ctx->opcode);
1763 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1764 TCGv src = cpu_gpr[rS(ctx->opcode)];
1765 if (sh == 0) {
1766 tcg_gen_mov_tl(dst, src);
1767 tcg_gen_movi_tl(cpu_ca, 0);
1768 } else {
1769 TCGv t0;
1770 tcg_gen_ext32s_tl(dst, src);
1771 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1772 t0 = tcg_temp_new();
1773 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1774 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1775 tcg_temp_free(t0);
1776 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1777 tcg_gen_sari_tl(dst, dst, sh);
1778 }
1779 if (unlikely(Rc(ctx->opcode) != 0)) {
1780 gen_set_Rc0(ctx, dst);
1781 }
1782 }
1783
1784 /* srw & srw. */
1785 static void gen_srw(DisasContext *ctx)
1786 {
1787 TCGv t0, t1;
1788
1789 t0 = tcg_temp_new();
1790 /* AND rS with a mask that is 0 when rB >= 0x20 */
1791 #if defined(TARGET_PPC64)
1792 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1793 tcg_gen_sari_tl(t0, t0, 0x3f);
1794 #else
1795 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1796 tcg_gen_sari_tl(t0, t0, 0x1f);
1797 #endif
1798 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1799 tcg_gen_ext32u_tl(t0, t0);
1800 t1 = tcg_temp_new();
1801 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1802 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1803 tcg_temp_free(t1);
1804 tcg_temp_free(t0);
1805 if (unlikely(Rc(ctx->opcode) != 0))
1806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1807 }
1808
1809 #if defined(TARGET_PPC64)
1810 /* sld & sld. */
1811 static void gen_sld(DisasContext *ctx)
1812 {
1813 TCGv t0, t1;
1814
1815 t0 = tcg_temp_new();
1816 /* AND rS with a mask that is 0 when rB >= 0x40 */
1817 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1818 tcg_gen_sari_tl(t0, t0, 0x3f);
1819 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1820 t1 = tcg_temp_new();
1821 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1822 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1823 tcg_temp_free(t1);
1824 tcg_temp_free(t0);
1825 if (unlikely(Rc(ctx->opcode) != 0))
1826 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1827 }
1828
1829 /* srad & srad. */
1830 static void gen_srad(DisasContext *ctx)
1831 {
1832 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1833 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1834 if (unlikely(Rc(ctx->opcode) != 0))
1835 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1836 }
1837 /* sradi & sradi. */
1838 static inline void gen_sradi(DisasContext *ctx, int n)
1839 {
1840 int sh = SH(ctx->opcode) + (n << 5);
1841 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1842 TCGv src = cpu_gpr[rS(ctx->opcode)];
1843 if (sh == 0) {
1844 tcg_gen_mov_tl(dst, src);
1845 tcg_gen_movi_tl(cpu_ca, 0);
1846 } else {
1847 TCGv t0;
1848 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1849 t0 = tcg_temp_new();
1850 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1851 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1852 tcg_temp_free(t0);
1853 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1854 tcg_gen_sari_tl(dst, src, sh);
1855 }
1856 if (unlikely(Rc(ctx->opcode) != 0)) {
1857 gen_set_Rc0(ctx, dst);
1858 }
1859 }
1860
1861 static void gen_sradi0(DisasContext *ctx)
1862 {
1863 gen_sradi(ctx, 0);
1864 }
1865
1866 static void gen_sradi1(DisasContext *ctx)
1867 {
1868 gen_sradi(ctx, 1);
1869 }
1870
1871 /* srd & srd. */
1872 static void gen_srd(DisasContext *ctx)
1873 {
1874 TCGv t0, t1;
1875
1876 t0 = tcg_temp_new();
1877 /* AND rS with a mask that is 0 when rB >= 0x40 */
1878 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1879 tcg_gen_sari_tl(t0, t0, 0x3f);
1880 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1881 t1 = tcg_temp_new();
1882 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1883 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1884 tcg_temp_free(t1);
1885 tcg_temp_free(t0);
1886 if (unlikely(Rc(ctx->opcode) != 0))
1887 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1888 }
1889 #endif
1890
1891 /*** Floating-Point arithmetic ***/
1892 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1893 static void gen_f##name(DisasContext *ctx) \
1894 { \
1895 if (unlikely(!ctx->fpu_enabled)) { \
1896 gen_exception(ctx, POWERPC_EXCP_FPU); \
1897 return; \
1898 } \
1899 /* NIP cannot be restored if the memory exception comes from an helper */ \
1900 gen_update_nip(ctx, ctx->nip - 4); \
1901 gen_reset_fpstatus(); \
1902 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1903 cpu_fpr[rA(ctx->opcode)], \
1904 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1905 if (isfloat) { \
1906 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1907 cpu_fpr[rD(ctx->opcode)]); \
1908 } \
1909 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1910 Rc(ctx->opcode) != 0); \
1911 }
1912
1913 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1914 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1915 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1916
1917 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1918 static void gen_f##name(DisasContext *ctx) \
1919 { \
1920 if (unlikely(!ctx->fpu_enabled)) { \
1921 gen_exception(ctx, POWERPC_EXCP_FPU); \
1922 return; \
1923 } \
1924 /* NIP cannot be restored if the memory exception comes from an helper */ \
1925 gen_update_nip(ctx, ctx->nip - 4); \
1926 gen_reset_fpstatus(); \
1927 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1928 cpu_fpr[rA(ctx->opcode)], \
1929 cpu_fpr[rB(ctx->opcode)]); \
1930 if (isfloat) { \
1931 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1932 cpu_fpr[rD(ctx->opcode)]); \
1933 } \
1934 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1935 set_fprf, Rc(ctx->opcode) != 0); \
1936 }
1937 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1938 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1939 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1940
1941 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1942 static void gen_f##name(DisasContext *ctx) \
1943 { \
1944 if (unlikely(!ctx->fpu_enabled)) { \
1945 gen_exception(ctx, POWERPC_EXCP_FPU); \
1946 return; \
1947 } \
1948 /* NIP cannot be restored if the memory exception comes from an helper */ \
1949 gen_update_nip(ctx, ctx->nip - 4); \
1950 gen_reset_fpstatus(); \
1951 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1952 cpu_fpr[rA(ctx->opcode)], \
1953 cpu_fpr[rC(ctx->opcode)]); \
1954 if (isfloat) { \
1955 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1956 cpu_fpr[rD(ctx->opcode)]); \
1957 } \
1958 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1959 set_fprf, Rc(ctx->opcode) != 0); \
1960 }
1961 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1962 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1963 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1964
1965 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1966 static void gen_f##name(DisasContext *ctx) \
1967 { \
1968 if (unlikely(!ctx->fpu_enabled)) { \
1969 gen_exception(ctx, POWERPC_EXCP_FPU); \
1970 return; \
1971 } \
1972 /* NIP cannot be restored if the memory exception comes from an helper */ \
1973 gen_update_nip(ctx, ctx->nip - 4); \
1974 gen_reset_fpstatus(); \
1975 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1976 cpu_fpr[rB(ctx->opcode)]); \
1977 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1978 set_fprf, Rc(ctx->opcode) != 0); \
1979 }
1980
1981 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1982 static void gen_f##name(DisasContext *ctx) \
1983 { \
1984 if (unlikely(!ctx->fpu_enabled)) { \
1985 gen_exception(ctx, POWERPC_EXCP_FPU); \
1986 return; \
1987 } \
1988 /* NIP cannot be restored if the memory exception comes from an helper */ \
1989 gen_update_nip(ctx, ctx->nip - 4); \
1990 gen_reset_fpstatus(); \
1991 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1992 cpu_fpr[rB(ctx->opcode)]); \
1993 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1994 set_fprf, Rc(ctx->opcode) != 0); \
1995 }
1996
1997 /* fadd - fadds */
1998 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1999 /* fdiv - fdivs */
2000 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2001 /* fmul - fmuls */
2002 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2003
2004 /* fre */
2005 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2006
2007 /* fres */
2008 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2009
2010 /* frsqrte */
2011 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2012
2013 /* frsqrtes */
2014 static void gen_frsqrtes(DisasContext *ctx)
2015 {
2016 if (unlikely(!ctx->fpu_enabled)) {
2017 gen_exception(ctx, POWERPC_EXCP_FPU);
2018 return;
2019 }
2020 /* NIP cannot be restored if the memory exception comes from an helper */
2021 gen_update_nip(ctx, ctx->nip - 4);
2022 gen_reset_fpstatus();
2023 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2024 cpu_fpr[rB(ctx->opcode)]);
2025 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2026 cpu_fpr[rD(ctx->opcode)]);
2027 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2028 }
2029
2030 /* fsel */
2031 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2032 /* fsub - fsubs */
2033 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2034 /* Optional: */
2035
2036 /* fsqrt */
2037 static void gen_fsqrt(DisasContext *ctx)
2038 {
2039 if (unlikely(!ctx->fpu_enabled)) {
2040 gen_exception(ctx, POWERPC_EXCP_FPU);
2041 return;
2042 }
2043 /* NIP cannot be restored if the memory exception comes from an helper */
2044 gen_update_nip(ctx, ctx->nip - 4);
2045 gen_reset_fpstatus();
2046 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2047 cpu_fpr[rB(ctx->opcode)]);
2048 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2049 }
2050
2051 static void gen_fsqrts(DisasContext *ctx)
2052 {
2053 if (unlikely(!ctx->fpu_enabled)) {
2054 gen_exception(ctx, POWERPC_EXCP_FPU);
2055 return;
2056 }
2057 /* NIP cannot be restored if the memory exception comes from an helper */
2058 gen_update_nip(ctx, ctx->nip - 4);
2059 gen_reset_fpstatus();
2060 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2061 cpu_fpr[rB(ctx->opcode)]);
2062 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2063 cpu_fpr[rD(ctx->opcode)]);
2064 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2065 }
2066
2067 /*** Floating-Point multiply-and-add ***/
2068 /* fmadd - fmadds */
2069 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2070 /* fmsub - fmsubs */
2071 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2072 /* fnmadd - fnmadds */
2073 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2074 /* fnmsub - fnmsubs */
2075 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2076
2077 /*** Floating-Point round & convert ***/
2078 /* fctiw */
2079 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2080 /* fctiwz */
2081 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2082 /* frsp */
2083 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2084 #if defined(TARGET_PPC64)
2085 /* fcfid */
2086 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2087 /* fctid */
2088 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2089 /* fctidz */
2090 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2091 #endif
2092
2093 /* frin */
2094 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2095 /* friz */
2096 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2097 /* frip */
2098 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2099 /* frim */
2100 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2101
2102 /*** Floating-Point compare ***/
2103
2104 /* fcmpo */
2105 static void gen_fcmpo(DisasContext *ctx)
2106 {
2107 TCGv_i32 crf;
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 crf = tcg_const_i32(crfD(ctx->opcode));
2116 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2117 cpu_fpr[rB(ctx->opcode)], crf);
2118 tcg_temp_free_i32(crf);
2119 gen_helper_float_check_status(cpu_env);
2120 }
2121
2122 /* fcmpu */
2123 static void gen_fcmpu(DisasContext *ctx)
2124 {
2125 TCGv_i32 crf;
2126 if (unlikely(!ctx->fpu_enabled)) {
2127 gen_exception(ctx, POWERPC_EXCP_FPU);
2128 return;
2129 }
2130 /* NIP cannot be restored if the memory exception comes from an helper */
2131 gen_update_nip(ctx, ctx->nip - 4);
2132 gen_reset_fpstatus();
2133 crf = tcg_const_i32(crfD(ctx->opcode));
2134 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2135 cpu_fpr[rB(ctx->opcode)], crf);
2136 tcg_temp_free_i32(crf);
2137 gen_helper_float_check_status(cpu_env);
2138 }
2139
2140 /*** Floating-point move ***/
2141 /* fabs */
2142 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2143 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2144
2145 /* fmr - fmr. */
2146 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2147 static void gen_fmr(DisasContext *ctx)
2148 {
2149 if (unlikely(!ctx->fpu_enabled)) {
2150 gen_exception(ctx, POWERPC_EXCP_FPU);
2151 return;
2152 }
2153 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2154 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2155 }
2156
2157 /* fnabs */
2158 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2159 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2160 /* fneg */
2161 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2162 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2163
2164 /*** Floating-Point status & ctrl register ***/
2165
2166 /* mcrfs */
2167 static void gen_mcrfs(DisasContext *ctx)
2168 {
2169 TCGv tmp = tcg_temp_new();
2170 int bfa;
2171
2172 if (unlikely(!ctx->fpu_enabled)) {
2173 gen_exception(ctx, POWERPC_EXCP_FPU);
2174 return;
2175 }
2176 bfa = 4 * (7 - crfS(ctx->opcode));
2177 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2178 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2179 tcg_temp_free(tmp);
2180 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2181 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2182 }
2183
2184 /* mffs */
2185 static void gen_mffs(DisasContext *ctx)
2186 {
2187 if (unlikely(!ctx->fpu_enabled)) {
2188 gen_exception(ctx, POWERPC_EXCP_FPU);
2189 return;
2190 }
2191 gen_reset_fpstatus();
2192 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2193 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2194 }
2195
2196 /* mtfsb0 */
2197 static void gen_mtfsb0(DisasContext *ctx)
2198 {
2199 uint8_t crb;
2200
2201 if (unlikely(!ctx->fpu_enabled)) {
2202 gen_exception(ctx, POWERPC_EXCP_FPU);
2203 return;
2204 }
2205 crb = 31 - crbD(ctx->opcode);
2206 gen_reset_fpstatus();
2207 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2208 TCGv_i32 t0;
2209 /* NIP cannot be restored if the memory exception comes from an helper */
2210 gen_update_nip(ctx, ctx->nip - 4);
2211 t0 = tcg_const_i32(crb);
2212 gen_helper_fpscr_clrbit(cpu_env, t0);
2213 tcg_temp_free_i32(t0);
2214 }
2215 if (unlikely(Rc(ctx->opcode) != 0)) {
2216 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2217 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2218 }
2219 }
2220
2221 /* mtfsb1 */
2222 static void gen_mtfsb1(DisasContext *ctx)
2223 {
2224 uint8_t crb;
2225
2226 if (unlikely(!ctx->fpu_enabled)) {
2227 gen_exception(ctx, POWERPC_EXCP_FPU);
2228 return;
2229 }
2230 crb = 31 - crbD(ctx->opcode);
2231 gen_reset_fpstatus();
2232 /* XXX: we pretend we can only do IEEE floating-point computations */
2233 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2234 TCGv_i32 t0;
2235 /* NIP cannot be restored if the memory exception comes from an helper */
2236 gen_update_nip(ctx, ctx->nip - 4);
2237 t0 = tcg_const_i32(crb);
2238 gen_helper_fpscr_setbit(cpu_env, t0);
2239 tcg_temp_free_i32(t0);
2240 }
2241 if (unlikely(Rc(ctx->opcode) != 0)) {
2242 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2243 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2244 }
2245 /* We can raise a differed exception */
2246 gen_helper_float_check_status(cpu_env);
2247 }
2248
2249 /* mtfsf */
2250 static void gen_mtfsf(DisasContext *ctx)
2251 {
2252 TCGv_i32 t0;
2253 int L = ctx->opcode & 0x02000000;
2254
2255 if (unlikely(!ctx->fpu_enabled)) {
2256 gen_exception(ctx, POWERPC_EXCP_FPU);
2257 return;
2258 }
2259 /* NIP cannot be restored if the memory exception comes from an helper */
2260 gen_update_nip(ctx, ctx->nip - 4);
2261 gen_reset_fpstatus();
2262 if (L)
2263 t0 = tcg_const_i32(0xff);
2264 else
2265 t0 = tcg_const_i32(FM(ctx->opcode));
2266 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2267 tcg_temp_free_i32(t0);
2268 if (unlikely(Rc(ctx->opcode) != 0)) {
2269 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2270 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2271 }
2272 /* We can raise a differed exception */
2273 gen_helper_float_check_status(cpu_env);
2274 }
2275
2276 /* mtfsfi */
2277 static void gen_mtfsfi(DisasContext *ctx)
2278 {
2279 int bf, sh;
2280 TCGv_i64 t0;
2281 TCGv_i32 t1;
2282
2283 if (unlikely(!ctx->fpu_enabled)) {
2284 gen_exception(ctx, POWERPC_EXCP_FPU);
2285 return;
2286 }
2287 bf = crbD(ctx->opcode) >> 2;
2288 sh = 7 - bf;
2289 /* NIP cannot be restored if the memory exception comes from an helper */
2290 gen_update_nip(ctx, ctx->nip - 4);
2291 gen_reset_fpstatus();
2292 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2293 t1 = tcg_const_i32(1 << sh);
2294 gen_helper_store_fpscr(cpu_env, t0, t1);
2295 tcg_temp_free_i64(t0);
2296 tcg_temp_free_i32(t1);
2297 if (unlikely(Rc(ctx->opcode) != 0)) {
2298 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2299 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2300 }
2301 /* We can raise a differed exception */
2302 gen_helper_float_check_status(cpu_env);
2303 }
2304
2305 /*** Addressing modes ***/
2306 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2307 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2308 target_long maskl)
2309 {
2310 target_long simm = SIMM(ctx->opcode);
2311
2312 simm &= ~maskl;
2313 if (rA(ctx->opcode) == 0) {
2314 #if defined(TARGET_PPC64)
2315 if (!ctx->sf_mode) {
2316 tcg_gen_movi_tl(EA, (uint32_t)simm);
2317 } else
2318 #endif
2319 tcg_gen_movi_tl(EA, simm);
2320 } else if (likely(simm != 0)) {
2321 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2322 #if defined(TARGET_PPC64)
2323 if (!ctx->sf_mode) {
2324 tcg_gen_ext32u_tl(EA, EA);
2325 }
2326 #endif
2327 } else {
2328 #if defined(TARGET_PPC64)
2329 if (!ctx->sf_mode) {
2330 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2331 } else
2332 #endif
2333 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2334 }
2335 }
2336
2337 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2338 {
2339 if (rA(ctx->opcode) == 0) {
2340 #if defined(TARGET_PPC64)
2341 if (!ctx->sf_mode) {
2342 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2343 } else
2344 #endif
2345 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2346 } else {
2347 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2348 #if defined(TARGET_PPC64)
2349 if (!ctx->sf_mode) {
2350 tcg_gen_ext32u_tl(EA, EA);
2351 }
2352 #endif
2353 }
2354 }
2355
2356 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2357 {
2358 if (rA(ctx->opcode) == 0) {
2359 tcg_gen_movi_tl(EA, 0);
2360 } else {
2361 #if defined(TARGET_PPC64)
2362 if (!ctx->sf_mode) {
2363 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2364 } else
2365 #endif
2366 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2367 }
2368 }
2369
2370 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2371 target_long val)
2372 {
2373 tcg_gen_addi_tl(ret, arg1, val);
2374 #if defined(TARGET_PPC64)
2375 if (!ctx->sf_mode) {
2376 tcg_gen_ext32u_tl(ret, ret);
2377 }
2378 #endif
2379 }
2380
2381 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2382 {
2383 int l1 = gen_new_label();
2384 TCGv t0 = tcg_temp_new();
2385 TCGv_i32 t1, t2;
2386 /* NIP cannot be restored if the memory exception comes from an helper */
2387 gen_update_nip(ctx, ctx->nip - 4);
2388 tcg_gen_andi_tl(t0, EA, mask);
2389 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2390 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2391 t2 = tcg_const_i32(0);
2392 gen_helper_raise_exception_err(cpu_env, t1, t2);
2393 tcg_temp_free_i32(t1);
2394 tcg_temp_free_i32(t2);
2395 gen_set_label(l1);
2396 tcg_temp_free(t0);
2397 }
2398
2399 /*** Integer load ***/
2400 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2401 {
2402 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2403 }
2404
2405 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2406 {
2407 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2408 }
2409
2410 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2411 {
2412 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2413 if (unlikely(ctx->le_mode)) {
2414 tcg_gen_bswap16_tl(arg1, arg1);
2415 }
2416 }
2417
2418 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2419 {
2420 if (unlikely(ctx->le_mode)) {
2421 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2422 tcg_gen_bswap16_tl(arg1, arg1);
2423 tcg_gen_ext16s_tl(arg1, arg1);
2424 } else {
2425 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2426 }
2427 }
2428
2429 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2430 {
2431 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2432 if (unlikely(ctx->le_mode)) {
2433 tcg_gen_bswap32_tl(arg1, arg1);
2434 }
2435 }
2436
2437 #if defined(TARGET_PPC64)
2438 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2439 {
2440 if (unlikely(ctx->le_mode)) {
2441 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2442 tcg_gen_bswap32_tl(arg1, arg1);
2443 tcg_gen_ext32s_tl(arg1, arg1);
2444 } else
2445 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2446 }
2447 #endif
2448
2449 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2450 {
2451 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2452 if (unlikely(ctx->le_mode)) {
2453 tcg_gen_bswap64_i64(arg1, arg1);
2454 }
2455 }
2456
2457 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2458 {
2459 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2460 }
2461
2462 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2463 {
2464 if (unlikely(ctx->le_mode)) {
2465 TCGv t0 = tcg_temp_new();
2466 tcg_gen_ext16u_tl(t0, arg1);
2467 tcg_gen_bswap16_tl(t0, t0);
2468 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2469 tcg_temp_free(t0);
2470 } else {
2471 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2472 }
2473 }
2474
2475 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2476 {
2477 if (unlikely(ctx->le_mode)) {
2478 TCGv t0 = tcg_temp_new();
2479 tcg_gen_ext32u_tl(t0, arg1);
2480 tcg_gen_bswap32_tl(t0, t0);
2481 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2482 tcg_temp_free(t0);
2483 } else {
2484 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2485 }
2486 }
2487
2488 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2489 {
2490 if (unlikely(ctx->le_mode)) {
2491 TCGv_i64 t0 = tcg_temp_new_i64();
2492 tcg_gen_bswap64_i64(t0, arg1);
2493 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2494 tcg_temp_free_i64(t0);
2495 } else
2496 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2497 }
2498
2499 #define GEN_LD(name, ldop, opc, type) \
2500 static void glue(gen_, name)(DisasContext *ctx) \
2501 { \
2502 TCGv EA; \
2503 gen_set_access_type(ctx, ACCESS_INT); \
2504 EA = tcg_temp_new(); \
2505 gen_addr_imm_index(ctx, EA, 0); \
2506 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2507 tcg_temp_free(EA); \
2508 }
2509
2510 #define GEN_LDU(name, ldop, opc, type) \
2511 static void glue(gen_, name##u)(DisasContext *ctx) \
2512 { \
2513 TCGv EA; \
2514 if (unlikely(rA(ctx->opcode) == 0 || \
2515 rA(ctx->opcode) == rD(ctx->opcode))) { \
2516 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2517 return; \
2518 } \
2519 gen_set_access_type(ctx, ACCESS_INT); \
2520 EA = tcg_temp_new(); \
2521 if (type == PPC_64B) \
2522 gen_addr_imm_index(ctx, EA, 0x03); \
2523 else \
2524 gen_addr_imm_index(ctx, EA, 0); \
2525 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2526 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2527 tcg_temp_free(EA); \
2528 }
2529
2530 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2531 static void glue(gen_, name##ux)(DisasContext *ctx) \
2532 { \
2533 TCGv EA; \
2534 if (unlikely(rA(ctx->opcode) == 0 || \
2535 rA(ctx->opcode) == rD(ctx->opcode))) { \
2536 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2537 return; \
2538 } \
2539 gen_set_access_type(ctx, ACCESS_INT); \
2540 EA = tcg_temp_new(); \
2541 gen_addr_reg_index(ctx, EA); \
2542 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2543 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2544 tcg_temp_free(EA); \
2545 }
2546
2547 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2548 static void glue(gen_, name##x)(DisasContext *ctx) \
2549 { \
2550 TCGv EA; \
2551 gen_set_access_type(ctx, ACCESS_INT); \
2552 EA = tcg_temp_new(); \
2553 gen_addr_reg_index(ctx, EA); \
2554 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2555 tcg_temp_free(EA); \
2556 }
2557 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2558 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2559
2560 #define GEN_LDS(name, ldop, op, type) \
2561 GEN_LD(name, ldop, op | 0x20, type); \
2562 GEN_LDU(name, ldop, op | 0x21, type); \
2563 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2564 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2565
2566 /* lbz lbzu lbzux lbzx */
2567 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2568 /* lha lhau lhaux lhax */
2569 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2570 /* lhz lhzu lhzux lhzx */
2571 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2572 /* lwz lwzu lwzux lwzx */
2573 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2574 #if defined(TARGET_PPC64)
2575 /* lwaux */
2576 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2577 /* lwax */
2578 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2579 /* ldux */
2580 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2581 /* ldx */
2582 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2583
2584 static void gen_ld(DisasContext *ctx)
2585 {
2586 TCGv EA;
2587 if (Rc(ctx->opcode)) {
2588 if (unlikely(rA(ctx->opcode) == 0 ||
2589 rA(ctx->opcode) == rD(ctx->opcode))) {
2590 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2591 return;
2592 }
2593 }
2594 gen_set_access_type(ctx, ACCESS_INT);
2595 EA = tcg_temp_new();
2596 gen_addr_imm_index(ctx, EA, 0x03);
2597 if (ctx->opcode & 0x02) {
2598 /* lwa (lwau is undefined) */
2599 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2600 } else {
2601 /* ld - ldu */
2602 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2603 }
2604 if (Rc(ctx->opcode))
2605 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2606 tcg_temp_free(EA);
2607 }
2608
2609 /* lq */
2610 static void gen_lq(DisasContext *ctx)
2611 {
2612 #if defined(CONFIG_USER_ONLY)
2613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2614 #else
2615 int ra, rd;
2616 TCGv EA;
2617
2618 /* Restore CPU state */
2619 if (unlikely(ctx->mem_idx == 0)) {
2620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2621 return;
2622 }
2623 ra = rA(ctx->opcode);
2624 rd = rD(ctx->opcode);
2625 if (unlikely((rd & 1) || rd == ra)) {
2626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2627 return;
2628 }
2629 if (unlikely(ctx->le_mode)) {
2630 /* Little-endian mode is not handled */
2631 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2632 return;
2633 }
2634 gen_set_access_type(ctx, ACCESS_INT);
2635 EA = tcg_temp_new();
2636 gen_addr_imm_index(ctx, EA, 0x0F);
2637 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2638 gen_addr_add(ctx, EA, EA, 8);
2639 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2640 tcg_temp_free(EA);
2641 #endif
2642 }
2643 #endif
2644
2645 /*** Integer store ***/
2646 #define GEN_ST(name, stop, opc, type) \
2647 static void glue(gen_, name)(DisasContext *ctx) \
2648 { \
2649 TCGv EA; \
2650 gen_set_access_type(ctx, ACCESS_INT); \
2651 EA = tcg_temp_new(); \
2652 gen_addr_imm_index(ctx, EA, 0); \
2653 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2654 tcg_temp_free(EA); \
2655 }
2656
2657 #define GEN_STU(name, stop, opc, type) \
2658 static void glue(gen_, stop##u)(DisasContext *ctx) \
2659 { \
2660 TCGv EA; \
2661 if (unlikely(rA(ctx->opcode) == 0)) { \
2662 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2663 return; \
2664 } \
2665 gen_set_access_type(ctx, ACCESS_INT); \
2666 EA = tcg_temp_new(); \
2667 if (type == PPC_64B) \
2668 gen_addr_imm_index(ctx, EA, 0x03); \
2669 else \
2670 gen_addr_imm_index(ctx, EA, 0); \
2671 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2672 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2673 tcg_temp_free(EA); \
2674 }
2675
2676 #define GEN_STUX(name, stop, opc2, opc3, type) \
2677 static void glue(gen_, name##ux)(DisasContext *ctx) \
2678 { \
2679 TCGv EA; \
2680 if (unlikely(rA(ctx->opcode) == 0)) { \
2681 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2682 return; \
2683 } \
2684 gen_set_access_type(ctx, ACCESS_INT); \
2685 EA = tcg_temp_new(); \
2686 gen_addr_reg_index(ctx, EA); \
2687 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2688 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2689 tcg_temp_free(EA); \
2690 }
2691
2692 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2693 static void glue(gen_, name##x)(DisasContext *ctx) \
2694 { \
2695 TCGv EA; \
2696 gen_set_access_type(ctx, ACCESS_INT); \
2697 EA = tcg_temp_new(); \
2698 gen_addr_reg_index(ctx, EA); \
2699 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2700 tcg_temp_free(EA); \
2701 }
2702 #define GEN_STX(name, stop, opc2, opc3, type) \
2703 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2704
2705 #define GEN_STS(name, stop, op, type) \
2706 GEN_ST(name, stop, op | 0x20, type); \
2707 GEN_STU(name, stop, op | 0x21, type); \
2708 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2709 GEN_STX(name, stop, 0x17, op | 0x00, type)
2710
2711 /* stb stbu stbux stbx */
2712 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2713 /* sth sthu sthux sthx */
2714 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2715 /* stw stwu stwux stwx */
2716 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2717 #if defined(TARGET_PPC64)
2718 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2719 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2720
2721 static void gen_std(DisasContext *ctx)
2722 {
2723 int rs;
2724 TCGv EA;
2725
2726 rs = rS(ctx->opcode);
2727 if ((ctx->opcode & 0x3) == 0x2) {
2728 #if defined(CONFIG_USER_ONLY)
2729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2730 #else
2731 /* stq */
2732 if (unlikely(ctx->mem_idx == 0)) {
2733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2734 return;
2735 }
2736 if (unlikely(rs & 1)) {
2737 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2738 return;
2739 }
2740 if (unlikely(ctx->le_mode)) {
2741 /* Little-endian mode is not handled */
2742 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2743 return;
2744 }
2745 gen_set_access_type(ctx, ACCESS_INT);
2746 EA = tcg_temp_new();
2747 gen_addr_imm_index(ctx, EA, 0x03);
2748 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2749 gen_addr_add(ctx, EA, EA, 8);
2750 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2751 tcg_temp_free(EA);
2752 #endif
2753 } else {
2754 /* std / stdu */
2755 if (Rc(ctx->opcode)) {
2756 if (unlikely(rA(ctx->opcode) == 0)) {
2757 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2758 return;
2759 }
2760 }
2761 gen_set_access_type(ctx, ACCESS_INT);
2762 EA = tcg_temp_new();
2763 gen_addr_imm_index(ctx, EA, 0x03);
2764 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2765 if (Rc(ctx->opcode))
2766 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2767 tcg_temp_free(EA);
2768 }
2769 }
2770 #endif
2771 /*** Integer load and store with byte reverse ***/
2772 /* lhbrx */
2773 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2774 {
2775 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2776 if (likely(!ctx->le_mode)) {
2777 tcg_gen_bswap16_tl(arg1, arg1);
2778 }
2779 }
2780 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2781
2782 /* lwbrx */
2783 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2784 {
2785 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2786 if (likely(!ctx->le_mode)) {
2787 tcg_gen_bswap32_tl(arg1, arg1);
2788 }
2789 }
2790 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2791
2792 #if defined(TARGET_PPC64)
2793 /* ldbrx */
2794 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2795 {
2796 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2797 if (likely(!ctx->le_mode)) {
2798 tcg_gen_bswap64_tl(arg1, arg1);
2799 }
2800 }
2801 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2802 #endif /* TARGET_PPC64 */
2803
2804 /* sthbrx */
2805 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2806 {
2807 if (likely(!ctx->le_mode)) {
2808 TCGv t0 = tcg_temp_new();
2809 tcg_gen_ext16u_tl(t0, arg1);
2810 tcg_gen_bswap16_tl(t0, t0);
2811 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2812 tcg_temp_free(t0);
2813 } else {
2814 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2815 }
2816 }
2817 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2818
2819 /* stwbrx */
2820 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2821 {
2822 if (likely(!ctx->le_mode)) {
2823 TCGv t0 = tcg_temp_new();
2824 tcg_gen_ext32u_tl(t0, arg1);
2825 tcg_gen_bswap32_tl(t0, t0);
2826 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2827 tcg_temp_free(t0);
2828 } else {
2829 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2830 }
2831 }
2832 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2833
2834 #if defined(TARGET_PPC64)
2835 /* stdbrx */
2836 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2837 {
2838 if (likely(!ctx->le_mode)) {
2839 TCGv t0 = tcg_temp_new();
2840 tcg_gen_bswap64_tl(t0, arg1);
2841 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2842 tcg_temp_free(t0);
2843 } else {
2844 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2845 }
2846 }
2847 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2848 #endif /* TARGET_PPC64 */
2849
2850 /*** Integer load and store multiple ***/
2851
2852 /* lmw */
2853 static void gen_lmw(DisasContext *ctx)
2854 {
2855 TCGv t0;
2856 TCGv_i32 t1;
2857 gen_set_access_type(ctx, ACCESS_INT);
2858 /* NIP cannot be restored if the memory exception comes from an helper */
2859 gen_update_nip(ctx, ctx->nip - 4);
2860 t0 = tcg_temp_new();
2861 t1 = tcg_const_i32(rD(ctx->opcode));
2862 gen_addr_imm_index(ctx, t0, 0);
2863 gen_helper_lmw(cpu_env, t0, t1);
2864 tcg_temp_free(t0);
2865 tcg_temp_free_i32(t1);
2866 }
2867
2868 /* stmw */
2869 static void gen_stmw(DisasContext *ctx)
2870 {
2871 TCGv t0;
2872 TCGv_i32 t1;
2873 gen_set_access_type(ctx, ACCESS_INT);
2874 /* NIP cannot be restored if the memory exception comes from an helper */
2875 gen_update_nip(ctx, ctx->nip - 4);
2876 t0 = tcg_temp_new();
2877 t1 = tcg_const_i32(rS(ctx->opcode));
2878 gen_addr_imm_index(ctx, t0, 0);
2879 gen_helper_stmw(cpu_env, t0, t1);
2880 tcg_temp_free(t0);
2881 tcg_temp_free_i32(t1);
2882 }
2883
2884 /*** Integer load and store strings ***/
2885
2886 /* lswi */
2887 /* PowerPC32 specification says we must generate an exception if
2888 * rA is in the range of registers to be loaded.
2889 * In an other hand, IBM says this is valid, but rA won't be loaded.
2890 * For now, I'll follow the spec...
2891 */
2892 static void gen_lswi(DisasContext *ctx)
2893 {
2894 TCGv t0;
2895 TCGv_i32 t1, t2;
2896 int nb = NB(ctx->opcode);
2897 int start = rD(ctx->opcode);
2898 int ra = rA(ctx->opcode);
2899 int nr;
2900
2901 if (nb == 0)
2902 nb = 32;
2903 nr = nb / 4;
2904 if (unlikely(((start + nr) > 32 &&
2905 start <= ra && (start + nr - 32) > ra) ||
2906 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2907 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2908 return;
2909 }
2910 gen_set_access_type(ctx, ACCESS_INT);
2911 /* NIP cannot be restored if the memory exception comes from an helper */
2912 gen_update_nip(ctx, ctx->nip - 4);
2913 t0 = tcg_temp_new();
2914 gen_addr_register(ctx, t0);
2915 t1 = tcg_const_i32(nb);
2916 t2 = tcg_const_i32(start);
2917 gen_helper_lsw(cpu_env, t0, t1, t2);
2918 tcg_temp_free(t0);
2919 tcg_temp_free_i32(t1);
2920 tcg_temp_free_i32(t2);
2921 }
2922
2923 /* lswx */
2924 static void gen_lswx(DisasContext *ctx)
2925 {
2926 TCGv t0;
2927 TCGv_i32 t1, t2, t3;
2928 gen_set_access_type(ctx, ACCESS_INT);
2929 /* NIP cannot be restored if the memory exception comes from an helper */
2930 gen_update_nip(ctx, ctx->nip - 4);
2931 t0 = tcg_temp_new();
2932 gen_addr_reg_index(ctx, t0);
2933 t1 = tcg_const_i32(rD(ctx->opcode));
2934 t2 = tcg_const_i32(rA(ctx->opcode));
2935 t3 = tcg_const_i32(rB(ctx->opcode));
2936 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2937 tcg_temp_free(t0);
2938 tcg_temp_free_i32(t1);
2939 tcg_temp_free_i32(t2);
2940 tcg_temp_free_i32(t3);
2941 }
2942
2943 /* stswi */
2944 static void gen_stswi(DisasContext *ctx)
2945 {
2946 TCGv t0;
2947 TCGv_i32 t1, t2;
2948 int nb = NB(ctx->opcode);
2949 gen_set_access_type(ctx, ACCESS_INT);
2950 /* NIP cannot be restored if the memory exception comes from an helper */
2951 gen_update_nip(ctx, ctx->nip - 4);
2952 t0 = tcg_temp_new();
2953 gen_addr_register(ctx, t0);
2954 if (nb == 0)
2955 nb = 32;
2956 t1 = tcg_const_i32(nb);
2957 t2 = tcg_const_i32(rS(ctx->opcode));
2958 gen_helper_stsw(cpu_env, t0, t1, t2);
2959 tcg_temp_free(t0);
2960 tcg_temp_free_i32(t1);
2961 tcg_temp_free_i32(t2);
2962 }
2963
2964 /* stswx */
2965 static void gen_stswx(DisasContext *ctx)
2966 {
2967 TCGv t0;
2968 TCGv_i32 t1, t2;
2969 gen_set_access_type(ctx, ACCESS_INT);
2970 /* NIP cannot be restored if the memory exception comes from an helper */
2971 gen_update_nip(ctx, ctx->nip - 4);
2972 t0 = tcg_temp_new();
2973 gen_addr_reg_index(ctx, t0);
2974 t1 = tcg_temp_new_i32();
2975 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2976 tcg_gen_andi_i32(t1, t1, 0x7F);
2977 t2 = tcg_const_i32(rS(ctx->opcode));
2978 gen_helper_stsw(cpu_env, t0, t1, t2);
2979 tcg_temp_free(t0);
2980 tcg_temp_free_i32(t1);
2981 tcg_temp_free_i32(t2);
2982 }
2983
2984 /*** Memory synchronisation ***/
2985 /* eieio */
2986 static void gen_eieio(DisasContext *ctx)
2987 {
2988 }
2989
2990 /* isync */
2991 static void gen_isync(DisasContext *ctx)
2992 {
2993 gen_stop_exception(ctx);
2994 }
2995
2996 /* lwarx */
2997 static void gen_lwarx(DisasContext *ctx)
2998 {
2999 TCGv t0;
3000 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3001 gen_set_access_type(ctx, ACCESS_RES);
3002 t0 = tcg_temp_local_new();
3003 gen_addr_reg_index(ctx, t0);
3004 gen_check_align(ctx, t0, 0x03);
3005 gen_qemu_ld32u(ctx, gpr, t0);
3006 tcg_gen_mov_tl(cpu_reserve, t0);
3007 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3008 tcg_temp_free(t0);
3009 }
3010
3011 #if defined(CONFIG_USER_ONLY)
3012 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3013 int reg, int size)
3014 {
3015 TCGv t0 = tcg_temp_new();
3016 uint32_t save_exception = ctx->exception;
3017
3018 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3019 tcg_gen_movi_tl(t0, (size << 5) | reg);
3020 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3021 tcg_temp_free(t0);
3022 gen_update_nip(ctx, ctx->nip-4);
3023 ctx->exception = POWERPC_EXCP_BRANCH;
3024 gen_exception(ctx, POWERPC_EXCP_STCX);
3025 ctx->exception = save_exception;
3026 }
3027 #endif
3028
3029 /* stwcx. */
3030 static void gen_stwcx_(DisasContext *ctx)
3031 {
3032 TCGv t0;
3033 gen_set_access_type(ctx, ACCESS_RES);
3034 t0 = tcg_temp_local_new();
3035 gen_addr_reg_index(ctx, t0);
3036 gen_check_align(ctx, t0, 0x03);
3037 #if defined(CONFIG_USER_ONLY)
3038 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3039 #else
3040 {
3041 int l1;
3042
3043 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3044 l1 = gen_new_label();
3045 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3046 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3047 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3048 gen_set_label(l1);
3049 tcg_gen_movi_tl(cpu_reserve, -1);
3050 }
3051 #endif
3052 tcg_temp_free(t0);
3053 }
3054
3055 #if defined(TARGET_PPC64)
3056 /* ldarx */
3057 static void gen_ldarx(DisasContext *ctx)
3058 {
3059 TCGv t0;
3060 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3061 gen_set_access_type(ctx, ACCESS_RES);
3062 t0 = tcg_temp_local_new();
3063 gen_addr_reg_index(ctx, t0);
3064 gen_check_align(ctx, t0, 0x07);
3065 gen_qemu_ld64(ctx, gpr, t0);
3066 tcg_gen_mov_tl(cpu_reserve, t0);
3067 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3068 tcg_temp_free(t0);
3069 }
3070
3071 /* stdcx. */
3072 static void gen_stdcx_(DisasContext *ctx)
3073 {
3074 TCGv t0;
3075 gen_set_access_type(ctx, ACCESS_RES);
3076 t0 = tcg_temp_local_new();
3077 gen_addr_reg_index(ctx, t0);
3078 gen_check_align(ctx, t0, 0x07);
3079 #if defined(CONFIG_USER_ONLY)
3080 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3081 #else
3082 {
3083 int l1;
3084 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3085 l1 = gen_new_label();
3086 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3087 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3088 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3089 gen_set_label(l1);
3090 tcg_gen_movi_tl(cpu_reserve, -1);
3091 }
3092 #endif
3093 tcg_temp_free(t0);
3094 }
3095 #endif /* defined(TARGET_PPC64) */
3096
3097 /* sync */
3098 static void gen_sync(DisasContext *ctx)
3099 {
3100 }
3101
3102 /* wait */
3103 static void gen_wait(DisasContext *ctx)
3104 {
3105 TCGv_i32 t0 = tcg_temp_new_i32();
3106 tcg_gen_st_i32(t0, cpu_env,
3107 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3108 tcg_temp_free_i32(t0);
3109 /* Stop translation, as the CPU is supposed to sleep from now */
3110 gen_exception_err(ctx, EXCP_HLT, 1);
3111 }
3112
3113 /*** Floating-point load ***/
3114 #define GEN_LDF(name, ldop, opc, type) \
3115 static void glue(gen_, name)(DisasContext *ctx) \
3116 { \
3117 TCGv EA; \
3118 if (unlikely(!ctx->fpu_enabled)) { \
3119 gen_exception(ctx, POWERPC_EXCP_FPU); \
3120 return; \
3121 } \
3122 gen_set_access_type(ctx, ACCESS_FLOAT); \
3123 EA = tcg_temp_new(); \
3124 gen_addr_imm_index(ctx, EA, 0); \
3125 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3126 tcg_temp_free(EA); \
3127 }
3128
3129 #define GEN_LDUF(name, ldop, opc, type) \
3130 static void glue(gen_, name##u)(DisasContext *ctx) \
3131 { \
3132 TCGv EA; \
3133 if (unlikely(!ctx->fpu_enabled)) { \
3134 gen_exception(ctx, POWERPC_EXCP_FPU); \
3135 return; \
3136 } \
3137 if (unlikely(rA(ctx->opcode) == 0)) { \
3138 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3139 return; \
3140 } \
3141 gen_set_access_type(ctx, ACCESS_FLOAT); \
3142 EA = tcg_temp_new(); \
3143 gen_addr_imm_index(ctx, EA, 0); \
3144 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3145 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3146 tcg_temp_free(EA); \
3147 }
3148
3149 #define GEN_LDUXF(name, ldop, opc, type) \
3150 static void glue(gen_, name##ux)(DisasContext *ctx) \
3151 { \
3152 TCGv EA; \
3153 if (unlikely(!ctx->fpu_enabled)) { \
3154 gen_exception(ctx, POWERPC_EXCP_FPU); \
3155 return; \
3156 } \
3157 if (unlikely(rA(ctx->opcode) == 0)) { \
3158 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3159 return; \
3160 } \
3161 gen_set_access_type(ctx, ACCESS_FLOAT); \
3162 EA = tcg_temp_new(); \
3163 gen_addr_reg_index(ctx, EA); \
3164 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3165 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3166 tcg_temp_free(EA); \
3167 }
3168
3169 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3170 static void glue(gen_, name##x)(DisasContext *ctx) \
3171 { \
3172 TCGv EA; \
3173 if (unlikely(!ctx->fpu_enabled)) { \
3174 gen_exception(ctx, POWERPC_EXCP_FPU); \
3175 return; \
3176 } \
3177 gen_set_access_type(ctx, ACCESS_FLOAT); \
3178 EA = tcg_temp_new(); \
3179 gen_addr_reg_index(ctx, EA); \
3180 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3181 tcg_temp_free(EA); \
3182 }
3183
3184 #define GEN_LDFS(name, ldop, op, type) \
3185 GEN_LDF(name, ldop, op | 0x20, type); \
3186 GEN_LDUF(name, ldop, op | 0x21, type); \
3187 GEN_LDUXF(name, ldop, op | 0x01, type); \
3188 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3189
3190 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3191 {
3192 TCGv t0 = tcg_temp_new();
3193 TCGv_i32 t1 = tcg_temp_new_i32();
3194 gen_qemu_ld32u(ctx, t0, arg2);
3195 tcg_gen_trunc_tl_i32(t1, t0);
3196 tcg_temp_free(t0);
3197 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3198 tcg_temp_free_i32(t1);
3199 }
3200
3201 /* lfd lfdu lfdux lfdx */
3202 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3203 /* lfs lfsu lfsux lfsx */
3204 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3205
3206 /*** Floating-point store ***/
3207 #define GEN_STF(name, stop, opc, type) \
3208 static void glue(gen_, name)(DisasContext *ctx) \
3209 { \
3210 TCGv EA; \
3211 if (unlikely(!ctx->fpu_enabled)) { \
3212 gen_exception(ctx, POWERPC_EXCP_FPU); \
3213 return; \
3214 } \
3215 gen_set_access_type(ctx, ACCESS_FLOAT); \
3216 EA = tcg_temp_new(); \
3217 gen_addr_imm_index(ctx, EA, 0); \
3218 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3219 tcg_temp_free(EA); \
3220 }
3221
3222 #define GEN_STUF(name, stop, opc, type) \
3223 static void glue(gen_, name##u)(DisasContext *ctx) \
3224 { \
3225 TCGv EA; \
3226 if (unlikely(!ctx->fpu_enabled)) { \
3227 gen_exception(ctx, POWERPC_EXCP_FPU); \
3228 return; \
3229 } \
3230 if (unlikely(rA(ctx->opcode) == 0)) { \
3231 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3232 return; \
3233 } \
3234 gen_set_access_type(ctx, ACCESS_FLOAT); \
3235 EA = tcg_temp_new(); \
3236 gen_addr_imm_index(ctx, EA, 0); \
3237 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3238 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3239 tcg_temp_free(EA); \
3240 }
3241
3242 #define GEN_STUXF(name, stop, opc, type) \
3243 static void glue(gen_, name##ux)(DisasContext *ctx) \
3244 { \
3245 TCGv EA; \
3246 if (unlikely(!ctx->fpu_enabled)) { \
3247 gen_exception(ctx, POWERPC_EXCP_FPU); \
3248 return; \
3249 } \
3250 if (unlikely(rA(ctx->opcode) == 0)) { \
3251 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3252 return; \
3253 } \
3254 gen_set_access_type(ctx, ACCESS_FLOAT); \
3255 EA = tcg_temp_new(); \
3256 gen_addr_reg_index(ctx, EA); \
3257 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3258 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3259 tcg_temp_free(EA); \
3260 }
3261
3262 #define GEN_STXF(name, stop, opc2, opc3, type) \
3263 static void glue(gen_, name##x)(DisasContext *ctx) \
3264 { \
3265 TCGv EA; \
3266 if (unlikely(!ctx->fpu_enabled)) { \
3267 gen_exception(ctx, POWERPC_EXCP_FPU); \
3268 return; \
3269 } \
3270 gen_set_access_type(ctx, ACCESS_FLOAT); \
3271 EA = tcg_temp_new(); \
3272 gen_addr_reg_index(ctx, EA); \
3273 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3274 tcg_temp_free(EA); \
3275 }
3276
3277 #define GEN_STFS(name, stop, op, type) \
3278 GEN_STF(name, stop, op | 0x20, type); \
3279 GEN_STUF(name, stop, op | 0x21, type); \
3280 GEN_STUXF(name, stop, op | 0x01, type); \
3281 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3282
3283 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3284 {
3285 TCGv_i32 t0 = tcg_temp_new_i32();
3286 TCGv t1 = tcg_temp_new();
3287 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3288 tcg_gen_extu_i32_tl(t1, t0);
3289 tcg_temp_free_i32(t0);
3290 gen_qemu_st32(ctx, t1, arg2);
3291 tcg_temp_free(t1);
3292 }
3293
3294 /* stfd stfdu stfdux stfdx */
3295 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3296 /* stfs stfsu stfsux stfsx */
3297 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3298
3299 /* Optional: */
3300 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3301 {
3302 TCGv t0 = tcg_temp_new();
3303 tcg_gen_trunc_i64_tl(t0, arg1),
3304 gen_qemu_st32(ctx, t0, arg2);
3305 tcg_temp_free(t0);
3306 }
3307 /* stfiwx */
3308 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3309
3310 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3311 {
3312 #if defined(TARGET_PPC64)
3313 if (ctx->has_cfar)
3314 tcg_gen_movi_tl(cpu_cfar, nip);
3315 #endif
3316 }
3317
3318 /*** Branch ***/
3319 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3320 {
3321 TranslationBlock *tb;
3322 tb = ctx->tb;
3323 #if defined(TARGET_PPC64)
3324 if (!ctx->sf_mode)
3325 dest = (uint32_t) dest;
3326 #endif
3327 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3328 likely(!ctx->singlestep_enabled)) {
3329 tcg_gen_goto_tb(n);
3330 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3331 tcg_gen_exit_tb((tcg_target_long)tb + n);
3332 } else {
3333 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3334 if (unlikely(ctx->singlestep_enabled)) {
3335 if ((ctx->singlestep_enabled &
3336 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3337 (ctx->exception == POWERPC_EXCP_BRANCH ||
3338 ctx->exception == POWERPC_EXCP_TRACE)) {
3339 target_ulong tmp = ctx->nip;
3340 ctx->nip = dest;
3341 gen_exception(ctx, POWERPC_EXCP_TRACE);
3342 ctx->nip = tmp;
3343 }
3344 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3345 gen_debug_exception(ctx);
3346 }
3347 }
3348 tcg_gen_exit_tb(0);
3349 }
3350 }
3351
3352 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3353 {
3354 #if defined(TARGET_PPC64)
3355 if (ctx->sf_mode == 0)
3356 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3357 else
3358 #endif
3359 tcg_gen_movi_tl(cpu_lr, nip);
3360 }
3361
3362 /* b ba bl bla */
3363 static void gen_b(DisasContext *ctx)
3364 {
3365 target_ulong li, target;
3366
3367 ctx->exception = POWERPC_EXCP_BRANCH;
3368 /* sign extend LI */
3369 #if defined(TARGET_PPC64)
3370 if (ctx->sf_mode)
3371 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3372 else
3373 #endif
3374 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3375 if (likely(AA(ctx->opcode) == 0))
3376 target = ctx->nip + li - 4;
3377 else
3378 target = li;
3379 if (LK(ctx->opcode))
3380 gen_setlr(ctx, ctx->nip);
3381 gen_update_cfar(ctx, ctx->nip);
3382 gen_goto_tb(ctx, 0, target);
3383 }
3384
3385 #define BCOND_IM 0
3386 #define BCOND_LR 1
3387 #define BCOND_CTR 2
3388
3389 static inline void gen_bcond(DisasContext *ctx, int type)
3390 {
3391 uint32_t bo = BO(ctx->opcode);
3392 int l1;
3393 TCGv target;
3394
3395 ctx->exception = POWERPC_EXCP_BRANCH;
3396 if (type == BCOND_LR || type == BCOND_CTR) {
3397 target = tcg_temp_local_new();
3398 if (type == BCOND_CTR)
3399 tcg_gen_mov_tl(target, cpu_ctr);
3400 else
3401 tcg_gen_mov_tl(target, cpu_lr);
3402 } else {
3403 TCGV_UNUSED(target);
3404 }
3405 if (LK(ctx->opcode))
3406 gen_setlr(ctx, ctx->nip);
3407 l1 = gen_new_label();
3408 if ((bo & 0x4) == 0) {
3409 /* Decrement and test CTR */
3410 TCGv temp = tcg_temp_new();
3411 if (unlikely(type == BCOND_CTR)) {
3412 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3413 return;
3414 }
3415 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3416 #if defined(TARGET_PPC64)
3417 if (!ctx->sf_mode)
3418 tcg_gen_ext32u_tl(temp, cpu_ctr);
3419 else
3420 #endif
3421 tcg_gen_mov_tl(temp, cpu_ctr);
3422 if (bo & 0x2) {
3423 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3424 } else {
3425 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3426 }
3427 tcg_temp_free(temp);
3428 }
3429 if ((bo & 0x10) == 0) {
3430 /* Test CR */
3431 uint32_t bi = BI(ctx->opcode);
3432 uint32_t mask = 1 << (3 - (bi & 0x03));
3433 TCGv_i32 temp = tcg_temp_new_i32();
3434
3435 if (bo & 0x8) {
3436 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3437 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3438 } else {
3439 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3440 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3441 }
3442 tcg_temp_free_i32(temp);
3443 }
3444 gen_update_cfar(ctx, ctx->nip);
3445 if (type == BCOND_IM) {
3446 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3447 if (likely(AA(ctx->opcode) == 0)) {
3448 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3449 } else {
3450 gen_goto_tb(ctx, 0, li);
3451 }
3452 gen_set_label(l1);
3453 gen_goto_tb(ctx, 1, ctx->nip);
3454 } else {
3455 #if defined(TARGET_PPC64)
3456 if (!(ctx->sf_mode))
3457 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3458 else
3459 #endif
3460 tcg_gen_andi_tl(cpu_nip, target, ~3);
3461 tcg_gen_exit_tb(0);
3462 gen_set_label(l1);
3463 #if defined(TARGET_PPC64)
3464 if (!(ctx->sf_mode))
3465 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3466 else
3467 #endif
3468 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3469 tcg_gen_exit_tb(0);
3470 }
3471 }
3472
3473 static void gen_bc(DisasContext *ctx)
3474 {
3475 gen_bcond(ctx, BCOND_IM);
3476 }
3477
3478 static void gen_bcctr(DisasContext *ctx)
3479 {
3480 gen_bcond(ctx, BCOND_CTR);
3481 }
3482
3483 static void gen_bclr(DisasContext *ctx)
3484 {
3485 gen_bcond(ctx, BCOND_LR);
3486 }
3487
3488 /*** Condition register logical ***/
3489 #define GEN_CRLOGIC(name, tcg_op, opc) \
3490 static void glue(gen_, name)(DisasContext *ctx) \
3491 { \
3492 uint8_t bitmask; \
3493 int sh; \
3494 TCGv_i32 t0, t1; \
3495 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3496 t0 = tcg_temp_new_i32(); \
3497 if (sh > 0) \
3498 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3499 else if (sh < 0) \
3500 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3501 else \
3502 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3503 t1 = tcg_temp_new_i32(); \
3504 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3505 if (sh > 0) \
3506 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3507 else if (sh < 0) \
3508 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3509 else \
3510 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3511 tcg_op(t0, t0, t1); \
3512 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3513 tcg_gen_andi_i32(t0, t0, bitmask); \
3514 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3515 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3516 tcg_temp_free_i32(t0); \
3517 tcg_temp_free_i32(t1); \
3518 }
3519
3520 /* crand */
3521 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3522 /* crandc */
3523 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3524 /* creqv */
3525 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3526 /* crnand */
3527 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3528 /* crnor */
3529 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3530 /* cror */
3531 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3532 /* crorc */
3533 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3534 /* crxor */
3535 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3536
3537 /* mcrf */
3538 static void gen_mcrf(DisasContext *ctx)
3539 {
3540 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3541 }
3542
3543 /*** System linkage ***/
3544
3545 /* rfi (mem_idx only) */
3546 static void gen_rfi(DisasContext *ctx)
3547 {
3548 #if defined(CONFIG_USER_ONLY)
3549 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3550 #else
3551 /* Restore CPU state */
3552 if (unlikely(!ctx->mem_idx)) {
3553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3554 return;
3555 }
3556 gen_update_cfar(ctx, ctx->nip);
3557 gen_helper_rfi(cpu_env);
3558 gen_sync_exception(ctx);
3559 #endif
3560 }
3561
3562 #if defined(TARGET_PPC64)
3563 static void gen_rfid(DisasContext *ctx)
3564 {
3565 #if defined(CONFIG_USER_ONLY)
3566 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3567 #else
3568 /* Restore CPU state */
3569 if (unlikely(!ctx->mem_idx)) {
3570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3571 return;
3572 }
3573 gen_update_cfar(ctx, ctx->nip);
3574 gen_helper_rfid(cpu_env);
3575 gen_sync_exception(ctx);
3576 #endif
3577 }
3578
3579 static void gen_hrfid(DisasContext *ctx)
3580 {
3581 #if defined(CONFIG_USER_ONLY)
3582 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3583 #else
3584 /* Restore CPU state */
3585 if (unlikely(ctx->mem_idx <= 1)) {
3586 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3587 return;
3588 }
3589 gen_helper_hrfid(cpu_env);
3590 gen_sync_exception(ctx);
3591 #endif
3592 }
3593 #endif
3594
3595 /* sc */
3596 #if defined(CONFIG_USER_ONLY)
3597 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3598 #else
3599 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3600 #endif
3601 static void gen_sc(DisasContext *ctx)
3602 {
3603 uint32_t lev;
3604
3605 lev = (ctx->opcode >> 5) & 0x7F;
3606 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3607 }
3608
3609 /*** Trap ***/
3610
3611 /* tw */
3612 static void gen_tw(DisasContext *ctx)
3613 {
3614 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3615 /* Update the nip since this might generate a trap exception */
3616 gen_update_nip(ctx, ctx->nip);
3617 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3618 t0);
3619 tcg_temp_free_i32(t0);
3620 }
3621
3622 /* twi */
3623 static void gen_twi(DisasContext *ctx)
3624 {
3625 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3626 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3627 /* Update the nip since this might generate a trap exception */
3628 gen_update_nip(ctx, ctx->nip);
3629 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3630 tcg_temp_free(t0);
3631 tcg_temp_free_i32(t1);
3632 }
3633
3634 #if defined(TARGET_PPC64)
3635 /* td */
3636 static void gen_td(DisasContext *ctx)
3637 {
3638 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3639 /* Update the nip since this might generate a trap exception */
3640 gen_update_nip(ctx, ctx->nip);
3641 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3642 t0);
3643 tcg_temp_free_i32(t0);
3644 }
3645
3646 /* tdi */
3647 static void gen_tdi(DisasContext *ctx)
3648 {
3649 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3650 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3651 /* Update the nip since this might generate a trap exception */
3652 gen_update_nip(ctx, ctx->nip);
3653 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3654 tcg_temp_free(t0);
3655 tcg_temp_free_i32(t1);
3656 }
3657 #endif
3658
3659 /*** Processor control ***/
3660
3661 static void gen_read_xer(TCGv dst)
3662 {
3663 TCGv t0 = tcg_temp_new();
3664 TCGv t1 = tcg_temp_new();
3665 TCGv t2 = tcg_temp_new();
3666 tcg_gen_mov_tl(dst, cpu_xer);
3667 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3668 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3669 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3670 tcg_gen_or_tl(t0, t0, t1);
3671 tcg_gen_or_tl(dst, dst, t2);
3672 tcg_gen_or_tl(dst, dst, t0);
3673 tcg_temp_free(t0);
3674 tcg_temp_free(t1);
3675 tcg_temp_free(t2);
3676 }
3677
3678 static void gen_write_xer(TCGv src)
3679 {
3680 tcg_gen_andi_tl(cpu_xer, src,
3681 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3682 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3683 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3684 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3685 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3686 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3687 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3688 }
3689
3690 /* mcrxr */
3691 static void gen_mcrxr(DisasContext *ctx)
3692 {
3693 TCGv_i32 t0 = tcg_temp_new_i32();
3694 TCGv_i32 t1 = tcg_temp_new_i32();
3695 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3696
3697 tcg_gen_trunc_tl_i32(t0, cpu_so);
3698 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3699 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3700 tcg_gen_shri_i32(t0, t0, 2);
3701 tcg_gen_shri_i32(t1, t1, 1);
3702 tcg_gen_or_i32(dst, dst, t0);
3703 tcg_gen_or_i32(dst, dst, t1);
3704 tcg_temp_free_i32(t0);
3705 tcg_temp_free_i32(t1);
3706
3707 tcg_gen_movi_tl(cpu_so, 0);
3708 tcg_gen_movi_tl(cpu_ov, 0);
3709 tcg_gen_movi_tl(cpu_ca, 0);
3710 }
3711
3712 /* mfcr mfocrf */
3713 static void gen_mfcr(DisasContext *ctx)
3714 {
3715 uint32_t crm, crn;
3716
3717 if (likely(ctx->opcode & 0x00100000)) {
3718 crm = CRM(ctx->opcode);
3719 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3720 crn = ctz32 (crm);
3721 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3722 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3723 cpu_gpr[rD(ctx->opcode)], crn * 4);
3724 }
3725 } else {
3726 TCGv_i32 t0 = tcg_temp_new_i32();
3727 tcg_gen_mov_i32(t0, cpu_crf[0]);
3728 tcg_gen_shli_i32(t0, t0, 4);
3729 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3730 tcg_gen_shli_i32(t0, t0, 4);
3731 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3732 tcg_gen_shli_i32(t0, t0, 4);
3733 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3734 tcg_gen_shli_i32(t0, t0, 4);
3735 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3736 tcg_gen_shli_i32(t0, t0, 4);
3737 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3738 tcg_gen_shli_i32(t0, t0, 4);
3739 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3740 tcg_gen_shli_i32(t0, t0, 4);
3741 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3742 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3743 tcg_temp_free_i32(t0);
3744 }
3745 }
3746
3747 /* mfmsr */
3748 static void gen_mfmsr(DisasContext *ctx)
3749 {
3750 #if defined(CONFIG_USER_ONLY)
3751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3752 #else
3753 if (unlikely(!ctx->mem_idx)) {
3754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3755 return;
3756 }
3757 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3758 #endif
3759 }
3760
3761 static void spr_noaccess(void *opaque, int gprn, int sprn)
3762 {
3763 #if 0
3764 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3765 printf("ERROR: try to access SPR %d !\n", sprn);
3766 #endif
3767 }
3768 #define SPR_NOACCESS (&spr_noaccess)
3769
3770 /* mfspr */
3771 static inline void gen_op_mfspr(DisasContext *ctx)
3772 {
3773 void (*read_cb)(void *opaque, int gprn, int sprn);
3774 uint32_t sprn = SPR(ctx->opcode);
3775
3776 #if !defined(CONFIG_USER_ONLY)
3777 if (ctx->mem_idx == 2)
3778 read_cb = ctx->spr_cb[sprn].hea_read;
3779 else if (ctx->mem_idx)
3780 read_cb = ctx->spr_cb[sprn].oea_read;
3781 else
3782 #endif
3783 read_cb = ctx->spr_cb[sprn].uea_read;
3784 if (likely(read_cb != NULL)) {
3785 if (likely(read_cb != SPR_NOACCESS)) {
3786 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3787 } else {
3788 /* Privilege exception */
3789 /* This is a hack to avoid warnings when running Linux:
3790 * this OS breaks the PowerPC virtualisation model,
3791 * allowing userland application to read the PVR
3792 */
3793 if (sprn != SPR_PVR) {
3794 qemu_log("Trying to read privileged spr %d %03x at "
3795 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3796 printf("Trying to read privileged spr %d %03x at "
3797 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3798 }
3799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3800 }
3801 } else {
3802 /* Not defined */
3803 qemu_log("Trying to read invalid spr %d %03x at "
3804 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3805 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3806 sprn, sprn, ctx->nip);
3807 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3808 }
3809 }
3810
3811 static void gen_mfspr(DisasContext *ctx)
3812 {
3813 gen_op_mfspr(ctx);
3814 }
3815
3816 /* mftb */
3817 static void gen_mftb(DisasContext *ctx)
3818 {
3819 gen_op_mfspr(ctx);
3820 }
3821
3822 /* mtcrf mtocrf*/
3823 static void gen_mtcrf(DisasContext *ctx)
3824 {
3825 uint32_t crm, crn;
3826
3827 crm = CRM(ctx->opcode);
3828 if (likely((ctx->opcode & 0x00100000))) {
3829 if (crm && ((crm & (crm - 1)) == 0)) {
3830 TCGv_i32 temp = tcg_temp_new_i32();
3831 crn = ctz32 (crm);
3832 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3833 tcg_gen_shri_i32(temp, temp, crn * 4);
3834 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3835 tcg_temp_free_i32(temp);
3836 }
3837 } else {
3838 TCGv_i32 temp = tcg_temp_new_i32();
3839 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3840 for (crn = 0 ; crn < 8 ; crn++) {
3841 if (crm & (1 << crn)) {
3842 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3843 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3844 }
3845 }
3846 tcg_temp_free_i32(temp);
3847 }
3848 }
3849
3850 /* mtmsr */
3851 #if defined(TARGET_PPC64)
3852 static void gen_mtmsrd(DisasContext *ctx)
3853 {
3854 #if defined(CONFIG_USER_ONLY)
3855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3856 #else
3857 if (unlikely(!ctx->mem_idx)) {
3858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3859 return;
3860 }
3861 if (ctx->opcode & 0x00010000) {
3862 /* Special form that does not need any synchronisation */
3863 TCGv t0 = tcg_temp_new();
3864 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3865 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3866 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3867 tcg_temp_free(t0);
3868 } else {
3869 /* XXX: we need to update nip before the store
3870 * if we enter power saving mode, we will exit the loop
3871 * directly from ppc_store_msr
3872 */
3873 gen_update_nip(ctx, ctx->nip);
3874 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3875 /* Must stop the translation as machine state (may have) changed */
3876 /* Note that mtmsr is not always defined as context-synchronizing */
3877 gen_stop_exception(ctx);
3878 }
3879 #endif
3880 }
3881 #endif
3882
3883 static void gen_mtmsr(DisasContext *ctx)
3884 {
3885 #if defined(CONFIG_USER_ONLY)
3886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3887 #else
3888 if (unlikely(!ctx->mem_idx)) {
3889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3890 return;
3891 }
3892 if (ctx->opcode & 0x00010000) {
3893 /* Special form that does not need any synchronisation */
3894 TCGv t0 = tcg_temp_new();
3895 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3896 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3897 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3898 tcg_temp_free(t0);
3899 } else {
3900 TCGv msr = tcg_temp_new();
3901
3902 /* XXX: we need to update nip before the store
3903 * if we enter power saving mode, we will exit the loop
3904 * directly from ppc_store_msr
3905 */
3906 gen_update_nip(ctx, ctx->nip);
3907 #if defined(TARGET_PPC64)
3908 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3909 #else
3910 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3911 #endif
3912 gen_helper_store_msr(cpu_env, msr);
3913 /* Must stop the translation as machine state (may have) changed */
3914 /* Note that mtmsr is not always defined as context-synchronizing */
3915 gen_stop_exception(ctx);
3916 }
3917 #endif
3918 }
3919
3920 /* mtspr */
3921 static void gen_mtspr(DisasContext *ctx)
3922 {
3923 void (*write_cb)(void *opaque, int sprn, int gprn);
3924 uint32_t sprn = SPR(ctx->opcode);
3925
3926 #if !defined(CONFIG_USER_ONLY)
3927 if (ctx->mem_idx == 2)
3928 write_cb = ctx->spr_cb[sprn].hea_write;
3929 else if (ctx->mem_idx)
3930 write_cb = ctx->spr_cb[sprn].oea_write;
3931 else
3932 #endif
3933 write_cb = ctx->spr_cb[sprn].uea_write;
3934 if (likely(write_cb != NULL)) {
3935 if (likely(write_cb != SPR_NOACCESS)) {
3936 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3937 } else {
3938 /* Privilege exception */
3939 qemu_log("Trying to write privileged spr %d %03x at "
3940 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3941 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3942 "\n", sprn, sprn, ctx->nip);
3943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3944 }
3945 } else {
3946 /* Not defined */
3947 qemu_log("Trying to write invalid spr %d %03x at "
3948 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3949 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3950 sprn, sprn, ctx->nip);
3951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3952 }
3953 }
3954
3955 /*** Cache management ***/
3956
3957 /* dcbf */
3958 static void gen_dcbf(DisasContext *ctx)
3959 {
3960 /* XXX: specification says this is treated as a load by the MMU */
3961 TCGv t0;
3962 gen_set_access_type(ctx, ACCESS_CACHE);
3963 t0 = tcg_temp_new();
3964 gen_addr_reg_index(ctx, t0);
3965 gen_qemu_ld8u(ctx, t0, t0);
3966 tcg_temp_free(t0);
3967 }
3968
3969 /* dcbi (Supervisor only) */
3970 static void gen_dcbi(DisasContext *ctx)
3971 {
3972 #if defined(CONFIG_USER_ONLY)
3973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3974 #else
3975 TCGv EA, val;
3976 if (unlikely(!ctx->mem_idx)) {
3977 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3978 return;
3979 }
3980 EA = tcg_temp_new();
3981 gen_set_access_type(ctx, ACCESS_CACHE);
3982 gen_addr_reg_index(ctx, EA);
3983 val = tcg_temp_new();
3984 /* XXX: specification says this should be treated as a store by the MMU */
3985 gen_qemu_ld8u(ctx, val, EA);
3986 gen_qemu_st8(ctx, val, EA);
3987 tcg_temp_free(val);
3988 tcg_temp_free(EA);
3989 #endif
3990 }
3991
3992 /* dcdst */
3993 static void gen_dcbst(DisasContext *ctx)
3994 {
3995 /* XXX: specification say this is treated as a load by the MMU */
3996 TCGv t0;
3997 gen_set_access_type(ctx, ACCESS_CACHE);
3998 t0 = tcg_temp_new();
3999 gen_addr_reg_index(ctx, t0);
4000 gen_qemu_ld8u(ctx, t0, t0);
4001 tcg_temp_free(t0);
4002 }
4003
4004 /* dcbt */
4005 static void gen_dcbt(DisasContext *ctx)
4006 {
4007 /* interpreted as no-op */
4008 /* XXX: specification say this is treated as a load by the MMU
4009 * but does not generate any exception
4010 */
4011 }
4012
4013 /* dcbtst */
4014 static void gen_dcbtst(DisasContext *ctx)
4015 {
4016 /* interpreted as no-op */
4017 /* XXX: specification say this is treated as a load by the MMU
4018 * but does not generate any exception
4019 */
4020 }
4021
4022 /* dcbz */
4023 static void gen_dcbz(DisasContext *ctx)
4024 {
4025 TCGv tcgv_addr;
4026 TCGv_i32 tcgv_is_dcbzl;
4027 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4028
4029 gen_set_access_type(ctx, ACCESS_CACHE);
4030 /* NIP cannot be restored if the memory exception comes from an helper */
4031 gen_update_nip(ctx, ctx->nip - 4);
4032 tcgv_addr = tcg_temp_new();
4033 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4034
4035 gen_addr_reg_index(ctx, tcgv_addr);
4036 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4037
4038 tcg_temp_free(tcgv_addr);
4039 tcg_temp_free_i32(tcgv_is_dcbzl);
4040 }
4041
4042 /* dst / dstt */
4043 static void gen_dst(DisasContext *ctx)
4044 {
4045 if (rA(ctx->opcode) == 0) {
4046 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4047 } else {
4048 /* interpreted as no-op */
4049 }
4050 }
4051
4052 /* dstst /dststt */
4053 static void gen_dstst(DisasContext *ctx)
4054 {
4055 if (rA(ctx->opcode) == 0) {
4056 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4057 } else {
4058 /* interpreted as no-op */
4059 }
4060
4061 }
4062
4063 /* dss / dssall */
4064 static void gen_dss(DisasContext *ctx)
4065 {
4066 /* interpreted as no-op */
4067 }
4068
4069 /* icbi */
4070 static void gen_icbi(DisasContext *ctx)
4071 {
4072 TCGv t0;
4073 gen_set_access_type(ctx, ACCESS_CACHE);
4074 /* NIP cannot be restored if the memory exception comes from an helper */
4075 gen_update_nip(ctx, ctx->nip - 4);
4076 t0 = tcg_temp_new();
4077 gen_addr_reg_index(ctx, t0);
4078 gen_helper_icbi(cpu_env, t0);
4079 tcg_temp_free(t0);
4080 }
4081
4082 /* Optional: */
4083 /* dcba */
4084 static void gen_dcba(DisasContext *ctx)
4085 {
4086 /* interpreted as no-op */
4087 /* XXX: specification say this is treated as a store by the MMU
4088 * but does not generate any exception
4089 */
4090 }
4091
4092 /*** Segment register manipulation ***/
4093 /* Supervisor only: */
4094
4095 /* mfsr */
4096 static void gen_mfsr(DisasContext *ctx)
4097 {
4098 #if defined(CONFIG_USER_ONLY)
4099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4100 #else
4101 TCGv t0;
4102 if (unlikely(!ctx->mem_idx)) {
4103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4104 return;
4105 }
4106 t0 = tcg_const_tl(SR(ctx->opcode));
4107 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4108 tcg_temp_free(t0);
4109 #endif
4110 }
4111
4112 /* mfsrin */
4113 static void gen_mfsrin(DisasContext *ctx)
4114 {
4115 #if defined(CONFIG_USER_ONLY)
4116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4117 #else
4118 TCGv t0;
4119 if (unlikely(!ctx->mem_idx)) {
4120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4121 return;
4122 }
4123 t0 = tcg_temp_new();
4124 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4125 tcg_gen_andi_tl(t0, t0, 0xF);
4126 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4127 tcg_temp_free(t0);
4128 #endif
4129 }
4130
4131 /* mtsr */
4132 static void gen_mtsr(DisasContext *ctx)
4133 {
4134 #if defined(CONFIG_USER_ONLY)
4135 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4136 #else
4137 TCGv t0;
4138 if (unlikely(!ctx->mem_idx)) {
4139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4140 return;
4141 }
4142 t0 = tcg_const_tl(SR(ctx->opcode));
4143 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4144 tcg_temp_free(t0);
4145 #endif
4146 }
4147
4148 /* mtsrin */
4149 static void gen_mtsrin(DisasContext *ctx)
4150 {
4151 #if defined(CONFIG_USER_ONLY)
4152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4153 #else
4154 TCGv t0;
4155 if (unlikely(!ctx->mem_idx)) {
4156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4157 return;
4158 }
4159 t0 = tcg_temp_new();
4160 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4161 tcg_gen_andi_tl(t0, t0, 0xF);
4162 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4163 tcg_temp_free(t0);
4164 #endif
4165 }
4166
4167 #if defined(TARGET_PPC64)
4168 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4169
4170 /* mfsr */
4171 static void gen_mfsr_64b(DisasContext *ctx)
4172 {
4173 #if defined(CONFIG_USER_ONLY)
4174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4175 #else
4176 TCGv t0;
4177 if (unlikely(!ctx->mem_idx)) {
4178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4179 return;
4180 }
4181 t0 = tcg_const_tl(SR(ctx->opcode));
4182 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4183 tcg_temp_free(t0);
4184 #endif
4185 }
4186
4187 /* mfsrin */
4188 static void gen_mfsrin_64b(DisasContext *ctx)
4189 {
4190 #if defined(CONFIG_USER_ONLY)
4191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4192 #else
4193 TCGv t0;
4194 if (unlikely(!ctx->mem_idx)) {
4195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4196 return;
4197 }
4198 t0 = tcg_temp_new();
4199 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4200 tcg_gen_andi_tl(t0, t0, 0xF);
4201 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4202 tcg_temp_free(t0);
4203 #endif
4204 }
4205
4206 /* mtsr */
4207 static void gen_mtsr_64b(DisasContext *ctx)
4208 {
4209 #if defined(CONFIG_USER_ONLY)
4210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4211 #else
4212 TCGv t0;
4213 if (unlikely(!ctx->mem_idx)) {
4214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4215 return;
4216 }
4217 t0 = tcg_const_tl(SR(ctx->opcode));
4218 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4219 tcg_temp_free(t0);
4220 #endif
4221 }
4222
4223 /* mtsrin */
4224 static void gen_mtsrin_64b(DisasContext *ctx)
4225 {
4226 #if defined(CONFIG_USER_ONLY)
4227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4228 #else
4229 TCGv t0;
4230 if (unlikely(!ctx->mem_idx)) {
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232 return;
4233 }
4234 t0 = tcg_temp_new();
4235 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4236 tcg_gen_andi_tl(t0, t0, 0xF);
4237 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4238 tcg_temp_free(t0);
4239 #endif
4240 }
4241
4242 /* slbmte */
4243 static void gen_slbmte(DisasContext *ctx)
4244 {
4245 #if defined(CONFIG_USER_ONLY)
4246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4247 #else
4248 if (unlikely(!ctx->mem_idx)) {
4249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4250 return;
4251 }
4252 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4253 cpu_gpr[rS(ctx->opcode)]);
4254 #endif
4255 }
4256
4257 static void gen_slbmfee(DisasContext *ctx)
4258 {
4259 #if defined(CONFIG_USER_ONLY)
4260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4261 #else
4262 if (unlikely(!ctx->mem_idx)) {
4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4264 return;
4265 }
4266 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4267 cpu_gpr[rB(ctx->opcode)]);
4268 #endif
4269 }
4270
4271 static void gen_slbmfev(DisasContext *ctx)
4272 {
4273 #if defined(CONFIG_USER_ONLY)
4274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4275 #else
4276 if (unlikely(!ctx->mem_idx)) {
4277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4278 return;
4279 }
4280 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4281 cpu_gpr[rB(ctx->opcode)]);
4282 #endif
4283 }
4284 #endif /* defined(TARGET_PPC64) */
4285
4286 /*** Lookaside buffer management ***/
4287 /* Optional & mem_idx only: */
4288
4289 /* tlbia */
4290 static void gen_tlbia(DisasContext *ctx)
4291 {
4292 #if defined(CONFIG_USER_ONLY)
4293 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4294 #else
4295 if (unlikely(!ctx->mem_idx)) {
4296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4297 return;
4298 }
4299 gen_helper_tlbia(cpu_env);
4300 #endif
4301 }
4302
4303 /* tlbiel */
4304 static void gen_tlbiel(DisasContext *ctx)
4305 {
4306 #if defined(CONFIG_USER_ONLY)
4307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4308 #else
4309 if (unlikely(!ctx->mem_idx)) {
4310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4311 return;
4312 }
4313 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4314 #endif
4315 }
4316
4317 /* tlbie */
4318 static void gen_tlbie(DisasContext *ctx)
4319 {
4320 #if defined(CONFIG_USER_ONLY)
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4322 #else
4323 if (unlikely(!ctx->mem_idx)) {
4324 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4325 return;
4326 }
4327 #if defined(TARGET_PPC64)
4328 if (!ctx->sf_mode) {
4329 TCGv t0 = tcg_temp_new();
4330 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4331 gen_helper_tlbie(cpu_env, t0);
4332 tcg_temp_free(t0);
4333 } else
4334 #endif
4335 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4336 #endif
4337 }
4338
4339 /* tlbsync */
4340 static void gen_tlbsync(DisasContext *ctx)
4341 {
4342 #if defined(CONFIG_USER_ONLY)
4343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4344 #else
4345 if (unlikely(!ctx->mem_idx)) {
4346 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4347 return;
4348 }
4349 /* This has no effect: it should ensure that all previous
4350 * tlbie have completed
4351 */
4352 gen_stop_exception(ctx);
4353 #endif
4354 }
4355
4356 #if defined(TARGET_PPC64)
4357 /* slbia */
4358 static void gen_slbia(DisasContext *ctx)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4362 #else
4363 if (unlikely(!ctx->mem_idx)) {
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4365 return;
4366 }
4367 gen_helper_slbia(cpu_env);
4368 #endif
4369 }
4370
4371 /* slbie */
4372 static void gen_slbie(DisasContext *ctx)
4373 {
4374 #if defined(CONFIG_USER_ONLY)
4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4376 #else
4377 if (unlikely(!ctx->mem_idx)) {
4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4379 return;
4380 }
4381 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4382 #endif
4383 }
4384 #endif
4385
4386 /*** External control ***/
4387 /* Optional: */
4388
4389 /* eciwx */
4390 static void gen_eciwx(DisasContext *ctx)
4391 {
4392 TCGv t0;
4393 /* Should check EAR[E] ! */
4394 gen_set_access_type(ctx, ACCESS_EXT);
4395 t0 = tcg_temp_new();
4396 gen_addr_reg_index(ctx, t0);
4397 gen_check_align(ctx, t0, 0x03);
4398 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4399 tcg_temp_free(t0);
4400 }
4401
4402 /* ecowx */
4403 static void gen_ecowx(DisasContext *ctx)
4404 {
4405 TCGv t0;
4406 /* Should check EAR[E] ! */
4407 gen_set_access_type(ctx, ACCESS_EXT);
4408 t0 = tcg_temp_new();
4409 gen_addr_reg_index(ctx, t0);
4410 gen_check_align(ctx, t0, 0x03);
4411 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4412 tcg_temp_free(t0);
4413 }
4414
4415 /* PowerPC 601 specific instructions */
4416
4417 /* abs - abs. */
4418 static void gen_abs(DisasContext *ctx)
4419 {
4420 int l1 = gen_new_label();
4421 int l2 = gen_new_label();
4422 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4423 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4424 tcg_gen_br(l2);
4425 gen_set_label(l1);
4426 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4427 gen_set_label(l2);
4428 if (unlikely(Rc(ctx->opcode) != 0))
4429 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4430 }
4431
4432 /* abso - abso. */
4433 static void gen_abso(DisasContext *ctx)
4434 {
4435 int l1 = gen_new_label();
4436 int l2 = gen_new_label();
4437 int l3 = gen_new_label();
4438 /* Start with XER OV disabled, the most likely case */
4439 tcg_gen_movi_tl(cpu_ov, 0);
4440 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4441 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4442 tcg_gen_movi_tl(cpu_ov, 1);
4443 tcg_gen_movi_tl(cpu_so, 1);
4444 tcg_gen_br(l2);
4445 gen_set_label(l1);
4446 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4447 tcg_gen_br(l3);
4448 gen_set_label(l2);
4449 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4450 gen_set_label(l3);
4451 if (unlikely(Rc(ctx->opcode) != 0))
4452 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4453 }
4454
4455 /* clcs */
4456 static void gen_clcs(DisasContext *ctx)
4457 {
4458 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4459 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4460 tcg_temp_free_i32(t0);
4461 /* Rc=1 sets CR0 to an undefined state */
4462 }
4463
4464 /* div - div. */
4465 static void gen_div(DisasContext *ctx)
4466 {
4467 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4468 cpu_gpr[rB(ctx->opcode)]);
4469 if (unlikely(Rc(ctx->opcode) != 0))
4470 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4471 }
4472
4473 /* divo - divo. */
4474 static void gen_divo(DisasContext *ctx)
4475 {
4476 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4477 cpu_gpr[rB(ctx->opcode)]);
4478 if (unlikely(Rc(ctx->opcode) != 0))
4479 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4480 }
4481
4482 /* divs - divs. */
4483 static void gen_divs(DisasContext *ctx)
4484 {
4485 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4486 cpu_gpr[rB(ctx->opcode)]);
4487 if (unlikely(Rc(ctx->opcode) != 0))
4488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4489 }
4490
4491 /* divso - divso. */
4492 static void gen_divso(DisasContext *ctx)
4493 {
4494 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4495 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4496 if (unlikely(Rc(ctx->opcode) != 0))
4497 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4498 }
4499
4500 /* doz - doz. */
4501 static void gen_doz(DisasContext *ctx)
4502 {
4503 int l1 = gen_new_label();
4504 int l2 = gen_new_label();
4505 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4506 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4507 tcg_gen_br(l2);
4508 gen_set_label(l1);
4509 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4510 gen_set_label(l2);
4511 if (unlikely(Rc(ctx->opcode) != 0))
4512 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4513 }
4514
4515 /* dozo - dozo. */
4516 static void gen_dozo(DisasContext *ctx)
4517 {
4518 int l1 = gen_new_label();
4519 int l2 = gen_new_label();
4520 TCGv t0 = tcg_temp_new();
4521 TCGv t1 = tcg_temp_new();
4522 TCGv t2 = tcg_temp_new();
4523 /* Start with XER OV disabled, the most likely case */
4524 tcg_gen_movi_tl(cpu_ov, 0);
4525 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4526 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4527 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4528 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4529 tcg_gen_andc_tl(t1, t1, t2);
4530 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4531 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4532 tcg_gen_movi_tl(cpu_ov, 1);
4533 tcg_gen_movi_tl(cpu_so, 1);
4534 tcg_gen_br(l2);
4535 gen_set_label(l1);
4536 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4537 gen_set_label(l2);
4538 tcg_temp_free(t0);
4539 tcg_temp_free(t1);
4540 tcg_temp_free(t2);
4541 if (unlikely(Rc(ctx->opcode) != 0))
4542 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4543 }
4544
4545 /* dozi */
4546 static void gen_dozi(DisasContext *ctx)
4547 {
4548 target_long simm = SIMM(ctx->opcode);
4549 int l1 = gen_new_label();
4550 int l2 = gen_new_label();
4551 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4552 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4553 tcg_gen_br(l2);
4554 gen_set_label(l1);
4555 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4556 gen_set_label(l2);
4557 if (unlikely(Rc(ctx->opcode) != 0))
4558 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4559 }
4560
4561 /* lscbx - lscbx. */
4562 static void gen_lscbx(DisasContext *ctx)
4563 {
4564 TCGv t0 = tcg_temp_new();
4565 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4566 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4567 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4568
4569 gen_addr_reg_index(ctx, t0);
4570 /* NIP cannot be restored if the memory exception comes from an helper */
4571 gen_update_nip(ctx, ctx->nip - 4);
4572 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4573 tcg_temp_free_i32(t1);
4574 tcg_temp_free_i32(t2);
4575 tcg_temp_free_i32(t3);
4576 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4577 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4578 if (unlikely(Rc(ctx->opcode) != 0))
4579 gen_set_Rc0(ctx, t0);
4580 tcg_temp_free(t0);
4581 }
4582
4583 /* maskg - maskg. */
4584 static void gen_maskg(DisasContext *ctx)
4585 {
4586 int l1 = gen_new_label();
4587 TCGv t0 = tcg_temp_new();
4588 TCGv t1 = tcg_temp_new();
4589 TCGv t2 = tcg_temp_new();
4590 TCGv t3 = tcg_temp_new();
4591 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4592 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4593 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4594 tcg_gen_addi_tl(t2, t0, 1);
4595 tcg_gen_shr_tl(t2, t3, t2);
4596 tcg_gen_shr_tl(t3, t3, t1);
4597 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4598 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4599 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4600 gen_set_label(l1);
4601 tcg_temp_free(t0);
4602 tcg_temp_free(t1);
4603 tcg_temp_free(t2);
4604 tcg_temp_free(t3);
4605 if (unlikely(Rc(ctx->opcode) != 0))
4606 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4607 }
4608
4609 /* maskir - maskir. */
4610 static void gen_maskir(DisasContext *ctx)
4611 {
4612 TCGv t0 = tcg_temp_new();
4613 TCGv t1 = tcg_temp_new();
4614 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4615 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4616 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4617 tcg_temp_free(t0);
4618 tcg_temp_free(t1);
4619 if (unlikely(Rc(ctx->opcode) != 0))
4620 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4621 }
4622
4623 /* mul - mul. */
4624 static void gen_mul(DisasContext *ctx)
4625 {
4626 TCGv_i64 t0 = tcg_temp_new_i64();
4627 TCGv_i64 t1 = tcg_temp_new_i64();
4628 TCGv t2 = tcg_temp_new();
4629 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4630 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4631 tcg_gen_mul_i64(t0, t0, t1);
4632 tcg_gen_trunc_i64_tl(t2, t0);
4633 gen_store_spr(SPR_MQ, t2);
4634 tcg_gen_shri_i64(t1, t0, 32);
4635 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4636 tcg_temp_free_i64(t0);
4637 tcg_temp_free_i64(t1);
4638 tcg_temp_free(t2);
4639 if (unlikely(Rc(ctx->opcode) != 0))
4640 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4641 }
4642
4643 /* mulo - mulo. */
4644 static void gen_mulo(DisasContext *ctx)
4645 {
4646 int l1 = gen_new_label();
4647 TCGv_i64 t0 = tcg_temp_new_i64();
4648 TCGv_i64 t1 = tcg_temp_new_i64();
4649 TCGv t2 = tcg_temp_new();
4650 /* Start with XER OV disabled, the most likely case */
4651 tcg_gen_movi_tl(cpu_ov, 0);
4652 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4653 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4654 tcg_gen_mul_i64(t0, t0, t1);
4655 tcg_gen_trunc_i64_tl(t2, t0);
4656 gen_store_spr(SPR_MQ, t2);
4657 tcg_gen_shri_i64(t1, t0, 32);
4658 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4659 tcg_gen_ext32s_i64(t1, t0);
4660 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4661 tcg_gen_movi_tl(cpu_ov, 1);
4662 tcg_gen_movi_tl(cpu_so, 1);
4663 gen_set_label(l1);
4664 tcg_temp_free_i64(t0);
4665 tcg_temp_free_i64(t1);
4666 tcg_temp_free(t2);
4667 if (unlikely(Rc(ctx->opcode) != 0))
4668 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4669 }
4670
4671 /* nabs - nabs. */
4672 static void gen_nabs(DisasContext *ctx)
4673 {
4674 int l1 = gen_new_label();
4675 int l2 = gen_new_label();
4676 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4677 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4678 tcg_gen_br(l2);
4679 gen_set_label(l1);
4680 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4681 gen_set_label(l2);
4682 if (unlikely(Rc(ctx->opcode) != 0))
4683 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4684 }
4685
4686 /* nabso - nabso. */
4687 static void gen_nabso(DisasContext *ctx)
4688 {
4689 int l1 = gen_new_label();
4690 int l2 = gen_new_label();
4691 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4692 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4693 tcg_gen_br(l2);
4694 gen_set_label(l1);
4695 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4696 gen_set_label(l2);
4697 /* nabs never overflows */
4698 tcg_gen_movi_tl(cpu_ov, 0);
4699 if (unlikely(Rc(ctx->opcode) != 0))
4700 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4701 }
4702
4703 /* rlmi - rlmi. */
4704 static void gen_rlmi(DisasContext *ctx)
4705 {
4706 uint32_t mb = MB(ctx->opcode);
4707 uint32_t me = ME(ctx->opcode);
4708 TCGv t0 = tcg_temp_new();
4709 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4710 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4711 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4712 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4713 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4714 tcg_temp_free(t0);
4715 if (unlikely(Rc(ctx->opcode) != 0))
4716 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4717 }
4718
4719 /* rrib - rrib. */
4720 static void gen_rrib(DisasContext *ctx)
4721 {
4722 TCGv t0 = tcg_temp_new();
4723 TCGv t1 = tcg_temp_new();
4724 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4725 tcg_gen_movi_tl(t1, 0x80000000);
4726 tcg_gen_shr_tl(t1, t1, t0);
4727 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4728 tcg_gen_and_tl(t0, t0, t1);
4729 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4730 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4731 tcg_temp_free(t0);
4732 tcg_temp_free(t1);
4733 if (unlikely(Rc(ctx->opcode) != 0))
4734 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4735 }
4736
4737 /* sle - sle. */
4738 static void gen_sle(DisasContext *ctx)
4739 {
4740 TCGv t0 = tcg_temp_new();
4741 TCGv t1 = tcg_temp_new();
4742 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4743 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4744 tcg_gen_subfi_tl(t1, 32, t1);
4745 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4746 tcg_gen_or_tl(t1, t0, t1);
4747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4748 gen_store_spr(SPR_MQ, t1);
4749 tcg_temp_free(t0);
4750 tcg_temp_free(t1);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4753 }
4754
4755 /* sleq - sleq. */
4756 static void gen_sleq(DisasContext *ctx)
4757 {
4758 TCGv t0 = tcg_temp_new();
4759 TCGv t1 = tcg_temp_new();
4760 TCGv t2 = tcg_temp_new();
4761 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4762 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4763 tcg_gen_shl_tl(t2, t2, t0);
4764 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4765 gen_load_spr(t1, SPR_MQ);
4766 gen_store_spr(SPR_MQ, t0);
4767 tcg_gen_and_tl(t0, t0, t2);
4768 tcg_gen_andc_tl(t1, t1, t2);
4769 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4770 tcg_temp_free(t0);
4771 tcg_temp_free(t1);
4772 tcg_temp_free(t2);
4773 if (unlikely(Rc(ctx->opcode) != 0))
4774 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4775 }
4776
4777 /* sliq - sliq. */
4778 static void gen_sliq(DisasContext *ctx)
4779 {
4780 int sh = SH(ctx->opcode);
4781 TCGv t0 = tcg_temp_new();
4782 TCGv t1 = tcg_temp_new();
4783 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4784 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4785 tcg_gen_or_tl(t1, t0, t1);
4786 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4787 gen_store_spr(SPR_MQ, t1);
4788 tcg_temp_free(t0);
4789 tcg_temp_free(t1);
4790 if (unlikely(Rc(ctx->opcode) != 0))
4791 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4792 }
4793
4794 /* slliq - slliq. */
4795 static void gen_slliq(DisasContext *ctx)
4796 {
4797 int sh = SH(ctx->opcode);
4798 TCGv t0 = tcg_temp_new();
4799 TCGv t1 = tcg_temp_new();
4800 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4801 gen_load_spr(t1, SPR_MQ);
4802 gen_store_spr(SPR_MQ, t0);
4803 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4804 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4805 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4806 tcg_temp_free(t0);
4807 tcg_temp_free(t1);
4808 if (unlikely(Rc(ctx->opcode) != 0))
4809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4810 }
4811
4812 /* sllq - sllq. */
4813 static void gen_sllq(DisasContext *ctx)
4814 {
4815 int l1 = gen_new_label();
4816 int l2 = gen_new_label();
4817 TCGv t0 = tcg_temp_local_new();
4818 TCGv t1 = tcg_temp_local_new();
4819 TCGv t2 = tcg_temp_local_new();
4820 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4821 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4822 tcg_gen_shl_tl(t1, t1, t2);
4823 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4824 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4825 gen_load_spr(t0, SPR_MQ);
4826 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4827 tcg_gen_br(l2);
4828 gen_set_label(l1);
4829 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4830 gen_load_spr(t2, SPR_MQ);
4831 tcg_gen_andc_tl(t1, t2, t1);
4832 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4833 gen_set_label(l2);
4834 tcg_temp_free(t0);
4835 tcg_temp_free(t1);
4836 tcg_temp_free(t2);
4837 if (unlikely(Rc(ctx->opcode) != 0))
4838 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4839 }
4840
4841 /* slq - slq. */
4842 static void gen_slq(DisasContext *ctx)
4843 {
4844 int l1 = gen_new_label();
4845 TCGv t0 = tcg_temp_new();
4846 TCGv t1 = tcg_temp_new();
4847 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4848 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4849 tcg_gen_subfi_tl(t1, 32, t1);
4850 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4851 tcg_gen_or_tl(t1, t0, t1);
4852 gen_store_spr(SPR_MQ, t1);
4853 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4854 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4855 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4856 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4857 gen_set_label(l1);
4858 tcg_temp_free(t0);
4859 tcg_temp_free(t1);
4860 if (unlikely(Rc(ctx->opcode) != 0))
4861 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4862 }
4863
4864 /* sraiq - sraiq. */
4865 static void gen_sraiq(DisasContext *ctx)
4866 {
4867 int sh = SH(ctx->opcode);
4868 int l1 = gen_new_label();
4869 TCGv t0 = tcg_temp_new();
4870 TCGv t1 = tcg_temp_new();
4871 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4872 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4873 tcg_gen_or_tl(t0, t0, t1);
4874 gen_store_spr(SPR_MQ, t0);
4875 tcg_gen_movi_tl(cpu_ca, 0);
4876 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4877 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4878 tcg_gen_movi_tl(cpu_ca, 1);
4879 gen_set_label(l1);
4880 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4881 tcg_temp_free(t0);
4882 tcg_temp_free(t1);
4883 if (unlikely(Rc(ctx->opcode) != 0))
4884 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4885 }
4886
4887 /* sraq - sraq. */
4888 static void gen_sraq(DisasContext *ctx)
4889 {
4890 int l1 = gen_new_label();
4891 int l2 = gen_new_label();
4892 TCGv t0 = tcg_temp_new();
4893 TCGv t1 = tcg_temp_local_new();
4894 TCGv t2 = tcg_temp_local_new();
4895 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4896 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4897 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4898 tcg_gen_subfi_tl(t2, 32, t2);
4899 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4900 tcg_gen_or_tl(t0, t0, t2);
4901 gen_store_spr(SPR_MQ, t0);
4902 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4903 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4904 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4905 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4906 gen_set_label(l1);
4907 tcg_temp_free(t0);
4908 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4909 tcg_gen_movi_tl(cpu_ca, 0);
4910 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4911 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4912 tcg_gen_movi_tl(cpu_ca, 1);
4913 gen_set_label(l2);
4914 tcg_temp_free(t1);
4915 tcg_temp_free(t2);
4916 if (unlikely(Rc(ctx->opcode) != 0))
4917 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4918 }
4919
4920 /* sre - sre. */
4921 static void gen_sre(DisasContext *ctx)
4922 {
4923 TCGv t0 = tcg_temp_new();
4924 TCGv t1 = tcg_temp_new();
4925 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4926 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4927 tcg_gen_subfi_tl(t1, 32, t1);
4928 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4929 tcg_gen_or_tl(t1, t0, t1);
4930 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4931 gen_store_spr(SPR_MQ, t1);
4932 tcg_temp_free(t0);
4933 tcg_temp_free(t1);
4934 if (unlikely(Rc(ctx->opcode) != 0))
4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4936 }
4937
4938 /* srea - srea. */
4939 static void gen_srea(DisasContext *ctx)
4940 {
4941 TCGv t0 = tcg_temp_new();
4942 TCGv t1 = tcg_temp_new();
4943 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4944 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4945 gen_store_spr(SPR_MQ, t0);
4946 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4947 tcg_temp_free(t0);
4948 tcg_temp_free(t1);
4949 if (unlikely(Rc(ctx->opcode) != 0))
4950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4951 }
4952
4953 /* sreq */
4954 static void gen_sreq(DisasContext *ctx)
4955 {
4956 TCGv t0 = tcg_temp_new();
4957 TCGv t1 = tcg_temp_new();
4958 TCGv t2 = tcg_temp_new();
4959 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4960 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4961 tcg_gen_shr_tl(t1, t1, t0);
4962 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4963 gen_load_spr(t2, SPR_MQ);
4964 gen_store_spr(SPR_MQ, t0);
4965 tcg_gen_and_tl(t0, t0, t1);
4966 tcg_gen_andc_tl(t2, t2, t1);
4967 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4968 tcg_temp_free(t0);
4969 tcg_temp_free(t1);
4970 tcg_temp_free(t2);
4971 if (unlikely(Rc(ctx->opcode) != 0))
4972 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4973 }
4974
4975 /* sriq */
4976 static void gen_sriq(DisasContext *ctx)
4977 {
4978 int sh = SH(ctx->opcode);
4979 TCGv t0 = tcg_temp_new();
4980 TCGv t1 = tcg_temp_new();
4981 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4982 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4983 tcg_gen_or_tl(t1, t0, t1);
4984 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4985 gen_store_spr(SPR_MQ, t1);
4986 tcg_temp_free(t0);
4987 tcg_temp_free(t1);
4988 if (unlikely(Rc(ctx->opcode) != 0))
4989 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4990 }
4991
4992 /* srliq */
4993 static void gen_srliq(DisasContext *ctx)
4994 {
4995 int sh = SH(ctx->opcode);
4996 TCGv t0 = tcg_temp_new();
4997 TCGv t1 = tcg_temp_new();
4998 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4999 gen_load_spr(t1, SPR_MQ);
5000 gen_store_spr(SPR_MQ, t0);
5001 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5002 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5003 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5004 tcg_temp_free(t0);
5005 tcg_temp_free(t1);
5006 if (unlikely(Rc(ctx->opcode) != 0))
5007 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5008 }
5009
5010 /* srlq */
5011 static void gen_srlq(DisasContext *ctx)
5012 {
5013 int l1 = gen_new_label();
5014 int l2 = gen_new_label();
5015 TCGv t0 = tcg_temp_local_new();
5016 TCGv t1 = tcg_temp_local_new();
5017 TCGv t2 = tcg_temp_local_new();
5018 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5019 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5020 tcg_gen_shr_tl(t2, t1, t2);
5021 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5022 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5023 gen_load_spr(t0, SPR_MQ);
5024 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5025 tcg_gen_br(l2);
5026 gen_set_label(l1);
5027 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5028 tcg_gen_and_tl(t0, t0, t2);
5029 gen_load_spr(t1, SPR_MQ);
5030 tcg_gen_andc_tl(t1, t1, t2);
5031 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5032 gen_set_label(l2);
5033 tcg_temp_free(t0);
5034 tcg_temp_free(t1);
5035 tcg_temp_free(t2);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* srq */
5041 static void gen_srq(DisasContext *ctx)
5042 {
5043 int l1 = gen_new_label();
5044 TCGv t0 = tcg_temp_new();
5045 TCGv t1 = tcg_temp_new();
5046 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5047 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5048 tcg_gen_subfi_tl(t1, 32, t1);
5049 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5050 tcg_gen_or_tl(t1, t0, t1);
5051 gen_store_spr(SPR_MQ, t1);
5052 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5053 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5054 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5055 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5056 gen_set_label(l1);
5057 tcg_temp_free(t0);
5058 tcg_temp_free(t1);
5059 if (unlikely(Rc(ctx->opcode) != 0))
5060 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5061 }
5062
5063 /* PowerPC 602 specific instructions */
5064
5065 /* dsa */
5066 static void gen_dsa(DisasContext *ctx)
5067 {
5068 /* XXX: TODO */
5069 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5070 }
5071
5072 /* esa */
5073 static void gen_esa(DisasContext *ctx)
5074 {
5075 /* XXX: TODO */
5076 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5077 }
5078
5079 /* mfrom */
5080 static void gen_mfrom(DisasContext *ctx)
5081 {
5082 #if defined(CONFIG_USER_ONLY)
5083 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5084 #else
5085 if (unlikely(!ctx->mem_idx)) {
5086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5087 return;
5088 }
5089 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5090 #endif
5091 }
5092
5093 /* 602 - 603 - G2 TLB management */
5094
5095 /* tlbld */
5096 static void gen_tlbld_6xx(DisasContext *ctx)
5097 {
5098 #if defined(CONFIG_USER_ONLY)
5099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5100 #else
5101 if (unlikely(!ctx->mem_idx)) {
5102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5103 return;
5104 }
5105 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5106 #endif
5107 }
5108
5109 /* tlbli */
5110 static void gen_tlbli_6xx(DisasContext *ctx)
5111 {
5112 #if defined(CONFIG_USER_ONLY)
5113 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5114 #else
5115 if (unlikely(!ctx->mem_idx)) {
5116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5117 return;
5118 }
5119 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5120 #endif
5121 }
5122
5123 /* 74xx TLB management */
5124
5125 /* tlbld */
5126 static void gen_tlbld_74xx(DisasContext *ctx)
5127 {
5128 #if defined(CONFIG_USER_ONLY)
5129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5130 #else
5131 if (unlikely(!ctx->mem_idx)) {
5132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5133 return;
5134 }
5135 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5136 #endif
5137 }
5138
5139 /* tlbli */
5140 static void gen_tlbli_74xx(DisasContext *ctx)
5141 {
5142 #if defined(CONFIG_USER_ONLY)
5143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5144 #else
5145 if (unlikely(!ctx->mem_idx)) {
5146 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5147 return;
5148 }
5149 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5150 #endif
5151 }
5152
5153 /* POWER instructions not in PowerPC 601 */
5154
5155 /* clf */
5156 static void gen_clf(DisasContext *ctx)
5157 {
5158 /* Cache line flush: implemented as no-op */
5159 }
5160
5161 /* cli */
5162 static void gen_cli(DisasContext *ctx)
5163 {
5164 /* Cache line invalidate: privileged and treated as no-op */
5165 #if defined(CONFIG_USER_ONLY)
5166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5167 #else
5168 if (unlikely(!ctx->mem_idx)) {
5169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5170 return;
5171 }
5172 #endif
5173 }
5174
5175 /* dclst */
5176 static void gen_dclst(DisasContext *ctx)
5177 {
5178 /* Data cache line store: treated as no-op */
5179 }
5180
5181 static void gen_mfsri(DisasContext *ctx)
5182 {
5183 #if defined(CONFIG_USER_ONLY)
5184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5185 #else
5186 int ra = rA(ctx->opcode);
5187 int rd = rD(ctx->opcode);
5188 TCGv t0;
5189 if (unlikely(!ctx->mem_idx)) {
5190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5191 return;
5192 }
5193 t0 = tcg_temp_new();
5194 gen_addr_reg_index(ctx, t0);
5195 tcg_gen_shri_tl(t0, t0, 28);
5196 tcg_gen_andi_tl(t0, t0, 0xF);
5197 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5198 tcg_temp_free(t0);
5199 if (ra != 0 && ra != rd)
5200 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5201 #endif
5202 }
5203
5204 static void gen_rac(DisasContext *ctx)
5205 {
5206 #if defined(CONFIG_USER_ONLY)
5207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5208 #else
5209 TCGv t0;
5210 if (unlikely(!ctx->mem_idx)) {
5211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5212 return;
5213 }
5214 t0 = tcg_temp_new();
5215 gen_addr_reg_index(ctx, t0);
5216 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5217 tcg_temp_free(t0);
5218 #endif
5219 }
5220
5221 static void gen_rfsvc(DisasContext *ctx)
5222 {
5223 #if defined(CONFIG_USER_ONLY)
5224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5225 #else
5226 if (unlikely(!ctx->mem_idx)) {
5227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5228 return;
5229 }
5230 gen_helper_rfsvc(cpu_env);
5231 gen_sync_exception(ctx);
5232 #endif
5233 }
5234
5235 /* svc is not implemented for now */
5236
5237 /* POWER2 specific instructions */
5238 /* Quad manipulation (load/store two floats at a time) */
5239
5240 /* lfq */
5241 static void gen_lfq(DisasContext *ctx)
5242 {
5243 int rd = rD(ctx->opcode);
5244 TCGv t0;
5245 gen_set_access_type(ctx, ACCESS_FLOAT);
5246 t0 = tcg_temp_new();
5247 gen_addr_imm_index(ctx, t0, 0);
5248 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5249 gen_addr_add(ctx, t0, t0, 8);
5250 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5251 tcg_temp_free(t0);
5252 }
5253
5254 /* lfqu */
5255 static void gen_lfqu(DisasContext *ctx)
5256 {
5257 int ra = rA(ctx->opcode);
5258 int rd = rD(ctx->opcode);
5259 TCGv t0, t1;
5260 gen_set_access_type(ctx, ACCESS_FLOAT);
5261 t0 = tcg_temp_new();
5262 t1 = tcg_temp_new();
5263 gen_addr_imm_index(ctx, t0, 0);
5264 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5265 gen_addr_add(ctx, t1, t0, 8);
5266 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5267 if (ra != 0)
5268 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5269 tcg_temp_free(t0);
5270 tcg_temp_free(t1);
5271 }
5272
5273 /* lfqux */
5274 static void gen_lfqux(DisasContext *ctx)
5275 {
5276 int ra = rA(ctx->opcode);
5277 int rd = rD(ctx->opcode);
5278 gen_set_access_type(ctx, ACCESS_FLOAT);
5279 TCGv t0, t1;
5280 t0 = tcg_temp_new();
5281 gen_addr_reg_index(ctx, t0);
5282 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5283 t1 = tcg_temp_new();
5284 gen_addr_add(ctx, t1, t0, 8);
5285 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5286 tcg_temp_free(t1);
5287 if (ra != 0)
5288 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5289 tcg_temp_free(t0);
5290 }
5291
5292 /* lfqx */
5293 static void gen_lfqx(DisasContext *ctx)
5294 {
5295 int rd = rD(ctx->opcode);
5296 TCGv t0;
5297 gen_set_access_type(ctx, ACCESS_FLOAT);
5298 t0 = tcg_temp_new();
5299 gen_addr_reg_index(ctx, t0);
5300 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5301 gen_addr_add(ctx, t0, t0, 8);
5302 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5303 tcg_temp_free(t0);
5304 }
5305
5306 /* stfq */
5307 static void gen_stfq(DisasContext *ctx)
5308 {
5309 int rd = rD(ctx->opcode);
5310 TCGv t0;
5311 gen_set_access_type(ctx, ACCESS_FLOAT);
5312 t0 = tcg_temp_new();
5313 gen_addr_imm_index(ctx, t0, 0);
5314 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5315 gen_addr_add(ctx, t0, t0, 8);
5316 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5317 tcg_temp_free(t0);
5318 }
5319
5320 /* stfqu */
5321 static void gen_stfqu(DisasContext *ctx)
5322 {
5323 int ra = rA(ctx->opcode);
5324 int rd = rD(ctx->opcode);
5325 TCGv t0, t1;
5326 gen_set_access_type(ctx, ACCESS_FLOAT);
5327 t0 = tcg_temp_new();
5328 gen_addr_imm_index(ctx, t0, 0);
5329 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5330 t1 = tcg_temp_new();
5331 gen_addr_add(ctx, t1, t0, 8);
5332 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5333 tcg_temp_free(t1);
5334 if (ra != 0)
5335 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5336 tcg_temp_free(t0);
5337 }
5338
5339 /* stfqux */
5340 static void gen_stfqux(DisasContext *ctx)
5341 {
5342 int ra = rA(ctx->opcode);
5343 int rd = rD(ctx->opcode);
5344 TCGv t0, t1;
5345 gen_set_access_type(ctx, ACCESS_FLOAT);
5346 t0 = tcg_temp_new();
5347 gen_addr_reg_index(ctx, t0);
5348 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5349 t1 = tcg_temp_new();
5350 gen_addr_add(ctx, t1, t0, 8);
5351 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5352 tcg_temp_free(t1);
5353 if (ra != 0)
5354 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5355 tcg_temp_free(t0);
5356 }
5357
5358 /* stfqx */
5359 static void gen_stfqx(DisasContext *ctx)
5360 {
5361 int rd = rD(ctx->opcode);
5362 TCGv t0;
5363 gen_set_access_type(ctx, ACCESS_FLOAT);
5364 t0 = tcg_temp_new();
5365 gen_addr_reg_index(ctx, t0);
5366 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5367 gen_addr_add(ctx, t0, t0, 8);
5368 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5369 tcg_temp_free(t0);
5370 }
5371
5372 /* BookE specific instructions */
5373
5374 /* XXX: not implemented on 440 ? */
5375 static void gen_mfapidi(DisasContext *ctx)
5376 {
5377 /* XXX: TODO */
5378 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5379 }
5380
5381 /* XXX: not implemented on 440 ? */
5382 static void gen_tlbiva(DisasContext *ctx)
5383 {
5384 #if defined(CONFIG_USER_ONLY)
5385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5386 #else
5387 TCGv t0;
5388 if (unlikely(!ctx->mem_idx)) {
5389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5390 return;
5391 }
5392 t0 = tcg_temp_new();
5393 gen_addr_reg_index(ctx, t0);
5394 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5395 tcg_temp_free(t0);
5396 #endif
5397 }
5398
5399 /* All 405 MAC instructions are translated here */
5400 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5401 int ra, int rb, int rt, int Rc)
5402 {
5403 TCGv t0, t1;
5404
5405 t0 = tcg_temp_local_new();
5406 t1 = tcg_temp_local_new();
5407
5408 switch (opc3 & 0x0D) {
5409 case 0x05:
5410 /* macchw - macchw. - macchwo - macchwo. */
5411 /* macchws - macchws. - macchwso - macchwso. */
5412 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5413 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5414 /* mulchw - mulchw. */
5415 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5416 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5417 tcg_gen_ext16s_tl(t1, t1);
5418 break;
5419 case 0x04:
5420 /* macchwu - macchwu. - macchwuo - macchwuo. */
5421 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5422 /* mulchwu - mulchwu. */
5423 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5424 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5425 tcg_gen_ext16u_tl(t1, t1);
5426 break;
5427 case 0x01:
5428 /* machhw - machhw. - machhwo - machhwo. */
5429 /* machhws - machhws. - machhwso - machhwso. */
5430 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5431 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5432 /* mulhhw - mulhhw. */
5433 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5434 tcg_gen_ext16s_tl(t0, t0);
5435 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5436 tcg_gen_ext16s_tl(t1, t1);
5437 break;
5438 case 0x00:
5439 /* machhwu - machhwu. - machhwuo - machhwuo. */
5440 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5441 /* mulhhwu - mulhhwu. */
5442 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5443 tcg_gen_ext16u_tl(t0, t0);
5444 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5445 tcg_gen_ext16u_tl(t1, t1);
5446 break;
5447 case 0x0D:
5448 /* maclhw - maclhw. - maclhwo - maclhwo. */
5449 /* maclhws - maclhws. - maclhwso - maclhwso. */
5450 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5451 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5452 /* mullhw - mullhw. */
5453 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5454 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5455 break;
5456 case 0x0C:
5457 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5458 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5459 /* mullhwu - mullhwu. */
5460 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5461 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5462 break;
5463 }
5464 if (opc2 & 0x04) {
5465 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5466 tcg_gen_mul_tl(t1, t0, t1);
5467 if (opc2 & 0x02) {
5468 /* nmultiply-and-accumulate (0x0E) */
5469 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5470 } else {
5471 /* multiply-and-accumulate (0x0C) */
5472 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5473 }
5474
5475 if (opc3 & 0x12) {
5476 /* Check overflow and/or saturate */
5477 int l1 = gen_new_label();
5478
5479 if (opc3 & 0x10) {
5480 /* Start with XER OV disabled, the most likely case */
5481 tcg_gen_movi_tl(cpu_ov, 0);
5482 }
5483 if (opc3 & 0x01) {
5484 /* Signed */
5485 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5486 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5487 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5488 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5489 if (opc3 & 0x02) {
5490 /* Saturate */
5491 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5492 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5493 }
5494 } else {
5495 /* Unsigned */
5496 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5497 if (opc3 & 0x02) {
5498 /* Saturate */
5499 tcg_gen_movi_tl(t0, UINT32_MAX);
5500 }
5501 }
5502 if (opc3 & 0x10) {
5503 /* Check overflow */
5504 tcg_gen_movi_tl(cpu_ov, 1);
5505 tcg_gen_movi_tl(cpu_so, 1);
5506 }
5507 gen_set_label(l1);
5508 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5509 }
5510 } else {
5511 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5512 }
5513 tcg_temp_free(t0);
5514 tcg_temp_free(t1);
5515 if (unlikely(Rc) != 0) {
5516 /* Update Rc0 */
5517 gen_set_Rc0(ctx, cpu_gpr[rt]);
5518 }
5519 }
5520
5521 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5522 static void glue(gen_, name)(DisasContext *ctx) \
5523 { \
5524 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5525 rD(ctx->opcode), Rc(ctx->opcode)); \
5526 }
5527
5528 /* macchw - macchw. */
5529 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5530 /* macchwo - macchwo. */
5531 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5532 /* macchws - macchws. */
5533 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5534 /* macchwso - macchwso. */
5535 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5536 /* macchwsu - macchwsu. */
5537 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5538 /* macchwsuo - macchwsuo. */
5539 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5540 /* macchwu - macchwu. */
5541 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5542 /* macchwuo - macchwuo. */
5543 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5544 /* machhw - machhw. */
5545 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5546 /* machhwo - machhwo. */
5547 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5548 /* machhws - machhws. */
5549 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5550 /* machhwso - machhwso. */
5551 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5552 /* machhwsu - machhwsu. */
5553 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5554 /* machhwsuo - machhwsuo. */
5555 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5556 /* machhwu - machhwu. */
5557 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5558 /* machhwuo - machhwuo. */
5559 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5560 /* maclhw - maclhw. */
5561 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5562 /* maclhwo - maclhwo. */
5563 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5564 /* maclhws - maclhws. */
5565 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5566 /* maclhwso - maclhwso. */
5567 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5568 /* maclhwu - maclhwu. */
5569 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5570 /* maclhwuo - maclhwuo. */
5571 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5572 /* maclhwsu - maclhwsu. */
5573 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5574 /* maclhwsuo - maclhwsuo. */
5575 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5576 /* nmacchw - nmacchw. */
5577 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5578 /* nmacchwo - nmacchwo. */
5579 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5580 /* nmacchws - nmacchws. */
5581 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5582 /* nmacchwso - nmacchwso. */
5583 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5584 /* nmachhw - nmachhw. */
5585 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5586 /* nmachhwo - nmachhwo. */
5587 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5588 /* nmachhws - nmachhws. */
5589 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5590 /* nmachhwso - nmachhwso. */
5591 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5592 /* nmaclhw - nmaclhw. */
5593 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5594 /* nmaclhwo - nmaclhwo. */
5595 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5596 /* nmaclhws - nmaclhws. */
5597 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5598 /* nmaclhwso - nmaclhwso. */
5599 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5600
5601 /* mulchw - mulchw. */
5602 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5603 /* mulchwu - mulchwu. */
5604 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5605 /* mulhhw - mulhhw. */
5606 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5607 /* mulhhwu - mulhhwu. */
5608 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5609 /* mullhw - mullhw. */
5610 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5611 /* mullhwu - mullhwu. */
5612 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5613
5614 /* mfdcr */
5615 static void gen_mfdcr(DisasContext *ctx)
5616 {
5617 #if defined(CONFIG_USER_ONLY)
5618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5619 #else
5620 TCGv dcrn;
5621 if (unlikely(!ctx->mem_idx)) {
5622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5623 return;
5624 }
5625 /* NIP cannot be restored if the memory exception comes from an helper */
5626 gen_update_nip(ctx, ctx->nip - 4);
5627 dcrn = tcg_const_tl(SPR(ctx->opcode));
5628 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5629 tcg_temp_free(dcrn);
5630 #endif
5631 }
5632
5633 /* mtdcr */
5634 static void gen_mtdcr(DisasContext *ctx)
5635 {
5636 #if defined(CONFIG_USER_ONLY)
5637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5638 #else
5639 TCGv dcrn;
5640 if (unlikely(!ctx->mem_idx)) {
5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5642 return;
5643 }
5644 /* NIP cannot be restored if the memory exception comes from an helper */
5645 gen_update_nip(ctx, ctx->nip - 4);
5646 dcrn = tcg_const_tl(SPR(ctx->opcode));
5647 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5648 tcg_temp_free(dcrn);
5649 #endif
5650 }
5651
5652 /* mfdcrx */
5653 /* XXX: not implemented on 440 ? */
5654 static void gen_mfdcrx(DisasContext *ctx)
5655 {
5656 #if defined(CONFIG_USER_ONLY)
5657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5658 #else
5659 if (unlikely(!ctx->mem_idx)) {
5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5661 return;
5662 }
5663 /* NIP cannot be restored if the memory exception comes from an helper */
5664 gen_update_nip(ctx, ctx->nip - 4);
5665 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5666 cpu_gpr[rA(ctx->opcode)]);
5667 /* Note: Rc update flag set leads to undefined state of Rc0 */
5668 #endif
5669 }
5670
5671 /* mtdcrx */
5672 /* XXX: not implemented on 440 ? */
5673 static void gen_mtdcrx(DisasContext *ctx)
5674 {
5675 #if defined(CONFIG_USER_ONLY)
5676 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5677 #else
5678 if (unlikely(!ctx->mem_idx)) {
5679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5680 return;
5681 }
5682 /* NIP cannot be restored if the memory exception comes from an helper */
5683 gen_update_nip(ctx, ctx->nip - 4);
5684 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5685 cpu_gpr[rS(ctx->opcode)]);
5686 /* Note: Rc update flag set leads to undefined state of Rc0 */
5687 #endif
5688 }
5689
5690 /* mfdcrux (PPC 460) : user-mode access to DCR */
5691 static void gen_mfdcrux(DisasContext *ctx)
5692 {
5693 /* NIP cannot be restored if the memory exception comes from an helper */
5694 gen_update_nip(ctx, ctx->nip - 4);
5695 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5696 cpu_gpr[rA(ctx->opcode)]);
5697 /* Note: Rc update flag set leads to undefined state of Rc0 */
5698 }
5699
5700 /* mtdcrux (PPC 460) : user-mode access to DCR */
5701 static void gen_mtdcrux(DisasContext *ctx)
5702 {
5703 /* NIP cannot be restored if the memory exception comes from an helper */
5704 gen_update_nip(ctx, ctx->nip - 4);
5705 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5706 cpu_gpr[rS(ctx->opcode)]);
5707 /* Note: Rc update flag set leads to undefined state of Rc0 */
5708 }
5709
5710 /* dccci */
5711 static void gen_dccci(DisasContext *ctx)
5712 {
5713 #if defined(CONFIG_USER_ONLY)
5714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5715 #else
5716 if (unlikely(!ctx->mem_idx)) {
5717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5718 return;
5719 }
5720 /* interpreted as no-op */
5721 #endif
5722 }
5723
5724 /* dcread */
5725 static void gen_dcread(DisasContext *ctx)
5726 {
5727 #if defined(CONFIG_USER_ONLY)
5728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5729 #else
5730 TCGv EA, val;
5731 if (unlikely(!ctx->mem_idx)) {
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 return;
5734 }
5735 gen_set_access_type(ctx, ACCESS_CACHE);
5736 EA = tcg_temp_new();
5737 gen_addr_reg_index(ctx, EA);
5738 val = tcg_temp_new();
5739 gen_qemu_ld32u(ctx, val, EA);
5740 tcg_temp_free(val);
5741 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5742 tcg_temp_free(EA);
5743 #endif
5744 }
5745
5746 /* icbt */
5747 static void gen_icbt_40x(DisasContext *ctx)
5748 {
5749 /* interpreted as no-op */
5750 /* XXX: specification say this is treated as a load by the MMU
5751 * but does not generate any exception
5752 */
5753 }
5754
5755 /* iccci */
5756 static void gen_iccci(DisasContext *ctx)
5757 {
5758 #if defined(CONFIG_USER_ONLY)
5759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5760 #else
5761 if (unlikely(!ctx->mem_idx)) {
5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5763 return;
5764 }
5765 /* interpreted as no-op */
5766 #endif
5767 }
5768
5769 /* icread */
5770 static void gen_icread(DisasContext *ctx)
5771 {
5772 #if defined(CONFIG_USER_ONLY)
5773 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5774 #else
5775 if (unlikely(!ctx->mem_idx)) {
5776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5777 return;
5778 }
5779 /* interpreted as no-op */
5780 #endif
5781 }
5782
5783 /* rfci (mem_idx only) */
5784 static void gen_rfci_40x(DisasContext *ctx)
5785 {
5786 #if defined(CONFIG_USER_ONLY)
5787 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5788 #else
5789 if (unlikely(!ctx->mem_idx)) {
5790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5791 return;
5792 }
5793 /* Restore CPU state */
5794 gen_helper_40x_rfci(cpu_env);
5795 gen_sync_exception(ctx);
5796 #endif
5797 }
5798
5799 static void gen_rfci(DisasContext *ctx)
5800 {
5801 #if defined(CONFIG_USER_ONLY)
5802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5803 #else
5804 if (unlikely(!ctx->mem_idx)) {
5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5806 return;
5807 }
5808 /* Restore CPU state */
5809 gen_helper_rfci(cpu_env);
5810 gen_sync_exception(ctx);
5811 #endif
5812 }
5813
5814 /* BookE specific */
5815
5816 /* XXX: not implemented on 440 ? */
5817 static void gen_rfdi(DisasContext *ctx)
5818 {
5819 #if defined(CONFIG_USER_ONLY)
5820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5821 #else
5822 if (unlikely(!ctx->mem_idx)) {
5823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5824 return;
5825 }
5826 /* Restore CPU state */
5827 gen_helper_rfdi(cpu_env);
5828 gen_sync_exception(ctx);
5829 #endif
5830 }
5831
5832 /* XXX: not implemented on 440 ? */
5833 static void gen_rfmci(DisasContext *ctx)
5834 {
5835 #if defined(CONFIG_USER_ONLY)
5836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5837 #else
5838 if (unlikely(!ctx->mem_idx)) {
5839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5840 return;
5841 }
5842 /* Restore CPU state */
5843 gen_helper_rfmci(cpu_env);
5844 gen_sync_exception(ctx);
5845 #endif
5846 }
5847
5848 /* TLB management - PowerPC 405 implementation */
5849
5850 /* tlbre */
5851 static void gen_tlbre_40x(DisasContext *ctx)
5852 {
5853 #if defined(CONFIG_USER_ONLY)
5854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5855 #else
5856 if (unlikely(!ctx->mem_idx)) {
5857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5858 return;
5859 }
5860 switch (rB(ctx->opcode)) {
5861 case 0:
5862 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5863 cpu_gpr[rA(ctx->opcode)]);
5864 break;
5865 case 1:
5866 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5867 cpu_gpr[rA(ctx->opcode)]);
5868 break;
5869 default:
5870 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5871 break;
5872 }
5873 #endif
5874 }
5875
5876 /* tlbsx - tlbsx. */
5877 static void gen_tlbsx_40x(DisasContext *ctx)
5878 {
5879 #if defined(CONFIG_USER_ONLY)
5880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5881 #else
5882 TCGv t0;
5883 if (unlikely(!ctx->mem_idx)) {
5884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5885 return;
5886 }
5887 t0 = tcg_temp_new();
5888 gen_addr_reg_index(ctx, t0);
5889 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5890 tcg_temp_free(t0);
5891 if (Rc(ctx->opcode)) {
5892 int l1 = gen_new_label();
5893 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5894 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5895 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5896 gen_set_label(l1);
5897 }
5898 #endif
5899 }
5900
5901 /* tlbwe */
5902 static void gen_tlbwe_40x(DisasContext *ctx)
5903 {
5904 #if defined(CONFIG_USER_ONLY)
5905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5906 #else
5907 if (unlikely(!ctx->mem_idx)) {
5908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5909 return;
5910 }
5911 switch (rB(ctx->opcode)) {
5912 case 0:
5913 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5914 cpu_gpr[rS(ctx->opcode)]);
5915 break;
5916 case 1:
5917 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5918 cpu_gpr[rS(ctx->opcode)]);
5919 break;
5920 default:
5921 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5922 break;
5923 }
5924 #endif
5925 }
5926
5927 /* TLB management - PowerPC 440 implementation */
5928
5929 /* tlbre */
5930 static void gen_tlbre_440(DisasContext *ctx)
5931 {
5932 #if defined(CONFIG_USER_ONLY)
5933 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5934 #else
5935 if (unlikely(!ctx->mem_idx)) {
5936 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5937 return;
5938 }
5939 switch (rB(ctx->opcode)) {
5940 case 0:
5941 case 1:
5942 case 2:
5943 {
5944 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5945 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5946 t0, cpu_gpr[rA(ctx->opcode)]);
5947 tcg_temp_free_i32(t0);
5948 }
5949 break;
5950 default:
5951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5952 break;
5953 }
5954 #endif
5955 }
5956
5957 /* tlbsx - tlbsx. */
5958 static void gen_tlbsx_440(DisasContext *ctx)
5959 {
5960 #if defined(CONFIG_USER_ONLY)
5961 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5962 #else
5963 TCGv t0;
5964 if (unlikely(!ctx->mem_idx)) {
5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5966 return;
5967 }
5968 t0 = tcg_temp_new();
5969 gen_addr_reg_index(ctx, t0);
5970 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5971 tcg_temp_free(t0);
5972 if (Rc(ctx->opcode)) {
5973 int l1 = gen_new_label();
5974 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5975 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5976 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5977 gen_set_label(l1);
5978 }
5979 #endif
5980 }
5981
5982 /* tlbwe */
5983 static void gen_tlbwe_440(DisasContext *ctx)
5984 {
5985 #if defined(CONFIG_USER_ONLY)
5986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5987 #else
5988 if (unlikely(!ctx->mem_idx)) {
5989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5990 return;
5991 }
5992 switch (rB(ctx->opcode)) {
5993 case 0:
5994 case 1:
5995 case 2:
5996 {
5997 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5998 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5999 cpu_gpr[rS(ctx->opcode)]);
6000 tcg_temp_free_i32(t0);
6001 }
6002 break;
6003 default:
6004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6005 break;
6006 }
6007 #endif
6008 }
6009
6010 /* TLB management - PowerPC BookE 2.06 implementation */
6011
6012 /* tlbre */
6013 static void gen_tlbre_booke206(DisasContext *ctx)
6014 {
6015 #if defined(CONFIG_USER_ONLY)
6016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6017 #else
6018 if (unlikely(!ctx->mem_idx)) {
6019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6020 return;
6021 }
6022
6023 gen_helper_booke206_tlbre(cpu_env);
6024 #endif
6025 }
6026
6027 /* tlbsx - tlbsx. */
6028 static void gen_tlbsx_booke206(DisasContext *ctx)
6029 {
6030 #if defined(CONFIG_USER_ONLY)
6031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6032 #else
6033 TCGv t0;
6034 if (unlikely(!ctx->mem_idx)) {
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036 return;
6037 }
6038
6039 if (rA(ctx->opcode)) {
6040 t0 = tcg_temp_new();
6041 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6042 } else {
6043 t0 = tcg_const_tl(0);
6044 }
6045
6046 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6047 gen_helper_booke206_tlbsx(cpu_env, t0);
6048 #endif
6049 }
6050
6051 /* tlbwe */
6052 static void gen_tlbwe_booke206(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6056 #else
6057 if (unlikely(!ctx->mem_idx)) {
6058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6059 return;
6060 }
6061 gen_update_nip(ctx, ctx->nip - 4);
6062 gen_helper_booke206_tlbwe(cpu_env);
6063 #endif
6064 }
6065
6066 static void gen_tlbivax_booke206(DisasContext *ctx)
6067 {
6068 #if defined(CONFIG_USER_ONLY)
6069 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6070 #else
6071 TCGv t0;
6072 if (unlikely(!ctx->mem_idx)) {
6073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6074 return;
6075 }
6076
6077 t0 = tcg_temp_new();
6078 gen_addr_reg_index(ctx, t0);
6079
6080 gen_helper_booke206_tlbivax(cpu_env, t0);
6081 #endif
6082 }
6083
6084 static void gen_tlbilx_booke206(DisasContext *ctx)
6085 {
6086 #if defined(CONFIG_USER_ONLY)
6087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6088 #else
6089 TCGv t0;
6090 if (unlikely(!ctx->mem_idx)) {
6091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6092 return;
6093 }
6094
6095 t0 = tcg_temp_new();
6096 gen_addr_reg_index(ctx, t0);
6097
6098 switch((ctx->opcode >> 21) & 0x3) {
6099 case 0:
6100 gen_helper_booke206_tlbilx0(cpu_env, t0);
6101 break;
6102 case 1:
6103 gen_helper_booke206_tlbilx1(cpu_env, t0);
6104 break;
6105 case 3:
6106 gen_helper_booke206_tlbilx3(cpu_env, t0);
6107 break;
6108 default:
6109 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6110 break;
6111 }
6112
6113 tcg_temp_free(t0);
6114 #endif
6115 }
6116
6117
6118 /* wrtee */
6119 static void gen_wrtee(DisasContext *ctx)
6120 {
6121 #if defined(CONFIG_USER_ONLY)
6122 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6123 #else
6124 TCGv t0;
6125 if (unlikely(!ctx->mem_idx)) {
6126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6127 return;
6128 }
6129 t0 = tcg_temp_new();
6130 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6131 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6132 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6133 tcg_temp_free(t0);
6134 /* Stop translation to have a chance to raise an exception
6135 * if we just set msr_ee to 1
6136 */
6137 gen_stop_exception(ctx);
6138 #endif
6139 }
6140
6141 /* wrteei */
6142 static void gen_wrteei(DisasContext *ctx)
6143 {
6144 #if defined(CONFIG_USER_ONLY)
6145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6146 #else
6147 if (unlikely(!ctx->mem_idx)) {
6148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6149 return;
6150 }
6151 if (ctx->opcode & 0x00008000) {
6152 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6153 /* Stop translation to have a chance to raise an exception */
6154 gen_stop_exception(ctx);
6155 } else {
6156 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6157 }
6158 #endif
6159 }
6160
6161 /* PowerPC 440 specific instructions */
6162
6163 /* dlmzb */
6164 static void gen_dlmzb(DisasContext *ctx)
6165 {
6166 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6167 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6168 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6169 tcg_temp_free_i32(t0);
6170 }
6171
6172 /* mbar replaces eieio on 440 */
6173 static void gen_mbar(DisasContext *ctx)
6174 {
6175 /* interpreted as no-op */
6176 }
6177
6178 /* msync replaces sync on 440 */
6179 static void gen_msync_4xx(DisasContext *ctx)
6180 {
6181 /* interpreted as no-op */
6182 }
6183
6184 /* icbt */
6185 static void gen_icbt_440(DisasContext *ctx)
6186 {
6187 /* interpreted as no-op */
6188 /* XXX: specification say this is treated as a load by the MMU
6189 * but does not generate any exception
6190 */
6191 }
6192
6193 /* Embedded.Processor Control */
6194
6195 static void gen_msgclr(DisasContext *ctx)
6196 {
6197 #if defined(CONFIG_USER_ONLY)
6198 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6199 #else
6200 if (unlikely(ctx->mem_idx == 0)) {
6201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6202 return;
6203 }
6204
6205 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6206 #endif
6207 }
6208
6209 static void gen_msgsnd(DisasContext *ctx)
6210 {
6211 #if defined(CONFIG_USER_ONLY)
6212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6213 #else
6214 if (unlikely(ctx->mem_idx == 0)) {
6215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6216 return;
6217 }
6218
6219 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6220 #endif
6221 }
6222
6223 /*** Altivec vector extension ***/
6224 /* Altivec registers moves */
6225
6226 static inline TCGv_ptr gen_avr_ptr(int reg)
6227 {
6228 TCGv_ptr r = tcg_temp_new_ptr();
6229 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6230 return r;
6231 }
6232
6233 #define GEN_VR_LDX(name, opc2, opc3) \
6234 static void glue(gen_, name)(DisasContext *ctx) \
6235 { \
6236 TCGv EA; \
6237 if (unlikely(!ctx->altivec_enabled)) { \
6238 gen_exception(ctx, POWERPC_EXCP_VPU); \
6239 return; \
6240 } \
6241 gen_set_access_type(ctx, ACCESS_INT); \
6242 EA = tcg_temp_new(); \
6243 gen_addr_reg_index(ctx, EA); \
6244 tcg_gen_andi_tl(EA, EA, ~0xf); \
6245 if (ctx->le_mode) { \
6246 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6247 tcg_gen_addi_tl(EA, EA, 8); \
6248 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6249 } else { \
6250 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6251 tcg_gen_addi_tl(EA, EA, 8); \
6252 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6253 } \
6254 tcg_temp_free(EA); \
6255 }
6256
6257 #define GEN_VR_STX(name, opc2, opc3) \
6258 static void gen_st##name(DisasContext *ctx) \
6259 { \
6260 TCGv EA; \
6261 if (unlikely(!ctx->altivec_enabled)) { \
6262 gen_exception(ctx, POWERPC_EXCP_VPU); \
6263 return; \
6264 } \
6265 gen_set_access_type(ctx, ACCESS_INT); \
6266 EA = tcg_temp_new(); \
6267 gen_addr_reg_index(ctx, EA); \
6268 tcg_gen_andi_tl(EA, EA, ~0xf); \
6269 if (ctx->le_mode) { \
6270 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6271 tcg_gen_addi_tl(EA, EA, 8); \
6272 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6273 } else { \
6274 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6275 tcg_gen_addi_tl(EA, EA, 8); \
6276 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6277 } \
6278 tcg_temp_free(EA); \
6279 }
6280
6281 #define GEN_VR_LVE(name, opc2, opc3) \
6282 static void gen_lve##name(DisasContext *ctx) \
6283 { \
6284 TCGv EA; \
6285 TCGv_ptr rs; \
6286 if (unlikely(!ctx->altivec_enabled)) { \
6287 gen_exception(ctx, POWERPC_EXCP_VPU); \
6288 return; \
6289 } \
6290 gen_set_access_type(ctx, ACCESS_INT); \
6291 EA = tcg_temp_new(); \
6292 gen_addr_reg_index(ctx, EA); \
6293 rs = gen_avr_ptr(rS(ctx->opcode)); \
6294 gen_helper_lve##name(cpu_env, rs, EA); \
6295 tcg_temp_free(EA); \
6296 tcg_temp_free_ptr(rs); \
6297 }
6298
6299 #define GEN_VR_STVE(name, opc2, opc3) \
6300 static void gen_stve##name(DisasContext *ctx) \
6301 { \
6302 TCGv EA; \
6303 TCGv_ptr rs; \
6304 if (unlikely(!ctx->altivec_enabled)) { \
6305 gen_exception(ctx, POWERPC_EXCP_VPU); \
6306 return; \
6307 } \
6308 gen_set_access_type(ctx, ACCESS_INT); \
6309 EA = tcg_temp_new(); \
6310 gen_addr_reg_index(ctx, EA); \
6311 rs = gen_avr_ptr(rS(ctx->opcode)); \
6312 gen_helper_stve##name(cpu_env, rs, EA); \
6313 tcg_temp_free(EA); \
6314 tcg_temp_free_ptr(rs); \
6315 }
6316
6317 GEN_VR_LDX(lvx, 0x07, 0x03);
6318 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6319 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6320
6321 GEN_VR_LVE(bx, 0x07, 0x00);
6322 GEN_VR_LVE(hx, 0x07, 0x01);
6323 GEN_VR_LVE(wx, 0x07, 0x02);
6324
6325 GEN_VR_STX(svx, 0x07, 0x07);
6326 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6327 GEN_VR_STX(svxl, 0x07, 0x0F);
6328
6329 GEN_VR_STVE(bx, 0x07, 0x04);
6330 GEN_VR_STVE(hx, 0x07, 0x05);
6331 GEN_VR_STVE(wx, 0x07, 0x06);
6332
6333 static void gen_lvsl(DisasContext *ctx)
6334 {
6335 TCGv_ptr rd;
6336 TCGv EA;
6337 if (unlikely(!ctx->altivec_enabled)) {
6338 gen_exception(ctx, POWERPC_EXCP_VPU);
6339 return;
6340 }
6341 EA = tcg_temp_new();
6342 gen_addr_reg_index(ctx, EA);
6343 rd = gen_avr_ptr(rD(ctx->opcode));
6344 gen_helper_lvsl(rd, EA);
6345 tcg_temp_free(EA);
6346 tcg_temp_free_ptr(rd);
6347 }
6348
6349 static void gen_lvsr(DisasContext *ctx)
6350 {
6351 TCGv_ptr rd;
6352 TCGv EA;
6353 if (unlikely(!ctx->altivec_enabled)) {
6354 gen_exception(ctx, POWERPC_EXCP_VPU);
6355 return;
6356 }
6357 EA = tcg_temp_new();
6358 gen_addr_reg_index(ctx, EA);
6359 rd = gen_avr_ptr(rD(ctx->opcode));
6360 gen_helper_lvsr(rd, EA);
6361 tcg_temp_free(EA);
6362 tcg_temp_free_ptr(rd);
6363 }
6364
6365 static void gen_mfvscr(DisasContext *ctx)
6366 {
6367 TCGv_i32 t;
6368 if (unlikely(!ctx->altivec_enabled)) {
6369 gen_exception(ctx, POWERPC_EXCP_VPU);
6370 return;
6371 }
6372 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6373 t = tcg_temp_new_i32();
6374 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6375 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6376 tcg_temp_free_i32(t);
6377 }
6378
6379 static void gen_mtvscr(DisasContext *ctx)
6380 {
6381 TCGv_ptr p;
6382 if (unlikely(!ctx->altivec_enabled)) {
6383 gen_exception(ctx, POWERPC_EXCP_VPU);
6384 return;
6385 }
6386 p = gen_avr_ptr(rD(ctx->opcode));
6387 gen_helper_mtvscr(cpu_env, p);
6388 tcg_temp_free_ptr(p);
6389 }
6390
6391 /* Logical operations */
6392 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6393 static void glue(gen_, name)(DisasContext *ctx) \
6394 { \
6395 if (unlikely(!ctx->altivec_enabled)) { \
6396 gen_exception(ctx, POWERPC_EXCP_VPU); \
6397 return; \
6398 } \
6399 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6400 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6401 }
6402
6403 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6404 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6405 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6406 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6407 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6408
6409 #define GEN_VXFORM(name, opc2, opc3) \
6410 static void glue(gen_, name)(DisasContext *ctx) \
6411 { \
6412 TCGv_ptr ra, rb, rd; \
6413 if (unlikely(!ctx->altivec_enabled)) { \
6414 gen_exception(ctx, POWERPC_EXCP_VPU); \
6415 return; \
6416 } \
6417 ra = gen_avr_ptr(rA(ctx->opcode)); \
6418 rb = gen_avr_ptr(rB(ctx->opcode)); \
6419 rd = gen_avr_ptr(rD(ctx->opcode)); \
6420 gen_helper_##name (rd, ra, rb); \
6421 tcg_temp_free_ptr(ra); \
6422 tcg_temp_free_ptr(rb); \
6423 tcg_temp_free_ptr(rd); \
6424 }
6425
6426 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6427 static void glue(gen_, name)(DisasContext *ctx) \
6428 { \
6429 TCGv_ptr ra, rb, rd; \
6430 if (unlikely(!ctx->altivec_enabled)) { \
6431 gen_exception(ctx, POWERPC_EXCP_VPU); \
6432 return; \
6433 } \
6434 ra = gen_avr_ptr(rA(ctx->opcode)); \
6435 rb = gen_avr_ptr(rB(ctx->opcode)); \
6436 rd = gen_avr_ptr(rD(ctx->opcode)); \
6437 gen_helper_##name(cpu_env, rd, ra, rb); \
6438 tcg_temp_free_ptr(ra); \
6439 tcg_temp_free_ptr(rb); \
6440 tcg_temp_free_ptr(rd); \
6441 }
6442
6443 GEN_VXFORM(vaddubm, 0, 0);
6444 GEN_VXFORM(vadduhm, 0, 1);
6445 GEN_VXFORM(vadduwm, 0, 2);
6446 GEN_VXFORM(vsububm, 0, 16);
6447 GEN_VXFORM(vsubuhm, 0, 17);
6448 GEN_VXFORM(vsubuwm, 0, 18);
6449 GEN_VXFORM(vmaxub, 1, 0);
6450 GEN_VXFORM(vmaxuh, 1, 1);
6451 GEN_VXFORM(vmaxuw, 1, 2);
6452 GEN_VXFORM(vmaxsb, 1, 4);
6453 GEN_VXFORM(vmaxsh, 1, 5);
6454 GEN_VXFORM(vmaxsw, 1, 6);
6455 GEN_VXFORM(vminub, 1, 8);
6456 GEN_VXFORM(vminuh, 1, 9);
6457 GEN_VXFORM(vminuw, 1, 10);
6458 GEN_VXFORM(vminsb, 1, 12);
6459 GEN_VXFORM(vminsh, 1, 13);
6460 GEN_VXFORM(vminsw, 1, 14);
6461 GEN_VXFORM(vavgub, 1, 16);
6462 GEN_VXFORM(vavguh, 1, 17);
6463 GEN_VXFORM(vavguw, 1, 18);
6464 GEN_VXFORM(vavgsb, 1, 20);
6465 GEN_VXFORM(vavgsh, 1, 21);
6466 GEN_VXFORM(vavgsw, 1, 22);
6467 GEN_VXFORM(vmrghb, 6, 0);
6468 GEN_VXFORM(vmrghh, 6, 1);
6469 GEN_VXFORM(vmrghw, 6, 2);
6470 GEN_VXFORM(vmrglb, 6, 4);
6471 GEN_VXFORM(vmrglh, 6, 5);
6472 GEN_VXFORM(vmrglw, 6, 6);
6473 GEN_VXFORM(vmuloub, 4, 0);
6474 GEN_VXFORM(vmulouh, 4, 1);
6475 GEN_VXFORM(vmulosb, 4, 4);
6476 GEN_VXFORM(vmulosh, 4, 5);
6477 GEN_VXFORM(vmuleub, 4, 8);
6478 GEN_VXFORM(vmuleuh, 4, 9);
6479 GEN_VXFORM(vmulesb, 4, 12);
6480 GEN_VXFORM(vmulesh, 4, 13);
6481 GEN_VXFORM(vslb, 2, 4);
6482 GEN_VXFORM(vslh, 2, 5);
6483 GEN_VXFORM(vslw, 2, 6);
6484 GEN_VXFORM(vsrb, 2, 8);
6485 GEN_VXFORM(vsrh, 2, 9);
6486 GEN_VXFORM(vsrw, 2, 10);
6487 GEN_VXFORM(vsrab, 2, 12);
6488 GEN_VXFORM(vsrah, 2, 13);
6489 GEN_VXFORM(vsraw, 2, 14);
6490 GEN_VXFORM(vslo, 6, 16);
6491 GEN_VXFORM(vsro, 6, 17);
6492 GEN_VXFORM(vaddcuw, 0, 6);
6493 GEN_VXFORM(vsubcuw, 0, 22);
6494 GEN_VXFORM_ENV(vaddubs, 0, 8);
6495 GEN_VXFORM_ENV(vadduhs, 0, 9);
6496 GEN_VXFORM_ENV(vadduws, 0, 10);
6497 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6498 GEN_VXFORM_ENV(vaddshs, 0, 13);
6499 GEN_VXFORM_ENV(vaddsws, 0, 14);
6500 GEN_VXFORM_ENV(vsububs, 0, 24);
6501 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6502 GEN_VXFORM_ENV(vsubuws, 0, 26);
6503 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6504 GEN_VXFORM_ENV(vsubshs, 0, 29);
6505 GEN_VXFORM_ENV(vsubsws, 0, 30);
6506 GEN_VXFORM(vrlb, 2, 0);
6507 GEN_VXFORM(vrlh, 2, 1);
6508 GEN_VXFORM(vrlw, 2, 2);
6509 GEN_VXFORM(vsl, 2, 7);
6510 GEN_VXFORM(vsr, 2, 11);
6511 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6512 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6513 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6514 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6515 GEN_VXFORM_ENV(vpkshus, 7, 4);
6516 GEN_VXFORM_ENV(vpkswus, 7, 5);
6517 GEN_VXFORM_ENV(vpkshss, 7, 6);
6518 GEN_VXFORM_ENV(vpkswss, 7, 7);
6519 GEN_VXFORM(vpkpx, 7, 12);
6520 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6521 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6522 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6523 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6524 GEN_VXFORM_ENV(vsumsws, 4, 30);
6525 GEN_VXFORM_ENV(vaddfp, 5, 0);
6526 GEN_VXFORM_ENV(vsubfp, 5, 1);
6527 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6528 GEN_VXFORM_ENV(vminfp, 5, 17);
6529
6530 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6531 static void glue(gen_, name)(DisasContext *ctx) \
6532 { \
6533 TCGv_ptr ra, rb, rd; \
6534 if (unlikely(!ctx->altivec_enabled)) { \
6535 gen_exception(ctx, POWERPC_EXCP_VPU); \
6536 return; \
6537 } \
6538 ra = gen_avr_ptr(rA(ctx->opcode)); \
6539 rb = gen_avr_ptr(rB(ctx->opcode)); \
6540 rd = gen_avr_ptr(rD(ctx->opcode)); \
6541 gen_helper_##opname(cpu_env, rd, ra, rb); \
6542 tcg_temp_free_ptr(ra); \
6543 tcg_temp_free_ptr(rb); \
6544 tcg_temp_free_ptr(rd); \
6545 }
6546
6547 #define GEN_VXRFORM(name, opc2, opc3) \
6548 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6549 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6550
6551 GEN_VXRFORM(vcmpequb, 3, 0)
6552 GEN_VXRFORM(vcmpequh, 3, 1)
6553 GEN_VXRFORM(vcmpequw, 3, 2)
6554 GEN_VXRFORM(vcmpgtsb, 3, 12)
6555 GEN_VXRFORM(vcmpgtsh, 3, 13)
6556 GEN_VXRFORM(vcmpgtsw, 3, 14)
6557 GEN_VXRFORM(vcmpgtub, 3, 8)
6558 GEN_VXRFORM(vcmpgtuh, 3, 9)
6559 GEN_VXRFORM(vcmpgtuw, 3, 10)
6560 GEN_VXRFORM(vcmpeqfp, 3, 3)
6561 GEN_VXRFORM(vcmpgefp, 3, 7)
6562 GEN_VXRFORM(vcmpgtfp, 3, 11)
6563 GEN_VXRFORM(vcmpbfp, 3, 15)
6564
6565 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6566 static void glue(gen_, name)(DisasContext *ctx) \
6567 { \
6568 TCGv_ptr rd; \
6569 TCGv_i32 simm; \
6570 if (unlikely(!ctx->altivec_enabled)) { \
6571 gen_exception(ctx, POWERPC_EXCP_VPU); \
6572 return; \
6573 } \
6574 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6575 rd = gen_avr_ptr(rD(ctx->opcode)); \
6576 gen_helper_##name (rd, simm); \
6577 tcg_temp_free_i32(simm); \
6578 tcg_temp_free_ptr(rd); \
6579 }
6580
6581 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6582 GEN_VXFORM_SIMM(vspltish, 6, 13);
6583 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6584
6585 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6586 static void glue(gen_, name)(DisasContext *ctx) \
6587 { \
6588 TCGv_ptr rb, rd; \
6589 if (unlikely(!ctx->altivec_enabled)) { \
6590 gen_exception(ctx, POWERPC_EXCP_VPU); \
6591 return; \
6592 } \
6593 rb = gen_avr_ptr(rB(ctx->opcode)); \
6594 rd = gen_avr_ptr(rD(ctx->opcode)); \
6595 gen_helper_##name (rd, rb); \
6596 tcg_temp_free_ptr(rb); \
6597 tcg_temp_free_ptr(rd); \
6598 }
6599
6600 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6601 static void glue(gen_, name)(DisasContext *ctx) \
6602 { \
6603 TCGv_ptr rb, rd; \
6604 \
6605 if (unlikely(!ctx->altivec_enabled)) { \
6606 gen_exception(ctx, POWERPC_EXCP_VPU); \
6607 return; \
6608 } \
6609 rb = gen_avr_ptr(rB(ctx->opcode)); \
6610 rd = gen_avr_ptr(rD(ctx->opcode)); \
6611 gen_helper_##name(cpu_env, rd, rb); \
6612 tcg_temp_free_ptr(rb); \
6613 tcg_temp_free_ptr(rd); \
6614 }
6615
6616 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6617 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6618 GEN_VXFORM_NOA(vupklsb, 7, 10);
6619 GEN_VXFORM_NOA(vupklsh, 7, 11);
6620 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6621 GEN_VXFORM_NOA(vupklpx, 7, 15);
6622 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6623 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6624 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6625 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6626 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6627 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6628 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6629 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6630
6631 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6632 static void glue(gen_, name)(DisasContext *ctx) \
6633 { \
6634 TCGv_ptr rd; \
6635 TCGv_i32 simm; \
6636 if (unlikely(!ctx->altivec_enabled)) { \
6637 gen_exception(ctx, POWERPC_EXCP_VPU); \
6638 return; \
6639 } \
6640 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6641 rd = gen_avr_ptr(rD(ctx->opcode)); \
6642 gen_helper_##name (rd, simm); \
6643 tcg_temp_free_i32(simm); \
6644 tcg_temp_free_ptr(rd); \
6645 }
6646
6647 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6648 static void glue(gen_, name)(DisasContext *ctx) \
6649 { \
6650 TCGv_ptr rb, rd; \
6651 TCGv_i32 uimm; \
6652 if (unlikely(!ctx->altivec_enabled)) { \
6653 gen_exception(ctx, POWERPC_EXCP_VPU); \
6654 return; \
6655 } \
6656 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6657 rb = gen_avr_ptr(rB(ctx->opcode)); \
6658 rd = gen_avr_ptr(rD(ctx->opcode)); \
6659 gen_helper_##name (rd, rb, uimm); \
6660 tcg_temp_free_i32(uimm); \
6661 tcg_temp_free_ptr(rb); \
6662 tcg_temp_free_ptr(rd); \
6663 }
6664
6665 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6666 static void glue(gen_, name)(DisasContext *ctx) \
6667 { \
6668 TCGv_ptr rb, rd; \
6669 TCGv_i32 uimm; \
6670 \
6671 if (unlikely(!ctx->altivec_enabled)) { \
6672 gen_exception(ctx, POWERPC_EXCP_VPU); \
6673 return; \
6674 } \
6675 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6676 rb = gen_avr_ptr(rB(ctx->opcode)); \
6677 rd = gen_avr_ptr(rD(ctx->opcode)); \
6678 gen_helper_##name(cpu_env, rd, rb, uimm); \
6679 tcg_temp_free_i32(uimm); \
6680 tcg_temp_free_ptr(rb); \
6681 tcg_temp_free_ptr(rd); \
6682 }
6683
6684 GEN_VXFORM_UIMM(vspltb, 6, 8);
6685 GEN_VXFORM_UIMM(vsplth, 6, 9);
6686 GEN_VXFORM_UIMM(vspltw, 6, 10);
6687 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6688 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6689 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6690 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6691
6692 static void gen_vsldoi(DisasContext *ctx)
6693 {
6694 TCGv_ptr ra, rb, rd;
6695 TCGv_i32 sh;
6696 if (unlikely(!ctx->altivec_enabled)) {
6697 gen_exception(ctx, POWERPC_EXCP_VPU);
6698 return;
6699 }
6700 ra = gen_avr_ptr(rA(ctx->opcode));
6701 rb = gen_avr_ptr(rB(ctx->opcode));
6702 rd = gen_avr_ptr(rD(ctx->opcode));
6703 sh = tcg_const_i32(VSH(ctx->opcode));
6704 gen_helper_vsldoi (rd, ra, rb, sh);
6705 tcg_temp_free_ptr(ra);
6706 tcg_temp_free_ptr(rb);
6707 tcg_temp_free_ptr(rd);
6708 tcg_temp_free_i32(sh);
6709 }
6710
6711 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6712 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6713 { \
6714 TCGv_ptr ra, rb, rc, rd; \
6715 if (unlikely(!ctx->altivec_enabled)) { \
6716 gen_exception(ctx, POWERPC_EXCP_VPU); \
6717 return; \
6718 } \
6719 ra = gen_avr_ptr(rA(ctx->opcode)); \
6720 rb = gen_avr_ptr(rB(ctx->opcode)); \
6721 rc = gen_avr_ptr(rC(ctx->opcode)); \
6722 rd = gen_avr_ptr(rD(ctx->opcode)); \
6723 if (Rc(ctx->opcode)) { \
6724 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6725 } else { \
6726 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6727 } \
6728 tcg_temp_free_ptr(ra); \
6729 tcg_temp_free_ptr(rb); \
6730 tcg_temp_free_ptr(rc); \
6731 tcg_temp_free_ptr(rd); \
6732 }
6733
6734 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6735
6736 static void gen_vmladduhm(DisasContext *ctx)
6737 {
6738 TCGv_ptr ra, rb, rc, rd;
6739 if (unlikely(!ctx->altivec_enabled)) {
6740 gen_exception(ctx, POWERPC_EXCP_VPU);
6741 return;
6742 }
6743 ra = gen_avr_ptr(rA(ctx->opcode));
6744 rb = gen_avr_ptr(rB(ctx->opcode));
6745 rc = gen_avr_ptr(rC(ctx->opcode));
6746 rd = gen_avr_ptr(rD(ctx->opcode));
6747 gen_helper_vmladduhm(rd, ra, rb, rc);
6748 tcg_temp_free_ptr(ra);
6749 tcg_temp_free_ptr(rb);
6750 tcg_temp_free_ptr(rc);
6751 tcg_temp_free_ptr(rd);
6752 }
6753
6754 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6755 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6756 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6757 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6758 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6759
6760 /*** SPE extension ***/
6761 /* Register moves */
6762
6763
6764 static inline void gen_evmra(DisasContext *ctx)
6765 {
6766
6767 if (unlikely(!ctx->spe_enabled)) {
6768 gen_exception(ctx, POWERPC_EXCP_SPEU);
6769 return;
6770 }
6771
6772 #if defined(TARGET_PPC64)
6773 /* rD := rA */
6774 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6775
6776 /* spe_acc := rA */
6777 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6778 cpu_env,
6779 offsetof(CPUPPCState, spe_acc));
6780 #else
6781 TCGv_i64 tmp = tcg_temp_new_i64();
6782
6783 /* tmp := rA_lo + rA_hi << 32 */
6784 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6785
6786 /* spe_acc := tmp */
6787 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6788 tcg_temp_free_i64(tmp);
6789
6790 /* rD := rA */
6791 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6792 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6793 #endif
6794 }
6795
6796 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6797 {
6798 #if defined(TARGET_PPC64)
6799 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6800 #else
6801 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6802 #endif
6803 }
6804
6805 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6806 {
6807 #if defined(TARGET_PPC64)
6808 tcg_gen_mov_i64(cpu_gpr[reg], t);
6809 #else
6810 TCGv_i64 tmp = tcg_temp_new_i64();
6811 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6812 tcg_gen_shri_i64(tmp, t, 32);
6813 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6814 tcg_temp_free_i64(tmp);
6815 #endif
6816 }
6817
6818 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6819 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6820 { \
6821 if (Rc(ctx->opcode)) \
6822 gen_##name1(ctx); \
6823 else \
6824 gen_##name0(ctx); \
6825 }
6826
6827 /* Handler for undefined SPE opcodes */
6828 static inline void gen_speundef(DisasContext *ctx)
6829 {
6830 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6831 }
6832
6833 /* SPE logic */
6834 #if defined(TARGET_PPC64)
6835 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6836 static inline void gen_##name(DisasContext *ctx) \
6837 { \
6838 if (unlikely(!ctx->spe_enabled)) { \
6839 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6840 return; \
6841 } \
6842 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6843 cpu_gpr[rB(ctx->opcode)]); \
6844 }
6845 #else
6846 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6847 static inline void gen_##name(DisasContext *ctx) \
6848 { \
6849 if (unlikely(!ctx->spe_enabled)) { \
6850 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6851 return; \
6852 } \
6853 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6854 cpu_gpr[rB(ctx->opcode)]); \
6855 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6856 cpu_gprh[rB(ctx->opcode)]); \
6857 }
6858 #endif
6859
6860 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6861 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6862 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6863 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6864 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6865 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6866 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6867 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6868
6869 /* SPE logic immediate */
6870 #if defined(TARGET_PPC64)
6871 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6872 static inline void gen_##name(DisasContext *ctx) \
6873 { \
6874 if (unlikely(!ctx->spe_enabled)) { \
6875 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6876 return; \
6877 } \
6878 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6879 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6880 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6881 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6882 tcg_opi(t0, t0, rB(ctx->opcode)); \
6883 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6884 tcg_gen_trunc_i64_i32(t1, t2); \
6885 tcg_temp_free_i64(t2); \
6886 tcg_opi(t1, t1, rB(ctx->opcode)); \
6887 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6888 tcg_temp_free_i32(t0); \
6889 tcg_temp_free_i32(t1); \
6890 }
6891 #else
6892 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6893 static inline void gen_##name(DisasContext *ctx) \
6894 { \
6895 if (unlikely(!ctx->spe_enabled)) { \
6896 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6897 return; \
6898 } \
6899 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6900 rB(ctx->opcode)); \
6901 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6902 rB(ctx->opcode)); \
6903 }
6904 #endif
6905 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6906 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6907 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6908 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6909
6910 /* SPE arithmetic */
6911 #if defined(TARGET_PPC64)
6912 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6913 static inline void gen_##name(DisasContext *ctx) \
6914 { \
6915 if (unlikely(!ctx->spe_enabled)) { \
6916 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6917 return; \
6918 } \
6919 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6920 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6921 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6922 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6923 tcg_op(t0, t0); \
6924 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6925 tcg_gen_trunc_i64_i32(t1, t2); \
6926 tcg_temp_free_i64(t2); \
6927 tcg_op(t1, t1); \
6928 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6929 tcg_temp_free_i32(t0); \
6930 tcg_temp_free_i32(t1); \
6931 }
6932 #else
6933 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6934 static inline void gen_##name(DisasContext *ctx) \
6935 { \
6936 if (unlikely(!ctx->spe_enabled)) { \
6937 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6938 return; \
6939 } \
6940 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6941 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6942 }
6943 #endif
6944
6945 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6946 {
6947 int l1 = gen_new_label();
6948 int l2 = gen_new_label();
6949
6950 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6951 tcg_gen_neg_i32(ret, arg1);
6952 tcg_gen_br(l2);
6953 gen_set_label(l1);
6954 tcg_gen_mov_i32(ret, arg1);
6955 gen_set_label(l2);
6956 }
6957 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6958 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6959 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6960 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6961 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6962 {
6963 tcg_gen_addi_i32(ret, arg1, 0x8000);
6964 tcg_gen_ext16u_i32(ret, ret);
6965 }
6966 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6967 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6968 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6969
6970 #if defined(TARGET_PPC64)
6971 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6972 static inline void gen_##name(DisasContext *ctx) \
6973 { \
6974 if (unlikely(!ctx->spe_enabled)) { \
6975 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6976 return; \
6977 } \
6978 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6979 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6980 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6981 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6982 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6983 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6984 tcg_op(t0, t0, t2); \
6985 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6986 tcg_gen_trunc_i64_i32(t1, t3); \
6987 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6988 tcg_gen_trunc_i64_i32(t2, t3); \
6989 tcg_temp_free_i64(t3); \
6990 tcg_op(t1, t1, t2); \
6991 tcg_temp_free_i32(t2); \
6992 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6993 tcg_temp_free_i32(t0); \
6994 tcg_temp_free_i32(t1); \
6995 }
6996 #else
6997 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6998 static inline void gen_##name(DisasContext *ctx) \
6999 { \
7000 if (unlikely(!ctx->spe_enabled)) { \
7001 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7002 return; \
7003 } \
7004 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7005 cpu_gpr[rB(ctx->opcode)]); \
7006 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7007 cpu_gprh[rB(ctx->opcode)]); \
7008 }
7009 #endif
7010
7011 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7012 {
7013 TCGv_i32 t0;
7014 int l1, l2;
7015
7016 l1 = gen_new_label();
7017 l2 = gen_new_label();
7018 t0 = tcg_temp_local_new_i32();
7019 /* No error here: 6 bits are used */
7020 tcg_gen_andi_i32(t0, arg2, 0x3F);
7021 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7022 tcg_gen_shr_i32(ret, arg1, t0);
7023 tcg_gen_br(l2);
7024 gen_set_label(l1);
7025 tcg_gen_movi_i32(ret, 0);
7026 gen_set_label(l2);
7027 tcg_temp_free_i32(t0);
7028 }
7029 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7030 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7031 {
7032 TCGv_i32 t0;
7033 int l1, l2;
7034
7035 l1 = gen_new_label();
7036 l2 = gen_new_label();
7037 t0 = tcg_temp_local_new_i32();
7038 /* No error here: 6 bits are used */
7039 tcg_gen_andi_i32(t0, arg2, 0x3F);
7040 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7041 tcg_gen_sar_i32(ret, arg1, t0);
7042 tcg_gen_br(l2);
7043 gen_set_label(l1);
7044 tcg_gen_movi_i32(ret, 0);
7045 gen_set_label(l2);
7046 tcg_temp_free_i32(t0);
7047 }
7048 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7049 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7050 {
7051 TCGv_i32 t0;
7052 int l1, l2;
7053
7054 l1 = gen_new_label();
7055 l2 = gen_new_label();
7056 t0 = tcg_temp_local_new_i32();
7057 /* No error here: 6 bits are used */
7058 tcg_gen_andi_i32(t0, arg2, 0x3F);
7059 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7060 tcg_gen_shl_i32(ret, arg1, t0);
7061 tcg_gen_br(l2);
7062 gen_set_label(l1);
7063 tcg_gen_movi_i32(ret, 0);
7064 gen_set_label(l2);
7065 tcg_temp_free_i32(t0);
7066 }
7067 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7068 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7069 {
7070 TCGv_i32 t0 = tcg_temp_new_i32();
7071 tcg_gen_andi_i32(t0, arg2, 0x1F);
7072 tcg_gen_rotl_i32(ret, arg1, t0);
7073 tcg_temp_free_i32(t0);
7074 }
7075 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7076 static inline void gen_evmergehi(DisasContext *ctx)
7077 {
7078 if (unlikely(!ctx->spe_enabled)) {
7079 gen_exception(ctx, POWERPC_EXCP_SPEU);
7080 return;
7081 }
7082 #if defined(TARGET_PPC64)
7083 TCGv t0 = tcg_temp_new();
7084 TCGv t1 = tcg_temp_new();
7085 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7086 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7087 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7088 tcg_temp_free(t0);
7089 tcg_temp_free(t1);
7090 #else
7091 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7092 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7093 #endif
7094 }
7095 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7096 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7097 {
7098 tcg_gen_sub_i32(ret, arg2, arg1);
7099 }
7100 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7101
7102 /* SPE arithmetic immediate */
7103 #if defined(TARGET_PPC64)
7104 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7105 static inline void gen_##name(DisasContext *ctx) \
7106 { \
7107 if (unlikely(!ctx->spe_enabled)) { \
7108 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7109 return; \
7110 } \
7111 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7112 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7113 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7114 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7115 tcg_op(t0, t0, rA(ctx->opcode)); \
7116 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7117 tcg_gen_trunc_i64_i32(t1, t2); \
7118 tcg_temp_free_i64(t2); \
7119 tcg_op(t1, t1, rA(ctx->opcode)); \
7120 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7121 tcg_temp_free_i32(t0); \
7122 tcg_temp_free_i32(t1); \
7123 }
7124 #else
7125 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7126 static inline void gen_##name(DisasContext *ctx) \
7127 { \
7128 if (unlikely(!ctx->spe_enabled)) { \
7129 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7130 return; \
7131 } \
7132 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7133 rA(ctx->opcode)); \
7134 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7135 rA(ctx->opcode)); \
7136 }
7137 #endif
7138 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7139 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7140
7141 /* SPE comparison */
7142 #if defined(TARGET_PPC64)
7143 #define GEN_SPEOP_COMP(name, tcg_cond) \
7144 static inline void gen_##name(DisasContext *ctx) \
7145 { \
7146 if (unlikely(!ctx->spe_enabled)) { \
7147 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7148 return; \
7149 } \
7150 int l1 = gen_new_label(); \
7151 int l2 = gen_new_label(); \
7152 int l3 = gen_new_label(); \
7153 int l4 = gen_new_label(); \
7154 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7155 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7156 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7157 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7158 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7159 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7160 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7161 tcg_gen_br(l2); \
7162 gen_set_label(l1); \
7163 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7164 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7165 gen_set_label(l2); \
7166 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7167 tcg_gen_trunc_i64_i32(t0, t2); \
7168 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7169 tcg_gen_trunc_i64_i32(t1, t2); \
7170 tcg_temp_free_i64(t2); \
7171 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7172 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7173 ~(CRF_CH | CRF_CH_AND_CL)); \
7174 tcg_gen_br(l4); \
7175 gen_set_label(l3); \
7176 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7177 CRF_CH | CRF_CH_OR_CL); \
7178 gen_set_label(l4); \
7179 tcg_temp_free_i32(t0); \
7180 tcg_temp_free_i32(t1); \
7181 }
7182 #else
7183 #define GEN_SPEOP_COMP(name, tcg_cond) \
7184 static inline void gen_##name(DisasContext *ctx) \
7185 { \
7186 if (unlikely(!ctx->spe_enabled)) { \
7187 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7188 return; \
7189 } \
7190 int l1 = gen_new_label(); \
7191 int l2 = gen_new_label(); \
7192 int l3 = gen_new_label(); \
7193 int l4 = gen_new_label(); \
7194 \
7195 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7196 cpu_gpr[rB(ctx->opcode)], l1); \
7197 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7198 tcg_gen_br(l2); \
7199 gen_set_label(l1); \
7200 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7201 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7202 gen_set_label(l2); \
7203 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7204 cpu_gprh[rB(ctx->opcode)], l3); \
7205 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7206 ~(CRF_CH | CRF_CH_AND_CL)); \
7207 tcg_gen_br(l4); \
7208 gen_set_label(l3); \
7209 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7210 CRF_CH | CRF_CH_OR_CL); \
7211 gen_set_label(l4); \
7212 }
7213 #endif
7214 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7215 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7216 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7217 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7218 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7219
7220 /* SPE misc */
7221 static inline void gen_brinc(DisasContext *ctx)
7222 {
7223 /* Note: brinc is usable even if SPE is disabled */
7224 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7225 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7226 }
7227 static inline void gen_evmergelo(DisasContext *ctx)
7228 {
7229 if (unlikely(!ctx->spe_enabled)) {
7230 gen_exception(ctx, POWERPC_EXCP_SPEU);
7231 return;
7232 }
7233 #if defined(TARGET_PPC64)
7234 TCGv t0 = tcg_temp_new();
7235 TCGv t1 = tcg_temp_new();
7236 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7237 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7238 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7239 tcg_temp_free(t0);
7240 tcg_temp_free(t1);
7241 #else
7242 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7243 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7244 #endif
7245 }
7246 static inline void gen_evmergehilo(DisasContext *ctx)
7247 {
7248 if (unlikely(!ctx->spe_enabled)) {
7249 gen_exception(ctx, POWERPC_EXCP_SPEU);
7250 return;
7251 }
7252 #if defined(TARGET_PPC64)
7253 TCGv t0 = tcg_temp_new();
7254 TCGv t1 = tcg_temp_new();
7255 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7256 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7257 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7258 tcg_temp_free(t0);
7259 tcg_temp_free(t1);
7260 #else
7261 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7262 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7263 #endif
7264 }
7265 static inline void gen_evmergelohi(DisasContext *ctx)
7266 {
7267 if (unlikely(!ctx->spe_enabled)) {
7268 gen_exception(ctx, POWERPC_EXCP_SPEU);
7269 return;
7270 }
7271 #if defined(TARGET_PPC64)
7272 TCGv t0 = tcg_temp_new();
7273 TCGv t1 = tcg_temp_new();
7274 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7275 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7276 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7277 tcg_temp_free(t0);
7278 tcg_temp_free(t1);
7279 #else
7280 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7281 TCGv_i32 tmp = tcg_temp_new_i32();
7282 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7283 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7284 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7285 tcg_temp_free_i32(tmp);
7286 } else {
7287 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7288 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7289 }
7290 #endif
7291 }
7292 static inline void gen_evsplati(DisasContext *ctx)
7293 {
7294 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7295
7296 #if defined(TARGET_PPC64)
7297 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7298 #else
7299 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7300 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7301 #endif
7302 }
7303 static inline void gen_evsplatfi(DisasContext *ctx)
7304 {
7305 uint64_t imm = rA(ctx->opcode) << 27;
7306
7307 #if defined(TARGET_PPC64)
7308 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7309 #else
7310 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7311 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7312 #endif
7313 }
7314
7315 static inline void gen_evsel(DisasContext *ctx)
7316 {
7317 int l1 = gen_new_label();
7318 int l2 = gen_new_label();
7319 int l3 = gen_new_label();
7320 int l4 = gen_new_label();
7321 TCGv_i32 t0 = tcg_temp_local_new_i32();
7322 #if defined(TARGET_PPC64)
7323 TCGv t1 = tcg_temp_local_new();
7324 TCGv t2 = tcg_temp_local_new();
7325 #endif
7326 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7327 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7328 #if defined(TARGET_PPC64)
7329 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7330 #else
7331 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7332 #endif
7333 tcg_gen_br(l2);
7334 gen_set_label(l1);
7335 #if defined(TARGET_PPC64)
7336 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7337 #else
7338 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7339 #endif
7340 gen_set_label(l2);
7341 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7342 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7343 #if defined(TARGET_PPC64)
7344 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7345 #else
7346 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7347 #endif
7348 tcg_gen_br(l4);
7349 gen_set_label(l3);
7350 #if defined(TARGET_PPC64)
7351 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7352 #else
7353 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7354 #endif
7355 gen_set_label(l4);
7356 tcg_temp_free_i32(t0);
7357 #if defined(TARGET_PPC64)
7358 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7359 tcg_temp_free(t1);
7360 tcg_temp_free(t2);
7361 #endif
7362 }
7363
7364 static void gen_evsel0(DisasContext *ctx)
7365 {
7366 gen_evsel(ctx);
7367 }
7368
7369 static void gen_evsel1(DisasContext *ctx)
7370 {
7371 gen_evsel(ctx);
7372 }
7373
7374 static void gen_evsel2(DisasContext *ctx)
7375 {
7376 gen_evsel(ctx);
7377 }
7378
7379 static void gen_evsel3(DisasContext *ctx)
7380 {
7381 gen_evsel(ctx);
7382 }
7383
7384 /* Multiply */
7385
7386 static inline void gen_evmwumi(DisasContext *ctx)
7387 {
7388 TCGv_i64 t0, t1;
7389
7390 if (unlikely(!ctx->spe_enabled)) {
7391 gen_exception(ctx, POWERPC_EXCP_SPEU);
7392 return;
7393 }
7394
7395 t0 = tcg_temp_new_i64();
7396 t1 = tcg_temp_new_i64();
7397
7398 /* t0 := rA; t1 := rB */
7399 #if defined(TARGET_PPC64)
7400 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7401 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7402 #else
7403 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7404 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7405 #endif
7406
7407 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7408
7409 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7410
7411 tcg_temp_free_i64(t0);
7412 tcg_temp_free_i64(t1);
7413 }
7414
7415 static inline void gen_evmwumia(DisasContext *ctx)
7416 {
7417 TCGv_i64 tmp;
7418
7419 if (unlikely(!ctx->spe_enabled)) {
7420 gen_exception(ctx, POWERPC_EXCP_SPEU);
7421 return;
7422 }
7423
7424 gen_evmwumi(ctx); /* rD := rA * rB */
7425
7426 tmp = tcg_temp_new_i64();
7427
7428 /* acc := rD */
7429 gen_load_gpr64(tmp, rD(ctx->opcode));
7430 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7431 tcg_temp_free_i64(tmp);
7432 }
7433
7434 static inline void gen_evmwumiaa(DisasContext *ctx)
7435 {
7436 TCGv_i64 acc;
7437 TCGv_i64 tmp;
7438
7439 if (unlikely(!ctx->spe_enabled)) {
7440 gen_exception(ctx, POWERPC_EXCP_SPEU);
7441 return;
7442 }
7443
7444 gen_evmwumi(ctx); /* rD := rA * rB */
7445
7446 acc = tcg_temp_new_i64();
7447 tmp = tcg_temp_new_i64();
7448
7449 /* tmp := rD */
7450 gen_load_gpr64(tmp, rD(ctx->opcode));
7451
7452 /* Load acc */
7453 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7454
7455 /* acc := tmp + acc */
7456 tcg_gen_add_i64(acc, acc, tmp);
7457
7458 /* Store acc */
7459 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7460
7461 /* rD := acc */
7462 gen_store_gpr64(rD(ctx->opcode), acc);
7463
7464 tcg_temp_free_i64(acc);
7465 tcg_temp_free_i64(tmp);
7466 }
7467
7468 static inline void gen_evmwsmi(DisasContext *ctx)
7469 {
7470 TCGv_i64 t0, t1;
7471
7472 if (unlikely(!ctx->spe_enabled)) {
7473 gen_exception(ctx, POWERPC_EXCP_SPEU);
7474 return;
7475 }
7476
7477 t0 = tcg_temp_new_i64();
7478 t1 = tcg_temp_new_i64();
7479
7480 /* t0 := rA; t1 := rB */
7481 #if defined(TARGET_PPC64)
7482 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7483 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7484 #else
7485 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7486 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7487 #endif
7488
7489 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7490
7491 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7492
7493 tcg_temp_free_i64(t0);
7494 tcg_temp_free_i64(t1);
7495 }
7496
7497 static inline void gen_evmwsmia(DisasContext *ctx)
7498 {
7499 TCGv_i64 tmp;
7500
7501 gen_evmwsmi(ctx); /* rD := rA * rB */
7502
7503 tmp = tcg_temp_new_i64();
7504
7505 /* acc := rD */
7506 gen_load_gpr64(tmp, rD(ctx->opcode));
7507 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7508
7509 tcg_temp_free_i64(tmp);
7510 }
7511
7512 static inline void gen_evmwsmiaa(DisasContext *ctx)
7513 {
7514 TCGv_i64 acc = tcg_temp_new_i64();
7515 TCGv_i64 tmp = tcg_temp_new_i64();
7516
7517 gen_evmwsmi(ctx); /* rD := rA * rB */
7518
7519 acc = tcg_temp_new_i64();
7520 tmp = tcg_temp_new_i64();
7521
7522 /* tmp := rD */
7523 gen_load_gpr64(tmp, rD(ctx->opcode));
7524
7525 /* Load acc */
7526 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7527
7528 /* acc := tmp + acc */
7529 tcg_gen_add_i64(acc, acc, tmp);
7530
7531 /* Store acc */
7532 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7533
7534 /* rD := acc */
7535 gen_store_gpr64(rD(ctx->opcode), acc);
7536
7537 tcg_temp_free_i64(acc);
7538 tcg_temp_free_i64(tmp);
7539 }
7540
7541 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7542 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7543 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7544 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7545 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7546 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7547 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7548 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7549 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7550 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7551 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7552 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7553 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7554 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7555 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7556 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7557 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7558 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7559 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7560 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7561 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7562 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7563 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7564 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7565 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7566 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7567 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7568 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7569 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7570
7571 /* SPE load and stores */
7572 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7573 {
7574 target_ulong uimm = rB(ctx->opcode);
7575
7576 if (rA(ctx->opcode) == 0) {
7577 tcg_gen_movi_tl(EA, uimm << sh);
7578 } else {
7579 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7580 #if defined(TARGET_PPC64)
7581 if (!ctx->sf_mode) {
7582 tcg_gen_ext32u_tl(EA, EA);
7583 }
7584 #endif
7585 }
7586 }
7587
7588 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7589 {
7590 #if defined(TARGET_PPC64)
7591 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7592 #else
7593 TCGv_i64 t0 = tcg_temp_new_i64();
7594 gen_qemu_ld64(ctx, t0, addr);
7595 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7596 tcg_gen_shri_i64(t0, t0, 32);
7597 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7598 tcg_temp_free_i64(t0);
7599 #endif
7600 }
7601
7602 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7603 {
7604 #if defined(TARGET_PPC64)
7605 TCGv t0 = tcg_temp_new();
7606 gen_qemu_ld32u(ctx, t0, addr);
7607 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7608 gen_addr_add(ctx, addr, addr, 4);
7609 gen_qemu_ld32u(ctx, t0, addr);
7610 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7611 tcg_temp_free(t0);
7612 #else
7613 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7614 gen_addr_add(ctx, addr, addr, 4);
7615 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7616 #endif
7617 }
7618
7619 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7620 {
7621 TCGv t0 = tcg_temp_new();
7622 #if defined(TARGET_PPC64)
7623 gen_qemu_ld16u(ctx, t0, addr);
7624 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7625 gen_addr_add(ctx, addr, addr, 2);
7626 gen_qemu_ld16u(ctx, t0, addr);
7627 tcg_gen_shli_tl(t0, t0, 32);
7628 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7629 gen_addr_add(ctx, addr, addr, 2);
7630 gen_qemu_ld16u(ctx, t0, addr);
7631 tcg_gen_shli_tl(t0, t0, 16);
7632 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7633 gen_addr_add(ctx, addr, addr, 2);
7634 gen_qemu_ld16u(ctx, t0, addr);
7635 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7636 #else
7637 gen_qemu_ld16u(ctx, t0, addr);
7638 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7639 gen_addr_add(ctx, addr, addr, 2);
7640 gen_qemu_ld16u(ctx, t0, addr);
7641 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7642 gen_addr_add(ctx, addr, addr, 2);
7643 gen_qemu_ld16u(ctx, t0, addr);
7644 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7645 gen_addr_add(ctx, addr, addr, 2);
7646 gen_qemu_ld16u(ctx, t0, addr);
7647 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7648 #endif
7649 tcg_temp_free(t0);
7650 }
7651
7652 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7653 {
7654 TCGv t0 = tcg_temp_new();
7655 gen_qemu_ld16u(ctx, t0, addr);
7656 #if defined(TARGET_PPC64)
7657 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7658 tcg_gen_shli_tl(t0, t0, 16);
7659 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7660 #else
7661 tcg_gen_shli_tl(t0, t0, 16);
7662 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7663 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7664 #endif
7665 tcg_temp_free(t0);
7666 }
7667
7668 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7669 {
7670 TCGv t0 = tcg_temp_new();
7671 gen_qemu_ld16u(ctx, t0, addr);
7672 #if defined(TARGET_PPC64)
7673 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7674 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7675 #else
7676 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7677 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7678 #endif
7679 tcg_temp_free(t0);
7680 }
7681
7682 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7683 {
7684 TCGv t0 = tcg_temp_new();
7685 gen_qemu_ld16s(ctx, t0, addr);
7686 #if defined(TARGET_PPC64)
7687 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7688 tcg_gen_ext32u_tl(t0, t0);
7689 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7690 #else
7691 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7692 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7693 #endif
7694 tcg_temp_free(t0);
7695 }
7696
7697 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7698 {
7699 TCGv t0 = tcg_temp_new();
7700 #if defined(TARGET_PPC64)
7701 gen_qemu_ld16u(ctx, t0, addr);
7702 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7703 gen_addr_add(ctx, addr, addr, 2);
7704 gen_qemu_ld16u(ctx, t0, addr);
7705 tcg_gen_shli_tl(t0, t0, 16);
7706 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7707 #else
7708 gen_qemu_ld16u(ctx, t0, addr);
7709 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7710 gen_addr_add(ctx, addr, addr, 2);
7711 gen_qemu_ld16u(ctx, t0, addr);
7712 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7713 #endif
7714 tcg_temp_free(t0);
7715 }
7716
7717 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7718 {
7719 #if defined(TARGET_PPC64)
7720 TCGv t0 = tcg_temp_new();
7721 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7722 gen_addr_add(ctx, addr, addr, 2);
7723 gen_qemu_ld16u(ctx, t0, addr);
7724 tcg_gen_shli_tl(t0, t0, 32);
7725 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7726 tcg_temp_free(t0);
7727 #else
7728 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7729 gen_addr_add(ctx, addr, addr, 2);
7730 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7731 #endif
7732 }
7733
7734 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7735 {
7736 #if defined(TARGET_PPC64)
7737 TCGv t0 = tcg_temp_new();
7738 gen_qemu_ld16s(ctx, t0, addr);
7739 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7740 gen_addr_add(ctx, addr, addr, 2);
7741 gen_qemu_ld16s(ctx, t0, addr);
7742 tcg_gen_shli_tl(t0, t0, 32);
7743 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7744 tcg_temp_free(t0);
7745 #else
7746 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7747 gen_addr_add(ctx, addr, addr, 2);
7748 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7749 #endif
7750 }
7751
7752 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7753 {
7754 TCGv t0 = tcg_temp_new();
7755 gen_qemu_ld32u(ctx, t0, addr);
7756 #if defined(TARGET_PPC64)
7757 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7758 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7759 #else
7760 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7761 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7762 #endif
7763 tcg_temp_free(t0);
7764 }
7765
7766 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7767 {
7768 TCGv t0 = tcg_temp_new();
7769 #if defined(TARGET_PPC64)
7770 gen_qemu_ld16u(ctx, t0, addr);
7771 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7772 tcg_gen_shli_tl(t0, t0, 32);
7773 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7774 gen_addr_add(ctx, addr, addr, 2);
7775 gen_qemu_ld16u(ctx, t0, addr);
7776 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7777 tcg_gen_shli_tl(t0, t0, 16);
7778 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7779 #else
7780 gen_qemu_ld16u(ctx, t0, addr);
7781 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7782 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7783 gen_addr_add(ctx, addr, addr, 2);
7784 gen_qemu_ld16u(ctx, t0, addr);
7785 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7786 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7787 #endif
7788 tcg_temp_free(t0);
7789 }
7790
7791 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7792 {
7793 #if defined(TARGET_PPC64)
7794 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7795 #else
7796 TCGv_i64 t0 = tcg_temp_new_i64();
7797 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7798 gen_qemu_st64(ctx, t0, addr);
7799 tcg_temp_free_i64(t0);
7800 #endif
7801 }
7802
7803 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7804 {
7805 #if defined(TARGET_PPC64)
7806 TCGv t0 = tcg_temp_new();
7807 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7808 gen_qemu_st32(ctx, t0, addr);
7809 tcg_temp_free(t0);
7810 #else
7811 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7812 #endif
7813 gen_addr_add(ctx, addr, addr, 4);
7814 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7815 }
7816
7817 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7818 {
7819 TCGv t0 = tcg_temp_new();
7820 #if defined(TARGET_PPC64)
7821 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7822 #else
7823 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7824 #endif
7825 gen_qemu_st16(ctx, t0, addr);
7826 gen_addr_add(ctx, addr, addr, 2);
7827 #if defined(TARGET_PPC64)
7828 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7829 gen_qemu_st16(ctx, t0, addr);
7830 #else
7831 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7832 #endif
7833 gen_addr_add(ctx, addr, addr, 2);
7834 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7835 gen_qemu_st16(ctx, t0, addr);
7836 tcg_temp_free(t0);
7837 gen_addr_add(ctx, addr, addr, 2);
7838 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7839 }
7840
7841 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7842 {
7843 TCGv t0 = tcg_temp_new();
7844 #if defined(TARGET_PPC64)
7845 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7846 #else
7847 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7848 #endif
7849 gen_qemu_st16(ctx, t0, addr);
7850 gen_addr_add(ctx, addr, addr, 2);
7851 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7852 gen_qemu_st16(ctx, t0, addr);
7853 tcg_temp_free(t0);
7854 }
7855
7856 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7857 {
7858 #if defined(TARGET_PPC64)
7859 TCGv t0 = tcg_temp_new();
7860 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7861 gen_qemu_st16(ctx, t0, addr);
7862 tcg_temp_free(t0);
7863 #else
7864 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7865 #endif
7866 gen_addr_add(ctx, addr, addr, 2);
7867 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7868 }
7869
7870 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7871 {
7872 #if defined(TARGET_PPC64)
7873 TCGv t0 = tcg_temp_new();
7874 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7875 gen_qemu_st32(ctx, t0, addr);
7876 tcg_temp_free(t0);
7877 #else
7878 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7879 #endif
7880 }
7881
7882 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7883 {
7884 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7885 }
7886
7887 #define GEN_SPEOP_LDST(name, opc2, sh) \
7888 static void glue(gen_, name)(DisasContext *ctx) \
7889 { \
7890 TCGv t0; \
7891 if (unlikely(!ctx->spe_enabled)) { \
7892 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7893 return; \
7894 } \
7895 gen_set_access_type(ctx, ACCESS_INT); \
7896 t0 = tcg_temp_new(); \
7897 if (Rc(ctx->opcode)) { \
7898 gen_addr_spe_imm_index(ctx, t0, sh); \
7899 } else { \
7900 gen_addr_reg_index(ctx, t0); \
7901 } \
7902 gen_op_##name(ctx, t0); \
7903 tcg_temp_free(t0); \
7904 }
7905
7906 GEN_SPEOP_LDST(evldd, 0x00, 3);
7907 GEN_SPEOP_LDST(evldw, 0x01, 3);
7908 GEN_SPEOP_LDST(evldh, 0x02, 3);
7909 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7910 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7911 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7912 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7913 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7914 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7915 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7916 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7917
7918 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7919 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7920 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7921 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7922 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7923 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7924 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7925
7926 /* Multiply and add - TODO */
7927 #if 0
7928 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7929 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7930 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7931 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7932 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7933 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7934 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7935 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7936 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7937 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7938 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7939 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7940
7941 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7942 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7943 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7944 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7945 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7946 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7947 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7948 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7949 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7950 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7951 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7952 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7953
7954 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7955 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7956 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7957 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7958 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7959
7960 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7961 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7962 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7963 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7964 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7965 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7966 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7967 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7968 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7969 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7970 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7971 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7972
7973 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7974 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7975 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7976 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7977
7978 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7979 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7980 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7983 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7984 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7985 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7986 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7987 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7989 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7990
7991 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7992 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7993 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7994 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7995 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7996 #endif
7997
7998 /*** SPE floating-point extension ***/
7999 #if defined(TARGET_PPC64)
8000 #define GEN_SPEFPUOP_CONV_32_32(name) \
8001 static inline void gen_##name(DisasContext *ctx) \
8002 { \
8003 TCGv_i32 t0; \
8004 TCGv t1; \
8005 t0 = tcg_temp_new_i32(); \
8006 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8007 gen_helper_##name(t0, cpu_env, t0); \
8008 t1 = tcg_temp_new(); \
8009 tcg_gen_extu_i32_tl(t1, t0); \
8010 tcg_temp_free_i32(t0); \
8011 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8012 0xFFFFFFFF00000000ULL); \
8013 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8014 tcg_temp_free(t1); \
8015 }
8016 #define GEN_SPEFPUOP_CONV_32_64(name) \
8017 static inline void gen_##name(DisasContext *ctx) \
8018 { \
8019 TCGv_i32 t0; \
8020 TCGv t1; \
8021 t0 = tcg_temp_new_i32(); \
8022 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8023 t1 = tcg_temp_new(); \
8024 tcg_gen_extu_i32_tl(t1, t0); \
8025 tcg_temp_free_i32(t0); \
8026 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8027 0xFFFFFFFF00000000ULL); \
8028 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8029 tcg_temp_free(t1); \
8030 }
8031 #define GEN_SPEFPUOP_CONV_64_32(name) \
8032 static inline void gen_##name(DisasContext *ctx) \
8033 { \
8034 TCGv_i32 t0 = tcg_temp_new_i32(); \
8035 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8036 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8037 tcg_temp_free_i32(t0); \
8038 }
8039 #define GEN_SPEFPUOP_CONV_64_64(name) \
8040 static inline void gen_##name(DisasContext *ctx) \
8041 { \
8042 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8043 cpu_gpr[rB(ctx->opcode)]); \
8044 }
8045 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8046 static inline void gen_##name(DisasContext *ctx) \
8047 { \
8048 TCGv_i32 t0, t1; \
8049 TCGv_i64 t2; \
8050 if (unlikely(!ctx->spe_enabled)) { \
8051 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8052 return; \
8053 } \
8054 t0 = tcg_temp_new_i32(); \
8055 t1 = tcg_temp_new_i32(); \
8056 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8057 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8058 gen_helper_##name(t0, cpu_env, t0, t1); \
8059 tcg_temp_free_i32(t1); \
8060 t2 = tcg_temp_new(); \
8061 tcg_gen_extu_i32_tl(t2, t0); \
8062 tcg_temp_free_i32(t0); \
8063 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8064 0xFFFFFFFF00000000ULL); \
8065 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8066 tcg_temp_free(t2); \
8067 }
8068 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8069 static inline void gen_##name(DisasContext *ctx) \
8070 { \
8071 if (unlikely(!ctx->spe_enabled)) { \
8072 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8073 return; \
8074 } \
8075 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8076 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8077 }
8078 #define GEN_SPEFPUOP_COMP_32(name) \
8079 static inline void gen_##name(DisasContext *ctx) \
8080 { \
8081 TCGv_i32 t0, t1; \
8082 if (unlikely(!ctx->spe_enabled)) { \
8083 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8084 return; \
8085 } \
8086 t0 = tcg_temp_new_i32(); \
8087 t1 = tcg_temp_new_i32(); \
8088 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8089 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8090 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8091 tcg_temp_free_i32(t0); \
8092 tcg_temp_free_i32(t1); \
8093 }
8094 #define GEN_SPEFPUOP_COMP_64(name) \
8095 static inline void gen_##name(DisasContext *ctx) \
8096 { \
8097 if (unlikely(!ctx->spe_enabled)) { \
8098 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8099 return; \
8100 } \
8101 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8102 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8103 }
8104 #else
8105 #define GEN_SPEFPUOP_CONV_32_32(name) \
8106 static inline void gen_##name(DisasContext *ctx) \
8107 { \
8108 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8109 cpu_gpr[rB(ctx->opcode)]); \
8110 }
8111 #define GEN_SPEFPUOP_CONV_32_64(name) \
8112 static inline void gen_##name(DisasContext *ctx) \
8113 { \
8114 TCGv_i64 t0 = tcg_temp_new_i64(); \
8115 gen_load_gpr64(t0, rB(ctx->opcode)); \
8116 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8117 tcg_temp_free_i64(t0); \
8118 }
8119 #define GEN_SPEFPUOP_CONV_64_32(name) \
8120 static inline void gen_##name(DisasContext *ctx) \
8121 { \
8122 TCGv_i64 t0 = tcg_temp_new_i64(); \
8123 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8124 gen_store_gpr64(rD(ctx->opcode), t0); \
8125 tcg_temp_free_i64(t0); \
8126 }
8127 #define GEN_SPEFPUOP_CONV_64_64(name) \
8128 static inline void gen_##name(DisasContext *ctx) \
8129 { \
8130 TCGv_i64 t0 = tcg_temp_new_i64(); \
8131 gen_load_gpr64(t0, rB(ctx->opcode)); \
8132 gen_helper_##name(t0, cpu_env, t0); \
8133 gen_store_gpr64(rD(ctx->opcode), t0); \
8134 tcg_temp_free_i64(t0); \
8135 }
8136 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8137 static inline void gen_##name(DisasContext *ctx) \
8138 { \
8139 if (unlikely(!ctx->spe_enabled)) { \
8140 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8141 return; \
8142 } \
8143 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8144 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8145 }
8146 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8147 static inline void gen_##name(DisasContext *ctx) \
8148 { \
8149 TCGv_i64 t0, t1; \
8150 if (unlikely(!ctx->spe_enabled)) { \
8151 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8152 return; \
8153 } \
8154 t0 = tcg_temp_new_i64(); \
8155 t1 = tcg_temp_new_i64(); \
8156 gen_load_gpr64(t0, rA(ctx->opcode)); \
8157 gen_load_gpr64(t1, rB(ctx->opcode)); \
8158 gen_helper_##name(t0, cpu_env, t0, t1); \
8159 gen_store_gpr64(rD(ctx->opcode), t0); \
8160 tcg_temp_free_i64(t0); \
8161 tcg_temp_free_i64(t1); \
8162 }
8163 #define GEN_SPEFPUOP_COMP_32(name) \
8164 static inline void gen_##name(DisasContext *ctx) \
8165 { \
8166 if (unlikely(!ctx->spe_enabled)) { \
8167 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8168 return; \
8169 } \
8170 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8171 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8172 }
8173 #define GEN_SPEFPUOP_COMP_64(name) \
8174 static inline void gen_##name(DisasContext *ctx) \
8175 { \
8176 TCGv_i64 t0, t1; \
8177 if (unlikely(!ctx->spe_enabled)) { \
8178 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8179 return; \
8180 } \
8181 t0 = tcg_temp_new_i64(); \
8182 t1 = tcg_temp_new_i64(); \
8183 gen_load_gpr64(t0, rA(ctx->opcode)); \
8184 gen_load_gpr64(t1, rB(ctx->opcode)); \
8185 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8186 tcg_temp_free_i64(t0); \
8187 tcg_temp_free_i64(t1); \
8188 }
8189 #endif
8190
8191 /* Single precision floating-point vectors operations */
8192 /* Arithmetic */
8193 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8194 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8195 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8196 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8197 static inline void gen_evfsabs(DisasContext *ctx)
8198 {
8199 if (unlikely(!ctx->spe_enabled)) {
8200 gen_exception(ctx, POWERPC_EXCP_SPEU);
8201 return;
8202 }
8203 #if defined(TARGET_PPC64)
8204 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8205 #else
8206 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8207 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8208 #endif
8209 }
8210 static inline void gen_evfsnabs(DisasContext *ctx)
8211 {
8212 if (unlikely(!ctx->spe_enabled)) {
8213 gen_exception(ctx, POWERPC_EXCP_SPEU);
8214 return;
8215 }
8216 #if defined(TARGET_PPC64)
8217 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8218 #else
8219 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8220 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8221 #endif
8222 }
8223 static inline void gen_evfsneg(DisasContext *ctx)
8224 {
8225 if (unlikely(!ctx->spe_enabled)) {
8226 gen_exception(ctx, POWERPC_EXCP_SPEU);
8227 return;
8228 }
8229 #if defined(TARGET_PPC64)
8230 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8231 #else
8232 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8233 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8234 #endif
8235 }
8236
8237 /* Conversion */
8238 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8239 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8240 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8241 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8242 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8243 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8244 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8245 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8246 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8247 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8248
8249 /* Comparison */
8250 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8251 GEN_SPEFPUOP_COMP_64(evfscmplt);
8252 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8253 GEN_SPEFPUOP_COMP_64(evfststgt);
8254 GEN_SPEFPUOP_COMP_64(evfststlt);
8255 GEN_SPEFPUOP_COMP_64(evfststeq);
8256
8257 /* Opcodes definitions */
8258 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8259 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8260 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8261 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8262 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8263 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8264 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8265 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8266 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8267 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8268 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8269 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8270 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8271 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8272
8273 /* Single precision floating-point operations */
8274 /* Arithmetic */
8275 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8276 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8277 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8278 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8279 static inline void gen_efsabs(DisasContext *ctx)
8280 {
8281 if (unlikely(!ctx->spe_enabled)) {
8282 gen_exception(ctx, POWERPC_EXCP_SPEU);
8283 return;
8284 }
8285 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8286 }
8287 static inline void gen_efsnabs(DisasContext *ctx)
8288 {
8289 if (unlikely(!ctx->spe_enabled)) {
8290 gen_exception(ctx, POWERPC_EXCP_SPEU);
8291 return;
8292 }
8293 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8294 }
8295 static inline void gen_efsneg(DisasContext *ctx)
8296 {
8297 if (unlikely(!ctx->spe_enabled)) {
8298 gen_exception(ctx, POWERPC_EXCP_SPEU);
8299 return;
8300 }
8301 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8302 }
8303
8304 /* Conversion */
8305 GEN_SPEFPUOP_CONV_32_32(efscfui);
8306 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8307 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8308 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8309 GEN_SPEFPUOP_CONV_32_32(efsctui);
8310 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8311 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8312 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8313 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8314 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8315 GEN_SPEFPUOP_CONV_32_64(efscfd);
8316
8317 /* Comparison */
8318 GEN_SPEFPUOP_COMP_32(efscmpgt);
8319 GEN_SPEFPUOP_COMP_32(efscmplt);
8320 GEN_SPEFPUOP_COMP_32(efscmpeq);
8321 GEN_SPEFPUOP_COMP_32(efststgt);
8322 GEN_SPEFPUOP_COMP_32(efststlt);
8323 GEN_SPEFPUOP_COMP_32(efststeq);
8324
8325 /* Opcodes definitions */
8326 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8327 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8328 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8329 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8330 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8331 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8332 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8333 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8334 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8335 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8336 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8337 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8338 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8339 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8340
8341 /* Double precision floating-point operations */
8342 /* Arithmetic */
8343 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8344 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8345 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8346 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8347 static inline void gen_efdabs(DisasContext *ctx)
8348 {
8349 if (unlikely(!ctx->spe_enabled)) {
8350 gen_exception(ctx, POWERPC_EXCP_SPEU);
8351 return;
8352 }
8353 #if defined(TARGET_PPC64)
8354 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8355 #else
8356 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8357 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8358 #endif
8359 }
8360 static inline void gen_efdnabs(DisasContext *ctx)
8361 {
8362 if (unlikely(!ctx->spe_enabled)) {
8363 gen_exception(ctx, POWERPC_EXCP_SPEU);
8364 return;
8365 }
8366 #if defined(TARGET_PPC64)
8367 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8368 #else
8369 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8370 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8371 #endif
8372 }
8373 static inline void gen_efdneg(DisasContext *ctx)
8374 {
8375 if (unlikely(!ctx->spe_enabled)) {
8376 gen_exception(ctx, POWERPC_EXCP_SPEU);
8377 return;
8378 }
8379 #if defined(TARGET_PPC64)
8380 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8381 #else
8382 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8383 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8384 #endif
8385 }
8386
8387 /* Conversion */
8388 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8389 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8390 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8391 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8392 GEN_SPEFPUOP_CONV_32_64(efdctui);
8393 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8394 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8395 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8396 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8397 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8398 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8399 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8400 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8401 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8402 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8403
8404 /* Comparison */
8405 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8406 GEN_SPEFPUOP_COMP_64(efdcmplt);
8407 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8408 GEN_SPEFPUOP_COMP_64(efdtstgt);
8409 GEN_SPEFPUOP_COMP_64(efdtstlt);
8410 GEN_SPEFPUOP_COMP_64(efdtsteq);
8411
8412 /* Opcodes definitions */
8413 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8414 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8415 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8416 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8417 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8418 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8419 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8420 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8421 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8422 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8423 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8424 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8425 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8426 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8427 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8428 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8429
8430 static opcode_t opcodes[] = {
8431 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8432 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8433 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8434 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8435 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8436 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8437 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8438 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8439 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8440 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8441 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8442 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8443 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8444 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8445 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8446 #if defined(TARGET_PPC64)
8447 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8448 #endif
8449 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8450 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8451 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8452 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8453 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8454 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8455 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8456 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8457 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8458 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8459 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8460 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8461 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8462 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8463 #if defined(TARGET_PPC64)
8464 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8465 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8466 #endif
8467 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8468 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8469 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8471 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8472 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8473 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8474 #if defined(TARGET_PPC64)
8475 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8476 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8477 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8478 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8479 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8480 #endif
8481 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8482 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8483 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8484 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8485 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8486 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8487 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8488 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8489 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8490 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8491 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8492 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8493 #if defined(TARGET_PPC64)
8494 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8495 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8496 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8497 #endif
8498 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8499 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8500 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8501 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8502 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8503 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8504 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8505 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8506 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8507 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8508 #if defined(TARGET_PPC64)
8509 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8510 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8511 #endif
8512 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8513 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8514 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8515 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8516 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8517 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8518 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8519 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8520 #if defined(TARGET_PPC64)
8521 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8522 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8523 #endif
8524 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8525 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8526 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8527 #if defined(TARGET_PPC64)
8528 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8529 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8530 #endif
8531 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8532 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8533 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8534 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8535 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8536 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8537 #if defined(TARGET_PPC64)
8538 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8539 #endif
8540 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8541 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8542 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8543 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8544 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8545 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8546 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8547 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8548 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8549 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8550 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8551 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8552 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8553 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8554 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8555 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8556 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8557 #if defined(TARGET_PPC64)
8558 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8559 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8560 PPC_SEGMENT_64B),
8561 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8562 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8563 PPC_SEGMENT_64B),
8564 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8565 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8566 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8567 #endif
8568 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8569 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8570 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8571 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8572 #if defined(TARGET_PPC64)
8573 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8574 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8575 #endif
8576 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8577 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8578 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8579 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8580 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8581 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8582 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8583 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8584 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8585 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8586 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8587 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8588 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8589 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8590 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8591 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8592 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8593 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8612 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8613 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8614 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8615 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8616 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8617 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8618 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8619 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8620 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8621 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8622 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8623 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8624 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8625 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8626 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8627 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8628 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8629 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8630 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8631 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8632 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8633 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8634 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8635 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8636 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8637 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8638 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8639 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8640 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8641 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8642 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8643 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8644 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8645 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8646 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8647 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8648 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8649 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8650 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8651 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8652 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8653 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8654 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8655 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8656 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8657 PPC_NONE, PPC2_BOOKE206),
8658 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8659 PPC_NONE, PPC2_BOOKE206),
8660 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8661 PPC_NONE, PPC2_BOOKE206),
8662 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8663 PPC_NONE, PPC2_BOOKE206),
8664 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8665 PPC_NONE, PPC2_BOOKE206),
8666 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8667 PPC_NONE, PPC2_PRCNTL),
8668 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8669 PPC_NONE, PPC2_PRCNTL),
8670 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8671 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8672 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8673 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8674 PPC_BOOKE, PPC2_BOOKE206),
8675 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8676 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8677 PPC_BOOKE, PPC2_BOOKE206),
8678 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8679 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8680 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8681 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8682 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8683 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8684 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8685 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8686 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8687 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8688
8689 #undef GEN_INT_ARITH_ADD
8690 #undef GEN_INT_ARITH_ADD_CONST
8691 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8692 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8693 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8694 add_ca, compute_ca, compute_ov) \
8695 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8696 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8697 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8698 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8699 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8700 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8701 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8702 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8703 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8704 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8705 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8706
8707 #undef GEN_INT_ARITH_DIVW
8708 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8709 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8710 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8711 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8712 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8713 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8714
8715 #if defined(TARGET_PPC64)
8716 #undef GEN_INT_ARITH_DIVD
8717 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8718 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8719 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8720 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8721 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8722 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8723
8724 #undef GEN_INT_ARITH_MUL_HELPER
8725 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8726 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8727 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8728 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8729 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8730 #endif
8731
8732 #undef GEN_INT_ARITH_SUBF
8733 #undef GEN_INT_ARITH_SUBF_CONST
8734 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8735 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8736 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8737 add_ca, compute_ca, compute_ov) \
8738 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8739 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8740 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8741 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8742 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8743 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8744 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8745 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8746 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8747 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8748 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8749
8750 #undef GEN_LOGICAL1
8751 #undef GEN_LOGICAL2
8752 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8753 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8754 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8755 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8756 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8757 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8758 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8759 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8760 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8761 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8762 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8763 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8764 #if defined(TARGET_PPC64)
8765 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8766 #endif
8767
8768 #if defined(TARGET_PPC64)
8769 #undef GEN_PPC64_R2
8770 #undef GEN_PPC64_R4
8771 #define GEN_PPC64_R2(name, opc1, opc2) \
8772 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8773 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8774 PPC_64B)
8775 #define GEN_PPC64_R4(name, opc1, opc2) \
8776 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8777 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8778 PPC_64B), \
8779 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8780 PPC_64B), \
8781 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8782 PPC_64B)
8783 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8784 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8785 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8786 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8787 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8788 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8789 #endif
8790
8791 #undef _GEN_FLOAT_ACB
8792 #undef GEN_FLOAT_ACB
8793 #undef _GEN_FLOAT_AB
8794 #undef GEN_FLOAT_AB
8795 #undef _GEN_FLOAT_AC
8796 #undef GEN_FLOAT_AC
8797 #undef GEN_FLOAT_B
8798 #undef GEN_FLOAT_BS
8799 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8800 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8801 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8802 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8803 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8804 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8805 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8806 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8807 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8808 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8809 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8810 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8811 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8812 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8813 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8814 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8815 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8816 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8817 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8818
8819 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8820 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8821 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8822 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8823 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8824 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8825 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8826 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8827 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8828 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8829 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8830 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8831 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8832 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8833 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8834 #if defined(TARGET_PPC64)
8835 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8836 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8837 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8838 #endif
8839 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8840 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8841 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8842 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8843 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8844 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8845 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8846
8847 #undef GEN_LD
8848 #undef GEN_LDU
8849 #undef GEN_LDUX
8850 #undef GEN_LDX_E
8851 #undef GEN_LDS
8852 #define GEN_LD(name, ldop, opc, type) \
8853 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8854 #define GEN_LDU(name, ldop, opc, type) \
8855 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8856 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8857 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8858 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8859 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8860 #define GEN_LDS(name, ldop, op, type) \
8861 GEN_LD(name, ldop, op | 0x20, type) \
8862 GEN_LDU(name, ldop, op | 0x21, type) \
8863 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8864 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8865
8866 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8867 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8868 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8869 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8870 #if defined(TARGET_PPC64)
8871 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8872 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8873 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8874 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8875 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8876 #endif
8877 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8878 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8879
8880 #undef GEN_ST
8881 #undef GEN_STU
8882 #undef GEN_STUX
8883 #undef GEN_STX_E
8884 #undef GEN_STS
8885 #define GEN_ST(name, stop, opc, type) \
8886 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8887 #define GEN_STU(name, stop, opc, type) \
8888 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8889 #define GEN_STUX(name, stop, opc2, opc3, type) \
8890 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8891 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8892 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8893 #define GEN_STS(name, stop, op, type) \
8894 GEN_ST(name, stop, op | 0x20, type) \
8895 GEN_STU(name, stop, op | 0x21, type) \
8896 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8897 GEN_STX(name, stop, 0x17, op | 0x00, type)
8898
8899 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8900 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8901 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8902 #if defined(TARGET_PPC64)
8903 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8904 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8905 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8906 #endif
8907 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8908 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8909
8910 #undef GEN_LDF
8911 #undef GEN_LDUF
8912 #undef GEN_LDUXF
8913 #undef GEN_LDXF
8914 #undef GEN_LDFS
8915 #define GEN_LDF(name, ldop, opc, type) \
8916 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8917 #define GEN_LDUF(name, ldop, opc, type) \
8918 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8919 #define GEN_LDUXF(name, ldop, opc, type) \
8920 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8921 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8922 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8923 #define GEN_LDFS(name, ldop, op, type) \
8924 GEN_LDF(name, ldop, op | 0x20, type) \
8925 GEN_LDUF(name, ldop, op | 0x21, type) \
8926 GEN_LDUXF(name, ldop, op | 0x01, type) \
8927 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8928
8929 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8930 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8931
8932 #undef GEN_STF
8933 #undef GEN_STUF
8934 #undef GEN_STUXF
8935 #undef GEN_STXF
8936 #undef GEN_STFS
8937 #define GEN_STF(name, stop, opc, type) \
8938 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8939 #define GEN_STUF(name, stop, opc, type) \
8940 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8941 #define GEN_STUXF(name, stop, opc, type) \
8942 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8943 #define GEN_STXF(name, stop, opc2, opc3, type) \
8944 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8945 #define GEN_STFS(name, stop, op, type) \
8946 GEN_STF(name, stop, op | 0x20, type) \
8947 GEN_STUF(name, stop, op | 0x21, type) \
8948 GEN_STUXF(name, stop, op | 0x01, type) \
8949 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8950
8951 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8952 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8953 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8954
8955 #undef GEN_CRLOGIC
8956 #define GEN_CRLOGIC(name, tcg_op, opc) \
8957 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8958 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8959 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8960 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8961 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8962 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8963 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8964 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8965 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8966
8967 #undef GEN_MAC_HANDLER
8968 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8969 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8970 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8971 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8972 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8973 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8974 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8975 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8976 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8977 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8978 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8979 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8980 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8981 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8982 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8983 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8984 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8985 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8986 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8987 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8988 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8989 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8990 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8991 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8992 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8993 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8994 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8995 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8996 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8997 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8998 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8999 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9000 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9001 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9002 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9003 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9004 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9005 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9006 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9007 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9008 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9009 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9010 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9011 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9012
9013 #undef GEN_VR_LDX
9014 #undef GEN_VR_STX
9015 #undef GEN_VR_LVE
9016 #undef GEN_VR_STVE
9017 #define GEN_VR_LDX(name, opc2, opc3) \
9018 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9019 #define GEN_VR_STX(name, opc2, opc3) \
9020 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9021 #define GEN_VR_LVE(name, opc2, opc3) \
9022 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9023 #define GEN_VR_STVE(name, opc2, opc3) \
9024 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9025 GEN_VR_LDX(lvx, 0x07, 0x03),
9026 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9027 GEN_VR_LVE(bx, 0x07, 0x00),
9028 GEN_VR_LVE(hx, 0x07, 0x01),
9029 GEN_VR_LVE(wx, 0x07, 0x02),
9030 GEN_VR_STX(svx, 0x07, 0x07),
9031 GEN_VR_STX(svxl, 0x07, 0x0F),
9032 GEN_VR_STVE(bx, 0x07, 0x04),
9033 GEN_VR_STVE(hx, 0x07, 0x05),
9034 GEN_VR_STVE(wx, 0x07, 0x06),
9035
9036 #undef GEN_VX_LOGICAL
9037 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9038 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9039 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9040 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9041 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9042 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9043 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9044
9045 #undef GEN_VXFORM
9046 #define GEN_VXFORM(name, opc2, opc3) \
9047 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9048 GEN_VXFORM(vaddubm, 0, 0),
9049 GEN_VXFORM(vadduhm, 0, 1),
9050 GEN_VXFORM(vadduwm, 0, 2),
9051 GEN_VXFORM(vsububm, 0, 16),
9052 GEN_VXFORM(vsubuhm, 0, 17),
9053 GEN_VXFORM(vsubuwm, 0, 18),
9054 GEN_VXFORM(vmaxub, 1, 0),
9055 GEN_VXFORM(vmaxuh, 1, 1),
9056 GEN_VXFORM(vmaxuw, 1, 2),
9057 GEN_VXFORM(vmaxsb, 1, 4),
9058 GEN_VXFORM(vmaxsh, 1, 5),
9059 GEN_VXFORM(vmaxsw, 1, 6),
9060 GEN_VXFORM(vminub, 1, 8),
9061 GEN_VXFORM(vminuh, 1, 9),
9062 GEN_VXFORM(vminuw, 1, 10),
9063 GEN_VXFORM(vminsb, 1, 12),
9064 GEN_VXFORM(vminsh, 1, 13),
9065 GEN_VXFORM(vminsw, 1, 14),
9066 GEN_VXFORM(vavgub, 1, 16),
9067 GEN_VXFORM(vavguh, 1, 17),
9068 GEN_VXFORM(vavguw, 1, 18),
9069 GEN_VXFORM(vavgsb, 1, 20),
9070 GEN_VXFORM(vavgsh, 1, 21),
9071 GEN_VXFORM(vavgsw, 1, 22),
9072 GEN_VXFORM(vmrghb, 6, 0),
9073 GEN_VXFORM(vmrghh, 6, 1),
9074 GEN_VXFORM(vmrghw, 6, 2),
9075 GEN_VXFORM(vmrglb, 6, 4),
9076 GEN_VXFORM(vmrglh, 6, 5),
9077 GEN_VXFORM(vmrglw, 6, 6),
9078 GEN_VXFORM(vmuloub, 4, 0),
9079 GEN_VXFORM(vmulouh, 4, 1),
9080 GEN_VXFORM(vmulosb, 4, 4),
9081 GEN_VXFORM(vmulosh, 4, 5),
9082 GEN_VXFORM(vmuleub, 4, 8),
9083 GEN_VXFORM(vmuleuh, 4, 9),
9084 GEN_VXFORM(vmulesb, 4, 12),
9085 GEN_VXFORM(vmulesh, 4, 13),
9086 GEN_VXFORM(vslb, 2, 4),
9087 GEN_VXFORM(vslh, 2, 5),
9088 GEN_VXFORM(vslw, 2, 6),
9089 GEN_VXFORM(vsrb, 2, 8),
9090 GEN_VXFORM(vsrh, 2, 9),
9091 GEN_VXFORM(vsrw, 2, 10),
9092 GEN_VXFORM(vsrab, 2, 12),
9093 GEN_VXFORM(vsrah, 2, 13),
9094 GEN_VXFORM(vsraw, 2, 14),
9095 GEN_VXFORM(vslo, 6, 16),
9096 GEN_VXFORM(vsro, 6, 17),
9097 GEN_VXFORM(vaddcuw, 0, 6),
9098 GEN_VXFORM(vsubcuw, 0, 22),
9099 GEN_VXFORM(vaddubs, 0, 8),
9100 GEN_VXFORM(vadduhs, 0, 9),
9101 GEN_VXFORM(vadduws, 0, 10),
9102 GEN_VXFORM(vaddsbs, 0, 12),
9103 GEN_VXFORM(vaddshs, 0, 13),
9104 GEN_VXFORM(vaddsws, 0, 14),
9105 GEN_VXFORM(vsububs, 0, 24),
9106 GEN_VXFORM(vsubuhs, 0, 25),
9107 GEN_VXFORM(vsubuws, 0, 26),
9108 GEN_VXFORM(vsubsbs, 0, 28),
9109 GEN_VXFORM(vsubshs, 0, 29),
9110 GEN_VXFORM(vsubsws, 0, 30),
9111 GEN_VXFORM(vrlb, 2, 0),
9112 GEN_VXFORM(vrlh, 2, 1),
9113 GEN_VXFORM(vrlw, 2, 2),
9114 GEN_VXFORM(vsl, 2, 7),
9115 GEN_VXFORM(vsr, 2, 11),
9116 GEN_VXFORM(vpkuhum, 7, 0),
9117 GEN_VXFORM(vpkuwum, 7, 1),
9118 GEN_VXFORM(vpkuhus, 7, 2),
9119 GEN_VXFORM(vpkuwus, 7, 3),
9120 GEN_VXFORM(vpkshus, 7, 4),
9121 GEN_VXFORM(vpkswus, 7, 5),
9122 GEN_VXFORM(vpkshss, 7, 6),
9123 GEN_VXFORM(vpkswss, 7, 7),
9124 GEN_VXFORM(vpkpx, 7, 12),
9125 GEN_VXFORM(vsum4ubs, 4, 24),
9126 GEN_VXFORM(vsum4sbs, 4, 28),
9127 GEN_VXFORM(vsum4shs, 4, 25),
9128 GEN_VXFORM(vsum2sws, 4, 26),
9129 GEN_VXFORM(vsumsws, 4, 30),
9130 GEN_VXFORM(vaddfp, 5, 0),
9131 GEN_VXFORM(vsubfp, 5, 1),
9132 GEN_VXFORM(vmaxfp, 5, 16),
9133 GEN_VXFORM(vminfp, 5, 17),
9134
9135 #undef GEN_VXRFORM1
9136 #undef GEN_VXRFORM
9137 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9138 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9139 #define GEN_VXRFORM(name, opc2, opc3) \
9140 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9141 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9142 GEN_VXRFORM(vcmpequb, 3, 0)
9143 GEN_VXRFORM(vcmpequh, 3, 1)
9144 GEN_VXRFORM(vcmpequw, 3, 2)
9145 GEN_VXRFORM(vcmpgtsb, 3, 12)
9146 GEN_VXRFORM(vcmpgtsh, 3, 13)
9147 GEN_VXRFORM(vcmpgtsw, 3, 14)
9148 GEN_VXRFORM(vcmpgtub, 3, 8)
9149 GEN_VXRFORM(vcmpgtuh, 3, 9)
9150 GEN_VXRFORM(vcmpgtuw, 3, 10)
9151 GEN_VXRFORM(vcmpeqfp, 3, 3)
9152 GEN_VXRFORM(vcmpgefp, 3, 7)
9153 GEN_VXRFORM(vcmpgtfp, 3, 11)
9154 GEN_VXRFORM(vcmpbfp, 3, 15)
9155
9156 #undef GEN_VXFORM_SIMM
9157 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9158 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9159 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9160 GEN_VXFORM_SIMM(vspltish, 6, 13),
9161 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9162
9163 #undef GEN_VXFORM_NOA
9164 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9165 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9166 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9167 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9168 GEN_VXFORM_NOA(vupklsb, 7, 10),
9169 GEN_VXFORM_NOA(vupklsh, 7, 11),
9170 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9171 GEN_VXFORM_NOA(vupklpx, 7, 15),
9172 GEN_VXFORM_NOA(vrefp, 5, 4),
9173 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9174 GEN_VXFORM_NOA(vexptefp, 5, 6),
9175 GEN_VXFORM_NOA(vlogefp, 5, 7),
9176 GEN_VXFORM_NOA(vrfim, 5, 8),
9177 GEN_VXFORM_NOA(vrfin, 5, 9),
9178 GEN_VXFORM_NOA(vrfip, 5, 10),
9179 GEN_VXFORM_NOA(vrfiz, 5, 11),
9180
9181 #undef GEN_VXFORM_UIMM
9182 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9183 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9184 GEN_VXFORM_UIMM(vspltb, 6, 8),
9185 GEN_VXFORM_UIMM(vsplth, 6, 9),
9186 GEN_VXFORM_UIMM(vspltw, 6, 10),
9187 GEN_VXFORM_UIMM(vcfux, 5, 12),
9188 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9189 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9190 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9191
9192 #undef GEN_VAFORM_PAIRED
9193 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9194 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9195 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9196 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9197 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9198 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9199 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9200 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9201
9202 #undef GEN_SPE
9203 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9204 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9205 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9206 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9207 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9208 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9209 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9210 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9211 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9212 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9213 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9214 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9215 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9216 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9217 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9218 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9219 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9220 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9221 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9222 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9223 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9224 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9225 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9226 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9227 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9228 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9229 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9230 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9231 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9232 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9233 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9234
9235 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9236 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9237 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9238 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9239 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9240 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9241 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9242 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9243 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9244 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9245 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9246 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9247 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9248 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9249
9250 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9251 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9252 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9253 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9254 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9255 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9256 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9257 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9258 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9259 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9260 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9261 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9262 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9263 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9264
9265 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9266 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9267 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9268 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9269 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9270 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9271 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9272 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9273 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9274 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9275 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9276 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9277 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9278 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9279 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9280 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9281
9282 #undef GEN_SPEOP_LDST
9283 #define GEN_SPEOP_LDST(name, opc2, sh) \
9284 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9285 GEN_SPEOP_LDST(evldd, 0x00, 3),
9286 GEN_SPEOP_LDST(evldw, 0x01, 3),
9287 GEN_SPEOP_LDST(evldh, 0x02, 3),
9288 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9289 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9290 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9291 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9292 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9293 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9294 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9295 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9296
9297 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9298 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9299 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9300 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9301 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9302 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9303 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9304 };
9305
9306 #include "helper_regs.h"
9307 #include "translate_init.c"
9308
9309 /*****************************************************************************/
9310 /* Misc PowerPC helpers */
9311 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9312 int flags)
9313 {
9314 #define RGPL 4
9315 #define RFPL 4
9316
9317 int i;
9318
9319 cpu_synchronize_state(env);
9320
9321 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9322 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9323 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9324 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9325 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9326 env->hflags, env->mmu_idx);
9327 #if !defined(NO_TIMER_DUMP)
9328 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9329 #if !defined(CONFIG_USER_ONLY)
9330 " DECR %08" PRIu32
9331 #endif
9332 "\n",
9333 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9334 #if !defined(CONFIG_USER_ONLY)
9335 , cpu_ppc_load_decr(env)
9336 #endif
9337 );
9338 #endif
9339 for (i = 0; i < 32; i++) {
9340 if ((i & (RGPL - 1)) == 0)
9341 cpu_fprintf(f, "GPR%02d", i);
9342 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9343 if ((i & (RGPL - 1)) == (RGPL - 1))
9344 cpu_fprintf(f, "\n");
9345 }
9346 cpu_fprintf(f, "CR ");
9347 for (i = 0; i < 8; i++)
9348 cpu_fprintf(f, "%01x", env->crf[i]);
9349 cpu_fprintf(f, " [");
9350 for (i = 0; i < 8; i++) {
9351 char a = '-';
9352 if (env->crf[i] & 0x08)
9353 a = 'L';
9354 else if (env->crf[i] & 0x04)
9355 a = 'G';
9356 else if (env->crf[i] & 0x02)
9357 a = 'E';
9358 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9359 }
9360 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9361 env->reserve_addr);
9362 for (i = 0; i < 32; i++) {
9363 if ((i & (RFPL - 1)) == 0)
9364 cpu_fprintf(f, "FPR%02d", i);
9365 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9366 if ((i & (RFPL - 1)) == (RFPL - 1))
9367 cpu_fprintf(f, "\n");
9368 }
9369 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9370 #if !defined(CONFIG_USER_ONLY)
9371 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9372 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9373 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9374 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9375
9376 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9377 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9378 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9379 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9380
9381 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9382 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9383 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9384 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9385
9386 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9387 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9388 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9389 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9390 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9391
9392 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9393 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9394 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9395 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9396
9397 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9398 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9399 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9400 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9401
9402 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9403 " EPR " TARGET_FMT_lx "\n",
9404 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9405 env->spr[SPR_BOOKE_EPR]);
9406
9407 /* FSL-specific */
9408 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9409 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9410 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9411 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9412
9413 /*
9414 * IVORs are left out as they are large and do not change often --
9415 * they can be read with "p $ivor0", "p $ivor1", etc.
9416 */
9417 }
9418
9419 #if defined(TARGET_PPC64)
9420 if (env->flags & POWERPC_FLAG_CFAR) {
9421 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9422 }
9423 #endif
9424
9425 switch (env->mmu_model) {
9426 case POWERPC_MMU_32B:
9427 case POWERPC_MMU_601:
9428 case POWERPC_MMU_SOFT_6xx:
9429 case POWERPC_MMU_SOFT_74xx:
9430 #if defined(TARGET_PPC64)
9431 case POWERPC_MMU_620:
9432 case POWERPC_MMU_64B:
9433 #endif
9434 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9435 break;
9436 case POWERPC_MMU_BOOKE206:
9437 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9438 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9439 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9440 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9441
9442 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9443 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9444 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9445 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9446
9447 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9448 " TLB1CFG " TARGET_FMT_lx "\n",
9449 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9450 env->spr[SPR_BOOKE_TLB1CFG]);
9451 break;
9452 default:
9453 break;
9454 }
9455 #endif
9456
9457 #undef RGPL
9458 #undef RFPL
9459 }
9460
9461 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9462 int flags)
9463 {
9464 #if defined(DO_PPC_STATISTICS)
9465 opc_handler_t **t1, **t2, **t3, *handler;
9466 int op1, op2, op3;
9467
9468 t1 = env->opcodes;
9469 for (op1 = 0; op1 < 64; op1++) {
9470 handler = t1[op1];
9471 if (is_indirect_opcode(handler)) {
9472 t2 = ind_table(handler);
9473 for (op2 = 0; op2 < 32; op2++) {
9474 handler = t2[op2];
9475 if (is_indirect_opcode(handler)) {
9476 t3 = ind_table(handler);
9477 for (op3 = 0; op3 < 32; op3++) {
9478 handler = t3[op3];
9479 if (handler->count == 0)
9480 continue;
9481 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9482 "%016" PRIx64 " %" PRId64 "\n",
9483 op1, op2, op3, op1, (op3 << 5) | op2,
9484 handler->oname,
9485 handler->count, handler->count);
9486 }
9487 } else {
9488 if (handler->count == 0)
9489 continue;
9490 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9491 "%016" PRIx64 " %" PRId64 "\n",
9492 op1, op2, op1, op2, handler->oname,
9493 handler->count, handler->count);
9494 }
9495 }
9496 } else {
9497 if (handler->count == 0)
9498 continue;
9499 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9500 " %" PRId64 "\n",
9501 op1, op1, handler->oname,
9502 handler->count, handler->count);
9503 }
9504 }
9505 #endif
9506 }
9507
9508 /*****************************************************************************/
9509 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9510 TranslationBlock *tb,
9511 int search_pc)
9512 {
9513 DisasContext ctx, *ctxp = &ctx;
9514 opc_handler_t **table, *handler;
9515 target_ulong pc_start;
9516 uint16_t *gen_opc_end;
9517 CPUBreakpoint *bp;
9518 int j, lj = -1;
9519 int num_insns;
9520 int max_insns;
9521
9522 pc_start = tb->pc;
9523 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9524 ctx.nip = pc_start;
9525 ctx.tb = tb;
9526 ctx.exception = POWERPC_EXCP_NONE;
9527 ctx.spr_cb = env->spr_cb;
9528 ctx.mem_idx = env->mmu_idx;
9529 ctx.access_type = -1;
9530 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9531 #if defined(TARGET_PPC64)
9532 ctx.sf_mode = msr_is_64bit(env, env->msr);
9533 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9534 #endif
9535 ctx.fpu_enabled = msr_fp;
9536 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9537 ctx.spe_enabled = msr_spe;
9538 else
9539 ctx.spe_enabled = 0;
9540 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9541 ctx.altivec_enabled = msr_vr;
9542 else
9543 ctx.altivec_enabled = 0;
9544 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9545 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9546 else
9547 ctx.singlestep_enabled = 0;
9548 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9549 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9550 if (unlikely(env->singlestep_enabled))
9551 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9552 #if defined (DO_SINGLE_STEP) && 0
9553 /* Single step trace mode */
9554 msr_se = 1;
9555 #endif
9556 num_insns = 0;
9557 max_insns = tb->cflags & CF_COUNT_MASK;
9558 if (max_insns == 0)
9559 max_insns = CF_COUNT_MASK;
9560
9561 gen_tb_start();
9562 /* Set env in case of segfault during code fetch */
9563 while (ctx.exception == POWERPC_EXCP_NONE
9564 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9565 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9566 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9567 if (bp->pc == ctx.nip) {
9568 gen_debug_exception(ctxp);
9569 break;
9570 }
9571 }
9572 }
9573 if (unlikely(search_pc)) {
9574 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9575 if (lj < j) {
9576 lj++;
9577 while (lj < j)
9578 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9579 }
9580 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9581 tcg_ctx.gen_opc_instr_start[lj] = 1;
9582 tcg_ctx.gen_opc_icount[lj] = num_insns;
9583 }
9584 LOG_DISAS("----------------\n");
9585 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9586 ctx.nip, ctx.mem_idx, (int)msr_ir);
9587 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9588 gen_io_start();
9589 if (unlikely(ctx.le_mode)) {
9590 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9591 } else {
9592 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9593 }
9594 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9595 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9596 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9597 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9598 tcg_gen_debug_insn_start(ctx.nip);
9599 }
9600 ctx.nip += 4;
9601 table = env->opcodes;
9602 num_insns++;
9603 handler = table[opc1(ctx.opcode)];
9604 if (is_indirect_opcode(handler)) {
9605 table = ind_table(handler);
9606 handler = table[opc2(ctx.opcode)];
9607 if (is_indirect_opcode(handler)) {
9608 table = ind_table(handler);
9609 handler = table[opc3(ctx.opcode)];
9610 }
9611 }
9612 /* Is opcode *REALLY* valid ? */
9613 if (unlikely(handler->handler == &gen_invalid)) {
9614 if (qemu_log_enabled()) {
9615 qemu_log("invalid/unsupported opcode: "
9616 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9617 opc1(ctx.opcode), opc2(ctx.opcode),
9618 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9619 }
9620 } else {
9621 uint32_t inval;
9622
9623 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9624 inval = handler->inval2;
9625 } else {
9626 inval = handler->inval1;
9627 }
9628
9629 if (unlikely((ctx.opcode & inval) != 0)) {
9630 if (qemu_log_enabled()) {
9631 qemu_log("invalid bits: %08x for opcode: "
9632 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9633 ctx.opcode & inval, opc1(ctx.opcode),
9634 opc2(ctx.opcode), opc3(ctx.opcode),
9635 ctx.opcode, ctx.nip - 4);
9636 }
9637 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9638 break;
9639 }
9640 }
9641 (*(handler->handler))(&ctx);
9642 #if defined(DO_PPC_STATISTICS)
9643 handler->count++;
9644 #endif
9645 /* Check trace mode exceptions */
9646 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9647 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9648 ctx.exception != POWERPC_SYSCALL &&
9649 ctx.exception != POWERPC_EXCP_TRAP &&
9650 ctx.exception != POWERPC_EXCP_BRANCH)) {
9651 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9652 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9653 (env->singlestep_enabled) ||
9654 singlestep ||
9655 num_insns >= max_insns)) {
9656 /* if we reach a page boundary or are single stepping, stop
9657 * generation
9658 */
9659 break;
9660 }
9661 }
9662 if (tb->cflags & CF_LAST_IO)
9663 gen_io_end();
9664 if (ctx.exception == POWERPC_EXCP_NONE) {
9665 gen_goto_tb(&ctx, 0, ctx.nip);
9666 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9667 if (unlikely(env->singlestep_enabled)) {
9668 gen_debug_exception(ctxp);
9669 }
9670 /* Generate the return instruction */
9671 tcg_gen_exit_tb(0);
9672 }
9673 gen_tb_end(tb, num_insns);
9674 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9675 if (unlikely(search_pc)) {
9676 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9677 lj++;
9678 while (lj <= j)
9679 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9680 } else {
9681 tb->size = ctx.nip - pc_start;
9682 tb->icount = num_insns;
9683 }
9684 #if defined(DEBUG_DISAS)
9685 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9686 int flags;
9687 flags = env->bfd_mach;
9688 flags |= ctx.le_mode << 16;
9689 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9690 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9691 qemu_log("\n");
9692 }
9693 #endif
9694 }
9695
9696 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9697 {
9698 gen_intermediate_code_internal(env, tb, 0);
9699 }
9700
9701 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9702 {
9703 gen_intermediate_code_internal(env, tb, 1);
9704 }
9705
9706 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9707 {
9708 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9709 }
CRIS target port of Qemu