target-sparc/fop_helper.c

   1 /*
   2  * FPU op helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "dyngen-exec.h"
  22 #include "helper.h"
  23
  24 #define DT0 (env->dt0)
  25 #define DT1 (env->dt1)
  26 #define QT0 (env->qt0)
  27 #define QT1 (env->qt1)
  28
  29 #define F_HELPER(name, p) void helper_f##name##p(void)
  30
  31 #define F_BINOP(name)                                           \
  32     float32 helper_f ## name ## s (float32 src1, float32 src2)  \
  33     {                                                           \
  34         return float32_ ## name (src1, src2, &env->fp_status);  \
  35     }                                                           \
  36     F_HELPER(name, d)                                           \
  37     {                                                           \
  38         DT0 = float64_ ## name (DT0, DT1, &env->fp_status);     \
  39     }                                                           \
  40     F_HELPER(name, q)                                           \
  41     {                                                           \
  42         QT0 = float128_ ## name (QT0, QT1, &env->fp_status);    \
  43     }
  44
  45 F_BINOP(add);
  46 F_BINOP(sub);
  47 F_BINOP(mul);
  48 F_BINOP(div);
  49 #undef F_BINOP
  50
  51 void helper_fsmuld(float32 src1, float32 src2)
  52 {
  53     DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
  54                       float32_to_float64(src2, &env->fp_status),
  55                       &env->fp_status);
  56 }
  57
  58 void helper_fdmulq(void)
  59 {
  60     QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
  61                        float64_to_float128(DT1, &env->fp_status),
  62                        &env->fp_status);
  63 }
  64
  65 float32 helper_fnegs(float32 src)
  66 {
  67     return float32_chs(src);
  68 }
  69
  70 #ifdef TARGET_SPARC64
  71 F_HELPER(neg, d)
  72 {
  73     DT0 = float64_chs(DT1);
  74 }
  75
  76 F_HELPER(neg, q)
  77 {
  78     QT0 = float128_chs(QT1);
  79 }
  80 #endif
  81
  82 /* Integer to float conversion.  */
  83 float32 helper_fitos(int32_t src)
  84 {
  85     return int32_to_float32(src, &env->fp_status);
  86 }
  87
  88 void helper_fitod(int32_t src)
  89 {
  90     DT0 = int32_to_float64(src, &env->fp_status);
  91 }
  92
  93 void helper_fitoq(int32_t src)
  94 {
  95     QT0 = int32_to_float128(src, &env->fp_status);
  96 }
  97
  98 #ifdef TARGET_SPARC64
  99 float32 helper_fxtos(void)
 100 {
 101     return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
 102 }
 103
 104 F_HELPER(xto, d)
 105 {
 106     DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
 107 }
 108
 109 F_HELPER(xto, q)
 110 {
 111     QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
 112 }
 113 #endif
 114 #undef F_HELPER
 115
 116 /* floating point conversion */
 117 float32 helper_fdtos(void)
 118 {
 119     return float64_to_float32(DT1, &env->fp_status);
 120 }
 121
 122 void helper_fstod(float32 src)
 123 {
 124     DT0 = float32_to_float64(src, &env->fp_status);
 125 }
 126
 127 float32 helper_fqtos(void)
 128 {
 129     return float128_to_float32(QT1, &env->fp_status);
 130 }
 131
 132 void helper_fstoq(float32 src)
 133 {
 134     QT0 = float32_to_float128(src, &env->fp_status);
 135 }
 136
 137 void helper_fqtod(void)
 138 {
 139     DT0 = float128_to_float64(QT1, &env->fp_status);
 140 }
 141
 142 void helper_fdtoq(void)
 143 {
 144     QT0 = float64_to_float128(DT1, &env->fp_status);
 145 }
 146
 147 /* Float to integer conversion.  */
 148 int32_t helper_fstoi(float32 src)
 149 {
 150     return float32_to_int32_round_to_zero(src, &env->fp_status);
 151 }
 152
 153 int32_t helper_fdtoi(void)
 154 {
 155     return float64_to_int32_round_to_zero(DT1, &env->fp_status);
 156 }
 157
 158 int32_t helper_fqtoi(void)
 159 {
 160     return float128_to_int32_round_to_zero(QT1, &env->fp_status);
 161 }
 162
 163 #ifdef TARGET_SPARC64
 164 void helper_fstox(float32 src)
 165 {
 166     *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
 167 }
 168
 169 void helper_fdtox(void)
 170 {
 171     *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
 172 }
 173
 174 void helper_fqtox(void)
 175 {
 176     *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
 177 }
 178 #endif
 179
 180 float32 helper_fabss(float32 src)
 181 {
 182     return float32_abs(src);
 183 }
 184
 185 #ifdef TARGET_SPARC64
 186 void helper_fabsd(void)
 187 {
 188     DT0 = float64_abs(DT1);
 189 }
 190
 191 void helper_fabsq(void)
 192 {
 193     QT0 = float128_abs(QT1);
 194 }
 195 #endif
 196
 197 float32 helper_fsqrts(float32 src)
 198 {
 199     return float32_sqrt(src, &env->fp_status);
 200 }
 201
 202 void helper_fsqrtd(void)
 203 {
 204     DT0 = float64_sqrt(DT1, &env->fp_status);
 205 }
 206
 207 void helper_fsqrtq(void)
 208 {
 209     QT0 = float128_sqrt(QT1, &env->fp_status);
 210 }
 211
 212 #define GEN_FCMP(name, size, reg1, reg2, FS, E)                         \
 213     void glue(helper_, name) (void)                                     \
 214     {                                                                   \
 215         env->fsr &= FSR_FTT_NMASK;                                      \
 216         if (E && (glue(size, _is_any_nan)(reg1) ||                      \
 217                   glue(size, _is_any_nan)(reg2)) &&                     \
 218             (env->fsr & FSR_NVM)) {                                     \
 219             env->fsr |= FSR_NVC;                                        \
 220             env->fsr |= FSR_FTT_IEEE_EXCP;                              \
 221             helper_raise_exception(env, TT_FP_EXCP);                    \
 222         }                                                               \
 223         switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
 224         case float_relation_unordered:                                  \
 225             if ((env->fsr & FSR_NVM)) {                                 \
 226                 env->fsr |= FSR_NVC;                                    \
 227                 env->fsr |= FSR_FTT_IEEE_EXCP;                          \
 228                 helper_raise_exception(env, TT_FP_EXCP);                \
 229             } else {                                                    \
 230                 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);             \
 231                 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                \
 232                 env->fsr |= FSR_NVA;                                    \
 233             }                                                           \
 234             break;                                                      \
 235         case float_relation_less:                                       \
 236             env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
 237             env->fsr |= FSR_FCC0 << FS;                                 \
 238             break;                                                      \
 239         case float_relation_greater:                                    \
 240             env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
 241             env->fsr |= FSR_FCC1 << FS;                                 \
 242             break;                                                      \
 243         default:                                                        \
 244             env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
 245             break;                                                      \
 246         }                                                               \
 247     }
 248 #define GEN_FCMPS(name, size, FS, E)                                    \
 249     void glue(helper_, name)(float32 src1, float32 src2)                \
 250     {                                                                   \
 251         env->fsr &= FSR_FTT_NMASK;                                      \
 252         if (E && (glue(size, _is_any_nan)(src1) ||                      \
 253                   glue(size, _is_any_nan)(src2)) &&                     \
 254             (env->fsr & FSR_NVM)) {                                     \
 255             env->fsr |= FSR_NVC;                                        \
 256             env->fsr |= FSR_FTT_IEEE_EXCP;                              \
 257             helper_raise_exception(env, TT_FP_EXCP);                    \
 258         }                                                               \
 259         switch (glue(size, _compare) (src1, src2, &env->fp_status)) {   \
 260         case float_relation_unordered:                                  \
 261             if ((env->fsr & FSR_NVM)) {                                 \
 262                 env->fsr |= FSR_NVC;                                    \
 263                 env->fsr |= FSR_FTT_IEEE_EXCP;                          \
 264                 helper_raise_exception(env, TT_FP_EXCP);                \
 265             } else {                                                    \
 266                 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);             \
 267                 env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                \
 268                 env->fsr |= FSR_NVA;                                    \
 269             }                                                           \
 270             break;                                                      \
 271         case float_relation_less:                                       \
 272             env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
 273             env->fsr |= FSR_FCC0 << FS;                                 \
 274             break;                                                      \
 275         case float_relation_greater:                                    \
 276             env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
 277             env->fsr |= FSR_FCC1 << FS;                                 \
 278             break;                                                      \
 279         default:                                                        \
 280             env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                 \
 281             break;                                                      \
 282         }                                                               \
 283     }
 284
 285 GEN_FCMPS(fcmps, float32, 0, 0);
 286 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
 287
 288 GEN_FCMPS(fcmpes, float32, 0, 1);
 289 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
 290
 291 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
 292 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
 293
 294 #ifdef TARGET_SPARC64
 295 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
 296 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
 297 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
 298
 299 GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
 300 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
 301 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
 302
 303 GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
 304 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
 305 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
 306
 307 GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
 308 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
 309 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
 310
 311 GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
 312 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
 313 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
 314
 315 GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
 316 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
 317 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
 318 #endif
 319 #undef GEN_FCMPS
 320
 321 void helper_check_ieee_exceptions(void)
 322 {
 323     target_ulong status;
 324
 325     status = get_float_exception_flags(&env->fp_status);
 326     if (status) {
 327         /* Copy IEEE 754 flags into FSR */
 328         if (status & float_flag_invalid) {
 329             env->fsr |= FSR_NVC;
 330         }
 331         if (status & float_flag_overflow) {
 332             env->fsr |= FSR_OFC;
 333         }
 334         if (status & float_flag_underflow) {
 335             env->fsr |= FSR_UFC;
 336         }
 337         if (status & float_flag_divbyzero) {
 338             env->fsr |= FSR_DZC;
 339         }
 340         if (status & float_flag_inexact) {
 341             env->fsr |= FSR_NXC;
 342         }
 343
 344         if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
 345             /* Unmasked exception, generate a trap */
 346             env->fsr |= FSR_FTT_IEEE_EXCP;
 347             helper_raise_exception(env, TT_FP_EXCP);
 348         } else {
 349             /* Accumulate exceptions */
 350             env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
 351         }
 352     }
 353 }
 354
 355 void helper_clear_float_exceptions(void)
 356 {
 357     set_float_exception_flags(0, &env->fp_status);
 358 }
 359
 360 static inline void set_fsr(void)
 361 {
 362     int rnd_mode;
 363
 364     switch (env->fsr & FSR_RD_MASK) {
 365     case FSR_RD_NEAREST:
 366         rnd_mode = float_round_nearest_even;
 367         break;
 368     default:
 369     case FSR_RD_ZERO:
 370         rnd_mode = float_round_to_zero;
 371         break;
 372     case FSR_RD_POS:
 373         rnd_mode = float_round_up;
 374         break;
 375     case FSR_RD_NEG:
 376         rnd_mode = float_round_down;
 377         break;
 378     }
 379     set_float_rounding_mode(rnd_mode, &env->fp_status);
 380 }
 381
 382 void helper_ldfsr(uint32_t new_fsr)
 383 {
 384     env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
 385     set_fsr();
 386 }
 387
 388 #ifdef TARGET_SPARC64
 389 void helper_ldxfsr(uint64_t new_fsr)
 390 {
 391     env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
 392     set_fsr();
 393 }
 394 #endif