target-lm32/translate.c

   1 /*
   2  *  LatticeMico32 main translation routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "disas/disas.h"
  23 #include "exec/helper-proto.h"
  24 #include "tcg-op.h"
  25
  26 #include "exec/cpu_ldst.h"
  27 #include "hw/lm32/lm32_pic.h"
  28
  29 #include "exec/helper-gen.h"
  30
  31 #include "trace-tcg.h"
  32 #include "exec/log.h"
  33
  34
  35 #define DISAS_LM32 1
  36 #if DISAS_LM32
  37 #  define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
  38 #else
  39 #  define LOG_DIS(...) do { } while (0)
  40 #endif
  41
  42 #define EXTRACT_FIELD(src, start, end) \
  43             (((src) >> start) & ((1 << (end - start + 1)) - 1))
  44
  45 #define MEM_INDEX 0
  46
  47 static TCGv_env cpu_env;
  48 static TCGv cpu_R[32];
  49 static TCGv cpu_pc;
  50 static TCGv cpu_ie;
  51 static TCGv cpu_icc;
  52 static TCGv cpu_dcc;
  53 static TCGv cpu_cc;
  54 static TCGv cpu_cfg;
  55 static TCGv cpu_eba;
  56 static TCGv cpu_dc;
  57 static TCGv cpu_deba;
  58 static TCGv cpu_bp[4];
  59 static TCGv cpu_wp[4];
  60
  61 #include "exec/gen-icount.h"
  62
  63 enum {
  64     OP_FMT_RI,
  65     OP_FMT_RR,
  66     OP_FMT_CR,
  67     OP_FMT_I
  68 };
  69
  70 /* This is the state at translation time.  */
  71 typedef struct DisasContext {
  72     target_ulong pc;
  73
  74     /* Decoder.  */
  75     int format;
  76     uint32_t ir;
  77     uint8_t opcode;
  78     uint8_t r0, r1, r2, csr;
  79     uint16_t imm5;
  80     uint16_t imm16;
  81     uint32_t imm26;
  82
  83     unsigned int delayed_branch;
  84     unsigned int tb_flags, synced_flags; /* tb dependent flags.  */
  85     int is_jmp;
  86
  87     struct TranslationBlock *tb;
  88     int singlestep_enabled;
  89
  90     uint32_t features;
  91     uint8_t num_breakpoints;
  92     uint8_t num_watchpoints;
  93 } DisasContext;
  94
  95 static const char *regnames[] = {
  96     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  97     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  98     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  99     "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
 100     "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
 101     "wp1", "wp2", "wp3"
 102 };
 103
 104 static inline int zero_extend(unsigned int val, int width)
 105 {
 106     return val & ((1 << width) - 1);
 107 }
 108
 109 static inline int sign_extend(unsigned int val, int width)
 110 {
 111     int sval;
 112
 113     /* LSL.  */
 114     val <<= 32 - width;
 115     sval = val;
 116     /* ASR.  */
 117     sval >>= 32 - width;
 118
 119     return sval;
 120 }
 121
 122 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
 123 {
 124     TCGv_i32 tmp = tcg_const_i32(index);
 125
 126     gen_helper_raise_exception(cpu_env, tmp);
 127     tcg_temp_free_i32(tmp);
 128 }
 129
 130 static inline void t_gen_illegal_insn(DisasContext *dc)
 131 {
 132     tcg_gen_movi_tl(cpu_pc, dc->pc);
 133     gen_helper_ill(cpu_env);
 134 }
 135
 136 static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
 137 {
 138     if (unlikely(dc->singlestep_enabled)) {
 139         return false;
 140     }
 141
 142 #ifndef CONFIG_USER_ONLY
 143     return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
 144 #else
 145     return true;
 146 #endif
 147 }
 148
 149 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
 150 {
 151     if (use_goto_tb(dc, dest)) {
 152         tcg_gen_goto_tb(n);
 153         tcg_gen_movi_tl(cpu_pc, dest);
 154         tcg_gen_exit_tb((uintptr_t)dc->tb + n);
 155     } else {
 156         tcg_gen_movi_tl(cpu_pc, dest);
 157         if (dc->singlestep_enabled) {
 158             t_gen_raise_exception(dc, EXCP_DEBUG);
 159         }
 160         tcg_gen_exit_tb(0);
 161     }
 162 }
 163
 164 static void dec_add(DisasContext *dc)
 165 {
 166     if (dc->format == OP_FMT_RI) {
 167         if (dc->r0 == R_R0) {
 168             if (dc->r1 == R_R0 && dc->imm16 == 0) {
 169                 LOG_DIS("nop\n");
 170             } else {
 171                 LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16));
 172             }
 173         } else {
 174             LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
 175                     sign_extend(dc->imm16, 16));
 176         }
 177     } else {
 178         LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 179     }
 180
 181     if (dc->format == OP_FMT_RI) {
 182         tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 183                 sign_extend(dc->imm16, 16));
 184     } else {
 185         tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 186     }
 187 }
 188
 189 static void dec_and(DisasContext *dc)
 190 {
 191     if (dc->format == OP_FMT_RI) {
 192         LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
 193                 zero_extend(dc->imm16, 16));
 194     } else {
 195         LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 196     }
 197
 198     if (dc->format == OP_FMT_RI) {
 199         tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 200                 zero_extend(dc->imm16, 16));
 201     } else  {
 202         if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) {
 203             tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 204             gen_helper_hlt(cpu_env);
 205         } else {
 206             tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 207         }
 208     }
 209 }
 210
 211 static void dec_andhi(DisasContext *dc)
 212 {
 213     LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
 214
 215     tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 216 }
 217
 218 static void dec_b(DisasContext *dc)
 219 {
 220     if (dc->r0 == R_RA) {
 221         LOG_DIS("ret\n");
 222     } else if (dc->r0 == R_EA) {
 223         LOG_DIS("eret\n");
 224     } else if (dc->r0 == R_BA) {
 225         LOG_DIS("bret\n");
 226     } else {
 227         LOG_DIS("b r%d\n", dc->r0);
 228     }
 229
 230     /* restore IE.IE in case of an eret */
 231     if (dc->r0 == R_EA) {
 232         TCGv t0 = tcg_temp_new();
 233         TCGLabel *l1 = gen_new_label();
 234         tcg_gen_andi_tl(t0, cpu_ie, IE_EIE);
 235         tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
 236         tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1);
 237         tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
 238         gen_set_label(l1);
 239         tcg_temp_free(t0);
 240     } else if (dc->r0 == R_BA) {
 241         TCGv t0 = tcg_temp_new();
 242         TCGLabel *l1 = gen_new_label();
 243         tcg_gen_andi_tl(t0, cpu_ie, IE_BIE);
 244         tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE);
 245         tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1);
 246         tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE);
 247         gen_set_label(l1);
 248         tcg_temp_free(t0);
 249     }
 250     tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
 251
 252     dc->is_jmp = DISAS_JUMP;
 253 }
 254
 255 static void dec_bi(DisasContext *dc)
 256 {
 257     LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26));
 258
 259     gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
 260
 261     dc->is_jmp = DISAS_TB_JUMP;
 262 }
 263
 264 static inline void gen_cond_branch(DisasContext *dc, int cond)
 265 {
 266     TCGLabel *l1 = gen_new_label();
 267     tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1);
 268     gen_goto_tb(dc, 0, dc->pc + 4);
 269     gen_set_label(l1);
 270     gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16)));
 271     dc->is_jmp = DISAS_TB_JUMP;
 272 }
 273
 274 static void dec_be(DisasContext *dc)
 275 {
 276     LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
 277             sign_extend(dc->imm16, 16) * 4);
 278
 279     gen_cond_branch(dc, TCG_COND_EQ);
 280 }
 281
 282 static void dec_bg(DisasContext *dc)
 283 {
 284     LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
 285             sign_extend(dc->imm16, 16 * 4));
 286
 287     gen_cond_branch(dc, TCG_COND_GT);
 288 }
 289
 290 static void dec_bge(DisasContext *dc)
 291 {
 292     LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
 293             sign_extend(dc->imm16, 16) * 4);
 294
 295     gen_cond_branch(dc, TCG_COND_GE);
 296 }
 297
 298 static void dec_bgeu(DisasContext *dc)
 299 {
 300     LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
 301             sign_extend(dc->imm16, 16) * 4);
 302
 303     gen_cond_branch(dc, TCG_COND_GEU);
 304 }
 305
 306 static void dec_bgu(DisasContext *dc)
 307 {
 308     LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
 309             sign_extend(dc->imm16, 16) * 4);
 310
 311     gen_cond_branch(dc, TCG_COND_GTU);
 312 }
 313
 314 static void dec_bne(DisasContext *dc)
 315 {
 316     LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
 317             sign_extend(dc->imm16, 16) * 4);
 318
 319     gen_cond_branch(dc, TCG_COND_NE);
 320 }
 321
 322 static void dec_call(DisasContext *dc)
 323 {
 324     LOG_DIS("call r%d\n", dc->r0);
 325
 326     tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
 327     tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]);
 328
 329     dc->is_jmp = DISAS_JUMP;
 330 }
 331
 332 static void dec_calli(DisasContext *dc)
 333 {
 334     LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4);
 335
 336     tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
 337     gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26)));
 338
 339     dc->is_jmp = DISAS_TB_JUMP;
 340 }
 341
 342 static inline void gen_compare(DisasContext *dc, int cond)
 343 {
 344     int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
 345     int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
 346     int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1;
 347     int i;
 348
 349     if (dc->format == OP_FMT_RI) {
 350         switch (cond) {
 351         case TCG_COND_GEU:
 352         case TCG_COND_GTU:
 353             i = zero_extend(dc->imm16, 16);
 354             break;
 355         default:
 356             i = sign_extend(dc->imm16, 16);
 357             break;
 358         }
 359
 360         tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], i);
 361     } else {
 362         tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]);
 363     }
 364 }
 365
 366 static void dec_cmpe(DisasContext *dc)
 367 {
 368     if (dc->format == OP_FMT_RI) {
 369         LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
 370                 sign_extend(dc->imm16, 16));
 371     } else {
 372         LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 373     }
 374
 375     gen_compare(dc, TCG_COND_EQ);
 376 }
 377
 378 static void dec_cmpg(DisasContext *dc)
 379 {
 380     if (dc->format == OP_FMT_RI) {
 381         LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
 382                 sign_extend(dc->imm16, 16));
 383     } else {
 384         LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 385     }
 386
 387     gen_compare(dc, TCG_COND_GT);
 388 }
 389
 390 static void dec_cmpge(DisasContext *dc)
 391 {
 392     if (dc->format == OP_FMT_RI) {
 393         LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
 394                 sign_extend(dc->imm16, 16));
 395     } else {
 396         LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 397     }
 398
 399     gen_compare(dc, TCG_COND_GE);
 400 }
 401
 402 static void dec_cmpgeu(DisasContext *dc)
 403 {
 404     if (dc->format == OP_FMT_RI) {
 405         LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
 406                 zero_extend(dc->imm16, 16));
 407     } else {
 408         LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 409     }
 410
 411     gen_compare(dc, TCG_COND_GEU);
 412 }
 413
 414 static void dec_cmpgu(DisasContext *dc)
 415 {
 416     if (dc->format == OP_FMT_RI) {
 417         LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
 418                 zero_extend(dc->imm16, 16));
 419     } else {
 420         LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 421     }
 422
 423     gen_compare(dc, TCG_COND_GTU);
 424 }
 425
 426 static void dec_cmpne(DisasContext *dc)
 427 {
 428     if (dc->format == OP_FMT_RI) {
 429         LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
 430                 sign_extend(dc->imm16, 16));
 431     } else {
 432         LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 433     }
 434
 435     gen_compare(dc, TCG_COND_NE);
 436 }
 437
 438 static void dec_divu(DisasContext *dc)
 439 {
 440     TCGLabel *l1;
 441
 442     LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 443
 444     if (!(dc->features & LM32_FEATURE_DIVIDE)) {
 445         qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
 446         t_gen_illegal_insn(dc);
 447         return;
 448     }
 449
 450     l1 = gen_new_label();
 451     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
 452     tcg_gen_movi_tl(cpu_pc, dc->pc);
 453     t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
 454     gen_set_label(l1);
 455     tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 456 }
 457
 458 static void dec_lb(DisasContext *dc)
 459 {
 460     TCGv t0;
 461
 462     LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 463
 464     t0 = tcg_temp_new();
 465     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 466     tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX);
 467     tcg_temp_free(t0);
 468 }
 469
 470 static void dec_lbu(DisasContext *dc)
 471 {
 472     TCGv t0;
 473
 474     LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 475
 476     t0 = tcg_temp_new();
 477     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 478     tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX);
 479     tcg_temp_free(t0);
 480 }
 481
 482 static void dec_lh(DisasContext *dc)
 483 {
 484     TCGv t0;
 485
 486     LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 487
 488     t0 = tcg_temp_new();
 489     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 490     tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX);
 491     tcg_temp_free(t0);
 492 }
 493
 494 static void dec_lhu(DisasContext *dc)
 495 {
 496     TCGv t0;
 497
 498     LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
 499
 500     t0 = tcg_temp_new();
 501     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 502     tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX);
 503     tcg_temp_free(t0);
 504 }
 505
 506 static void dec_lw(DisasContext *dc)
 507 {
 508     TCGv t0;
 509
 510     LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16));
 511
 512     t0 = tcg_temp_new();
 513     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 514     tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX);
 515     tcg_temp_free(t0);
 516 }
 517
 518 static void dec_modu(DisasContext *dc)
 519 {
 520     TCGLabel *l1;
 521
 522     LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
 523
 524     if (!(dc->features & LM32_FEATURE_DIVIDE)) {
 525         qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
 526         t_gen_illegal_insn(dc);
 527         return;
 528     }
 529
 530     l1 = gen_new_label();
 531     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
 532     tcg_gen_movi_tl(cpu_pc, dc->pc);
 533     t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO);
 534     gen_set_label(l1);
 535     tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 536 }
 537
 538 static void dec_mul(DisasContext *dc)
 539 {
 540     if (dc->format == OP_FMT_RI) {
 541         LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
 542                 sign_extend(dc->imm16, 16));
 543     } else {
 544         LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 545     }
 546
 547     if (!(dc->features & LM32_FEATURE_MULTIPLY)) {
 548         qemu_log_mask(LOG_GUEST_ERROR,
 549                       "hardware multiplier is not available\n");
 550         t_gen_illegal_insn(dc);
 551         return;
 552     }
 553
 554     if (dc->format == OP_FMT_RI) {
 555         tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 556                 sign_extend(dc->imm16, 16));
 557     } else {
 558         tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 559     }
 560 }
 561
 562 static void dec_nor(DisasContext *dc)
 563 {
 564     if (dc->format == OP_FMT_RI) {
 565         LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
 566                 zero_extend(dc->imm16, 16));
 567     } else {
 568         LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 569     }
 570
 571     if (dc->format == OP_FMT_RI) {
 572         TCGv t0 = tcg_temp_new();
 573         tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
 574         tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0);
 575         tcg_temp_free(t0);
 576     } else {
 577         tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 578     }
 579 }
 580
 581 static void dec_or(DisasContext *dc)
 582 {
 583     if (dc->format == OP_FMT_RI) {
 584         LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
 585                 zero_extend(dc->imm16, 16));
 586     } else {
 587         if (dc->r1 == R_R0) {
 588             LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
 589         } else {
 590             LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 591         }
 592     }
 593
 594     if (dc->format == OP_FMT_RI) {
 595         tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 596                 zero_extend(dc->imm16, 16));
 597     } else {
 598         tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 599     }
 600 }
 601
 602 static void dec_orhi(DisasContext *dc)
 603 {
 604     if (dc->r0 == R_R0) {
 605         LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
 606     } else {
 607         LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
 608     }
 609
 610     tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 611 }
 612
 613 static void dec_scall(DisasContext *dc)
 614 {
 615     switch (dc->imm5) {
 616     case 2:
 617         LOG_DIS("break\n");
 618         tcg_gen_movi_tl(cpu_pc, dc->pc);
 619         t_gen_raise_exception(dc, EXCP_BREAKPOINT);
 620         break;
 621     case 7:
 622         LOG_DIS("scall\n");
 623         tcg_gen_movi_tl(cpu_pc, dc->pc);
 624         t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
 625         break;
 626     default:
 627         qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode @0x%x", dc->pc);
 628         t_gen_illegal_insn(dc);
 629         break;
 630     }
 631 }
 632
 633 static void dec_rcsr(DisasContext *dc)
 634 {
 635     LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
 636
 637     switch (dc->csr) {
 638     case CSR_IE:
 639         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie);
 640         break;
 641     case CSR_IM:
 642         gen_helper_rcsr_im(cpu_R[dc->r2], cpu_env);
 643         break;
 644     case CSR_IP:
 645         gen_helper_rcsr_ip(cpu_R[dc->r2], cpu_env);
 646         break;
 647     case CSR_CC:
 648         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc);
 649         break;
 650     case CSR_CFG:
 651         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg);
 652         break;
 653     case CSR_EBA:
 654         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba);
 655         break;
 656     case CSR_DC:
 657         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc);
 658         break;
 659     case CSR_DEBA:
 660         tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba);
 661         break;
 662     case CSR_JTX:
 663         gen_helper_rcsr_jtx(cpu_R[dc->r2], cpu_env);
 664         break;
 665     case CSR_JRX:
 666         gen_helper_rcsr_jrx(cpu_R[dc->r2], cpu_env);
 667         break;
 668     case CSR_ICC:
 669     case CSR_DCC:
 670     case CSR_BP0:
 671     case CSR_BP1:
 672     case CSR_BP2:
 673     case CSR_BP3:
 674     case CSR_WP0:
 675     case CSR_WP1:
 676     case CSR_WP2:
 677     case CSR_WP3:
 678         qemu_log_mask(LOG_GUEST_ERROR, "invalid read access csr=%x\n", dc->csr);
 679         break;
 680     default:
 681         qemu_log_mask(LOG_GUEST_ERROR, "read_csr: unknown csr=%x\n", dc->csr);
 682         break;
 683     }
 684 }
 685
 686 static void dec_sb(DisasContext *dc)
 687 {
 688     TCGv t0;
 689
 690     LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
 691
 692     t0 = tcg_temp_new();
 693     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 694     tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX);
 695     tcg_temp_free(t0);
 696 }
 697
 698 static void dec_sextb(DisasContext *dc)
 699 {
 700     LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
 701
 702     if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
 703         qemu_log_mask(LOG_GUEST_ERROR,
 704                       "hardware sign extender is not available\n");
 705         t_gen_illegal_insn(dc);
 706         return;
 707     }
 708
 709     tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
 710 }
 711
 712 static void dec_sexth(DisasContext *dc)
 713 {
 714     LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
 715
 716     if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
 717         qemu_log_mask(LOG_GUEST_ERROR,
 718                       "hardware sign extender is not available\n");
 719         t_gen_illegal_insn(dc);
 720         return;
 721     }
 722
 723     tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
 724 }
 725
 726 static void dec_sh(DisasContext *dc)
 727 {
 728     TCGv t0;
 729
 730     LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
 731
 732     t0 = tcg_temp_new();
 733     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 734     tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX);
 735     tcg_temp_free(t0);
 736 }
 737
 738 static void dec_sl(DisasContext *dc)
 739 {
 740     if (dc->format == OP_FMT_RI) {
 741         LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 742     } else {
 743         LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 744     }
 745
 746     if (!(dc->features & LM32_FEATURE_SHIFT)) {
 747         qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not available\n");
 748         t_gen_illegal_insn(dc);
 749         return;
 750     }
 751
 752     if (dc->format == OP_FMT_RI) {
 753         tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 754     } else {
 755         TCGv t0 = tcg_temp_new();
 756         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 757         tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 758         tcg_temp_free(t0);
 759     }
 760 }
 761
 762 static void dec_sr(DisasContext *dc)
 763 {
 764     if (dc->format == OP_FMT_RI) {
 765         LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 766     } else {
 767         LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 768     }
 769
 770     /* The real CPU (w/o hardware shifter) only supports right shift by exactly
 771      * one bit */
 772     if (dc->format == OP_FMT_RI) {
 773         if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
 774             qemu_log_mask(LOG_GUEST_ERROR,
 775                     "hardware shifter is not available\n");
 776             t_gen_illegal_insn(dc);
 777             return;
 778         }
 779         tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 780     } else {
 781         TCGLabel *l1 = gen_new_label();
 782         TCGLabel *l2 = gen_new_label();
 783         TCGv t0 = tcg_temp_local_new();
 784         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 785
 786         if (!(dc->features & LM32_FEATURE_SHIFT)) {
 787             tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
 788             t_gen_illegal_insn(dc);
 789             tcg_gen_br(l2);
 790         }
 791
 792         gen_set_label(l1);
 793         tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 794         gen_set_label(l2);
 795
 796         tcg_temp_free(t0);
 797     }
 798 }
 799
 800 static void dec_sru(DisasContext *dc)
 801 {
 802     if (dc->format == OP_FMT_RI) {
 803         LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
 804     } else {
 805         LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 806     }
 807
 808     if (dc->format == OP_FMT_RI) {
 809         if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
 810             qemu_log_mask(LOG_GUEST_ERROR,
 811                     "hardware shifter is not available\n");
 812             t_gen_illegal_insn(dc);
 813             return;
 814         }
 815         tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
 816     } else {
 817         TCGLabel *l1 = gen_new_label();
 818         TCGLabel *l2 = gen_new_label();
 819         TCGv t0 = tcg_temp_local_new();
 820         tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
 821
 822         if (!(dc->features & LM32_FEATURE_SHIFT)) {
 823             tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
 824             t_gen_illegal_insn(dc);
 825             tcg_gen_br(l2);
 826         }
 827
 828         gen_set_label(l1);
 829         tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
 830         gen_set_label(l2);
 831
 832         tcg_temp_free(t0);
 833     }
 834 }
 835
 836 static void dec_sub(DisasContext *dc)
 837 {
 838     LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 839
 840     tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 841 }
 842
 843 static void dec_sw(DisasContext *dc)
 844 {
 845     TCGv t0;
 846
 847     LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1);
 848
 849     t0 = tcg_temp_new();
 850     tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
 851     tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX);
 852     tcg_temp_free(t0);
 853 }
 854
 855 static void dec_user(DisasContext *dc)
 856 {
 857     LOG_DIS("user");
 858
 859     qemu_log_mask(LOG_GUEST_ERROR, "user instruction undefined\n");
 860     t_gen_illegal_insn(dc);
 861 }
 862
 863 static void dec_wcsr(DisasContext *dc)
 864 {
 865     int no;
 866
 867     LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
 868
 869     switch (dc->csr) {
 870     case CSR_IE:
 871         tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]);
 872         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 873         dc->is_jmp = DISAS_UPDATE;
 874         break;
 875     case CSR_IM:
 876         /* mark as an io operation because it could cause an interrupt */
 877         if (dc->tb->cflags & CF_USE_ICOUNT) {
 878             gen_io_start();
 879         }
 880         gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]);
 881         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 882         if (dc->tb->cflags & CF_USE_ICOUNT) {
 883             gen_io_end();
 884         }
 885         dc->is_jmp = DISAS_UPDATE;
 886         break;
 887     case CSR_IP:
 888         /* mark as an io operation because it could cause an interrupt */
 889         if (dc->tb->cflags & CF_USE_ICOUNT) {
 890             gen_io_start();
 891         }
 892         gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]);
 893         tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
 894         if (dc->tb->cflags & CF_USE_ICOUNT) {
 895             gen_io_end();
 896         }
 897         dc->is_jmp = DISAS_UPDATE;
 898         break;
 899     case CSR_ICC:
 900         /* TODO */
 901         break;
 902     case CSR_DCC:
 903         /* TODO */
 904         break;
 905     case CSR_EBA:
 906         tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]);
 907         break;
 908     case CSR_DEBA:
 909         tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]);
 910         break;
 911     case CSR_JTX:
 912         gen_helper_wcsr_jtx(cpu_env, cpu_R[dc->r1]);
 913         break;
 914     case CSR_JRX:
 915         gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
 916         break;
 917     case CSR_DC:
 918         gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]);
 919         break;
 920     case CSR_BP0:
 921     case CSR_BP1:
 922     case CSR_BP2:
 923     case CSR_BP3:
 924         no = dc->csr - CSR_BP0;
 925         if (dc->num_breakpoints <= no) {
 926             qemu_log_mask(LOG_GUEST_ERROR,
 927                           "breakpoint #%i is not available\n", no);
 928             t_gen_illegal_insn(dc);
 929             break;
 930         }
 931         gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
 932         break;
 933     case CSR_WP0:
 934     case CSR_WP1:
 935     case CSR_WP2:
 936     case CSR_WP3:
 937         no = dc->csr - CSR_WP0;
 938         if (dc->num_watchpoints <= no) {
 939             qemu_log_mask(LOG_GUEST_ERROR,
 940                           "watchpoint #%i is not available\n", no);
 941             t_gen_illegal_insn(dc);
 942             break;
 943         }
 944         gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
 945         break;
 946     case CSR_CC:
 947     case CSR_CFG:
 948         qemu_log_mask(LOG_GUEST_ERROR, "invalid write access csr=%x\n",
 949                       dc->csr);
 950         break;
 951     default:
 952         qemu_log_mask(LOG_GUEST_ERROR, "write_csr: unknown csr=%x\n",
 953                       dc->csr);
 954         break;
 955     }
 956 }
 957
 958 static void dec_xnor(DisasContext *dc)
 959 {
 960     if (dc->format == OP_FMT_RI) {
 961         LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
 962                 zero_extend(dc->imm16, 16));
 963     } else {
 964         if (dc->r1 == R_R0) {
 965             LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
 966         } else {
 967             LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 968         }
 969     }
 970
 971     if (dc->format == OP_FMT_RI) {
 972         tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 973                 zero_extend(dc->imm16, 16));
 974         tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]);
 975     } else {
 976         tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 977     }
 978 }
 979
 980 static void dec_xor(DisasContext *dc)
 981 {
 982     if (dc->format == OP_FMT_RI) {
 983         LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
 984                 zero_extend(dc->imm16, 16));
 985     } else {
 986         LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
 987     }
 988
 989     if (dc->format == OP_FMT_RI) {
 990         tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0],
 991                 zero_extend(dc->imm16, 16));
 992     } else {
 993         tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]);
 994     }
 995 }
 996
 997 static void dec_ill(DisasContext *dc)
 998 {
 999     qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode 0x%02x\n", dc->opcode);
1000     t_gen_illegal_insn(dc);
1001 }
1002
1003 typedef void (*DecoderInfo)(DisasContext *dc);
1004 static const DecoderInfo decinfo[] = {
1005     dec_sru, dec_nor, dec_mul, dec_sh, dec_lb, dec_sr, dec_xor, dec_lh,
1006     dec_and, dec_xnor, dec_lw, dec_lhu, dec_sb, dec_add, dec_or, dec_sl,
1007     dec_lbu, dec_be, dec_bg, dec_bge, dec_bgeu, dec_bgu, dec_sw, dec_bne,
1008     dec_andhi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_orhi,
1009     dec_cmpne,
1010     dec_sru, dec_nor, dec_mul, dec_divu, dec_rcsr, dec_sr, dec_xor, dec_ill,
1011     dec_and, dec_xnor, dec_ill, dec_scall, dec_sextb, dec_add, dec_or, dec_sl,
1012     dec_b, dec_modu, dec_sub, dec_user, dec_wcsr, dec_ill, dec_call, dec_sexth,
1013     dec_bi, dec_cmpe, dec_cmpg, dec_cmpge, dec_cmpgeu, dec_cmpgu, dec_calli,
1014     dec_cmpne
1015 };
1016
1017 static inline void decode(DisasContext *dc, uint32_t ir)
1018 {
1019     dc->ir = ir;
1020     LOG_DIS("%8.8x\t", dc->ir);
1021
1022     dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1023
1024     dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
1025     dc->imm16 = EXTRACT_FIELD(ir, 0, 15);
1026     dc->imm26 = EXTRACT_FIELD(ir, 0, 25);
1027
1028     dc->csr = EXTRACT_FIELD(ir, 21, 25);
1029     dc->r0 = EXTRACT_FIELD(ir, 21, 25);
1030     dc->r1 = EXTRACT_FIELD(ir, 16, 20);
1031     dc->r2 = EXTRACT_FIELD(ir, 11, 15);
1032
1033     /* bit 31 seems to indicate insn type.  */
1034     if (ir & (1 << 31)) {
1035         dc->format = OP_FMT_RR;
1036     } else {
1037         dc->format = OP_FMT_RI;
1038     }
1039
1040     assert(ARRAY_SIZE(decinfo) == 64);
1041     assert(dc->opcode < 64);
1042
1043     decinfo[dc->opcode](dc);
1044 }
1045
1046 /* generate intermediate code for basic block 'tb'.  */
1047 void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
1048 {
1049     LM32CPU *cpu = lm32_env_get_cpu(env);
1050     CPUState *cs = CPU(cpu);
1051     struct DisasContext ctx, *dc = &ctx;
1052     uint32_t pc_start;
1053     uint32_t next_page_start;
1054     int num_insns;
1055     int max_insns;
1056
1057     pc_start = tb->pc;
1058     dc->features = cpu->features;
1059     dc->num_breakpoints = cpu->num_breakpoints;
1060     dc->num_watchpoints = cpu->num_watchpoints;
1061     dc->tb = tb;
1062
1063     dc->is_jmp = DISAS_NEXT;
1064     dc->pc = pc_start;
1065     dc->singlestep_enabled = cs->singlestep_enabled;
1066
1067     if (pc_start & 3) {
1068         qemu_log_mask(LOG_GUEST_ERROR,
1069                       "unaligned PC=%x. Ignoring lowest bits.\n", pc_start);
1070         pc_start &= ~3;
1071     }
1072
1073     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1074     num_insns = 0;
1075     max_insns = tb->cflags & CF_COUNT_MASK;
1076     if (max_insns == 0) {
1077         max_insns = CF_COUNT_MASK;
1078     }
1079     if (max_insns > TCG_MAX_INSNS) {
1080         max_insns = TCG_MAX_INSNS;
1081     }
1082
1083     gen_tb_start(tb);
1084     do {
1085         tcg_gen_insn_start(dc->pc);
1086         num_insns++;
1087
1088         if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
1089             tcg_gen_movi_tl(cpu_pc, dc->pc);
1090             t_gen_raise_exception(dc, EXCP_DEBUG);
1091             dc->is_jmp = DISAS_UPDATE;
1092             /* The address covered by the breakpoint must be included in
1093                [tb->pc, tb->pc + tb->size) in order to for it to be
1094                properly cleared -- thus we increment the PC here so that
1095                the logic setting tb->size below does the right thing.  */
1096             dc->pc += 4;
1097             break;
1098         }
1099
1100         /* Pretty disas.  */
1101         LOG_DIS("%8.8x:\t", dc->pc);
1102
1103         if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
1104             gen_io_start();
1105         }
1106
1107         decode(dc, cpu_ldl_code(env, dc->pc));
1108         dc->pc += 4;
1109     } while (!dc->is_jmp
1110          && !tcg_op_buf_full()
1111          && !cs->singlestep_enabled
1112          && !singlestep
1113          && (dc->pc < next_page_start)
1114          && num_insns < max_insns);
1115
1116     if (tb->cflags & CF_LAST_IO) {
1117         gen_io_end();
1118     }
1119
1120     if (unlikely(cs->singlestep_enabled)) {
1121         if (dc->is_jmp == DISAS_NEXT) {
1122             tcg_gen_movi_tl(cpu_pc, dc->pc);
1123         }
1124         t_gen_raise_exception(dc, EXCP_DEBUG);
1125     } else {
1126         switch (dc->is_jmp) {
1127         case DISAS_NEXT:
1128             gen_goto_tb(dc, 1, dc->pc);
1129             break;
1130         default:
1131         case DISAS_JUMP:
1132         case DISAS_UPDATE:
1133             /* indicate that the hash table must be used
1134                to find the next TB */
1135             tcg_gen_exit_tb(0);
1136             break;
1137         case DISAS_TB_JUMP:
1138             /* nothing more to generate */
1139             break;
1140         }
1141     }
1142
1143     gen_tb_end(tb, num_insns);
1144
1145     tb->size = dc->pc - pc_start;
1146     tb->icount = num_insns;
1147
1148 #ifdef DEBUG_DISAS
1149     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1150         qemu_log("\n");
1151         log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
1152         qemu_log("\nisize=%d osize=%d\n",
1153                  dc->pc - pc_start, tcg_op_buf_count());
1154     }
1155 #endif
1156 }
1157
1158 void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1159                          int flags)
1160 {
1161     LM32CPU *cpu = LM32_CPU(cs);
1162     CPULM32State *env = &cpu->env;
1163     int i;
1164
1165     if (!env || !f) {
1166         return;
1167     }
1168
1169     cpu_fprintf(f, "IN: PC=%x %s\n",
1170                 env->pc, lookup_symbol(env->pc));
1171
1172     cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1173              env->ie,
1174              (env->ie & IE_IE) ? 1 : 0,
1175              (env->ie & IE_EIE) ? 1 : 0,
1176              (env->ie & IE_BIE) ? 1 : 0,
1177              lm32_pic_get_im(env->pic_state),
1178              lm32_pic_get_ip(env->pic_state));
1179     cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
1180              env->eba,
1181              env->deba);
1182
1183     for (i = 0; i < 32; i++) {
1184         cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1185         if ((i + 1) % 4 == 0) {
1186             cpu_fprintf(f, "\n");
1187         }
1188     }
1189     cpu_fprintf(f, "\n\n");
1190 }
1191
1192 void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb,
1193                           target_ulong *data)
1194 {
1195     env->pc = data[0];
1196 }
1197
1198 void lm32_translate_init(void)
1199 {
1200     int i;
1201
1202     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1203
1204     for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1205         cpu_R[i] = tcg_global_mem_new(cpu_env,
1206                           offsetof(CPULM32State, regs[i]),
1207                           regnames[i]);
1208     }
1209
1210     for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) {
1211         cpu_bp[i] = tcg_global_mem_new(cpu_env,
1212                           offsetof(CPULM32State, bp[i]),
1213                           regnames[32+i]);
1214     }
1215
1216     for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) {
1217         cpu_wp[i] = tcg_global_mem_new(cpu_env,
1218                           offsetof(CPULM32State, wp[i]),
1219                           regnames[36+i]);
1220     }
1221
1222     cpu_pc = tcg_global_mem_new(cpu_env,
1223                     offsetof(CPULM32State, pc),
1224                     "pc");
1225     cpu_ie = tcg_global_mem_new(cpu_env,
1226                     offsetof(CPULM32State, ie),
1227                     "ie");
1228     cpu_icc = tcg_global_mem_new(cpu_env,
1229                     offsetof(CPULM32State, icc),
1230                     "icc");
1231     cpu_dcc = tcg_global_mem_new(cpu_env,
1232                     offsetof(CPULM32State, dcc),
1233                     "dcc");
1234     cpu_cc = tcg_global_mem_new(cpu_env,
1235                     offsetof(CPULM32State, cc),
1236                     "cc");
1237     cpu_cfg = tcg_global_mem_new(cpu_env,
1238                     offsetof(CPULM32State, cfg),
1239                     "cfg");
1240     cpu_eba = tcg_global_mem_new(cpu_env,
1241                     offsetof(CPULM32State, eba),
1242                     "eba");
1243     cpu_dc = tcg_global_mem_new(cpu_env,
1244                     offsetof(CPULM32State, dc),
1245                     "dc");
1246     cpu_deba = tcg_global_mem_new(cpu_env,
1247                     offsetof(CPULM32State, deba),
1248                     "deba");
1249 }
1250