softmmu_template.h

   1 /*
   2  *  Software MMU support
   3  *
   4  * Generate helpers used by TCG for qemu_ld/st ops and code load
   5  * functions.
   6  *
   7  * Included from target op helpers and exec.c.
   8  *
   9  *  Copyright (c) 2003 Fabrice Bellard
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License as published by the Free Software Foundation; either
  14  * version 2 of the License, or (at your option) any later version.
  15  *
  16  * This library is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * Lesser General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU Lesser General Public
  22  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24 #include "qemu/timer.h"
  25 #include "exec/address-spaces.h"
  26 #include "exec/memory.h"
  27
  28 #define DATA_SIZE (1 << SHIFT)
  29
  30 #if DATA_SIZE == 8
  31 #define SUFFIX q
  32 #define LSUFFIX q
  33 #define SDATA_TYPE  int64_t
  34 #define DATA_TYPE  uint64_t
  35 #elif DATA_SIZE == 4
  36 #define SUFFIX l
  37 #define LSUFFIX l
  38 #define SDATA_TYPE  int32_t
  39 #define DATA_TYPE  uint32_t
  40 #elif DATA_SIZE == 2
  41 #define SUFFIX w
  42 #define LSUFFIX uw
  43 #define SDATA_TYPE  int16_t
  44 #define DATA_TYPE  uint16_t
  45 #elif DATA_SIZE == 1
  46 #define SUFFIX b
  47 #define LSUFFIX ub
  48 #define SDATA_TYPE  int8_t
  49 #define DATA_TYPE  uint8_t
  50 #else
  51 #error unsupported data size
  52 #endif
  53
  54
  55 /* For the benefit of TCG generated code, we want to avoid the complication
  56    of ABI-specific return type promotion and always return a value extended
  57    to the register size of the host.  This is tcg_target_long, except in the
  58    case of a 32-bit host and 64-bit data, and for that we always have
  59    uint64_t.  Don't bother with this widened value for SOFTMMU_CODE_ACCESS.  */
  60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
  61 # define WORD_TYPE  DATA_TYPE
  62 # define USUFFIX    SUFFIX
  63 #else
  64 # define WORD_TYPE  tcg_target_ulong
  65 # define USUFFIX    glue(u, SUFFIX)
  66 # define SSUFFIX    glue(s, SUFFIX)
  67 #endif
  68
  69 #ifdef SOFTMMU_CODE_ACCESS
  70 #define READ_ACCESS_TYPE 2
  71 #define ADDR_READ addr_code
  72 #else
  73 #define READ_ACCESS_TYPE 0
  74 #define ADDR_READ addr_read
  75 #endif
  76
  77 #if DATA_SIZE == 8
  78 # define BSWAP(X)  bswap64(X)
  79 #elif DATA_SIZE == 4
  80 # define BSWAP(X)  bswap32(X)
  81 #elif DATA_SIZE == 2
  82 # define BSWAP(X)  bswap16(X)
  83 #else
  84 # define BSWAP(X)  (X)
  85 #endif
  86
  87 #ifdef TARGET_WORDS_BIGENDIAN
  88 # define TGT_BE(X)  (X)
  89 # define TGT_LE(X)  BSWAP(X)
  90 #else
  91 # define TGT_BE(X)  BSWAP(X)
  92 # define TGT_LE(X)  (X)
  93 #endif
  94
  95 #if DATA_SIZE == 1
  96 # define helper_le_ld_name  glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
  97 # define helper_be_ld_name  helper_le_ld_name
  98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
  99 # define helper_be_lds_name helper_le_lds_name
 100 # define helper_le_st_name  glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
 101 # define helper_be_st_name  helper_le_st_name
 102 #else
 103 # define helper_le_ld_name  glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
 104 # define helper_be_ld_name  glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
 105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
 106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
 107 # define helper_le_st_name  glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
 108 # define helper_be_st_name  glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
 109 #endif
 110
 111 #ifdef TARGET_WORDS_BIGENDIAN
 112 # define helper_te_ld_name  helper_be_ld_name
 113 # define helper_te_st_name  helper_be_st_name
 114 #else
 115 # define helper_te_ld_name  helper_le_ld_name
 116 # define helper_te_st_name  helper_le_st_name
 117 #endif
 118
 119 #ifndef SOFTMMU_CODE_ACCESS
 120 static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
 121                                               hwaddr physaddr,
 122                                               target_ulong addr,
 123                                               uintptr_t retaddr)
 124 {
 125     uint64_t val;
 126     CPUState *cpu = ENV_GET_CPU(env);
 127     MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
 128
 129     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 130     cpu->mem_io_pc = retaddr;
 131     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
 132         cpu_io_recompile(cpu, retaddr);
 133     }
 134
 135     cpu->mem_io_vaddr = addr;
 136     io_mem_read(mr, physaddr, &val, 1 << SHIFT);
 137     return val;
 138 }
 139 #endif
 140
 141 #ifdef SOFTMMU_CODE_ACCESS
 142 static __attribute__((unused))
 143 #endif
 144 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
 145                             uintptr_t retaddr)
 146 {
 147     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 148     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 149     uintptr_t haddr;
 150     DATA_TYPE res;
 151
 152     /* Adjust the given return address.  */
 153     retaddr -= GETPC_ADJ;
 154
 155     /* If the TLB entry is for a different page, reload and try again.  */
 156     if ((addr & TARGET_PAGE_MASK)
 157          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 158 #ifdef ALIGNED_ONLY
 159         if ((addr & (DATA_SIZE - 1)) != 0) {
 160             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 161                                  mmu_idx, retaddr);
 162         }
 163 #endif
 164         tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 165         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 166     }
 167
 168     /* Handle an IO access.  */
 169     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 170         hwaddr ioaddr;
 171         if ((addr & (DATA_SIZE - 1)) != 0) {
 172             goto do_unaligned_access;
 173         }
 174         ioaddr = env->iotlb[mmu_idx][index];
 175
 176         /* ??? Note that the io helpers always read data in the target
 177            byte ordering.  We should push the LE/BE request down into io.  */
 178         res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
 179         res = TGT_LE(res);
 180         return res;
 181     }
 182
 183     /* Handle slow unaligned access (it spans two pages or IO).  */
 184     if (DATA_SIZE > 1
 185         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 186                     >= TARGET_PAGE_SIZE)) {
 187         target_ulong addr1, addr2;
 188         DATA_TYPE res1, res2;
 189         unsigned shift;
 190     do_unaligned_access:
 191 #ifdef ALIGNED_ONLY
 192         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 193                              mmu_idx, retaddr);
 194 #endif
 195         addr1 = addr & ~(DATA_SIZE - 1);
 196         addr2 = addr1 + DATA_SIZE;
 197         /* Note the adjustment at the beginning of the function.
 198            Undo that for the recursion.  */
 199         res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
 200         res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
 201         shift = (addr & (DATA_SIZE - 1)) * 8;
 202
 203         /* Little-endian combine.  */
 204         res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
 205         return res;
 206     }
 207
 208     /* Handle aligned access or unaligned access in the same page.  */
 209 #ifdef ALIGNED_ONLY
 210     if ((addr & (DATA_SIZE - 1)) != 0) {
 211         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 212                              mmu_idx, retaddr);
 213     }
 214 #endif
 215
 216     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 217 #if DATA_SIZE == 1
 218     res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
 219 #else
 220     res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
 221 #endif
 222     return res;
 223 }
 224
 225 #if DATA_SIZE > 1
 226 #ifdef SOFTMMU_CODE_ACCESS
 227 static __attribute__((unused))
 228 #endif
 229 WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
 230                             uintptr_t retaddr)
 231 {
 232     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 233     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 234     uintptr_t haddr;
 235     DATA_TYPE res;
 236
 237     /* Adjust the given return address.  */
 238     retaddr -= GETPC_ADJ;
 239
 240     /* If the TLB entry is for a different page, reload and try again.  */
 241     if ((addr & TARGET_PAGE_MASK)
 242          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 243 #ifdef ALIGNED_ONLY
 244         if ((addr & (DATA_SIZE - 1)) != 0) {
 245             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 246                                  mmu_idx, retaddr);
 247         }
 248 #endif
 249         tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 250         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 251     }
 252
 253     /* Handle an IO access.  */
 254     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 255         hwaddr ioaddr;
 256         if ((addr & (DATA_SIZE - 1)) != 0) {
 257             goto do_unaligned_access;
 258         }
 259         ioaddr = env->iotlb[mmu_idx][index];
 260
 261         /* ??? Note that the io helpers always read data in the target
 262            byte ordering.  We should push the LE/BE request down into io.  */
 263         res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
 264         res = TGT_BE(res);
 265         return res;
 266     }
 267
 268     /* Handle slow unaligned access (it spans two pages or IO).  */
 269     if (DATA_SIZE > 1
 270         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 271                     >= TARGET_PAGE_SIZE)) {
 272         target_ulong addr1, addr2;
 273         DATA_TYPE res1, res2;
 274         unsigned shift;
 275     do_unaligned_access:
 276 #ifdef ALIGNED_ONLY
 277         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 278                              mmu_idx, retaddr);
 279 #endif
 280         addr1 = addr & ~(DATA_SIZE - 1);
 281         addr2 = addr1 + DATA_SIZE;
 282         /* Note the adjustment at the beginning of the function.
 283            Undo that for the recursion.  */
 284         res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
 285         res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
 286         shift = (addr & (DATA_SIZE - 1)) * 8;
 287
 288         /* Big-endian combine.  */
 289         res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
 290         return res;
 291     }
 292
 293     /* Handle aligned access or unaligned access in the same page.  */
 294 #ifdef ALIGNED_ONLY
 295     if ((addr & (DATA_SIZE - 1)) != 0) {
 296         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 297                              mmu_idx, retaddr);
 298     }
 299 #endif
 300
 301     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 302     res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
 303     return res;
 304 }
 305 #endif /* DATA_SIZE > 1 */
 306
 307 DATA_TYPE
 308 glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
 309                                          int mmu_idx)
 310 {
 311     return helper_te_ld_name (env, addr, mmu_idx, GETRA());
 312 }
 313
 314 #ifndef SOFTMMU_CODE_ACCESS
 315
 316 /* Provide signed versions of the load routines as well.  We can of course
 317    avoid this for 64-bit data, or for 32-bit data on 32-bit host.  */
 318 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
 319 WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
 320                              int mmu_idx, uintptr_t retaddr)
 321 {
 322     return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
 323 }
 324
 325 # if DATA_SIZE > 1
 326 WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
 327                              int mmu_idx, uintptr_t retaddr)
 328 {
 329     return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
 330 }
 331 # endif
 332 #endif
 333
 334 static inline void glue(io_write, SUFFIX)(CPUArchState *env,
 335                                           hwaddr physaddr,
 336                                           DATA_TYPE val,
 337                                           target_ulong addr,
 338                                           uintptr_t retaddr)
 339 {
 340     CPUState *cpu = ENV_GET_CPU(env);
 341     MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
 342
 343     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 344     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
 345         cpu_io_recompile(cpu, retaddr);
 346     }
 347
 348     cpu->mem_io_vaddr = addr;
 349     cpu->mem_io_pc = retaddr;
 350     io_mem_write(mr, physaddr, val, 1 << SHIFT);
 351 }
 352
 353 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 354                        int mmu_idx, uintptr_t retaddr)
 355 {
 356     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 357     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 358     uintptr_t haddr;
 359
 360     /* Adjust the given return address.  */
 361     retaddr -= GETPC_ADJ;
 362
 363     /* If the TLB entry is for a different page, reload and try again.  */
 364     if ((addr & TARGET_PAGE_MASK)
 365         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 366 #ifdef ALIGNED_ONLY
 367         if ((addr & (DATA_SIZE - 1)) != 0) {
 368             cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 369         }
 370 #endif
 371         tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 372         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 373     }
 374
 375     /* Handle an IO access.  */
 376     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 377         hwaddr ioaddr;
 378         if ((addr & (DATA_SIZE - 1)) != 0) {
 379             goto do_unaligned_access;
 380         }
 381         ioaddr = env->iotlb[mmu_idx][index];
 382
 383         /* ??? Note that the io helpers always read data in the target
 384            byte ordering.  We should push the LE/BE request down into io.  */
 385         val = TGT_LE(val);
 386         glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
 387         return;
 388     }
 389
 390     /* Handle slow unaligned access (it spans two pages or IO).  */
 391     if (DATA_SIZE > 1
 392         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 393                      >= TARGET_PAGE_SIZE)) {
 394         int i;
 395     do_unaligned_access:
 396 #ifdef ALIGNED_ONLY
 397         cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 398 #endif
 399         /* XXX: not efficient, but simple */
 400         /* Note: relies on the fact that tlb_fill() does not remove the
 401          * previous page from the TLB cache.  */
 402         for (i = DATA_SIZE - 1; i >= 0; i--) {
 403             /* Little-endian extract.  */
 404             uint8_t val8 = val >> (i * 8);
 405             /* Note the adjustment at the beginning of the function.
 406                Undo that for the recursion.  */
 407             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 408                                             mmu_idx, retaddr + GETPC_ADJ);
 409         }
 410         return;
 411     }
 412
 413     /* Handle aligned access or unaligned access in the same page.  */
 414 #ifdef ALIGNED_ONLY
 415     if ((addr & (DATA_SIZE - 1)) != 0) {
 416         cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 417     }
 418 #endif
 419
 420     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 421 #if DATA_SIZE == 1
 422     glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
 423 #else
 424     glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
 425 #endif
 426 }
 427
 428 #if DATA_SIZE > 1
 429 void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 430                        int mmu_idx, uintptr_t retaddr)
 431 {
 432     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 433     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 434     uintptr_t haddr;
 435
 436     /* Adjust the given return address.  */
 437     retaddr -= GETPC_ADJ;
 438
 439     /* If the TLB entry is for a different page, reload and try again.  */
 440     if ((addr & TARGET_PAGE_MASK)
 441         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 442 #ifdef ALIGNED_ONLY
 443         if ((addr & (DATA_SIZE - 1)) != 0) {
 444             cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 445         }
 446 #endif
 447         tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 448         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 449     }
 450
 451     /* Handle an IO access.  */
 452     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 453         hwaddr ioaddr;
 454         if ((addr & (DATA_SIZE - 1)) != 0) {
 455             goto do_unaligned_access;
 456         }
 457         ioaddr = env->iotlb[mmu_idx][index];
 458
 459         /* ??? Note that the io helpers always read data in the target
 460            byte ordering.  We should push the LE/BE request down into io.  */
 461         val = TGT_BE(val);
 462         glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
 463         return;
 464     }
 465
 466     /* Handle slow unaligned access (it spans two pages or IO).  */
 467     if (DATA_SIZE > 1
 468         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 469                      >= TARGET_PAGE_SIZE)) {
 470         int i;
 471     do_unaligned_access:
 472 #ifdef ALIGNED_ONLY
 473         cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 474 #endif
 475         /* XXX: not efficient, but simple */
 476         /* Note: relies on the fact that tlb_fill() does not remove the
 477          * previous page from the TLB cache.  */
 478         for (i = DATA_SIZE - 1; i >= 0; i--) {
 479             /* Big-endian extract.  */
 480             uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
 481             /* Note the adjustment at the beginning of the function.
 482                Undo that for the recursion.  */
 483             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 484                                             mmu_idx, retaddr + GETPC_ADJ);
 485         }
 486         return;
 487     }
 488
 489     /* Handle aligned access or unaligned access in the same page.  */
 490 #ifdef ALIGNED_ONLY
 491     if ((addr & (DATA_SIZE - 1)) != 0) {
 492         cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
 493     }
 494 #endif
 495
 496     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 497     glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
 498 }
 499 #endif /* DATA_SIZE > 1 */
 500
 501 void
 502 glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
 503                                          DATA_TYPE val, int mmu_idx)
 504 {
 505     helper_te_st_name(env, addr, val, mmu_idx, GETRA());
 506 }
 507
 508 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
 509
 510 #undef READ_ACCESS_TYPE
 511 #undef SHIFT
 512 #undef DATA_TYPE
 513 #undef SUFFIX
 514 #undef LSUFFIX
 515 #undef DATA_SIZE
 516 #undef ADDR_READ
 517 #undef WORD_TYPE
 518 #undef SDATA_TYPE
 519 #undef USUFFIX
 520 #undef SSUFFIX
 521 #undef BSWAP
 522 #undef TGT_BE
 523 #undef TGT_LE
 524 #undef CPU_BE
 525 #undef CPU_LE
 526 #undef helper_le_ld_name
 527 #undef helper_be_ld_name
 528 #undef helper_le_lds_name
 529 #undef helper_be_lds_name
 530 #undef helper_le_st_name
 531 #undef helper_be_st_name
 532 #undef helper_te_ld_name
 533 #undef helper_te_st_name