include/hw/ppc/xics.h

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27 #if !defined(__XICS_H__)
  28 #define __XICS_H__
  29
  30 #include "hw/sysbus.h"
  31
  32 #define TYPE_XICS_COMMON "xics-common"
  33 #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
  34
  35 /*
  36  * Retain xics as the type name to be compatible for migration. Rest all the
  37  * functions, class and variables are renamed as xics_spapr.
  38  */
  39 #define TYPE_XICS_SPAPR "xics"
  40 #define XICS_SPAPR(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR)
  41
  42 #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
  43 #define XICS_SPAPR_KVM(obj) \
  44      OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
  45
  46 #define XICS_COMMON_CLASS(klass) \
  47      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
  48 #define XICS_SPAPR_CLASS(klass) \
  49      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_SPAPR)
  50 #define XICS_COMMON_GET_CLASS(obj) \
  51      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
  52 #define XICS_SPAPR_GET_CLASS(obj) \
  53      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
  54
  55 #define XICS_IPI        0x2
  56 #define XICS_BUID       0x1
  57 #define XICS_IRQ_BASE   (XICS_BUID << 12)
  58
  59 /*
  60  * We currently only support one BUID which is our interrupt base
  61  * (the kernel implementation supports more but we don't exploit
  62  *  that yet)
  63  */
  64 typedef struct XICSStateClass XICSStateClass;
  65 typedef struct XICSState XICSState;
  66 typedef struct ICPStateClass ICPStateClass;
  67 typedef struct ICPState ICPState;
  68 typedef struct ICSStateClass ICSStateClass;
  69 typedef struct ICSState ICSState;
  70 typedef struct ICSIRQState ICSIRQState;
  71
  72 struct XICSStateClass {
  73     DeviceClass parent_class;
  74
  75     void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu);
  76     void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp);
  77     void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **errp);
  78 };
  79
  80 struct XICSState {
  81     /*< private >*/
  82     SysBusDevice parent_obj;
  83     /*< public >*/
  84     uint32_t nr_servers;
  85     uint32_t nr_irqs;
  86     ICPState *ss;
  87     ICSState *ics;
  88 };
  89
  90 #define TYPE_ICP "icp"
  91 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
  92
  93 #define TYPE_KVM_ICP "icp-kvm"
  94 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
  95
  96 #define ICP_CLASS(klass) \
  97      OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
  98 #define ICP_GET_CLASS(obj) \
  99      OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
 100
 101 struct ICPStateClass {
 102     DeviceClass parent_class;
 103
 104     void (*pre_save)(ICPState *s);
 105     int (*post_load)(ICPState *s, int version_id);
 106 };
 107
 108 struct ICPState {
 109     /*< private >*/
 110     DeviceState parent_obj;
 111     /*< public >*/
 112     CPUState *cs;
 113     uint32_t xirr;
 114     uint8_t pending_priority;
 115     uint8_t mfrr;
 116     qemu_irq output;
 117     bool cap_irq_xics_enabled;
 118 };
 119
 120 #define TYPE_ICS "ics"
 121 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
 122
 123 #define TYPE_KVM_ICS "icskvm"
 124 #define KVM_ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_KVM_ICS)
 125
 126 #define ICS_CLASS(klass) \
 127      OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
 128 #define ICS_GET_CLASS(obj) \
 129      OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
 130
 131 struct ICSStateClass {
 132     DeviceClass parent_class;
 133
 134     void (*pre_save)(ICSState *s);
 135     int (*post_load)(ICSState *s, int version_id);
 136 };
 137
 138 struct ICSState {
 139     /*< private >*/
 140     DeviceState parent_obj;
 141     /*< public >*/
 142     uint32_t nr_irqs;
 143     uint32_t offset;
 144     qemu_irq *qirqs;
 145     ICSIRQState *irqs;
 146     XICSState *xics;
 147 };
 148
 149 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
 150 {
 151     return (nr >= ics->offset)
 152         && (nr < (ics->offset + ics->nr_irqs));
 153 }
 154
 155 struct ICSIRQState {
 156     uint32_t server;
 157     uint8_t priority;
 158     uint8_t saved_priority;
 159 #define XICS_STATUS_ASSERTED           0x1
 160 #define XICS_STATUS_SENT               0x2
 161 #define XICS_STATUS_REJECTED           0x4
 162 #define XICS_STATUS_MASKED_PENDING     0x8
 163     uint8_t status;
 164 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
 165 #define XICS_FLAGS_IRQ_LSI             0x1
 166 #define XICS_FLAGS_IRQ_MSI             0x2
 167 #define XICS_FLAGS_IRQ_MASK            0x3
 168     uint8_t flags;
 169 };
 170
 171 #define XICS_IRQS_SPAPR               1024
 172
 173 qemu_irq xics_get_qirq(XICSState *icp, int irq);
 174 int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
 175                      Error **errp);
 176 int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
 177                            bool align, Error **errp);
 178 void xics_spapr_free(XICSState *icp, int irq, int num);
 179
 180 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
 181 void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
 182
 183 /* Internal XICS interfaces */
 184 int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
 185
 186 void icp_set_cppr(XICSState *icp, int server, uint8_t cppr);
 187 void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr);
 188 uint32_t icp_accept(ICPState *ss);
 189 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
 190 void icp_eoi(XICSState *icp, int server, uint32_t xirr);
 191
 192 void ics_write_xive(ICSState *ics, int nr, int server,
 193                     uint8_t priority, uint8_t saved_priority);
 194
 195 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 196
 197 int xics_find_source(XICSState *icp, int irq);
 198
 199 #endif /* __XICS_H__ */