include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 /* Maximum size a TCG op can expand to.  This is complicated because a
  66    single op may require several host instructions and register reloads.
  67    For now take a wild guess at 192 bytes, which should allow at least
  68    a couple of fixup instructions per argument.  */
  69 #define TCG_MAX_OP_SIZE 192
  70
  71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  72
  73 #include "qemu/log.h"
  74
  75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
  77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  78                           int pc_pos);
  79
  80 void cpu_gen_init(void);
  81 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
  82                  int *gen_code_size_ptr);
  83 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  84 void page_size_init(void);
  85
  86 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  87 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  88 TranslationBlock *tb_gen_code(CPUState *cpu,
  89                               target_ulong pc, target_ulong cs_base, int flags,
  90                               int cflags);
  91 void cpu_exec_init(CPUArchState *env);
  92 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  93 int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
  94 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
  95                                    int is_cpu_write_access);
  96 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
  97                               int is_cpu_write_access);
  98 #if !defined(CONFIG_USER_ONLY)
  99 bool qemu_in_vcpu_thread(void);
 100 void cpu_reload_memory_map(CPUState *cpu);
 101 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
 102 /* cputlb.c */
 103 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 104 void tlb_flush(CPUState *cpu, int flush_global);
 105 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 106                   hwaddr paddr, int prot,
 107                   int mmu_idx, target_ulong size);
 108 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 109                              hwaddr paddr, MemTxAttrs attrs,
 110                              int prot, int mmu_idx, target_ulong size);
 111 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 112 #else
 113 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 114 {
 115 }
 116
 117 static inline void tlb_flush(CPUState *cpu, int flush_global)
 118 {
 119 }
 120 #endif
 121
 122 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 123
 124 #define CODE_GEN_PHYS_HASH_BITS     15
 125 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 126
 127 /* estimated block size for TB allocation */
 128 /* XXX: use a per code average code fragment size and modulate it
 129    according to the host CPU */
 130 #if defined(CONFIG_SOFTMMU)
 131 #define CODE_GEN_AVG_BLOCK_SIZE 128
 132 #else
 133 #define CODE_GEN_AVG_BLOCK_SIZE 64
 134 #endif
 135
 136 #if defined(__arm__) || defined(_ARCH_PPC) \
 137     || defined(__x86_64__) || defined(__i386__) \
 138     || defined(__sparc__) || defined(__aarch64__) \
 139     || defined(__s390x__) || defined(__mips__) \
 140     || defined(CONFIG_TCG_INTERPRETER)
 141 #define USE_DIRECT_JUMP
 142 #endif
 143
 144 struct TranslationBlock {
 145     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 146     target_ulong cs_base; /* CS base for this block */
 147     uint64_t flags; /* flags defining in which context the code was generated */
 148     uint16_t size;      /* size of target code for this block (1 <=
 149                            size <= TARGET_PAGE_SIZE) */
 150     uint16_t icount;
 151     uint32_t cflags;    /* compile flags */
 152 #define CF_COUNT_MASK  0x7fff
 153 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 154 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 155 #define CF_USE_ICOUNT  0x20000
 156
 157     void *tc_ptr;    /* pointer to the translated code */
 158     /* next matching tb for physical address. */
 159     struct TranslationBlock *phys_hash_next;
 160     /* first and second physical page containing code. The lower bit
 161        of the pointer tells the index in page_next[] */
 162     struct TranslationBlock *page_next[2];
 163     tb_page_addr_t page_addr[2];
 164
 165     /* the following data are used to directly call another TB from
 166        the code of this one. */
 167     uint16_t tb_next_offset[2]; /* offset of original jump target */
 168 #ifdef USE_DIRECT_JUMP
 169     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 170 #else
 171     uintptr_t tb_next[2]; /* address of jump generated code */
 172 #endif
 173     /* list of TBs jumping to this one. This is a circular list using
 174        the two least significant bits of the pointers to tell what is
 175        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 176        jmp_first */
 177     struct TranslationBlock *jmp_next[2];
 178     struct TranslationBlock *jmp_first;
 179 };
 180
 181 #include "exec/spinlock.h"
 182
 183 typedef struct TBContext TBContext;
 184
 185 struct TBContext {
 186
 187     TranslationBlock *tbs;
 188     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 189     int nb_tbs;
 190     /* any access to the tbs or the page table must use this lock */
 191     spinlock_t tb_lock;
 192
 193     /* statistics */
 194     int tb_flush_count;
 195     int tb_phys_invalidate_count;
 196
 197     int tb_invalidated_flag;
 198 };
 199
 200 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 201 {
 202     target_ulong tmp;
 203     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 204     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 205 }
 206
 207 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 208 {
 209     target_ulong tmp;
 210     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 211     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 212             | (tmp & TB_JMP_ADDR_MASK));
 213 }
 214
 215 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
 216 {
 217     return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
 218 }
 219
 220 void tb_free(TranslationBlock *tb);
 221 void tb_flush(CPUArchState *env);
 222 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 223
 224 #if defined(USE_DIRECT_JUMP)
 225
 226 #if defined(CONFIG_TCG_INTERPRETER)
 227 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 228 {
 229     /* patch the branch destination */
 230     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 231     /* no need to flush icache explicitly */
 232 }
 233 #elif defined(_ARCH_PPC)
 234 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 235 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 236 #elif defined(__i386__) || defined(__x86_64__)
 237 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 238 {
 239     /* patch the branch destination */
 240     stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
 241     /* no need to flush icache explicitly */
 242 }
 243 #elif defined(__s390x__)
 244 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 245 {
 246     /* patch the branch destination */
 247     intptr_t disp = addr - (jmp_addr - 2);
 248     stl_be_p((void*)jmp_addr, disp / 2);
 249     /* no need to flush icache explicitly */
 250 }
 251 #elif defined(__aarch64__)
 252 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 253 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 254 #elif defined(__arm__)
 255 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 256 {
 257 #if !QEMU_GNUC_PREREQ(4, 1)
 258     register unsigned long _beg __asm ("a1");
 259     register unsigned long _end __asm ("a2");
 260     register unsigned long _flg __asm ("a3");
 261 #endif
 262
 263     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 264     *(uint32_t *)jmp_addr =
 265         (*(uint32_t *)jmp_addr & ~0xffffff)
 266         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 267
 268 #if QEMU_GNUC_PREREQ(4, 1)
 269     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 270 #else
 271     /* flush icache */
 272     _beg = jmp_addr;
 273     _end = jmp_addr + 4;
 274     _flg = 0;
 275     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 276 #endif
 277 }
 278 #elif defined(__sparc__) || defined(__mips__)
 279 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 280 #else
 281 #error tb_set_jmp_target1 is missing
 282 #endif
 283
 284 static inline void tb_set_jmp_target(TranslationBlock *tb,
 285                                      int n, uintptr_t addr)
 286 {
 287     uint16_t offset = tb->tb_jmp_offset[n];
 288     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 289 }
 290
 291 #else
 292
 293 /* set the jump target */
 294 static inline void tb_set_jmp_target(TranslationBlock *tb,
 295                                      int n, uintptr_t addr)
 296 {
 297     tb->tb_next[n] = addr;
 298 }
 299
 300 #endif
 301
 302 static inline void tb_add_jump(TranslationBlock *tb, int n,
 303                                TranslationBlock *tb_next)
 304 {
 305     /* NOTE: this test is only needed for thread safety */
 306     if (!tb->jmp_next[n]) {
 307         /* patch the native jump address */
 308         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 309
 310         /* add in TB jmp circular list */
 311         tb->jmp_next[n] = tb_next->jmp_first;
 312         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
 313     }
 314 }
 315
 316 /* GETRA is the true target of the return instruction that we'll execute,
 317    defined here for simplicity of defining the follow-up macros.  */
 318 #if defined(CONFIG_TCG_INTERPRETER)
 319 extern uintptr_t tci_tb_ptr;
 320 # define GETRA() tci_tb_ptr
 321 #else
 322 # define GETRA() \
 323     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 324 #endif
 325
 326 /* The true return address will often point to a host insn that is part of
 327    the next translated guest insn.  Adjust the address backward to point to
 328    the middle of the call insn.  Subtracting one would do the job except for
 329    several compressed mode architectures (arm, mips) which set the low bit
 330    to indicate the compressed mode; subtracting two works around that.  It
 331    is also the case that there are no host isas that contain a call insn
 332    smaller than 4 bytes, so we don't worry about special-casing this.  */
 333 #if defined(CONFIG_TCG_INTERPRETER)
 334 # define GETPC_ADJ   0
 335 #else
 336 # define GETPC_ADJ   2
 337 #endif
 338
 339 #define GETPC()  (GETRA() - GETPC_ADJ)
 340
 341 #if !defined(CONFIG_USER_ONLY)
 342
 343 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
 344
 345 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 346                                      hwaddr index);
 347
 348 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 349               uintptr_t retaddr);
 350
 351 #endif
 352
 353 #if defined(CONFIG_USER_ONLY)
 354 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 355 {
 356     return addr;
 357 }
 358 #else
 359 /* cputlb.c */
 360 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 361 #endif
 362
 363 /* vl.c */
 364 extern int singlestep;
 365
 366 /* cpu-exec.c */
 367 extern volatile sig_atomic_t exit_request;
 368
 369 /**
 370  * cpu_can_do_io:
 371  * @cpu: The CPU for which to check IO.
 372  *
 373  * Deterministic execution requires that IO only be performed on the last
 374  * instruction of a TB so that interrupts take effect immediately.
 375  *
 376  * Returns: %true if memory-mapped IO is safe, %false otherwise.
 377  */
 378 static inline bool cpu_can_do_io(CPUState *cpu)
 379 {
 380     if (!use_icount) {
 381         return true;
 382     }
 383     /* If not executing code then assume we are ok.  */
 384     if (cpu->current_tb == NULL) {
 385         return true;
 386     }
 387     return cpu->can_do_io != 0;
 388 }
 389
 390 #endif