target-ppc/misc_helper.c

   1 /*
   2  * Miscellaneous PowerPC emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "helper.h"
  21
  22 #include "helper_regs.h"
  23
  24 /*****************************************************************************/
  25 /* SPR accesses */
  26 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  27 {
  28     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  29              env->spr[sprn]);
  30 }
  31
  32 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  33 {
  34     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  35              env->spr[sprn]);
  36 }
  37 #if !defined(CONFIG_USER_ONLY)
  38 #if defined(TARGET_PPC64)
  39 void helper_store_asr(CPUPPCState *env, target_ulong val)
  40 {
  41     ppc_store_asr(env, val);
  42 }
  43 #endif
  44
  45 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  46 {
  47     ppc_store_sdr1(env, val);
  48 }
  49
  50 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
  51 {
  52     target_ulong hid0;
  53
  54     hid0 = env->spr[SPR_HID0];
  55     if ((val ^ hid0) & 0x00000008) {
  56         /* Change current endianness */
  57         env->hflags &= ~(1 << MSR_LE);
  58         env->hflags_nmsr &= ~(1 << MSR_LE);
  59         env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
  60         env->hflags |= env->hflags_nmsr;
  61         qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
  62                  val & 0x8 ? 'l' : 'b', env->hflags);
  63     }
  64     env->spr[SPR_HID0] = (uint32_t)val;
  65 }
  66
  67 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
  68 {
  69     if (likely(env->pb[num] != value)) {
  70         env->pb[num] = value;
  71         /* Should be optimized */
  72         tlb_flush(env, 1);
  73     }
  74 }
  75
  76 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
  77 {
  78     store_40x_dbcr0(env, val);
  79 }
  80
  81 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
  82 {
  83     store_40x_sler(env, val);
  84 }
  85 #endif
  86 /*****************************************************************************/
  87 /* PowerPC 601 specific instructions (POWER bridge) */
  88
  89 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
  90 {
  91     switch (arg) {
  92     case 0x0CUL:
  93         /* Instruction cache line size */
  94         return env->icache_line_size;
  95         break;
  96     case 0x0DUL:
  97         /* Data cache line size */
  98         return env->dcache_line_size;
  99         break;
 100     case 0x0EUL:
 101         /* Minimum cache line size */
 102         return (env->icache_line_size < env->dcache_line_size) ?
 103             env->icache_line_size : env->dcache_line_size;
 104         break;
 105     case 0x0FUL:
 106         /* Maximum cache line size */
 107         return (env->icache_line_size > env->dcache_line_size) ?
 108             env->icache_line_size : env->dcache_line_size;
 109         break;
 110     default:
 111         /* Undefined */
 112         return 0;
 113         break;
 114     }
 115 }
 116
 117 /*****************************************************************************/
 118 /* Special registers manipulation */
 119
 120 /* GDBstub can read and write MSR... */
 121 void ppc_store_msr(CPUPPCState *env, target_ulong value)
 122 {
 123     hreg_store_msr(env, value, 0);
 124 }