4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
25 #include "qemu-common.h"
26 #include "hw/qdev-properties.h"
27 #include "migration/vmstate.h"
30 static void mb_cpu_set_pc(CPUState
*cs
, vaddr value
)
32 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
34 cpu
->env
.sregs
[SR_PC
] = value
;
37 static bool mb_cpu_has_work(CPUState
*cs
)
39 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_NMI
);
42 #ifndef CONFIG_USER_ONLY
43 static void microblaze_cpu_set_irq(void *opaque
, int irq
, int level
)
45 MicroBlazeCPU
*cpu
= opaque
;
46 CPUState
*cs
= CPU(cpu
);
47 int type
= irq
? CPU_INTERRUPT_NMI
: CPU_INTERRUPT_HARD
;
50 cpu_interrupt(cs
, type
);
52 cpu_reset_interrupt(cs
, type
);
57 /* CPUClass::reset() */
58 static void mb_cpu_reset(CPUState
*s
)
60 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(s
);
61 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_GET_CLASS(cpu
);
62 CPUMBState
*env
= &cpu
->env
;
66 memset(env
, 0, sizeof(CPUMBState
));
67 env
->res_addr
= RES_ADDR_NONE
;
70 /* Disable stack protector. */
73 env
->pvr
.regs
[0] = PVR0_PVR_FULL_MASK \
74 | PVR0_USE_BARREL_MASK \
76 | PVR0_USE_HW_MUL_MASK \
78 | PVR0_USE_ICACHE_MASK \
79 | PVR0_USE_DCACHE_MASK \
82 env
->pvr
.regs
[2] = PVR2_D_OPB_MASK \
86 | PVR2_USE_MSR_INSTR \
87 | PVR2_USE_PCMP_INSTR \
88 | PVR2_USE_BARREL_MASK \
90 | PVR2_USE_HW_MUL_MASK \
91 | PVR2_USE_MUL64_MASK \
93 | PVR2_USE_FPU2_MASK \
96 env
->pvr
.regs
[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
97 env
->pvr
.regs
[11] = PVR11_USE_MMU
| (16 << 17);
99 #if defined(CONFIG_USER_ONLY)
100 /* start in user mode with interrupts enabled. */
101 env
->sregs
[SR_MSR
] = MSR_EE
| MSR_IE
| MSR_VM
| MSR_UM
;
102 env
->pvr
.regs
[10] = 0x0c000000; /* Spartan 3a dsp. */
104 env
->sregs
[SR_MSR
] = 0;
107 env
->mmu
.c_mmu_tlb_access
= 3;
108 env
->mmu
.c_mmu_zones
= 16;
112 static void mb_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
114 CPUState
*cs
= CPU(dev
);
115 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_GET_CLASS(dev
);
120 mcc
->parent_realize(dev
, errp
);
123 static void mb_cpu_initfn(Object
*obj
)
125 CPUState
*cs
= CPU(obj
);
126 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(obj
);
127 CPUMBState
*env
= &cpu
->env
;
128 static bool tcg_initialized
;
133 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
135 #ifndef CONFIG_USER_ONLY
136 /* Inbound IRQ and FIR lines */
137 qdev_init_gpio_in(DEVICE(cpu
), microblaze_cpu_set_irq
, 2);
140 if (tcg_enabled() && !tcg_initialized
) {
141 tcg_initialized
= true;
146 static const VMStateDescription vmstate_mb_cpu
= {
151 static Property mb_properties
[] = {
152 DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU
, base_vectors
, 0),
153 DEFINE_PROP_END_OF_LIST(),
156 static void mb_cpu_class_init(ObjectClass
*oc
, void *data
)
158 DeviceClass
*dc
= DEVICE_CLASS(oc
);
159 CPUClass
*cc
= CPU_CLASS(oc
);
160 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_CLASS(oc
);
162 mcc
->parent_realize
= dc
->realize
;
163 dc
->realize
= mb_cpu_realizefn
;
165 mcc
->parent_reset
= cc
->reset
;
166 cc
->reset
= mb_cpu_reset
;
168 cc
->has_work
= mb_cpu_has_work
;
169 cc
->do_interrupt
= mb_cpu_do_interrupt
;
170 cc
->dump_state
= mb_cpu_dump_state
;
171 cc
->set_pc
= mb_cpu_set_pc
;
172 cc
->gdb_read_register
= mb_cpu_gdb_read_register
;
173 cc
->gdb_write_register
= mb_cpu_gdb_write_register
;
174 #ifdef CONFIG_USER_ONLY
175 cc
->handle_mmu_fault
= mb_cpu_handle_mmu_fault
;
177 cc
->do_unassigned_access
= mb_cpu_unassigned_access
;
178 cc
->get_phys_page_debug
= mb_cpu_get_phys_page_debug
;
180 dc
->vmsd
= &vmstate_mb_cpu
;
181 dc
->props
= mb_properties
;
182 cc
->gdb_num_core_regs
= 32 + 5;
185 static const TypeInfo mb_cpu_type_info
= {
186 .name
= TYPE_MICROBLAZE_CPU
,
188 .instance_size
= sizeof(MicroBlazeCPU
),
189 .instance_init
= mb_cpu_initfn
,
190 .class_size
= sizeof(MicroBlazeCPUClass
),
191 .class_init
= mb_cpu_class_init
,
194 static void mb_cpu_register_types(void)
196 type_register_static(&mb_cpu_type_info
);
199 type_init(mb_cpu_register_types
)