2 * QEMU IDE Emulation: MacIO support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/ppc/mac.h"
28 #include "hw/ppc/mac_dbdma.h"
29 #include "sysemu/block-backend.h"
30 #include "sysemu/dma.h"
32 #include "hw/ide/internal.h"
35 // #define DEBUG_MACIO
38 static const int debug_macio
= 1;
40 static const int debug_macio
= 0;
43 #define MACIO_DPRINTF(fmt, ...) do { \
45 printf(fmt , ## __VA_ARGS__); \
50 /***********************************************************/
51 /* MacIO based PowerPC IDE */
53 #define MACIO_PAGE_SIZE 4096
56 * Unaligned DMA read/write access functions required for OS X/Darwin which
57 * don't perform DMA transactions on sector boundaries. These functions are
58 * modelled on bdrv_co_preadv()/bdrv_co_pwritev() and so should be easy to
59 * remove if the unaligned block APIs are ever exposed.
62 static void pmac_dma_read(BlockBackend
*blk
,
63 int64_t offset
, unsigned int bytes
,
64 void (*cb
)(void *opaque
, int ret
), void *opaque
)
66 DBDMA_io
*io
= opaque
;
67 MACIOIDEState
*m
= io
->opaque
;
68 IDEState
*s
= idebus_active_if(&m
->bus
);
72 uint64_t align
= BDRV_SECTOR_SIZE
;
73 size_t head_bytes
, tail_bytes
;
75 qemu_iovec_destroy(&io
->iov
);
76 qemu_iovec_init(&io
->iov
, io
->len
/ MACIO_PAGE_SIZE
+ 1);
78 sector_num
= (offset
>> 9);
79 nsector
= (io
->len
>> 9);
81 MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx
",0x%x): "
82 "sector_num: %" PRId64
", nsector: %d\n", io
->addr
, io
->len
,
86 io
->dir
= DMA_DIRECTION_FROM_DEVICE
;
87 io
->dma_len
= io
->len
;
88 io
->dma_mem
= dma_memory_map(&address_space_memory
, dma_addr
, &io
->dma_len
,
91 if (offset
& (align
- 1)) {
92 head_bytes
= offset
& (align
- 1);
94 MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64
", "
95 "discarding %zu bytes\n", sector_num
, head_bytes
);
97 qemu_iovec_add(&io
->iov
, &io
->head_remainder
, head_bytes
);
99 bytes
+= offset
& (align
- 1);
100 offset
= offset
& ~(align
- 1);
103 qemu_iovec_add(&io
->iov
, io
->dma_mem
, io
->len
);
105 if ((offset
+ bytes
) & (align
- 1)) {
106 tail_bytes
= (offset
+ bytes
) & (align
- 1);
108 MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64
", "
109 "discarding bytes %zu\n", sector_num
, tail_bytes
);
111 qemu_iovec_add(&io
->iov
, &io
->tail_remainder
, align
- tail_bytes
);
112 bytes
= ROUND_UP(bytes
, align
);
115 s
->io_buffer_size
-= io
->len
;
116 s
->io_buffer_index
+= io
->len
;
120 MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64
" "
121 "nsector: %x\n", (offset
>> 9), (bytes
>> 9));
123 s
->bus
->dma
->aiocb
= blk_aio_preadv(blk
, offset
, &io
->iov
, 0, cb
, io
);
126 static void pmac_dma_write(BlockBackend
*blk
,
127 int64_t offset
, int bytes
,
128 void (*cb
)(void *opaque
, int ret
), void *opaque
)
130 DBDMA_io
*io
= opaque
;
131 MACIOIDEState
*m
= io
->opaque
;
132 IDEState
*s
= idebus_active_if(&m
->bus
);
136 uint64_t align
= BDRV_SECTOR_SIZE
;
137 size_t head_bytes
, tail_bytes
;
138 bool unaligned_head
= false, unaligned_tail
= false;
140 qemu_iovec_destroy(&io
->iov
);
141 qemu_iovec_init(&io
->iov
, io
->len
/ MACIO_PAGE_SIZE
+ 1);
143 sector_num
= (offset
>> 9);
144 nsector
= (io
->len
>> 9);
146 MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx
",0x%x): "
147 "sector_num: %" PRId64
", nsector: %d\n", io
->addr
, io
->len
,
148 sector_num
, nsector
);
151 io
->dir
= DMA_DIRECTION_TO_DEVICE
;
152 io
->dma_len
= io
->len
;
153 io
->dma_mem
= dma_memory_map(&address_space_memory
, dma_addr
, &io
->dma_len
,
156 if (offset
& (align
- 1)) {
157 head_bytes
= offset
& (align
- 1);
158 sector_num
= ((offset
& ~(align
- 1)) >> 9);
160 MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
161 PRId64
"\n", sector_num
);
163 blk_pread(s
->blk
, (sector_num
<< 9), &io
->head_remainder
, align
);
165 qemu_iovec_add(&io
->iov
, &io
->head_remainder
, head_bytes
);
166 qemu_iovec_add(&io
->iov
, io
->dma_mem
, io
->len
);
168 bytes
+= offset
& (align
- 1);
169 offset
= offset
& ~(align
- 1);
171 unaligned_head
= true;
174 if ((offset
+ bytes
) & (align
- 1)) {
175 tail_bytes
= (offset
+ bytes
) & (align
- 1);
176 sector_num
= (((offset
+ bytes
) & ~(align
- 1)) >> 9);
178 MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
179 PRId64
"\n", sector_num
);
181 blk_pread(s
->blk
, (sector_num
<< 9), &io
->tail_remainder
, align
);
183 if (!unaligned_head
) {
184 qemu_iovec_add(&io
->iov
, io
->dma_mem
, io
->len
);
187 qemu_iovec_add(&io
->iov
, &io
->tail_remainder
+ tail_bytes
,
190 bytes
= ROUND_UP(bytes
, align
);
192 unaligned_tail
= true;
195 if (!unaligned_head
&& !unaligned_tail
) {
196 qemu_iovec_add(&io
->iov
, io
->dma_mem
, io
->len
);
199 s
->io_buffer_size
-= io
->len
;
200 s
->io_buffer_index
+= io
->len
;
204 MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64
" "
205 "nsector: %x\n", (offset
>> 9), (bytes
>> 9));
207 s
->bus
->dma
->aiocb
= blk_aio_pwritev(blk
, offset
, &io
->iov
, 0, cb
, io
);
210 static void pmac_dma_trim(BlockBackend
*blk
,
211 int64_t offset
, int bytes
,
212 void (*cb
)(void *opaque
, int ret
), void *opaque
)
214 DBDMA_io
*io
= opaque
;
215 MACIOIDEState
*m
= io
->opaque
;
216 IDEState
*s
= idebus_active_if(&m
->bus
);
219 qemu_iovec_destroy(&io
->iov
);
220 qemu_iovec_init(&io
->iov
, io
->len
/ MACIO_PAGE_SIZE
+ 1);
223 io
->dir
= DMA_DIRECTION_TO_DEVICE
;
224 io
->dma_len
= io
->len
;
225 io
->dma_mem
= dma_memory_map(&address_space_memory
, dma_addr
, &io
->dma_len
,
228 qemu_iovec_add(&io
->iov
, io
->dma_mem
, io
->len
);
229 s
->io_buffer_size
-= io
->len
;
230 s
->io_buffer_index
+= io
->len
;
233 s
->bus
->dma
->aiocb
= ide_issue_trim(offset
, &io
->iov
, cb
, io
, blk
);
236 static void pmac_ide_atapi_transfer_cb(void *opaque
, int ret
)
238 DBDMA_io
*io
= opaque
;
239 MACIOIDEState
*m
= io
->opaque
;
240 IDEState
*s
= idebus_active_if(&m
->bus
);
243 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
246 MACIO_DPRINTF("DMA error: %d\n", ret
);
247 ide_atapi_io_error(s
, ret
);
251 if (!m
->dma_active
) {
252 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
253 s
->nsector
, io
->len
, s
->status
);
254 /* data not ready yet, wait for the channel to get restarted */
255 io
->processing
= false;
259 if (s
->io_buffer_size
<= 0) {
260 MACIO_DPRINTF("End of IDE transfer\n");
262 m
->dma_active
= false;
267 MACIO_DPRINTF("End of DMA transfer\n");
272 /* Non-block ATAPI transfer - just copy to RAM */
273 s
->io_buffer_size
= MIN(s
->io_buffer_size
, io
->len
);
274 dma_memory_write(&address_space_memory
, io
->addr
, s
->io_buffer
,
277 m
->dma_active
= false;
281 /* Calculate current offset */
282 offset
= ((int64_t)s
->lba
<< 11) + s
->io_buffer_index
;
284 pmac_dma_read(s
->blk
, offset
, io
->len
, pmac_ide_atapi_transfer_cb
, io
);
288 dma_memory_unmap(&address_space_memory
, io
->dma_mem
, io
->dma_len
,
289 io
->dir
, io
->dma_len
);
292 block_acct_failed(blk_get_stats(s
->blk
), &s
->acct
);
294 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
297 ide_set_inactive(s
, false);
301 static void pmac_ide_transfer_cb(void *opaque
, int ret
)
303 DBDMA_io
*io
= opaque
;
304 MACIOIDEState
*m
= io
->opaque
;
305 IDEState
*s
= idebus_active_if(&m
->bus
);
308 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
311 MACIO_DPRINTF("DMA error: %d\n", ret
);
316 if (!m
->dma_active
) {
317 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
318 s
->nsector
, io
->len
, s
->status
);
319 /* data not ready yet, wait for the channel to get restarted */
320 io
->processing
= false;
324 if (s
->io_buffer_size
<= 0) {
325 MACIO_DPRINTF("End of IDE transfer\n");
326 s
->status
= READY_STAT
| SEEK_STAT
;
328 m
->dma_active
= false;
333 MACIO_DPRINTF("End of DMA transfer\n");
337 /* Calculate number of sectors */
338 offset
= (ide_get_sector(s
) << 9) + s
->io_buffer_index
;
340 switch (s
->dma_cmd
) {
342 pmac_dma_read(s
->blk
, offset
, io
->len
, pmac_ide_transfer_cb
, io
);
345 pmac_dma_write(s
->blk
, offset
, io
->len
, pmac_ide_transfer_cb
, io
);
348 pmac_dma_trim(s
->blk
, offset
, io
->len
, pmac_ide_transfer_cb
, io
);
357 dma_memory_unmap(&address_space_memory
, io
->dma_mem
, io
->dma_len
,
358 io
->dir
, io
->dma_len
);
360 if (s
->dma_cmd
== IDE_DMA_READ
|| s
->dma_cmd
== IDE_DMA_WRITE
) {
362 block_acct_failed(blk_get_stats(s
->blk
), &s
->acct
);
364 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
368 ide_set_inactive(s
, false);
372 static void pmac_ide_transfer(DBDMA_io
*io
)
374 MACIOIDEState
*m
= io
->opaque
;
375 IDEState
*s
= idebus_active_if(&m
->bus
);
379 if (s
->drive_kind
== IDE_CD
) {
380 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
383 pmac_ide_atapi_transfer_cb(io
, 0);
387 switch (s
->dma_cmd
) {
389 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
393 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
400 pmac_ide_transfer_cb(io
, 0);
403 static void pmac_ide_flush(DBDMA_io
*io
)
405 MACIOIDEState
*m
= io
->opaque
;
406 IDEState
*s
= idebus_active_if(&m
->bus
);
408 if (s
->bus
->dma
->aiocb
) {
413 /* PowerMac IDE memory IO */
414 static void pmac_ide_writeb (void *opaque
,
415 hwaddr addr
, uint32_t val
)
417 MACIOIDEState
*d
= opaque
;
419 addr
= (addr
& 0xFFF) >> 4;
422 ide_ioport_write(&d
->bus
, addr
, val
);
426 ide_cmd_write(&d
->bus
, 0, val
);
433 static uint32_t pmac_ide_readb (void *opaque
,hwaddr addr
)
436 MACIOIDEState
*d
= opaque
;
438 addr
= (addr
& 0xFFF) >> 4;
441 retval
= ide_ioport_read(&d
->bus
, addr
);
445 retval
= ide_status_read(&d
->bus
, 0);
454 static void pmac_ide_writew (void *opaque
,
455 hwaddr addr
, uint32_t val
)
457 MACIOIDEState
*d
= opaque
;
459 addr
= (addr
& 0xFFF) >> 4;
462 ide_data_writew(&d
->bus
, 0, val
);
466 static uint32_t pmac_ide_readw (void *opaque
,hwaddr addr
)
469 MACIOIDEState
*d
= opaque
;
471 addr
= (addr
& 0xFFF) >> 4;
473 retval
= ide_data_readw(&d
->bus
, 0);
477 retval
= bswap16(retval
);
481 static void pmac_ide_writel (void *opaque
,
482 hwaddr addr
, uint32_t val
)
484 MACIOIDEState
*d
= opaque
;
486 addr
= (addr
& 0xFFF) >> 4;
489 ide_data_writel(&d
->bus
, 0, val
);
493 static uint32_t pmac_ide_readl (void *opaque
,hwaddr addr
)
496 MACIOIDEState
*d
= opaque
;
498 addr
= (addr
& 0xFFF) >> 4;
500 retval
= ide_data_readl(&d
->bus
, 0);
504 retval
= bswap32(retval
);
508 static const MemoryRegionOps pmac_ide_ops
= {
521 .endianness
= DEVICE_NATIVE_ENDIAN
,
524 static const VMStateDescription vmstate_pmac
= {
527 .minimum_version_id
= 0,
528 .fields
= (VMStateField
[]) {
529 VMSTATE_IDE_BUS(bus
, MACIOIDEState
),
530 VMSTATE_IDE_DRIVES(bus
.ifs
, MACIOIDEState
),
531 VMSTATE_BOOL(dma_active
, MACIOIDEState
),
532 VMSTATE_END_OF_LIST()
536 static void macio_ide_reset(DeviceState
*dev
)
538 MACIOIDEState
*d
= MACIO_IDE(dev
);
540 ide_bus_reset(&d
->bus
);
543 static int ide_nop_int(IDEDMA
*dma
, int x
)
548 static int32_t ide_nop_int32(IDEDMA
*dma
, int32_t l
)
553 static void ide_dbdma_start(IDEDMA
*dma
, IDEState
*s
,
554 BlockCompletionFunc
*cb
)
556 MACIOIDEState
*m
= container_of(dma
, MACIOIDEState
, dma
);
558 s
->io_buffer_index
= 0;
559 if (s
->drive_kind
== IDE_CD
) {
560 s
->io_buffer_size
= s
->packet_transfer_size
;
562 s
->io_buffer_size
= s
->nsector
* BDRV_SECTOR_SIZE
;
565 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
566 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
567 s
->io_buffer_size
, s
->io_buffer_index
);
568 MACIO_DPRINTF("lba: %x size: %x\n", s
->lba
, s
->io_buffer_size
);
569 MACIO_DPRINTF("-------------------------\n");
571 m
->dma_active
= true;
572 DBDMA_kick(m
->dbdma
);
575 static const IDEDMAOps dbdma_ops
= {
576 .start_dma
= ide_dbdma_start
,
577 .prepare_buf
= ide_nop_int32
,
578 .rw_buf
= ide_nop_int
,
581 static void macio_ide_realizefn(DeviceState
*dev
, Error
**errp
)
583 MACIOIDEState
*s
= MACIO_IDE(dev
);
585 ide_init2(&s
->bus
, s
->irq
);
587 /* Register DMA callbacks */
588 s
->dma
.ops
= &dbdma_ops
;
589 s
->bus
.dma
= &s
->dma
;
592 static void macio_ide_initfn(Object
*obj
)
594 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
595 MACIOIDEState
*s
= MACIO_IDE(obj
);
597 ide_bus_new(&s
->bus
, sizeof(s
->bus
), DEVICE(obj
), 0, 2);
598 memory_region_init_io(&s
->mem
, obj
, &pmac_ide_ops
, s
, "pmac-ide", 0x1000);
599 sysbus_init_mmio(d
, &s
->mem
);
600 sysbus_init_irq(d
, &s
->irq
);
601 sysbus_init_irq(d
, &s
->dma_irq
);
604 static void macio_ide_class_init(ObjectClass
*oc
, void *data
)
606 DeviceClass
*dc
= DEVICE_CLASS(oc
);
608 dc
->realize
= macio_ide_realizefn
;
609 dc
->reset
= macio_ide_reset
;
610 dc
->vmsd
= &vmstate_pmac
;
611 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
614 static const TypeInfo macio_ide_type_info
= {
615 .name
= TYPE_MACIO_IDE
,
616 .parent
= TYPE_SYS_BUS_DEVICE
,
617 .instance_size
= sizeof(MACIOIDEState
),
618 .instance_init
= macio_ide_initfn
,
619 .class_init
= macio_ide_class_init
,
622 static void macio_ide_register_types(void)
624 type_register_static(&macio_ide_type_info
);
627 /* hd_table must contain 2 block drivers */
628 void macio_ide_init_drives(MACIOIDEState
*s
, DriveInfo
**hd_table
)
632 for (i
= 0; i
< 2; i
++) {
634 ide_create_drive(&s
->bus
, i
, hd_table
[i
]);
639 void macio_ide_register_dma(MACIOIDEState
*s
, void *dbdma
, int channel
)
642 DBDMA_register_channel(dbdma
, channel
, s
->dma_irq
,
643 pmac_ide_transfer
, pmac_ide_flush
, s
);
646 type_init(macio_ide_register_types
)