target-xtensa/helper.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30 #include "gdbstub.h"
  31 #include "host-utils.h"
  32 #if !defined(CONFIG_USER_ONLY)
  33 #include "hw/loader.h"
  34 #endif
  35
  36 static void reset_mmu(CPUXtensaState *env);
  37
  38 void cpu_state_reset(CPUXtensaState *env)
  39 {
  40     env->exception_taken = 0;
  41     env->pc = env->config->exception_vector[EXC_RESET];
  42     env->sregs[LITBASE] &= ~1;
  43     env->sregs[PS] = xtensa_option_enabled(env->config,
  44             XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
  45     env->sregs[VECBASE] = env->config->vecbase;
  46     env->sregs[IBREAKENABLE] = 0;
  47
  48     env->pending_irq_level = 0;
  49     reset_mmu(env);
  50 }
  51
  52 static struct XtensaConfigList *xtensa_cores;
  53
  54 void xtensa_register_core(XtensaConfigList *node)
  55 {
  56     node->next = xtensa_cores;
  57     xtensa_cores = node;
  58 }
  59
  60 static uint32_t check_hw_breakpoints(CPUXtensaState *env)
  61 {
  62     unsigned i;
  63
  64     for (i = 0; i < env->config->ndbreak; ++i) {
  65         if (env->cpu_watchpoint[i] &&
  66                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
  67             return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
  68         }
  69     }
  70     return 0;
  71 }
  72
  73 static CPUDebugExcpHandler *prev_debug_excp_handler;
  74
  75 static void breakpoint_handler(CPUXtensaState *env)
  76 {
  77     if (env->watchpoint_hit) {
  78         if (env->watchpoint_hit->flags & BP_CPU) {
  79             uint32_t cause;
  80
  81             env->watchpoint_hit = NULL;
  82             cause = check_hw_breakpoints(env);
  83             if (cause) {
  84                 debug_exception_env(env, cause);
  85             }
  86             cpu_resume_from_signal(env, NULL);
  87         }
  88     }
  89     if (prev_debug_excp_handler) {
  90         prev_debug_excp_handler(env);
  91     }
  92 }
  93
  94 CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
  95 {
  96     static int tcg_inited;
  97     static int debug_handler_inited;
  98     CPUXtensaState *env;
  99     const XtensaConfig *config = NULL;
 100     XtensaConfigList *core = xtensa_cores;
 101
 102     for (; core; core = core->next)
 103         if (strcmp(core->config->name, cpu_model) == 0) {
 104             config = core->config;
 105             break;
 106         }
 107
 108     if (config == NULL) {
 109         return NULL;
 110     }
 111
 112     env = g_malloc0(sizeof(*env));
 113     env->config = config;
 114     cpu_exec_init(env);
 115
 116     if (!tcg_inited) {
 117         tcg_inited = 1;
 118         xtensa_translate_init();
 119     }
 120
 121     if (!debug_handler_inited && tcg_enabled()) {
 122         debug_handler_inited = 1;
 123         prev_debug_excp_handler =
 124             cpu_set_debug_excp_handler(breakpoint_handler);
 125     }
 126
 127     xtensa_irq_init(env);
 128     qemu_init_vcpu(env);
 129     return env;
 130 }
 131
 132
 133 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 134 {
 135     XtensaConfigList *core = xtensa_cores;
 136     cpu_fprintf(f, "Available CPUs:\n");
 137     for (; core; core = core->next) {
 138         cpu_fprintf(f, "  %s\n", core->config->name);
 139     }
 140 }
 141
 142 target_phys_addr_t cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
 143 {
 144     uint32_t paddr;
 145     uint32_t page_size;
 146     unsigned access;
 147
 148     if (xtensa_get_physical_addr(env, addr, 0, 0,
 149                 &paddr, &page_size, &access) == 0) {
 150         return paddr;
 151     }
 152     if (xtensa_get_physical_addr(env, addr, 2, 0,
 153                 &paddr, &page_size, &access) == 0) {
 154         return paddr;
 155     }
 156     return ~0;
 157 }
 158
 159 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
 160 {
 161     if (xtensa_option_enabled(env->config,
 162                 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
 163         return vector - env->config->vecbase + env->sregs[VECBASE];
 164     } else {
 165         return vector;
 166     }
 167 }
 168
 169 /*!
 170  * Handle penging IRQ.
 171  * For the high priority interrupt jump to the corresponding interrupt vector.
 172  * For the level-1 interrupt convert it to either user, kernel or double
 173  * exception with the 'level-1 interrupt' exception cause.
 174  */
 175 static void handle_interrupt(CPUXtensaState *env)
 176 {
 177     int level = env->pending_irq_level;
 178
 179     if (level > xtensa_get_cintlevel(env) &&
 180             level <= env->config->nlevel &&
 181             (env->config->level_mask[level] &
 182              env->sregs[INTSET] &
 183              env->sregs[INTENABLE])) {
 184         if (level > 1) {
 185             env->sregs[EPC1 + level - 1] = env->pc;
 186             env->sregs[EPS2 + level - 2] = env->sregs[PS];
 187             env->sregs[PS] =
 188                 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
 189             env->pc = relocated_vector(env,
 190                     env->config->interrupt_vector[level]);
 191         } else {
 192             env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
 193
 194             if (env->sregs[PS] & PS_EXCM) {
 195                 if (env->config->ndepc) {
 196                     env->sregs[DEPC] = env->pc;
 197                 } else {
 198                     env->sregs[EPC1] = env->pc;
 199                 }
 200                 env->exception_index = EXC_DOUBLE;
 201             } else {
 202                 env->sregs[EPC1] = env->pc;
 203                 env->exception_index =
 204                     (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
 205             }
 206             env->sregs[PS] |= PS_EXCM;
 207         }
 208         env->exception_taken = 1;
 209     }
 210 }
 211
 212 void do_interrupt(CPUXtensaState *env)
 213 {
 214     if (env->exception_index == EXC_IRQ) {
 215         qemu_log_mask(CPU_LOG_INT,
 216                 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
 217                 "pc = %08x, a0 = %08x, ps = %08x, "
 218                 "intset = %08x, intenable = %08x, "
 219                 "ccount = %08x\n",
 220                 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
 221                 env->pc, env->regs[0], env->sregs[PS],
 222                 env->sregs[INTSET], env->sregs[INTENABLE],
 223                 env->sregs[CCOUNT]);
 224         handle_interrupt(env);
 225     }
 226
 227     switch (env->exception_index) {
 228     case EXC_WINDOW_OVERFLOW4:
 229     case EXC_WINDOW_UNDERFLOW4:
 230     case EXC_WINDOW_OVERFLOW8:
 231     case EXC_WINDOW_UNDERFLOW8:
 232     case EXC_WINDOW_OVERFLOW12:
 233     case EXC_WINDOW_UNDERFLOW12:
 234     case EXC_KERNEL:
 235     case EXC_USER:
 236     case EXC_DOUBLE:
 237     case EXC_DEBUG:
 238         qemu_log_mask(CPU_LOG_INT, "%s(%d) "
 239                 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
 240                 __func__, env->exception_index,
 241                 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
 242         if (env->config->exception_vector[env->exception_index]) {
 243             env->pc = relocated_vector(env,
 244                     env->config->exception_vector[env->exception_index]);
 245             env->exception_taken = 1;
 246         } else {
 247             qemu_log("%s(pc = %08x) bad exception_index: %d\n",
 248                     __func__, env->pc, env->exception_index);
 249         }
 250         break;
 251
 252     case EXC_IRQ:
 253         break;
 254
 255     default:
 256         qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
 257                 __func__, env->pc, env->exception_index);
 258         break;
 259     }
 260     check_interrupts(env);
 261 }
 262
 263 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
 264         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 265 {
 266     unsigned wi, ei;
 267
 268     for (wi = 0; wi < tlb->nways; ++wi) {
 269         for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
 270             entry[wi][ei].asid = 0;
 271             entry[wi][ei].variable = true;
 272         }
 273     }
 274 }
 275
 276 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
 277         const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 278 {
 279     if (!tlb->varway56) {
 280         static const xtensa_tlb_entry way5[] = {
 281             {
 282                 .vaddr = 0xd0000000,
 283                 .paddr = 0,
 284                 .asid = 1,
 285                 .attr = 7,
 286                 .variable = false,
 287             }, {
 288                 .vaddr = 0xd8000000,
 289                 .paddr = 0,
 290                 .asid = 1,
 291                 .attr = 3,
 292                 .variable = false,
 293             }
 294         };
 295         static const xtensa_tlb_entry way6[] = {
 296             {
 297                 .vaddr = 0xe0000000,
 298                 .paddr = 0xf0000000,
 299                 .asid = 1,
 300                 .attr = 7,
 301                 .variable = false,
 302             }, {
 303                 .vaddr = 0xf0000000,
 304                 .paddr = 0xf0000000,
 305                 .asid = 1,
 306                 .attr = 3,
 307                 .variable = false,
 308             }
 309         };
 310         memcpy(entry[5], way5, sizeof(way5));
 311         memcpy(entry[6], way6, sizeof(way6));
 312     } else {
 313         uint32_t ei;
 314         for (ei = 0; ei < 8; ++ei) {
 315             entry[6][ei].vaddr = ei << 29;
 316             entry[6][ei].paddr = ei << 29;
 317             entry[6][ei].asid = 1;
 318             entry[6][ei].attr = 3;
 319         }
 320     }
 321 }
 322
 323 static void reset_tlb_region_way0(CPUXtensaState *env,
 324         xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
 325 {
 326     unsigned ei;
 327
 328     for (ei = 0; ei < 8; ++ei) {
 329         entry[0][ei].vaddr = ei << 29;
 330         entry[0][ei].paddr = ei << 29;
 331         entry[0][ei].asid = 1;
 332         entry[0][ei].attr = 2;
 333         entry[0][ei].variable = true;
 334     }
 335 }
 336
 337 static void reset_mmu(CPUXtensaState *env)
 338 {
 339     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 340         env->sregs[RASID] = 0x04030201;
 341         env->sregs[ITLBCFG] = 0;
 342         env->sregs[DTLBCFG] = 0;
 343         env->autorefill_idx = 0;
 344         reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
 345         reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
 346         reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
 347         reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
 348     } else {
 349         reset_tlb_region_way0(env, env->itlb);
 350         reset_tlb_region_way0(env, env->dtlb);
 351     }
 352 }
 353
 354 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
 355 {
 356     unsigned i;
 357     for (i = 0; i < 4; ++i) {
 358         if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
 359             return i;
 360         }
 361     }
 362     return 0xff;
 363 }
 364
 365 /*!
 366  * Lookup xtensa TLB for the given virtual address.
 367  * See ISA, 4.6.2.2
 368  *
 369  * \param pwi: [out] way index
 370  * \param pei: [out] entry index
 371  * \param pring: [out] access ring
 372  * \return 0 if ok, exception cause code otherwise
 373  */
 374 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 375         uint32_t *pwi, uint32_t *pei, uint8_t *pring)
 376 {
 377     const xtensa_tlb *tlb = dtlb ?
 378         &env->config->dtlb : &env->config->itlb;
 379     const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
 380         env->dtlb : env->itlb;
 381
 382     int nhits = 0;
 383     unsigned wi;
 384
 385     for (wi = 0; wi < tlb->nways; ++wi) {
 386         uint32_t vpn;
 387         uint32_t ei;
 388         split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
 389         if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
 390             unsigned ring = get_ring(env, entry[wi][ei].asid);
 391             if (ring < 4) {
 392                 if (++nhits > 1) {
 393                     return dtlb ?
 394                         LOAD_STORE_TLB_MULTI_HIT_CAUSE :
 395                         INST_TLB_MULTI_HIT_CAUSE;
 396                 }
 397                 *pwi = wi;
 398                 *pei = ei;
 399                 *pring = ring;
 400             }
 401         }
 402     }
 403     return nhits ? 0 :
 404         (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
 405 }
 406
 407 /*!
 408  * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
 409  * See ISA, 4.6.5.10
 410  */
 411 static unsigned mmu_attr_to_access(uint32_t attr)
 412 {
 413     unsigned access = 0;
 414     if (attr < 12) {
 415         access |= PAGE_READ;
 416         if (attr & 0x1) {
 417             access |= PAGE_EXEC;
 418         }
 419         if (attr & 0x2) {
 420             access |= PAGE_WRITE;
 421         }
 422     } else if (attr == 13) {
 423         access |= PAGE_READ | PAGE_WRITE;
 424     }
 425     return access;
 426 }
 427
 428 /*!
 429  * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
 430  * See ISA, 4.6.3.3
 431  */
 432 static unsigned region_attr_to_access(uint32_t attr)
 433 {
 434     unsigned access = 0;
 435     if ((attr < 6 && attr != 3) || attr == 14) {
 436         access |= PAGE_READ | PAGE_WRITE;
 437     }
 438     if (attr > 0 && attr < 6) {
 439         access |= PAGE_EXEC;
 440     }
 441     return access;
 442 }
 443
 444 static bool is_access_granted(unsigned access, int is_write)
 445 {
 446     switch (is_write) {
 447     case 0:
 448         return access & PAGE_READ;
 449
 450     case 1:
 451         return access & PAGE_WRITE;
 452
 453     case 2:
 454         return access & PAGE_EXEC;
 455
 456     default:
 457         return 0;
 458     }
 459 }
 460
 461 static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
 462         uint32_t *wi, uint32_t *ei, uint8_t *ring);
 463
 464 static int get_physical_addr_mmu(CPUXtensaState *env,
 465         uint32_t vaddr, int is_write, int mmu_idx,
 466         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 467 {
 468     bool dtlb = is_write != 2;
 469     uint32_t wi;
 470     uint32_t ei;
 471     uint8_t ring;
 472     int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
 473
 474     if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
 475             (mmu_idx != 0 || ((vaddr ^ env->sregs[PTEVADDR]) & 0xffc00000)) &&
 476             autorefill_mmu(env, vaddr, dtlb, &wi, &ei, &ring) == 0) {
 477         ret = 0;
 478     }
 479     if (ret != 0) {
 480         return ret;
 481     }
 482
 483     const xtensa_tlb_entry *entry =
 484         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 485
 486     if (ring < mmu_idx) {
 487         return dtlb ?
 488             LOAD_STORE_PRIVILEGE_CAUSE :
 489             INST_FETCH_PRIVILEGE_CAUSE;
 490     }
 491
 492     *access = mmu_attr_to_access(entry->attr);
 493     if (!is_access_granted(*access, is_write)) {
 494         return dtlb ?
 495             (is_write ?
 496              STORE_PROHIBITED_CAUSE :
 497              LOAD_PROHIBITED_CAUSE) :
 498             INST_FETCH_PROHIBITED_CAUSE;
 499     }
 500
 501     *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
 502     *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 503
 504     return 0;
 505 }
 506
 507 static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb,
 508         uint32_t *wi, uint32_t *ei, uint8_t *ring)
 509 {
 510     uint32_t paddr;
 511     uint32_t page_size;
 512     unsigned access;
 513     uint32_t pt_vaddr =
 514         (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
 515     int ret = get_physical_addr_mmu(env, pt_vaddr, 0, 0,
 516             &paddr, &page_size, &access);
 517
 518     qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
 519             vaddr, ret ? ~0 : paddr);
 520
 521     if (ret == 0) {
 522         uint32_t vpn;
 523         uint32_t pte = ldl_phys(paddr);
 524
 525         *ring = (pte >> 4) & 0x3;
 526         *wi = (++env->autorefill_idx) & 0x3;
 527         split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei);
 528         xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte);
 529         qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
 530                 __func__, vaddr, vpn, pte);
 531     }
 532     return ret;
 533 }
 534
 535 static int get_physical_addr_region(CPUXtensaState *env,
 536         uint32_t vaddr, int is_write, int mmu_idx,
 537         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 538 {
 539     bool dtlb = is_write != 2;
 540     uint32_t wi = 0;
 541     uint32_t ei = (vaddr >> 29) & 0x7;
 542     const xtensa_tlb_entry *entry =
 543         xtensa_tlb_get_entry(env, dtlb, wi, ei);
 544
 545     *access = region_attr_to_access(entry->attr);
 546     if (!is_access_granted(*access, is_write)) {
 547         return dtlb ?
 548             (is_write ?
 549              STORE_PROHIBITED_CAUSE :
 550              LOAD_PROHIBITED_CAUSE) :
 551             INST_FETCH_PROHIBITED_CAUSE;
 552     }
 553
 554     *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
 555     *page_size = ~REGION_PAGE_MASK + 1;
 556
 557     return 0;
 558 }
 559
 560 /*!
 561  * Convert virtual address to physical addr.
 562  * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
 563  *
 564  * \return 0 if ok, exception cause code otherwise
 565  */
 566 int xtensa_get_physical_addr(CPUXtensaState *env,
 567         uint32_t vaddr, int is_write, int mmu_idx,
 568         uint32_t *paddr, uint32_t *page_size, unsigned *access)
 569 {
 570     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 571         return get_physical_addr_mmu(env, vaddr, is_write, mmu_idx,
 572                 paddr, page_size, access);
 573     } else if (xtensa_option_bits_enabled(env->config,
 574                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 575                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
 576         return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
 577                 paddr, page_size, access);
 578     } else {
 579         *paddr = vaddr;
 580         *page_size = TARGET_PAGE_SIZE;
 581         *access = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 582         return 0;
 583     }
 584 }
 585
 586 static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
 587         CPUXtensaState *env, bool dtlb)
 588 {
 589     unsigned wi, ei;
 590     const xtensa_tlb *conf =
 591         dtlb ? &env->config->dtlb : &env->config->itlb;
 592     unsigned (*attr_to_access)(uint32_t) =
 593         xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
 594         mmu_attr_to_access : region_attr_to_access;
 595
 596     for (wi = 0; wi < conf->nways; ++wi) {
 597         uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
 598         const char *sz_text;
 599         bool print_header = true;
 600
 601         if (sz >= 0x100000) {
 602             sz >>= 20;
 603             sz_text = "MB";
 604         } else {
 605             sz >>= 10;
 606             sz_text = "KB";
 607         }
 608
 609         for (ei = 0; ei < conf->way_size[wi]; ++ei) {
 610             const xtensa_tlb_entry *entry =
 611                 xtensa_tlb_get_entry(env, dtlb, wi, ei);
 612
 613             if (entry->asid) {
 614                 unsigned access = attr_to_access(entry->attr);
 615
 616                 if (print_header) {
 617                     print_header = false;
 618                     cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
 619                     cpu_fprintf(f,
 620                             "\tVaddr       Paddr       ASID  Attr RWX\n"
 621                             "\t----------  ----------  ----  ---- ---\n");
 622                 }
 623                 cpu_fprintf(f,
 624                         "\t0x%08x  0x%08x  0x%02x  0x%02x %c%c%c\n",
 625                         entry->vaddr,
 626                         entry->paddr,
 627                         entry->asid,
 628                         entry->attr,
 629                         (access & PAGE_READ) ? 'R' : '-',
 630                         (access & PAGE_WRITE) ? 'W' : '-',
 631                         (access & PAGE_EXEC) ? 'X' : '-');
 632             }
 633         }
 634     }
 635 }
 636
 637 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
 638 {
 639     if (xtensa_option_bits_enabled(env->config,
 640                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
 641                 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
 642                 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
 643
 644         cpu_fprintf(f, "ITLB:\n");
 645         dump_tlb(f, cpu_fprintf, env, false);
 646         cpu_fprintf(f, "\nDTLB:\n");
 647         dump_tlb(f, cpu_fprintf, env, true);
 648     } else {
 649         cpu_fprintf(f, "No TLB for this CPU core\n");
 650     }
 651 }