hw/isa/piix3.c

   1 /*
   2  * QEMU PIIX PCI ISA Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/range.h"
  27 #include "qapi/error.h"
  28 #include "hw/southbridge/piix.h"
  29 #include "hw/irq.h"
  30 #include "hw/isa/isa.h"
  31 #include "hw/xen/xen.h"
  32 #include "sysemu/xen.h"
  33 #include "sysemu/reset.h"
  34 #include "sysemu/runstate.h"
  35 #include "migration/vmstate.h"
  36 #include "hw/acpi/acpi_aml_interface.h"
  37
  38 #define XEN_PIIX_NUM_PIRQS      128ULL
  39
  40 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
  41 {
  42     qemu_set_irq(piix3->pic[pic_irq],
  43                  !!(piix3->pic_levels &
  44                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
  45                      (pic_irq * PIIX_NUM_PIRQS))));
  46 }
  47
  48 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
  49 {
  50     int pic_irq;
  51     uint64_t mask;
  52
  53     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  54     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
  55         return;
  56     }
  57
  58     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
  59     piix3->pic_levels &= ~mask;
  60     piix3->pic_levels |= mask * !!level;
  61 }
  62
  63 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
  64 {
  65     int pic_irq;
  66
  67     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  68     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
  69         return;
  70     }
  71
  72     piix3_set_irq_level_internal(piix3, pirq, level);
  73
  74     piix3_set_irq_pic(piix3, pic_irq);
  75 }
  76
  77 static void piix3_set_irq(void *opaque, int pirq, int level)
  78 {
  79     PIIX3State *piix3 = opaque;
  80     piix3_set_irq_level(piix3, pirq, level);
  81 }
  82
  83 /*
  84  * Return the global irq number corresponding to a given device irq
  85  * pin. We could also use the bus number to have a more precise mapping.
  86  */
  87 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
  88 {
  89     int slot_addend;
  90     slot_addend = PCI_SLOT(pci_dev->devfn) - 1;
  91     return (pci_intx + slot_addend) & 3;
  92 }
  93
  94 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
  95 {
  96     PIIX3State *piix3 = opaque;
  97     int irq = piix3->dev.config[PIIX_PIRQCA + pin];
  98     PCIINTxRoute route;
  99
 100     if (irq < PIIX_NUM_PIC_IRQS) {
 101         route.mode = PCI_INTX_ENABLED;
 102         route.irq = irq;
 103     } else {
 104         route.mode = PCI_INTX_DISABLED;
 105         route.irq = -1;
 106     }
 107     return route;
 108 }
 109
 110 /* irq routing is changed. so rebuild bitmap */
 111 static void piix3_update_irq_levels(PIIX3State *piix3)
 112 {
 113     PCIBus *bus = pci_get_bus(&piix3->dev);
 114     int pirq;
 115
 116     piix3->pic_levels = 0;
 117     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 118         piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
 119     }
 120 }
 121
 122 static void piix3_write_config(PCIDevice *dev,
 123                                uint32_t address, uint32_t val, int len)
 124 {
 125     pci_default_write_config(dev, address, val, len);
 126     if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
 127         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 128         int pic_irq;
 129
 130         pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
 131         piix3_update_irq_levels(piix3);
 132         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 133             piix3_set_irq_pic(piix3, pic_irq);
 134         }
 135     }
 136 }
 137
 138 static void piix3_write_config_xen(PCIDevice *dev,
 139                                    uint32_t address, uint32_t val, int len)
 140 {
 141     xen_piix_pci_write_config_client(address, val, len);
 142     piix3_write_config(dev, address, val, len);
 143 }
 144
 145 static void piix3_reset(void *opaque)
 146 {
 147     PIIX3State *d = opaque;
 148     uint8_t *pci_conf = d->dev.config;
 149
 150     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 151     pci_conf[0x05] = 0x00;
 152     pci_conf[0x06] = 0x00;
 153     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 154     pci_conf[0x4c] = 0x4d;
 155     pci_conf[0x4e] = 0x03;
 156     pci_conf[0x4f] = 0x00;
 157     pci_conf[0x60] = 0x80;
 158     pci_conf[0x61] = 0x80;
 159     pci_conf[0x62] = 0x80;
 160     pci_conf[0x63] = 0x80;
 161     pci_conf[0x69] = 0x02;
 162     pci_conf[0x70] = 0x80;
 163     pci_conf[0x76] = 0x0c;
 164     pci_conf[0x77] = 0x0c;
 165     pci_conf[0x78] = 0x02;
 166     pci_conf[0x79] = 0x00;
 167     pci_conf[0x80] = 0x00;
 168     pci_conf[0x82] = 0x00;
 169     pci_conf[0xa0] = 0x08;
 170     pci_conf[0xa2] = 0x00;
 171     pci_conf[0xa3] = 0x00;
 172     pci_conf[0xa4] = 0x00;
 173     pci_conf[0xa5] = 0x00;
 174     pci_conf[0xa6] = 0x00;
 175     pci_conf[0xa7] = 0x00;
 176     pci_conf[0xa8] = 0x0f;
 177     pci_conf[0xaa] = 0x00;
 178     pci_conf[0xab] = 0x00;
 179     pci_conf[0xac] = 0x00;
 180     pci_conf[0xae] = 0x00;
 181
 182     d->pic_levels = 0;
 183     d->rcr = 0;
 184 }
 185
 186 static int piix3_post_load(void *opaque, int version_id)
 187 {
 188     PIIX3State *piix3 = opaque;
 189     int pirq;
 190
 191     /*
 192      * Because the i8259 has not been deserialized yet, qemu_irq_raise
 193      * might bring the system to a different state than the saved one;
 194      * for example, the interrupt could be masked but the i8259 would
 195      * not know that yet and would trigger an interrupt in the CPU.
 196      *
 197      * Here, we update irq levels without raising the interrupt.
 198      * Interrupt state will be deserialized separately through the i8259.
 199      */
 200     piix3->pic_levels = 0;
 201     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 202         piix3_set_irq_level_internal(piix3, pirq,
 203             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
 204     }
 205     return 0;
 206 }
 207
 208 static int piix3_pre_save(void *opaque)
 209 {
 210     int i;
 211     PIIX3State *piix3 = opaque;
 212
 213     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 214         piix3->pci_irq_levels_vmstate[i] =
 215             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
 216     }
 217
 218     return 0;
 219 }
 220
 221 static bool piix3_rcr_needed(void *opaque)
 222 {
 223     PIIX3State *piix3 = opaque;
 224
 225     return (piix3->rcr != 0);
 226 }
 227
 228 static const VMStateDescription vmstate_piix3_rcr = {
 229     .name = "PIIX3/rcr",
 230     .version_id = 1,
 231     .minimum_version_id = 1,
 232     .needed = piix3_rcr_needed,
 233     .fields = (VMStateField[]) {
 234         VMSTATE_UINT8(rcr, PIIX3State),
 235         VMSTATE_END_OF_LIST()
 236     }
 237 };
 238
 239 static const VMStateDescription vmstate_piix3 = {
 240     .name = "PIIX3",
 241     .version_id = 3,
 242     .minimum_version_id = 2,
 243     .post_load = piix3_post_load,
 244     .pre_save = piix3_pre_save,
 245     .fields = (VMStateField[]) {
 246         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 247         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 248                               PIIX_NUM_PIRQS, 3),
 249         VMSTATE_END_OF_LIST()
 250     },
 251     .subsections = (const VMStateDescription*[]) {
 252         &vmstate_piix3_rcr,
 253         NULL
 254     }
 255 };
 256
 257
 258 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 259 {
 260     PIIX3State *d = opaque;
 261
 262     if (val & 4) {
 263         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 264         return;
 265     }
 266     d->rcr = val & 2; /* keep System Reset type only */
 267 }
 268
 269 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 270 {
 271     PIIX3State *d = opaque;
 272
 273     return d->rcr;
 274 }
 275
 276 static const MemoryRegionOps rcr_ops = {
 277     .read = rcr_read,
 278     .write = rcr_write,
 279     .endianness = DEVICE_LITTLE_ENDIAN
 280 };
 281
 282 static void pci_piix3_realize(PCIDevice *dev, Error **errp)
 283 {
 284     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 285
 286     if (!isa_bus_new(DEVICE(d), get_system_memory(),
 287                      pci_address_space_io(dev), errp)) {
 288         return;
 289     }
 290
 291     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 292                           "piix3-reset-control", 1);
 293     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 294                                         PIIX_RCR_IOPORT, &d->rcr_mem, 1);
 295
 296     qemu_register_reset(piix3_reset, d);
 297 }
 298
 299 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
 300 {
 301     BusChild *kid;
 302     BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
 303
 304     /* PIIX PCI to ISA irq remapping */
 305     aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
 306                                          aml_int(0x60), 0x04));
 307     QTAILQ_FOREACH(kid, &bus->children, sibling) {
 308         call_dev_aml_func(DEVICE(kid->child), scope);
 309     }
 310 }
 311
 312 static void pci_piix3_class_init(ObjectClass *klass, void *data)
 313 {
 314     DeviceClass *dc = DEVICE_CLASS(klass);
 315     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 316     AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 317
 318     dc->desc        = "ISA bridge";
 319     dc->vmsd        = &vmstate_piix3;
 320     dc->hotpluggable   = false;
 321     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 322     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 323     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 324     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 325     /*
 326      * Reason: part of PIIX3 southbridge, needs to be wired up by
 327      * pc_piix.c's pc_init1()
 328      */
 329     dc->user_creatable = false;
 330     adevc->build_dev_aml = build_pci_isa_aml;
 331 }
 332
 333 static const TypeInfo piix3_pci_type_info = {
 334     .name = TYPE_PIIX3_PCI_DEVICE,
 335     .parent = TYPE_PCI_DEVICE,
 336     .instance_size = sizeof(PIIX3State),
 337     .abstract = true,
 338     .class_init = pci_piix3_class_init,
 339     .interfaces = (InterfaceInfo[]) {
 340         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 341         { TYPE_ACPI_DEV_AML_IF },
 342         { },
 343     },
 344 };
 345
 346 static void piix3_realize(PCIDevice *dev, Error **errp)
 347 {
 348     ERRP_GUARD();
 349     PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 350     PCIBus *pci_bus = pci_get_bus(dev);
 351
 352     pci_piix3_realize(dev, errp);
 353     if (*errp) {
 354         return;
 355     }
 356
 357     pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
 358                  piix3, PIIX_NUM_PIRQS);
 359     pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
 360 };
 361
 362 static void piix3_class_init(ObjectClass *klass, void *data)
 363 {
 364     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 365
 366     k->config_write = piix3_write_config;
 367     k->realize = piix3_realize;
 368 }
 369
 370 static const TypeInfo piix3_info = {
 371     .name          = TYPE_PIIX3_DEVICE,
 372     .parent        = TYPE_PIIX3_PCI_DEVICE,
 373     .class_init    = piix3_class_init,
 374 };
 375
 376 static void piix3_xen_realize(PCIDevice *dev, Error **errp)
 377 {
 378     ERRP_GUARD();
 379     PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 380     PCIBus *pci_bus = pci_get_bus(dev);
 381
 382     pci_piix3_realize(dev, errp);
 383     if (*errp) {
 384         return;
 385     }
 386
 387     /*
 388      * Xen supports additional interrupt routes from the PCI devices to
 389      * the IOAPIC: the four pins of each PCI device on the bus are also
 390      * connected to the IOAPIC directly.
 391      * These additional routes can be discovered through ACPI.
 392      */
 393     pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 394                  piix3, XEN_PIIX_NUM_PIRQS);
 395 };
 396
 397 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 398 {
 399     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 400
 401     k->config_write = piix3_write_config_xen;
 402     k->realize = piix3_xen_realize;
 403 };
 404
 405 static const TypeInfo piix3_xen_info = {
 406     .name          = TYPE_PIIX3_XEN_DEVICE,
 407     .parent        = TYPE_PIIX3_PCI_DEVICE,
 408     .class_init    = piix3_xen_class_init,
 409 };
 410
 411 static void piix3_register_types(void)
 412 {
 413     type_register_static(&piix3_pci_type_info);
 414     type_register_static(&piix3_info);
 415     type_register_static(&piix3_xen_info);
 416 }
 417
 418 type_init(piix3_register_types)
 419
 420 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
 421 {
 422     PIIX3State *piix3;
 423     PCIDevice *pci_dev;
 424     const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE
 425                                      : TYPE_PIIX3_DEVICE;
 426
 427     pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type);
 428     piix3 = PIIX3_PCI_DEVICE(pci_dev);
 429     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
 430
 431     return piix3;
 432 }