4 * Copyright (c) 2019 Yoshinori Sato
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/qemu-print.h"
21 #include "qapi/error.h"
23 #include "migration/vmstate.h"
24 #include "exec/exec-all.h"
25 #include "hw/loader.h"
26 #include "fpu/softfloat.h"
27 #include "tcg/debug-assert.h"
29 static void rx_cpu_set_pc(CPUState
*cs
, vaddr value
)
31 RXCPU
*cpu
= RX_CPU(cs
);
36 static vaddr
rx_cpu_get_pc(CPUState
*cs
)
38 RXCPU
*cpu
= RX_CPU(cs
);
43 static void rx_cpu_synchronize_from_tb(CPUState
*cs
,
44 const TranslationBlock
*tb
)
46 RXCPU
*cpu
= RX_CPU(cs
);
48 tcg_debug_assert(!(cs
->tcg_cflags
& CF_PCREL
));
52 static void rx_restore_state_to_opc(CPUState
*cs
,
53 const TranslationBlock
*tb
,
56 RXCPU
*cpu
= RX_CPU(cs
);
58 cpu
->env
.pc
= data
[0];
61 static bool rx_cpu_has_work(CPUState
*cs
)
63 return cs
->interrupt_request
&
64 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_FIR
);
67 static int riscv_cpu_mmu_index(CPUState
*cs
, bool ifunc
)
72 static void rx_cpu_reset_hold(Object
*obj
)
74 RXCPU
*cpu
= RX_CPU(obj
);
75 RXCPUClass
*rcc
= RX_CPU_GET_CLASS(cpu
);
76 CPURXState
*env
= &cpu
->env
;
79 if (rcc
->parent_phases
.hold
) {
80 rcc
->parent_phases
.hold(obj
);
83 memset(env
, 0, offsetof(CPURXState
, end_reset_fields
));
85 resetvec
= rom_ptr(0xfffffffc, 4);
87 /* In the case of kernel, it is ignored because it is not set. */
88 env
->pc
= ldl_p(resetvec
);
90 rx_cpu_unpack_psw(env
, 0, 1);
91 env
->regs
[0] = env
->isp
= env
->usp
= 0;
93 set_flush_to_zero(1, &env
->fp_status
);
94 set_flush_inputs_to_zero(1, &env
->fp_status
);
97 static ObjectClass
*rx_cpu_class_by_name(const char *cpu_model
)
102 oc
= object_class_by_name(cpu_model
);
103 if (oc
!= NULL
&& object_class_dynamic_cast(oc
, TYPE_RX_CPU
) != NULL
) {
106 typename
= g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model
);
107 oc
= object_class_by_name(typename
);
113 static void rx_cpu_realize(DeviceState
*dev
, Error
**errp
)
115 CPUState
*cs
= CPU(dev
);
116 RXCPUClass
*rcc
= RX_CPU_GET_CLASS(dev
);
117 Error
*local_err
= NULL
;
119 cpu_exec_realizefn(cs
, &local_err
);
120 if (local_err
!= NULL
) {
121 error_propagate(errp
, local_err
);
128 rcc
->parent_realize(dev
, errp
);
131 static void rx_cpu_set_irq(void *opaque
, int no
, int request
)
134 CPUState
*cs
= CPU(cpu
);
135 int irq
= request
& 0xff;
137 static const int mask
[] = {
138 [RX_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
139 [RX_CPU_FIR
] = CPU_INTERRUPT_FIR
,
142 cpu
->env
.req_irq
= irq
;
143 cpu
->env
.req_ipl
= (request
>> 8) & 0x0f;
144 cpu_interrupt(cs
, mask
[no
]);
146 cpu_reset_interrupt(cs
, mask
[no
]);
150 static void rx_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
152 info
->mach
= bfd_mach_rx
;
153 info
->print_insn
= print_insn_rx
;
156 static bool rx_cpu_tlb_fill(CPUState
*cs
, vaddr addr
, int size
,
157 MMUAccessType access_type
, int mmu_idx
,
158 bool probe
, uintptr_t retaddr
)
160 uint32_t address
, physical
, prot
;
163 address
= physical
= addr
& TARGET_PAGE_MASK
;
164 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
165 tlb_set_page(cs
, address
, physical
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
169 static void rx_cpu_init(Object
*obj
)
171 RXCPU
*cpu
= RX_CPU(obj
);
173 qdev_init_gpio_in(DEVICE(cpu
), rx_cpu_set_irq
, 2);
176 #ifndef CONFIG_USER_ONLY
177 #include "hw/core/sysemu-cpu-ops.h"
179 static const struct SysemuCPUOps rx_sysemu_ops
= {
180 .get_phys_page_debug
= rx_cpu_get_phys_page_debug
,
184 #include "hw/core/tcg-cpu-ops.h"
186 static const TCGCPUOps rx_tcg_ops
= {
187 .initialize
= rx_translate_init
,
188 .synchronize_from_tb
= rx_cpu_synchronize_from_tb
,
189 .restore_state_to_opc
= rx_restore_state_to_opc
,
190 .tlb_fill
= rx_cpu_tlb_fill
,
192 #ifndef CONFIG_USER_ONLY
193 .cpu_exec_interrupt
= rx_cpu_exec_interrupt
,
194 .do_interrupt
= rx_cpu_do_interrupt
,
195 #endif /* !CONFIG_USER_ONLY */
198 static void rx_cpu_class_init(ObjectClass
*klass
, void *data
)
200 DeviceClass
*dc
= DEVICE_CLASS(klass
);
201 CPUClass
*cc
= CPU_CLASS(klass
);
202 RXCPUClass
*rcc
= RX_CPU_CLASS(klass
);
203 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
205 device_class_set_parent_realize(dc
, rx_cpu_realize
,
206 &rcc
->parent_realize
);
207 resettable_class_set_parent_phases(rc
, NULL
, rx_cpu_reset_hold
, NULL
,
208 &rcc
->parent_phases
);
210 cc
->class_by_name
= rx_cpu_class_by_name
;
211 cc
->has_work
= rx_cpu_has_work
;
212 cc
->mmu_index
= riscv_cpu_mmu_index
;
213 cc
->dump_state
= rx_cpu_dump_state
;
214 cc
->set_pc
= rx_cpu_set_pc
;
215 cc
->get_pc
= rx_cpu_get_pc
;
217 #ifndef CONFIG_USER_ONLY
218 cc
->sysemu_ops
= &rx_sysemu_ops
;
220 cc
->gdb_read_register
= rx_cpu_gdb_read_register
;
221 cc
->gdb_write_register
= rx_cpu_gdb_write_register
;
222 cc
->disas_set_info
= rx_cpu_disas_set_info
;
224 cc
->gdb_core_xml_file
= "rx-core.xml";
225 cc
->tcg_ops
= &rx_tcg_ops
;
228 static const TypeInfo rx_cpu_info
= {
231 .instance_size
= sizeof(RXCPU
),
232 .instance_align
= __alignof(RXCPU
),
233 .instance_init
= rx_cpu_init
,
235 .class_size
= sizeof(RXCPUClass
),
236 .class_init
= rx_cpu_class_init
,
239 static const TypeInfo rx62n_rx_cpu_info
= {
240 .name
= TYPE_RX62N_CPU
,
241 .parent
= TYPE_RX_CPU
,
244 static void rx_cpu_register_types(void)
246 type_register_static(&rx_cpu_info
);
247 type_register_static(&rx62n_rx_cpu_info
);
250 type_init(rx_cpu_register_types
)