2 * QEMU PowerPC 440 embedded processors emulation
4 * Copyright (c) 2012 François Revol
5 * Copyright (c) 2016-2019 BALATON Zoltan
7 * This work is licensed under the GNU GPL license version 2 or later.
11 #include "qemu/osdep.h"
12 #include "qemu/units.h"
13 #include "qapi/error.h"
16 #include "hw/ppc/ppc4xx.h"
17 #include "hw/qdev-properties.h"
18 #include "hw/pci/pci.h"
19 #include "sysemu/reset.h"
23 /*****************************************************************************/
24 /* L2 Cache as SRAM */
27 DCR_L2CACHE_BASE
= 0x30,
28 DCR_L2CACHE_CFG
= DCR_L2CACHE_BASE
,
36 DCR_L2CACHE_END
= DCR_L2CACHE_SNP1
,
39 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
41 DCR_ISRAM0_BASE
= 0x20,
42 DCR_ISRAM0_SB0CR
= DCR_ISRAM0_BASE
,
53 DCR_ISRAM0_END
= DCR_ISRAM0_DPC
57 DCR_ISRAM1_BASE
= 0xb0,
58 DCR_ISRAM1_SB0CR
= DCR_ISRAM1_BASE
,
60 DCR_ISRAM1_BEAR
= DCR_ISRAM1_BASE
+ 0x04,
67 DCR_ISRAM1_END
= DCR_ISRAM1_DPC
70 typedef struct ppc4xx_l2sram_t
{
77 static void l2sram_update_mappings(ppc4xx_l2sram_t
*l2sram
,
78 uint32_t isarc
, uint32_t isacntl
,
79 uint32_t dsarc
, uint32_t dsacntl
)
81 if (l2sram
->isarc
!= isarc
||
82 (l2sram
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
83 if (l2sram
->isacntl
& 0x80000000) {
84 /* Unmap previously assigned memory region */
85 memory_region_del_subregion(get_system_memory(),
88 if (isacntl
& 0x80000000) {
89 /* Map new instruction memory region */
90 memory_region_add_subregion(get_system_memory(), isarc
,
94 if (l2sram
->dsarc
!= dsarc
||
95 (l2sram
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
96 if (l2sram
->dsacntl
& 0x80000000) {
97 /* Beware not to unmap the region we just mapped */
98 if (!(isacntl
& 0x80000000) || l2sram
->dsarc
!= isarc
) {
99 /* Unmap previously assigned memory region */
100 memory_region_del_subregion(get_system_memory(),
104 if (dsacntl
& 0x80000000) {
105 /* Beware not to remap the region we just mapped */
106 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
107 /* Map new data memory region */
108 memory_region_add_subregion(get_system_memory(), dsarc
,
116 static uint32_t dcr_read_l2sram(void *opaque
, int dcrn
)
118 ppc4xx_l2sram_t
*l2sram
= opaque
;
122 case DCR_L2CACHE_CFG
:
123 case DCR_L2CACHE_CMD
:
124 case DCR_L2CACHE_ADDR
:
125 case DCR_L2CACHE_DATA
:
126 case DCR_L2CACHE_STAT
:
127 case DCR_L2CACHE_CVER
:
128 case DCR_L2CACHE_SNP0
:
129 case DCR_L2CACHE_SNP1
:
130 ret
= l2sram
->l2cache
[dcrn
- DCR_L2CACHE_BASE
];
133 case DCR_ISRAM0_SB0CR
:
134 case DCR_ISRAM0_SB1CR
:
135 case DCR_ISRAM0_SB2CR
:
136 case DCR_ISRAM0_SB3CR
:
137 case DCR_ISRAM0_BEAR
:
138 case DCR_ISRAM0_BESR0
:
139 case DCR_ISRAM0_BESR1
:
140 case DCR_ISRAM0_PMEG
:
142 case DCR_ISRAM0_REVID
:
144 ret
= l2sram
->isram0
[dcrn
- DCR_ISRAM0_BASE
];
154 static void dcr_write_l2sram(void *opaque
, int dcrn
, uint32_t val
)
156 /*ppc4xx_l2sram_t *l2sram = opaque;*/
157 /* FIXME: Actually handle L2 cache mapping */
160 case DCR_L2CACHE_CFG
:
161 case DCR_L2CACHE_CMD
:
162 case DCR_L2CACHE_ADDR
:
163 case DCR_L2CACHE_DATA
:
164 case DCR_L2CACHE_STAT
:
165 case DCR_L2CACHE_CVER
:
166 case DCR_L2CACHE_SNP0
:
167 case DCR_L2CACHE_SNP1
:
168 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
171 case DCR_ISRAM0_SB0CR
:
172 case DCR_ISRAM0_SB1CR
:
173 case DCR_ISRAM0_SB2CR
:
174 case DCR_ISRAM0_SB3CR
:
175 case DCR_ISRAM0_BEAR
:
176 case DCR_ISRAM0_BESR0
:
177 case DCR_ISRAM0_BESR1
:
178 case DCR_ISRAM0_PMEG
:
180 case DCR_ISRAM0_REVID
:
182 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
185 case DCR_ISRAM1_SB0CR
:
186 case DCR_ISRAM1_BEAR
:
187 case DCR_ISRAM1_BESR0
:
188 case DCR_ISRAM1_BESR1
:
189 case DCR_ISRAM1_PMEG
:
191 case DCR_ISRAM1_REVID
:
193 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
196 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
199 static void l2sram_reset(void *opaque
)
201 ppc4xx_l2sram_t
*l2sram
= opaque
;
203 memset(l2sram
->l2cache
, 0, sizeof(l2sram
->l2cache
));
204 l2sram
->l2cache
[DCR_L2CACHE_STAT
- DCR_L2CACHE_BASE
] = 0x80000000;
205 memset(l2sram
->isram0
, 0, sizeof(l2sram
->isram0
));
206 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
209 void ppc4xx_l2sram_init(CPUPPCState
*env
)
211 ppc4xx_l2sram_t
*l2sram
;
213 l2sram
= g_malloc0(sizeof(*l2sram
));
214 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
215 memory_region_init_ram(&l2sram
->bank
[0], NULL
, "ppc4xx.l2sram_bank0",
216 64 * KiB
, &error_abort
);
217 memory_region_init_ram(&l2sram
->bank
[1], NULL
, "ppc4xx.l2sram_bank1",
218 64 * KiB
, &error_abort
);
219 memory_region_init_ram(&l2sram
->bank
[2], NULL
, "ppc4xx.l2sram_bank2",
220 64 * KiB
, &error_abort
);
221 memory_region_init_ram(&l2sram
->bank
[3], NULL
, "ppc4xx.l2sram_bank3",
222 64 * KiB
, &error_abort
);
223 qemu_register_reset(&l2sram_reset
, l2sram
);
224 ppc_dcr_register(env
, DCR_L2CACHE_CFG
,
225 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
226 ppc_dcr_register(env
, DCR_L2CACHE_CMD
,
227 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
228 ppc_dcr_register(env
, DCR_L2CACHE_ADDR
,
229 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
230 ppc_dcr_register(env
, DCR_L2CACHE_DATA
,
231 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
232 ppc_dcr_register(env
, DCR_L2CACHE_STAT
,
233 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
234 ppc_dcr_register(env
, DCR_L2CACHE_CVER
,
235 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
236 ppc_dcr_register(env
, DCR_L2CACHE_SNP0
,
237 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
238 ppc_dcr_register(env
, DCR_L2CACHE_SNP1
,
239 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
241 ppc_dcr_register(env
, DCR_ISRAM0_SB0CR
,
242 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
243 ppc_dcr_register(env
, DCR_ISRAM0_SB1CR
,
244 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
245 ppc_dcr_register(env
, DCR_ISRAM0_SB2CR
,
246 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
247 ppc_dcr_register(env
, DCR_ISRAM0_SB3CR
,
248 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
249 ppc_dcr_register(env
, DCR_ISRAM0_PMEG
,
250 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
251 ppc_dcr_register(env
, DCR_ISRAM0_DPC
,
252 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
254 ppc_dcr_register(env
, DCR_ISRAM1_SB0CR
,
255 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
256 ppc_dcr_register(env
, DCR_ISRAM1_PMEG
,
257 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
258 ppc_dcr_register(env
, DCR_ISRAM1_DPC
,
259 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
262 /*****************************************************************************/
263 /* Clocking Power on Reset */
275 typedef struct ppc4xx_cpr_t
{
279 static uint32_t dcr_read_cpr(void *opaque
, int dcrn
)
281 ppc4xx_cpr_t
*cpr
= opaque
;
291 ret
= (0xb5 << 24) | (1 << 16) | (9 << 8);
314 static void dcr_write_cpr(void *opaque
, int dcrn
, uint32_t val
)
316 ppc4xx_cpr_t
*cpr
= opaque
;
329 static void ppc4xx_cpr_reset(void *opaque
)
331 ppc4xx_cpr_t
*cpr
= opaque
;
336 void ppc4xx_cpr_init(CPUPPCState
*env
)
340 cpr
= g_malloc0(sizeof(*cpr
));
341 ppc_dcr_register(env
, CPR0_CFGADDR
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
342 ppc_dcr_register(env
, CPR0_CFGDATA
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
343 qemu_register_reset(ppc4xx_cpr_reset
, cpr
);
346 /*****************************************************************************/
348 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t
;
349 struct ppc4xx_sdr_t
{
354 SDR0_CFGADDR
= 0x00e,
370 PESDR0_RSTSTA
= 0x310,
374 PESDR1_RSTSTA
= 0x365,
377 static uint32_t dcr_read_sdr(void *opaque
, int dcrn
)
379 ppc4xx_sdr_t
*sdr
= opaque
;
389 ret
= (0xb5 << 8) | (1 << 4) | 9;
392 ret
= (5 << 29) | (2 << 26) | (1 << 24);
395 ret
= 1 << 20; /* No Security/Kasumi support */
398 ret
= SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1
;
402 ret
= (1 << 24) | (1 << 16);
406 ret
= (1 << 16) | (1 << 12);
427 static void dcr_write_sdr(void *opaque
, int dcrn
, uint32_t val
)
429 ppc4xx_sdr_t
*sdr
= opaque
;
437 case 0x00: /* B0CR */
448 static void sdr_reset(void *opaque
)
450 ppc4xx_sdr_t
*sdr
= opaque
;
455 void ppc4xx_sdr_init(CPUPPCState
*env
)
459 sdr
= g_malloc0(sizeof(*sdr
));
460 qemu_register_reset(&sdr_reset
, sdr
);
461 ppc_dcr_register(env
, SDR0_CFGADDR
,
462 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
463 ppc_dcr_register(env
, SDR0_CFGDATA
,
464 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
465 ppc_dcr_register(env
, SDR0_102
,
466 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
467 ppc_dcr_register(env
, SDR0_103
,
468 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
469 ppc_dcr_register(env
, SDR0_128
,
470 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
471 ppc_dcr_register(env
, SDR0_USB0
,
472 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
475 /*****************************************************************************/
476 /* PLB to AHB bridge */
482 typedef struct ppc4xx_ahb_t
{
487 static uint32_t dcr_read_ahb(void *opaque
, int dcrn
)
489 ppc4xx_ahb_t
*ahb
= opaque
;
506 static void dcr_write_ahb(void *opaque
, int dcrn
, uint32_t val
)
508 ppc4xx_ahb_t
*ahb
= opaque
;
520 static void ppc4xx_ahb_reset(void *opaque
)
522 ppc4xx_ahb_t
*ahb
= opaque
;
529 void ppc4xx_ahb_init(CPUPPCState
*env
)
533 ahb
= g_malloc0(sizeof(*ahb
));
534 ppc_dcr_register(env
, AHB_TOP
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
535 ppc_dcr_register(env
, AHB_BOT
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
536 qemu_register_reset(ppc4xx_ahb_reset
, ahb
);
539 /*****************************************************************************/
542 #define DMA0_CR_CE (1 << 31)
543 #define DMA0_CR_PW (1 << 26 | 1 << 25)
544 #define DMA0_CR_DAI (1 << 24)
545 #define DMA0_CR_SAI (1 << 23)
546 #define DMA0_CR_DEC (1 << 2)
578 static uint32_t dcr_read_dma(void *opaque
, int dcrn
)
580 PPC4xxDmaState
*dma
= opaque
;
582 int addr
= dcrn
- dma
->base
;
589 val
= dma
->ch
[chnl
].cr
;
592 val
= dma
->ch
[chnl
].ct
;
595 val
= dma
->ch
[chnl
].sa
>> 32;
598 val
= dma
->ch
[chnl
].sa
;
601 val
= dma
->ch
[chnl
].da
>> 32;
604 val
= dma
->ch
[chnl
].da
;
607 val
= dma
->ch
[chnl
].sg
>> 32;
610 val
= dma
->ch
[chnl
].sg
;
618 qemu_log_mask(LOG_UNIMP
, "%s: unimplemented register %x (%d, %x)\n",
619 __func__
, dcrn
, chnl
, addr
);
625 static void dcr_write_dma(void *opaque
, int dcrn
, uint32_t val
)
627 PPC4xxDmaState
*dma
= opaque
;
628 int addr
= dcrn
- dma
->base
;
635 dma
->ch
[chnl
].cr
= val
;
636 if (val
& DMA0_CR_CE
) {
637 int count
= dma
->ch
[chnl
].ct
& 0xffff;
640 int width
, i
, sidx
, didx
;
641 uint8_t *rptr
, *wptr
;
646 width
= 1 << ((val
& DMA0_CR_PW
) >> 25);
647 xferlen
= count
* width
;
648 wlen
= rlen
= xferlen
;
649 rptr
= cpu_physical_memory_map(dma
->ch
[chnl
].sa
, &rlen
,
651 wptr
= cpu_physical_memory_map(dma
->ch
[chnl
].da
, &wlen
,
653 if (rptr
&& rlen
== xferlen
&& wptr
&& wlen
== xferlen
) {
654 if (!(val
& DMA0_CR_DEC
) &&
655 val
& DMA0_CR_SAI
&& val
& DMA0_CR_DAI
) {
656 /* optimise common case */
657 memmove(wptr
, rptr
, count
* width
);
658 sidx
= didx
= count
* width
;
660 /* do it the slow way */
661 for (sidx
= didx
= i
= 0; i
< count
; i
++) {
662 uint64_t v
= ldn_le_p(rptr
+ sidx
, width
);
663 stn_le_p(wptr
+ didx
, width
, v
);
664 if (val
& DMA0_CR_SAI
) {
667 if (val
& DMA0_CR_DAI
) {
674 cpu_physical_memory_unmap(wptr
, wlen
, 1, didx
);
677 cpu_physical_memory_unmap(rptr
, rlen
, 0, sidx
);
683 dma
->ch
[chnl
].ct
= val
;
686 dma
->ch
[chnl
].sa
&= 0xffffffffULL
;
687 dma
->ch
[chnl
].sa
|= (uint64_t)val
<< 32;
690 dma
->ch
[chnl
].sa
&= 0xffffffff00000000ULL
;
691 dma
->ch
[chnl
].sa
|= val
;
694 dma
->ch
[chnl
].da
&= 0xffffffffULL
;
695 dma
->ch
[chnl
].da
|= (uint64_t)val
<< 32;
698 dma
->ch
[chnl
].da
&= 0xffffffff00000000ULL
;
699 dma
->ch
[chnl
].da
|= val
;
702 dma
->ch
[chnl
].sg
&= 0xffffffffULL
;
703 dma
->ch
[chnl
].sg
|= (uint64_t)val
<< 32;
706 dma
->ch
[chnl
].sg
&= 0xffffffff00000000ULL
;
707 dma
->ch
[chnl
].sg
|= val
;
715 qemu_log_mask(LOG_UNIMP
, "%s: unimplemented register %x (%d, %x)\n",
716 __func__
, dcrn
, chnl
, addr
);
720 static void ppc4xx_dma_reset(void *opaque
)
722 PPC4xxDmaState
*dma
= opaque
;
723 int dma_base
= dma
->base
;
725 memset(dma
, 0, sizeof(*dma
));
726 dma
->base
= dma_base
;
729 void ppc4xx_dma_init(CPUPPCState
*env
, int dcr_base
)
734 dma
= g_malloc0(sizeof(*dma
));
735 dma
->base
= dcr_base
;
736 qemu_register_reset(&ppc4xx_dma_reset
, dma
);
737 for (i
= 0; i
< 4; i
++) {
738 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_CR
,
739 dma
, &dcr_read_dma
, &dcr_write_dma
);
740 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_CT
,
741 dma
, &dcr_read_dma
, &dcr_write_dma
);
742 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SAH
,
743 dma
, &dcr_read_dma
, &dcr_write_dma
);
744 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SAL
,
745 dma
, &dcr_read_dma
, &dcr_write_dma
);
746 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_DAH
,
747 dma
, &dcr_read_dma
, &dcr_write_dma
);
748 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_DAL
,
749 dma
, &dcr_read_dma
, &dcr_write_dma
);
750 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SGH
,
751 dma
, &dcr_read_dma
, &dcr_write_dma
);
752 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SGL
,
753 dma
, &dcr_read_dma
, &dcr_write_dma
);
755 ppc_dcr_register(env
, dcr_base
+ DMA0_SR
,
756 dma
, &dcr_read_dma
, &dcr_write_dma
);
757 ppc_dcr_register(env
, dcr_base
+ DMA0_SGC
,
758 dma
, &dcr_read_dma
, &dcr_write_dma
);
759 ppc_dcr_register(env
, dcr_base
+ DMA0_SLP
,
760 dma
, &dcr_read_dma
, &dcr_write_dma
);
761 ppc_dcr_register(env
, dcr_base
+ DMA0_POL
,
762 dma
, &dcr_read_dma
, &dcr_write_dma
);
765 /*****************************************************************************/
766 /* PCI Express controller */
768 * FIXME: This is not complete and does not work, only implemented partially
769 * to allow firmware and guests to find an empty bus. Cards should use PCI.
771 #include "hw/pci/pcie_host.h"
773 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState
, PPC460EX_PCIE_HOST
)
775 struct PPC460EXPCIEState
{
776 PCIExpressHost parent_obj
;
827 static uint32_t dcr_read_pcie(void *opaque
, int dcrn
)
829 PPC460EXPCIEState
*s
= opaque
;
832 switch (dcrn
- s
->dcrn_base
) {
834 ret
= s
->cfg_base
>> 32;
843 ret
= s
->msg_base
>> 32;
852 ret
= s
->omr1_base
>> 32;
858 ret
= s
->omr1_mask
>> 32;
864 ret
= s
->omr2_base
>> 32;
870 ret
= s
->omr2_mask
>> 32;
876 ret
= s
->omr3_base
>> 32;
882 ret
= s
->omr3_mask
>> 32;
888 ret
= s
->reg_base
>> 32;
907 static void dcr_write_pcie(void *opaque
, int dcrn
, uint32_t val
)
909 PPC460EXPCIEState
*s
= opaque
;
912 switch (dcrn
- s
->dcrn_base
) {
914 s
->cfg_base
= ((uint64_t)val
<< 32) | (s
->cfg_base
& 0xffffffff);
917 s
->cfg_base
= (s
->cfg_base
& 0xffffffff00000000ULL
) | val
;
921 size
= ~(val
& 0xfffffffe) + 1;
923 * Firmware sets this register to E0000001. Why we are not sure,
924 * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
927 if (size
> PCIE_MMCFG_SIZE_MAX
) {
928 size
= PCIE_MMCFG_SIZE_MAX
;
930 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s
), val
& 1, s
->cfg_base
, size
);
933 s
->msg_base
= ((uint64_t)val
<< 32) | (s
->msg_base
& 0xffffffff);
936 s
->msg_base
= (s
->msg_base
& 0xffffffff00000000ULL
) | val
;
942 s
->omr1_base
= ((uint64_t)val
<< 32) | (s
->omr1_base
& 0xffffffff);
945 s
->omr1_base
= (s
->omr1_base
& 0xffffffff00000000ULL
) | val
;
948 s
->omr1_mask
= ((uint64_t)val
<< 32) | (s
->omr1_mask
& 0xffffffff);
951 s
->omr1_mask
= (s
->omr1_mask
& 0xffffffff00000000ULL
) | val
;
954 s
->omr2_base
= ((uint64_t)val
<< 32) | (s
->omr2_base
& 0xffffffff);
957 s
->omr2_base
= (s
->omr2_base
& 0xffffffff00000000ULL
) | val
;
960 s
->omr2_mask
= ((uint64_t)val
<< 32) | (s
->omr2_mask
& 0xffffffff);
963 s
->omr2_mask
= (s
->omr2_mask
& 0xffffffff00000000ULL
) | val
;
966 s
->omr3_base
= ((uint64_t)val
<< 32) | (s
->omr3_base
& 0xffffffff);
969 s
->omr3_base
= (s
->omr3_base
& 0xffffffff00000000ULL
) | val
;
972 s
->omr3_mask
= ((uint64_t)val
<< 32) | (s
->omr3_mask
& 0xffffffff);
975 s
->omr3_mask
= (s
->omr3_mask
& 0xffffffff00000000ULL
) | val
;
978 s
->reg_base
= ((uint64_t)val
<< 32) | (s
->reg_base
& 0xffffffff);
981 s
->reg_base
= (s
->reg_base
& 0xffffffff00000000ULL
) | val
;
985 /* FIXME: how is size encoded? */
986 size
= (val
== 0x7001 ? 4096 : ~(val
& 0xfffffffe) + 1);
997 static void ppc460ex_set_irq(void *opaque
, int irq_num
, int level
)
999 PPC460EXPCIEState
*s
= opaque
;
1000 qemu_set_irq(s
->irq
[irq_num
], level
);
1003 #define PPC440_PCIE_DCR(s, dcrn) \
1004 ppc_dcr_register(&(s)->cpu->env, (s)->dcrn_base + (dcrn), (s), \
1005 &dcr_read_pcie, &dcr_write_pcie)
1008 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState
*s
)
1010 PPC440_PCIE_DCR(s
, PEGPL_CFGBAH
);
1011 PPC440_PCIE_DCR(s
, PEGPL_CFGBAL
);
1012 PPC440_PCIE_DCR(s
, PEGPL_CFGMSK
);
1013 PPC440_PCIE_DCR(s
, PEGPL_MSGBAH
);
1014 PPC440_PCIE_DCR(s
, PEGPL_MSGBAL
);
1015 PPC440_PCIE_DCR(s
, PEGPL_MSGMSK
);
1016 PPC440_PCIE_DCR(s
, PEGPL_OMR1BAH
);
1017 PPC440_PCIE_DCR(s
, PEGPL_OMR1BAL
);
1018 PPC440_PCIE_DCR(s
, PEGPL_OMR1MSKH
);
1019 PPC440_PCIE_DCR(s
, PEGPL_OMR1MSKL
);
1020 PPC440_PCIE_DCR(s
, PEGPL_OMR2BAH
);
1021 PPC440_PCIE_DCR(s
, PEGPL_OMR2BAL
);
1022 PPC440_PCIE_DCR(s
, PEGPL_OMR2MSKH
);
1023 PPC440_PCIE_DCR(s
, PEGPL_OMR2MSKL
);
1024 PPC440_PCIE_DCR(s
, PEGPL_OMR3BAH
);
1025 PPC440_PCIE_DCR(s
, PEGPL_OMR3BAL
);
1026 PPC440_PCIE_DCR(s
, PEGPL_OMR3MSKH
);
1027 PPC440_PCIE_DCR(s
, PEGPL_OMR3MSKL
);
1028 PPC440_PCIE_DCR(s
, PEGPL_REGBAH
);
1029 PPC440_PCIE_DCR(s
, PEGPL_REGBAL
);
1030 PPC440_PCIE_DCR(s
, PEGPL_REGMSK
);
1031 PPC440_PCIE_DCR(s
, PEGPL_SPECIAL
);
1032 PPC440_PCIE_DCR(s
, PEGPL_CFG
);
1035 static void ppc460ex_pcie_realize(DeviceState
*dev
, Error
**errp
)
1037 PPC460EXPCIEState
*s
= PPC460EX_PCIE_HOST(dev
);
1038 PCIHostState
*pci
= PCI_HOST_BRIDGE(dev
);
1043 error_setg(errp
, "cpu link property must be set");
1046 if (s
->num
< 0 || s
->dcrn_base
< 0) {
1047 error_setg(errp
, "busnum and dcrn-base properties must be set");
1050 snprintf(buf
, sizeof(buf
), "pcie%d-mem", s
->num
);
1051 memory_region_init(&s
->busmem
, OBJECT(s
), buf
, UINT64_MAX
);
1052 snprintf(buf
, sizeof(buf
), "pcie%d-io", s
->num
);
1053 memory_region_init(&s
->iomem
, OBJECT(s
), buf
, 64 * KiB
);
1054 for (i
= 0; i
< 4; i
++) {
1055 sysbus_init_irq(SYS_BUS_DEVICE(dev
), &s
->irq
[i
]);
1057 snprintf(buf
, sizeof(buf
), "pcie.%d", s
->num
);
1058 pci
->bus
= pci_register_root_bus(DEVICE(s
), buf
, ppc460ex_set_irq
,
1059 pci_swizzle_map_irq_fn
, s
, &s
->busmem
,
1060 &s
->iomem
, 0, 4, TYPE_PCIE_BUS
);
1061 ppc460ex_pcie_register_dcrs(s
);
1064 static Property ppc460ex_pcie_props
[] = {
1065 DEFINE_PROP_INT32("busnum", PPC460EXPCIEState
, num
, -1),
1066 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState
, dcrn_base
, -1),
1067 DEFINE_PROP_LINK("cpu", PPC460EXPCIEState
, cpu
, TYPE_POWERPC_CPU
,
1069 DEFINE_PROP_END_OF_LIST(),
1072 static void ppc460ex_pcie_class_init(ObjectClass
*klass
, void *data
)
1074 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1076 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1077 dc
->realize
= ppc460ex_pcie_realize
;
1078 device_class_set_props(dc
, ppc460ex_pcie_props
);
1079 dc
->hotpluggable
= false;
1082 static const TypeInfo ppc460ex_pcie_host_info
= {
1083 .name
= TYPE_PPC460EX_PCIE_HOST
,
1084 .parent
= TYPE_PCIE_HOST_BRIDGE
,
1085 .instance_size
= sizeof(PPC460EXPCIEState
),
1086 .class_init
= ppc460ex_pcie_class_init
,
1089 static void ppc460ex_pcie_register(void)
1091 type_register_static(&ppc460ex_pcie_host_info
);
1094 type_init(ppc460ex_pcie_register
)