igb: respect VMVIR and VMOLR for VLAN
[qemu/armbru.git] / tcg / aarch64 / tcg-target-con-set.h
blobd6c68668789c2b9de6b7d5171f9dd55cc1c1b7d0
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Define AArch64 target-specific constraint sets.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
9 * Each operand should be a sequence of constraint letters as defined by
10 * tcg-target-con-str.h; the constraint combination is inclusive or.
12 C_O0_I1(r)
13 C_O0_I2(lZ, l)
14 C_O0_I2(r, rA)
15 C_O0_I2(rZ, r)
16 C_O0_I2(w, r)
17 C_O1_I1(r, l)
18 C_O1_I1(r, r)
19 C_O1_I1(w, r)
20 C_O1_I1(w, w)
21 C_O1_I1(w, wr)
22 C_O1_I2(r, 0, rZ)
23 C_O1_I2(r, r, r)
24 C_O1_I2(r, r, rA)
25 C_O1_I2(r, r, rAL)
26 C_O1_I2(r, r, ri)
27 C_O1_I2(r, r, rL)
28 C_O1_I2(r, rZ, rZ)
29 C_O1_I2(w, 0, w)
30 C_O1_I2(w, w, w)
31 C_O1_I2(w, w, wN)
32 C_O1_I2(w, w, wO)
33 C_O1_I2(w, w, wZ)
34 C_O1_I3(w, w, w, w)
35 C_O1_I4(r, r, rA, rZ, rZ)
36 C_O2_I4(r, r, rZ, rZ, rA, rMZ)