hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  * Copyright (c) 2017 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/rtc/m48t59.h"
  28 #include "hw/char/serial.h"
  29 #include "hw/block/fdc.h"
  30 #include "net/net.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/ppc/ppc.h"
  35 #include "hw/boards.h"
  36 #include "qapi/error.h"
  37 #include "qemu/error-report.h"
  38 #include "qemu/log.h"
  39 #include "hw/loader.h"
  40 #include "hw/rtc/mc146818rtc.h"
  41 #include "hw/isa/pc87312.h"
  42 #include "hw/qdev-properties.h"
  43 #include "sysemu/kvm.h"
  44 #include "sysemu/reset.h"
  45 #include "trace.h"
  46 #include "elf.h"
  47 #include "qemu/units.h"
  48
  49 /* SMP is not enabled, for now */
  50 #define MAX_CPUS 1
  51
  52 #define CFG_ADDR 0xf0000510
  53
  54 #define KERNEL_LOAD_ADDR 0x01000000
  55 #define INITRD_LOAD_ADDR 0x01800000
  56
  57 #define NVRAM_SIZE        0x2000
  58
  59 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  60                             Error **errp)
  61 {
  62     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  63 }
  64
  65 static void ppc_prep_reset(void *opaque)
  66 {
  67     PowerPCCPU *cpu = opaque;
  68
  69     cpu_reset(CPU(cpu));
  70     cpu_ppc_tb_reset(&cpu->env);
  71 }
  72
  73
  74 /*****************************************************************************/
  75 /* NVRAM helpers */
  76 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
  77 {
  78     NvramClass *k = NVRAM_GET_CLASS(nvram);
  79     return (k->read)(nvram, addr);
  80 }
  81
  82 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
  83 {
  84     NvramClass *k = NVRAM_GET_CLASS(nvram);
  85     (k->write)(nvram, addr, val);
  86 }
  87
  88 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
  89 {
  90     nvram_write(nvram, addr, value);
  91 }
  92
  93 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
  94 {
  95     return nvram_read(nvram, addr);
  96 }
  97
  98 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
  99 {
 100     nvram_write(nvram, addr, value >> 8);
 101     nvram_write(nvram, addr + 1, value & 0xFF);
 102 }
 103
 104 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 105 {
 106     uint16_t tmp;
 107
 108     tmp = nvram_read(nvram, addr) << 8;
 109     tmp |= nvram_read(nvram, addr + 1);
 110
 111     return tmp;
 112 }
 113
 114 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 115 {
 116     nvram_write(nvram, addr, value >> 24);
 117     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 118     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 119     nvram_write(nvram, addr + 3, value & 0xFF);
 120 }
 121
 122 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 123                              uint32_t max)
 124 {
 125     int i;
 126
 127     for (i = 0; i < max && str[i] != '\0'; i++) {
 128         nvram_write(nvram, addr + i, str[i]);
 129     }
 130     nvram_write(nvram, addr + i, str[i]);
 131     nvram_write(nvram, addr + max - 1, '\0');
 132 }
 133
 134 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 135 {
 136     uint16_t tmp;
 137     uint16_t pd, pd1, pd2;
 138
 139     tmp = prev >> 8;
 140     pd = prev ^ value;
 141     pd1 = pd & 0x000F;
 142     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 143     tmp ^= (pd1 << 3) | (pd1 << 8);
 144     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 145
 146     return tmp;
 147 }
 148
 149 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 150 {
 151     uint32_t i;
 152     uint16_t crc = 0xFFFF;
 153     int odd;
 154
 155     odd = count & 1;
 156     count &= ~1;
 157     for (i = 0; i != count; i++) {
 158         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 159     }
 160     if (odd) {
 161         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 162     }
 163
 164     return crc;
 165 }
 166
 167 #define CMDLINE_ADDR 0x017ff000
 168
 169 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 170                           const char *arch,
 171                           uint32_t RAM_size, int boot_device,
 172                           uint32_t kernel_image, uint32_t kernel_size,
 173                           const char *cmdline,
 174                           uint32_t initrd_image, uint32_t initrd_size,
 175                           uint32_t NVRAM_image,
 176                           int width, int height, int depth)
 177 {
 178     uint16_t crc;
 179
 180     /* Set parameters for Open Hack'Ware BIOS */
 181     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 182     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 183     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 184     NVRAM_set_string(nvram, 0x20, arch, 16);
 185     NVRAM_set_lword(nvram,  0x30, RAM_size);
 186     NVRAM_set_byte(nvram,   0x34, boot_device);
 187     NVRAM_set_lword(nvram,  0x38, kernel_image);
 188     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 189     if (cmdline) {
 190         /* XXX: put the cmdline in NVRAM too ? */
 191         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 192                          cmdline);
 193         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 194         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 195     } else {
 196         NVRAM_set_lword(nvram,  0x40, 0);
 197         NVRAM_set_lword(nvram,  0x44, 0);
 198     }
 199     NVRAM_set_lword(nvram,  0x48, initrd_image);
 200     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 201     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 202
 203     NVRAM_set_word(nvram,   0x54, width);
 204     NVRAM_set_word(nvram,   0x56, height);
 205     NVRAM_set_word(nvram,   0x58, depth);
 206     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 207     NVRAM_set_word(nvram,   0xFC, crc);
 208
 209     return 0;
 210 }
 211
 212 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
 213 {
 214     uint16_t checksum = *(uint16_t *)opaque;
 215
 216     if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
 217         MC146818RtcState *rtc = MC146818_RTC(dev);
 218         mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff);
 219         mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff);
 220         mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8);
 221         mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8);
 222
 223         object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
 224                                   "date");
 225     }
 226     return 0;
 227 }
 228
 229 static void ibm_40p_init(MachineState *machine)
 230 {
 231     const char *bios_name = machine->firmware ?: "openbios-ppc";
 232     MachineClass *mc = MACHINE_GET_CLASS(machine);
 233     CPUPPCState *env = NULL;
 234     uint16_t cmos_checksum;
 235     PowerPCCPU *cpu;
 236     DeviceState *dev, *i82378_dev;
 237     SysBusDevice *pcihost, *s;
 238     Nvram *m48t59 = NULL;
 239     PCIBus *pci_bus;
 240     ISADevice *isa_dev;
 241     ISABus *isa_bus;
 242     void *fw_cfg;
 243     int i;
 244     uint32_t kernel_base = 0, initrd_base = 0;
 245     long kernel_size = 0, initrd_size = 0;
 246     char boot_device;
 247
 248     if (kvm_enabled()) {
 249         error_report("machine %s does not support the KVM accelerator",
 250                      MACHINE_GET_CLASS(machine)->name);
 251         exit(EXIT_FAILURE);
 252     }
 253
 254     /* init CPU */
 255     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 256     env = &cpu->env;
 257     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 258         error_report("only 6xx bus is supported on this machine");
 259         exit(1);
 260     }
 261
 262     /* Set time-base frequency to 100 Mhz */
 263     cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 264     qemu_register_reset(ppc_prep_reset, cpu);
 265
 266     /* PCI host */
 267     dev = qdev_new("raven-pcihost");
 268     qdev_prop_set_string(dev, "bios-name", bios_name);
 269     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 270     pcihost = SYS_BUS_DEVICE(dev);
 271     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
 272     sysbus_realize_and_unref(pcihost, &error_fatal);
 273     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 274     if (!pci_bus) {
 275         error_report("could not create PCI host controller");
 276         exit(1);
 277     }
 278
 279     /* PCI -> ISA bridge */
 280     i82378_dev = DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378"));
 281     qdev_connect_gpio_out(i82378_dev, 0,
 282                           qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
 283     qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal);
 284
 285     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
 286     isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
 287
 288     /* Memory controller */
 289     isa_dev = isa_new("rs6000-mc");
 290     dev = DEVICE(isa_dev);
 291     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
 292     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 293
 294     /* RTC */
 295     isa_dev = isa_new(TYPE_MC146818_RTC);
 296     dev = DEVICE(isa_dev);
 297     qdev_prop_set_int32(dev, "base_year", 1900);
 298     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 299
 300     /* initialize CMOS checksums */
 301     cmos_checksum = 0x6aa9;
 302     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
 303                        &cmos_checksum);
 304
 305     /* add some more devices */
 306     if (defaults_enabled()) {
 307         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
 308
 309         isa_dev = isa_new("cs4231a");
 310         dev = DEVICE(isa_dev);
 311         qdev_prop_set_uint32(dev, "iobase", 0x830);
 312         qdev_prop_set_uint32(dev, "irq", 10);
 313         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 314
 315         isa_dev = isa_new("pc87312");
 316         dev = DEVICE(isa_dev);
 317         qdev_prop_set_uint32(dev, "config", 12);
 318         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 319
 320         isa_dev = isa_new("prep-systemio");
 321         dev = DEVICE(isa_dev);
 322         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
 323         qdev_prop_set_uint32(dev, "equipment", 0xc0);
 324         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 325
 326         dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
 327                                        "lsi53c810"));
 328         lsi53c8xx_handle_legacy_cmdline(dev);
 329         qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
 330
 331         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
 332         pci_vga_init(pci_bus);
 333
 334         for (i = 0; i < nb_nics; i++) {
 335             pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic,
 336                                 i == 0 ? "3" : NULL);
 337         }
 338     }
 339
 340     /* Prepare firmware configuration for OpenBIOS */
 341     dev = qdev_new(TYPE_FW_CFG_MEM);
 342     fw_cfg = FW_CFG(dev);
 343     qdev_prop_set_uint32(dev, "data_width", 1);
 344     qdev_prop_set_bit(dev, "dma_enabled", false);
 345     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
 346                               OBJECT(fw_cfg));
 347     s = SYS_BUS_DEVICE(dev);
 348     sysbus_realize_and_unref(s, &error_fatal);
 349     sysbus_mmio_map(s, 0, CFG_ADDR);
 350     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
 351
 352     if (machine->kernel_filename) {
 353         /* load kernel */
 354         kernel_base = KERNEL_LOAD_ADDR;
 355         kernel_size = load_image_targphys(machine->kernel_filename,
 356                                           kernel_base,
 357                                           machine->ram_size - kernel_base);
 358         if (kernel_size < 0) {
 359             error_report("could not load kernel '%s'",
 360                          machine->kernel_filename);
 361             exit(1);
 362         }
 363         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 364         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 365         /* load initrd */
 366         if (machine->initrd_filename) {
 367             initrd_base = INITRD_LOAD_ADDR;
 368             initrd_size = load_image_targphys(machine->initrd_filename,
 369                                               initrd_base,
 370                                               machine->ram_size - initrd_base);
 371             if (initrd_size < 0) {
 372                 error_report("could not load initial ram disk '%s'",
 373                              machine->initrd_filename);
 374                 exit(1);
 375             }
 376             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 377             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 378         }
 379         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 380             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 381             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
 382                              machine->kernel_cmdline);
 383             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 384                               machine->kernel_cmdline);
 385             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 386                            strlen(machine->kernel_cmdline) + 1);
 387         }
 388         boot_device = 'm';
 389     } else {
 390         boot_device = machine->boot_config.order[0];
 391     }
 392
 393     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 394     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
 395     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
 396
 397     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 399     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 400
 401     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
 402     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
 403     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 404
 405     /* Prepare firmware configuration for Open Hack'Ware */
 406     if (m48t59) {
 407         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
 408                              boot_device,
 409                              kernel_base, kernel_size,
 410                              machine->kernel_cmdline,
 411                              initrd_base, initrd_size,
 412                              /* XXX: need an option to load a NVRAM image */
 413                              0,
 414                              graphic_width, graphic_height, graphic_depth);
 415     }
 416 }
 417
 418 static void ibm_40p_machine_init(MachineClass *mc)
 419 {
 420     mc->desc = "IBM RS/6000 7020 (40p)",
 421     mc->init = ibm_40p_init;
 422     mc->max_cpus = 1;
 423     mc->default_ram_size = 128 * MiB;
 424     mc->block_default_type = IF_SCSI;
 425     mc->default_boot_order = "c";
 426     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
 427     mc->default_display = "std";
 428     mc->default_nic = "pcnet";
 429 }
 430
 431 DEFINE_MACHINE("40p", ibm_40p_machine_init)