1 # AArch64 A64 allowed instruction decoding
3 # Copyright (c) 2023 Linaro, Ltd
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2.1 of the License, or (at your option) any later version.
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 # This file is processed by scripts/decodetree.py
23 %esz_sd 22:1 !function=plus_2
24 %esz_hsd 22:2 !function=xor_2
34 &rrx_e rd rn rm idx esz
35 &rrrr_e rd rn rm ra esz
37 &qrrr_e q rd rn rm esz
38 &qrrx_e q rd rn rm idx esz
39 &qrrrr_e q rd rn rm ra esz
41 @rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
42 @rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
43 @rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
45 @rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
46 @rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3
47 @rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd
48 @rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd
49 @rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e
50 @r2r_e ........ esz:2 . ..... ...... rm:5 rd:5 &rrr_e rn=%rd
52 @rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm
53 @rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl
54 @rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3
56 @rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0
57 @r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0
58 @rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0
59 @rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3
60 @rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3
62 @qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
63 @qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1
64 @qrrr_s . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=2
65 @qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd
66 @qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e
67 @qr2r_e . q:1 ...... esz:2 . ..... ...... rm:5 rd:5 &qrrr_e rn=%rd
69 @qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \
70 &qrrx_e esz=1 idx=%hlm
71 @qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \
73 @qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \
76 ### Data Processing - Immediate
81 @pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel
83 ADR 0 .. 10000 ................... ..... @pcrel
84 ADRP 1 .. 10000 ................... ..... @pcrel
86 # Add/subtract (immediate)
88 %imm12_sh12 10:12 !function=shl_12
89 @addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5
90 @addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12
92 ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm
93 ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12
94 ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm
95 ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12
97 SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm
98 SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12
99 SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm
100 SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
102 # Add/subtract (immediate with tags)
104 &rri_tag rd rn uimm6 uimm4
105 @addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag
107 ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
108 SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
110 # Logical (immediate)
112 &rri_log rd rn sf dbm
113 @logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1
114 @logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0
116 AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64
117 AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32
118 ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64
119 ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32
120 EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
121 EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
122 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
123 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32
125 # Move wide (immediate)
128 @movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1
129 @movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0
131 MOVN . 00 100101 .. ................ ..... @movw_64
132 MOVN . 00 100101 .. ................ ..... @movw_32
133 MOVZ . 10 100101 .. ................ ..... @movw_64
134 MOVZ . 10 100101 .. ................ ..... @movw_32
135 MOVK . 11 100101 .. ................ ..... @movw_64
136 MOVK . 11 100101 .. ................ ..... @movw_32
140 &bitfield rd rn sf immr imms
141 @bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1
142 @bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0
144 SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64
145 SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32
146 BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64
147 BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32
148 UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64
149 UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
153 &extract rd rn rm imm sf
155 EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
156 EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
160 %imm26 0:s26 !function=times_4
161 @branch . ..... .......................... &i imm=%imm26
163 B 0 00101 .......................... @branch
164 BL 1 00101 .......................... @branch
166 %imm19 5:s19 !function=times_4
169 CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
171 %imm14 5:s14 !function=times_4
173 &tbz rt imm nz bitpos
175 TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
178 B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19
180 BR 1101011 0000 11111 000000 rn:5 00000 &r
181 BLR 1101011 0001 11111 000000 rn:5 00000 &r
182 RET 1101011 0010 11111 000000 rn:5 00000 &r
185 BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ
186 BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ
189 RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB
192 BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB
193 BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB
195 ERET 1101011 0100 11111 000000 11111 00000
196 ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
198 # We don't need to decode DRPS because it always UNDEFs except when
199 # the processor is in halting debug state (which we don't implement).
200 # The pattern is listed here as documentation.
201 # DRPS 1101011 0101 11111 000000 11111 00000
203 # Hint instruction group
206 YIELD 1101 0101 0000 0011 0010 0000 001 11111
207 WFE 1101 0101 0000 0011 0010 0000 010 11111
208 WFI 1101 0101 0000 0011 0010 0000 011 11111
209 # We implement WFE to never block, so our SEV/SEVL are NOPs
210 # SEV 1101 0101 0000 0011 0010 0000 100 11111
211 # SEVL 1101 0101 0000 0011 0010 0000 101 11111
212 # Our DGL is a NOP because we don't merge memory accesses anyway.
213 # DGL 1101 0101 0000 0011 0010 0000 110 11111
214 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111
215 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111
216 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111
217 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111
218 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111
219 ESB 1101 0101 0000 0011 0010 0010 000 11111
220 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111
221 PACIASP 1101 0101 0000 0011 0010 0011 001 11111
222 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111
223 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111
224 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111
225 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111
226 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111
227 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111
229 # The canonical NOP has CRm == op2 == 0, but all of the space
230 # that isn't specifically allocated to an instruction must NOP
231 NOP 1101 0101 0000 0011 0010 ---- --- 11111
234 # System instructions with register argument
235 WFET 1101 0101 0000 0011 0001 0000 000 rd:5
236 WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
240 CLREX 1101 0101 0000 0011 0011 ---- 010 11111
241 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
242 ISB 1101 0101 0000 0011 0011 ---- 110 11111
243 SB 1101 0101 0000 0011 0011 0000 111 11111
247 CFINV 1101 0101 0000 0 000 0100 0000 000 11111
248 XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
249 AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111
251 # These are architecturally all "MSR (immediate)"; we decode the destination
252 # register too because there is no commonality in our implementation.
253 @msr_i .... .... .... . ... .... imm:4 ... .....
254 MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i
255 MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i
256 MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i
257 MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i
258 MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
259 MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
260 MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
261 MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
262 MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111
263 MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
265 # MRS, MSR (register), SYS, SYSL. These are all essentially the
266 # same instruction as far as QEMU is concerned.
267 # NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have
269 SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
270 SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
271 SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
273 # Exception generation
275 @i16 .... .... ... imm:16 ... .. &i
276 SVC 1101 0100 000 ................ 000 01 @i16
277 HVC 1101 0100 000 ................ 000 10 @i16
278 SMC 1101 0100 000 ................ 000 11 @i16
279 BRK 1101 0100 001 ................ 000 00 @i16
280 HLT 1101 0100 010 ................ 000 00 @i16
281 # These insns always UNDEF unless in halting debug state, which
282 # we don't implement. So we don't need to decode them. The patterns
283 # are listed here as documentation.
284 # DCPS1 1101 0100 101 ................ 000 01 @i16
285 # DCPS2 1101 0100 101 ................ 000 10 @i16
286 # DCPS3 1101 0100 101 ................ 000 11 @i16
290 &stxr rn rt rt2 rs sz lasr
292 @stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
293 @stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr
294 %imm1_30_p2 30:1 !function=plus_2
295 @stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2
296 STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR
297 LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR
298 STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR
299 LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR
301 STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP
302 LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP
304 # CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine
305 # acquire/release semantics because QEMU's cmpxchg always has those)
306 CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
307 # CAS, CASA, CASAL, CASL
308 CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
310 &ldlit rt imm sz sign
311 @ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19
313 LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0
314 LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0
315 LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1
316 LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0
317 LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0
318 LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0
321 NOP 11 011 0 00 ------------------- -----
323 &ldstpair rt2 rt rn imm sz sign w p
324 @ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair
326 # STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches
327 # so we ignore hints about data access patterns, and handle these like
328 # plain signed offset.
329 STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
330 LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
331 STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
332 LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
333 STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
334 LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
335 STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
336 LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
337 STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
338 LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
340 # STP and LDP: post-indexed
341 STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
342 LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
343 LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1
344 STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
345 LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
346 STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
347 LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
348 STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
349 LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
350 STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
351 LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
353 # STP and LDP: offset
354 STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
355 LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
356 LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0
357 STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
358 LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
359 STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
360 LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
361 STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
362 LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
363 STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
364 LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
366 # STP and LDP: pre-indexed
367 STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
368 LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
369 LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1
370 STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
371 LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
372 STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
373 LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
374 STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
375 LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
376 STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
377 LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
379 # STGP: store tag and pair
380 STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
381 STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
382 STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
384 # Load/store register (unscaled immediate)
385 &ldst_imm rt rn imm sz sign w p unpriv ext
386 @ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0
387 @ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1
388 @ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1
389 @ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0
391 STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
392 LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0
393 LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1
394 LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2
395 LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3
396 LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0
397 LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1
398 LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2
399 LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0
400 LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1
402 STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
403 LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0
404 LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1
405 LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2
406 LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3
407 LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0
408 LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1
409 LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2
410 LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0
411 LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1
413 STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0
414 LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0
415 LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1
416 LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2
417 LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3
418 LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0
419 LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1
420 LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2
421 LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0
422 LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1
424 STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
425 LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0
426 LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1
427 LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2
428 LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3
429 LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0
430 LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1
431 LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2
432 LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0
433 LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1
435 # PRFM : prefetch memory: a no-op for QEMU
436 NOP 11 111 0 00 10 0 --------- 00 ----- -----
438 STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
439 STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
440 LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
441 LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
443 STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
444 STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
445 LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
446 LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
448 STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
449 STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
450 LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
451 LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
453 # Load/store with an unsigned 12 bit immediate, which is scaled by the
454 # element size. The function gets the sz:imm and returns the scaled immediate.
455 %uimm_scaled 10:12 sz:3 !function=uimm_scaled
457 @ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled
459 STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
460 LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0
461 LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1
462 LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2
463 LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3
464 LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0
465 LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1
466 LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2
467 LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0
468 LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1
471 NOP 11 111 0 01 10 ------------ ----- -----
473 STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
474 STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
475 LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0
476 LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
478 # Load/store with register offset
479 &ldst rm rn rt sign ext sz opt s
480 @ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst
481 STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
482 LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0
483 LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1
484 LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2
485 LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3
486 LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0
487 LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1
488 LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2
489 LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0
490 LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1
493 NOP 11 111 0 00 10 1 ----- -1- - 10 ----- -----
495 STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
496 STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
497 LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
498 LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
500 # Atomic memory operations
501 &atomic rs rn rt a r sz
502 @atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic
503 LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic
504 LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic
505 LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic
506 LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic
507 LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic
508 LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic
509 LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic
510 LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic
511 SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic
513 LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
515 # Load/store register (pointer authentication)
517 # LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
518 %ldra_imm 22:s1 12:9 !function=times_8
520 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm
522 &ldapr_stlr_i rn rt imm sz sign ext
523 @ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i
524 STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
525 LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
526 LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0
527 LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1
528 LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2
529 LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0
530 LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1
532 # Load/store multiple structures
533 # The 4-bit opcode in [15:12] encodes repeat count and structure elements
534 &ldst_mult rm rn rt sz q p rpt selem
535 @ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult
536 ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
537 ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
538 ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
539 ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
540 ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
541 ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
542 ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
544 LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
545 LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
546 LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
547 LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
548 LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
549 LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
550 LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
552 # Load/store single structure
553 &ldst_single rm rn rt p selem index scale
555 %ldst_single_selem 13:1 21:1 !function=plus_1
557 %ldst_single_index_b 30:1 10:3
558 %ldst_single_index_h 30:1 11:2
559 %ldst_single_index_s 30:1 12:1
561 @ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
562 &ldst_single scale=0 selem=%ldst_single_selem \
563 index=%ldst_single_index_b
564 @ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
565 &ldst_single scale=1 selem=%ldst_single_selem \
566 index=%ldst_single_index_h
567 @ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
568 &ldst_single scale=2 selem=%ldst_single_selem \
569 index=%ldst_single_index_s
570 @ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \
571 &ldst_single scale=3 selem=%ldst_single_selem
573 ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b
574 ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h
575 ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s
576 ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d
578 LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b
579 LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h
580 LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s
581 LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d
583 # Replicating load case
584 LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem
586 %tag_offset 12:s9 !function=scale_by_log2_tag_granule
587 &ldst_tag rn rt imm p w
588 @ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset
589 @ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0
591 STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
592 STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
593 STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
594 STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
596 LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0
597 STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
598 STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
599 STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
601 STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
602 ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
603 ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
604 ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
606 LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
607 STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
608 STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
609 STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
611 # Memory operations (memset, memcpy, memmove)
612 # Each of these comes in a set of three, eg SETP (prologue), SETM (main),
613 # SETE (epilogue), and each of those has different flavours to
614 # indicate whether memory accesses should be unpriv or non-temporal.
615 # We don't distinguish temporal and non-temporal accesses, but we
616 # do need to report it in syndrome register values.
619 &set rs rn rd unpriv nontemp
620 # op2 bit 1 is nontemporal bit
621 @set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set
623 SETP 00 011001110 ..... 00 . . 01 ..... ..... @set
624 SETM 00 011001110 ..... 01 . . 01 ..... ..... @set
625 SETE 00 011001110 ..... 10 . . 01 ..... ..... @set
627 # Like SET, but also setting MTE tags
628 SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set
629 SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set
630 SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set
632 # Memmove/Memcopy: the CPY insns allow overlapping src/dest and
633 # copy in the correct direction; the CPYF insns always copy forwards.
635 # options has the nontemporal and unpriv bits for src and dest
636 &cpy rs rn rd options
637 @cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy
639 CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy
640 CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy
641 CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy
642 CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy
643 CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy
644 CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
646 ### Cryptographic AES
648 AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0
649 AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0
650 AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0
651 AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0
653 ### Cryptographic three-register SHA
655 SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0
656 SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0
657 SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0
658 SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0
659 SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0
660 SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0
661 SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0
663 ### Cryptographic two-register SHA
665 SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0
666 SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0
667 SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0
669 ### Cryptographic three-register SHA512
671 SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0
672 SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0
673 SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0
674 RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3
675 SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0
676 SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0
677 SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0
679 ### Cryptographic two-register SHA512
681 SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0
682 SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0
684 ### Cryptographic four-register
686 EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3
687 BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3
688 SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3
690 ### Cryptographic three-register, imm2
692 &crypto3i rd rn rm imm
693 @crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i
695 SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i
696 SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i
697 SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i
698 SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i
700 ### Cryptographic XAR
702 XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5
704 ### Advanced SIMD scalar copy
706 DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5
708 ### Advanced SIMD copy
710 DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5
711 DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5
712 INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5
713 SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5
714 UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5
715 INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5
717 ### Advanced SIMD scalar three same
719 FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd
720 FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd
721 FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd
722 FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd
723 FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd
725 FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd
726 FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd
727 FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd
728 FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd
730 FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h
731 FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd
733 FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h
734 FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd
736 FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h
737 FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd
739 FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h
740 FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd
742 FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h
743 FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd
745 FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h
746 FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd
748 FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h
749 FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd
751 FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h
752 FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd
754 FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h
755 FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd
757 SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e
758 UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e
759 SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
760 UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
762 SUQADD_s 0101 1110 ..1 00000 00111 0 ..... ..... @r2r_e
763 USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e
765 SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d
766 USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d
767 SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d
768 URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d
769 SQSHL_s 0101 1110 ..1 ..... 01001 1 ..... ..... @rrr_e
770 UQSHL_s 0111 1110 ..1 ..... 01001 1 ..... ..... @rrr_e
771 SQRSHL_s 0101 1110 ..1 ..... 01011 1 ..... ..... @rrr_e
772 UQRSHL_s 0111 1110 ..1 ..... 01011 1 ..... ..... @rrr_e
774 ADD_s 0101 1110 111 ..... 10000 1 ..... ..... @rrr_d
775 SUB_s 0111 1110 111 ..... 10000 1 ..... ..... @rrr_d
776 CMGT_s 0101 1110 111 ..... 00110 1 ..... ..... @rrr_d
777 CMHI_s 0111 1110 111 ..... 00110 1 ..... ..... @rrr_d
778 CMGE_s 0101 1110 111 ..... 00111 1 ..... ..... @rrr_d
779 CMHS_s 0111 1110 111 ..... 00111 1 ..... ..... @rrr_d
780 CMTST_s 0101 1110 111 ..... 10001 1 ..... ..... @rrr_d
781 CMEQ_s 0111 1110 111 ..... 10001 1 ..... ..... @rrr_d
783 SQDMULH_s 0101 1110 ..1 ..... 10110 1 ..... ..... @rrr_e
784 SQRDMULH_s 0111 1110 ..1 ..... 10110 1 ..... ..... @rrr_e
785 SQRDMLAH_s 0111 1110 ..0 ..... 10000 1 ..... ..... @rrr_e
786 SQRDMLSH_s 0111 1110 ..0 ..... 10001 1 ..... ..... @rrr_e
788 # Decode scalar x scalar as scalar x indexed, with index 0.
789 SQDMULL_si 0101 1110 011 rm:5 11010 0 rn:5 rd:5 &rrx_e idx=0 esz=1
790 SQDMULL_si 0101 1110 101 rm:5 11010 0 rn:5 rd:5 &rrx_e idx=0 esz=2
791 SQDMLAL_si 0101 1110 011 rm:5 10010 0 rn:5 rd:5 &rrx_e idx=0 esz=1
792 SQDMLAL_si 0101 1110 101 rm:5 10010 0 rn:5 rd:5 &rrx_e idx=0 esz=2
793 SQDMLSL_si 0101 1110 011 rm:5 10110 0 rn:5 rd:5 &rrx_e idx=0 esz=1
794 SQDMLSL_si 0101 1110 101 rm:5 10110 0 rn:5 rd:5 &rrx_e idx=0 esz=2
796 ### Advanced SIMD scalar pairwise
798 FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h
799 FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd
801 FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h
802 FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd
804 FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h
805 FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd
807 FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h
808 FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd
810 FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h
811 FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd
813 ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d
815 ### Advanced SIMD three same
817 FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h
818 FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd
820 FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h
821 FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd
823 FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h
824 FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd
826 FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h
827 FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd
829 FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h
830 FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd
832 FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h
833 FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd
835 FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h
836 FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd
838 FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h
839 FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd
841 FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h
842 FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd
844 FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h
845 FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd
847 FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h
848 FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd
850 FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h
851 FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h
852 FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h
853 FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h
855 FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h
856 FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd
858 FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h
859 FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd
861 FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h
862 FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd
864 FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h
865 FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd
867 FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h
868 FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd
870 FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h
871 FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd
873 FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h
874 FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd
876 FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h
877 FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd
879 FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h
880 FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd
882 FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h
883 FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd
885 FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h
886 FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd
888 FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h
889 FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd
891 FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h
892 FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd
894 ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e
895 SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e
896 SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e
897 UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e
898 UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e
900 AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b
901 BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b
902 ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b
903 ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b
904 EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b
905 BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b
906 BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b
907 BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b
909 SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e
910 UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e
911 SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
912 UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
914 SUQADD_v 0.00 1110 ..1 00000 00111 0 ..... ..... @qr2r_e
915 USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e
917 SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e
918 USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e
919 SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e
920 URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e
921 SQSHL_v 0.00 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e
922 UQSHL_v 0.10 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e
923 SQRSHL_v 0.00 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e
924 UQRSHL_v 0.10 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e
926 ADD_v 0.00 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e
927 SUB_v 0.10 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e
928 CMGT_v 0.00 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e
929 CMHI_v 0.10 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e
930 CMGE_v 0.00 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e
931 CMHS_v 0.10 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e
932 CMTST_v 0.00 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e
933 CMEQ_v 0.10 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e
934 SHADD_v 0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e
935 UHADD_v 0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e
936 SHSUB_v 0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
937 UHSUB_v 0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e
938 SRHADD_v 0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
939 URHADD_v 0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e
940 SMAX_v 0.00 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e
941 UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e
942 SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e
943 UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e
944 SABD_v 0.00 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e
945 UABD_v 0.10 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e
946 SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e
947 UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e
948 MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e
949 PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b
950 MLA_v 0.00 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e
951 MLS_v 0.10 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e
953 SQDMULH_v 0.00 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e
954 SQRDMULH_v 0.10 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e
955 SQRDMLAH_v 0.10 1110 ..0 ..... 10000 1 ..... ..... @qrrr_e
956 SQRDMLSH_v 0.10 1110 ..0 ..... 10001 1 ..... ..... @qrrr_e
958 SDOT_v 0.00 1110 100 ..... 10010 1 ..... ..... @qrrr_s
959 UDOT_v 0.10 1110 100 ..... 10010 1 ..... ..... @qrrr_s
960 USDOT_v 0.00 1110 100 ..... 10011 1 ..... ..... @qrrr_s
961 BFDOT_v 0.10 1110 010 ..... 11111 1 ..... ..... @qrrr_s
962 BFMLAL_v 0.10 1110 110 ..... 11111 1 ..... ..... @qrrr_h
963 BFMMLA 0110 1110 010 ..... 11101 1 ..... ..... @rrr_q1e0
964 SMMLA 0100 1110 100 ..... 10100 1 ..... ..... @rrr_q1e0
965 UMMLA 0110 1110 100 ..... 10100 1 ..... ..... @rrr_q1e0
966 USMMLA 0100 1110 100 ..... 10101 1 ..... ..... @rrr_q1e0
968 FCADD_90 0.10 1110 ..0 ..... 11100 1 ..... ..... @qrrr_e
969 FCADD_270 0.10 1110 ..0 ..... 11110 1 ..... ..... @qrrr_e
971 FCMLA_v 0 q:1 10 1110 esz:2 0 rm:5 110 rot:2 1 rn:5 rd:5
973 SMULL_v 0.00 1110 ..1 ..... 11000 0 ..... ..... @qrrr_e
974 UMULL_v 0.10 1110 ..1 ..... 11000 0 ..... ..... @qrrr_e
975 SMLAL_v 0.00 1110 ..1 ..... 10000 0 ..... ..... @qrrr_e
976 UMLAL_v 0.10 1110 ..1 ..... 10000 0 ..... ..... @qrrr_e
977 SMLSL_v 0.00 1110 ..1 ..... 10100 0 ..... ..... @qrrr_e
978 UMLSL_v 0.10 1110 ..1 ..... 10100 0 ..... ..... @qrrr_e
980 SADDL_v 0.00 1110 ..1 ..... 00000 0 ..... ..... @qrrr_e
981 UADDL_v 0.10 1110 ..1 ..... 00000 0 ..... ..... @qrrr_e
982 SSUBL_v 0.00 1110 ..1 ..... 00100 0 ..... ..... @qrrr_e
983 USUBL_v 0.10 1110 ..1 ..... 00100 0 ..... ..... @qrrr_e
984 SABAL_v 0.00 1110 ..1 ..... 01010 0 ..... ..... @qrrr_e
985 UABAL_v 0.10 1110 ..1 ..... 01010 0 ..... ..... @qrrr_e
986 SABDL_v 0.00 1110 ..1 ..... 01110 0 ..... ..... @qrrr_e
987 UABDL_v 0.10 1110 ..1 ..... 01110 0 ..... ..... @qrrr_e
989 SQDMULL_v 0.00 1110 011 ..... 11010 0 ..... ..... @qrrr_h
990 SQDMULL_v 0.00 1110 101 ..... 11010 0 ..... ..... @qrrr_s
991 SQDMLAL_v 0.00 1110 011 ..... 10010 0 ..... ..... @qrrr_h
992 SQDMLAL_v 0.00 1110 101 ..... 10010 0 ..... ..... @qrrr_s
993 SQDMLSL_v 0.00 1110 011 ..... 10110 0 ..... ..... @qrrr_h
994 SQDMLSL_v 0.00 1110 101 ..... 10110 0 ..... ..... @qrrr_s
996 SADDW 0.00 1110 ..1 ..... 00010 0 ..... ..... @qrrr_e
997 UADDW 0.10 1110 ..1 ..... 00010 0 ..... ..... @qrrr_e
998 SSUBW 0.00 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e
999 USUBW 0.10 1110 ..1 ..... 00110 0 ..... ..... @qrrr_e
1001 ADDHN 0.00 1110 ..1 ..... 01000 0 ..... ..... @qrrr_e
1002 RADDHN 0.10 1110 ..1 ..... 01000 0 ..... ..... @qrrr_e
1003 SUBHN 0.00 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e
1004 RSUBHN 0.10 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e
1006 ### Advanced SIMD scalar x indexed element
1008 FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
1009 FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s
1010 FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d
1012 FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h
1013 FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s
1014 FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d
1016 FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h
1017 FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s
1018 FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d
1020 FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
1021 FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s
1022 FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d
1024 SQDMULH_si 0101 1111 01 .. .... 1100 . 0 ..... ..... @rrx_h
1025 SQDMULH_si 0101 1111 10 .. .... 1100 . 0 ..... ..... @rrx_s
1027 SQRDMULH_si 0101 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h
1028 SQRDMULH_si 0101 1111 10 . ..... 1101 . 0 ..... ..... @rrx_s
1030 SQRDMLAH_si 0111 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h
1031 SQRDMLAH_si 0111 1111 10 .. .... 1101 . 0 ..... ..... @rrx_s
1033 SQRDMLSH_si 0111 1111 01 .. .... 1111 . 0 ..... ..... @rrx_h
1034 SQRDMLSH_si 0111 1111 10 .. .... 1111 . 0 ..... ..... @rrx_s
1036 SQDMULL_si 0101 1111 01 .. .... 1011 . 0 ..... ..... @rrx_h
1037 SQDMULL_si 0101 1111 10 . ..... 1011 . 0 ..... ..... @rrx_s
1039 SQDMLAL_si 0101 1111 01 .. .... 0011 . 0 ..... ..... @rrx_h
1040 SQDMLAL_si 0101 1111 10 . ..... 0011 . 0 ..... ..... @rrx_s
1042 SQDMLSL_si 0101 1111 01 .. .... 0111 . 0 ..... ..... @rrx_h
1043 SQDMLSL_si 0101 1111 10 . ..... 0111 . 0 ..... ..... @rrx_s
1045 ### Advanced SIMD vector x indexed element
1047 FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
1048 FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s
1049 FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d
1051 FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h
1052 FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s
1053 FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d
1055 FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h
1056 FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s
1057 FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d
1059 FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
1060 FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s
1061 FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d
1063 FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h
1064 FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h
1065 FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h
1066 FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h
1068 MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h
1069 MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s
1071 MLA_vi 0.10 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h
1072 MLA_vi 0.10 1111 10 . ..... 0000 . 0 ..... ..... @qrrx_s
1074 MLS_vi 0.10 1111 01 .. .... 0100 . 0 ..... ..... @qrrx_h
1075 MLS_vi 0.10 1111 10 . ..... 0100 . 0 ..... ..... @qrrx_s
1077 SQDMULH_vi 0.00 1111 01 .. .... 1100 . 0 ..... ..... @qrrx_h
1078 SQDMULH_vi 0.00 1111 10 . ..... 1100 . 0 ..... ..... @qrrx_s
1080 SQRDMULH_vi 0.00 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h
1081 SQRDMULH_vi 0.00 1111 10 . ..... 1101 . 0 ..... ..... @qrrx_s
1083 SQRDMLAH_vi 0.10 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h
1084 SQRDMLAH_vi 0.10 1111 10 .. .... 1101 . 0 ..... ..... @qrrx_s
1086 SQRDMLSH_vi 0.10 1111 01 .. .... 1111 . 0 ..... ..... @qrrx_h
1087 SQRDMLSH_vi 0.10 1111 10 .. .... 1111 . 0 ..... ..... @qrrx_s
1089 SDOT_vi 0.00 1111 10 .. .... 1110 . 0 ..... ..... @qrrx_s
1090 UDOT_vi 0.10 1111 10 .. .... 1110 . 0 ..... ..... @qrrx_s
1091 SUDOT_vi 0.00 1111 00 .. .... 1111 . 0 ..... ..... @qrrx_s
1092 USDOT_vi 0.00 1111 10 .. .... 1111 . 0 ..... ..... @qrrx_s
1093 BFDOT_vi 0.00 1111 01 .. .... 1111 . 0 ..... ..... @qrrx_s
1094 BFMLAL_vi 0.00 1111 11 .. .... 1111 . 0 ..... ..... @qrrx_h
1096 FCMLA_vi 0 0 10 1111 01 idx:1 rm:5 0 rot:2 1 0 0 rn:5 rd:5 esz=1 q=0
1097 FCMLA_vi 0 1 10 1111 01 . rm:5 0 rot:2 1 . 0 rn:5 rd:5 esz=1 idx=%hl q=1
1098 FCMLA_vi 0 1 10 1111 10 0 rm:5 0 rot:2 1 idx:1 0 rn:5 rd:5 esz=2 q=1
1100 SMULL_vi 0.00 1111 01 .. .... 1010 . 0 ..... ..... @qrrx_h
1101 SMULL_vi 0.00 1111 10 . ..... 1010 . 0 ..... ..... @qrrx_s
1102 UMULL_vi 0.10 1111 01 .. .... 1010 . 0 ..... ..... @qrrx_h
1103 UMULL_vi 0.10 1111 10 . ..... 1010 . 0 ..... ..... @qrrx_s
1105 SMLAL_vi 0.00 1111 01 .. .... 0010 . 0 ..... ..... @qrrx_h
1106 SMLAL_vi 0.00 1111 10 . ..... 0010 . 0 ..... ..... @qrrx_s
1107 UMLAL_vi 0.10 1111 01 .. .... 0010 . 0 ..... ..... @qrrx_h
1108 UMLAL_vi 0.10 1111 10 . ..... 0010 . 0 ..... ..... @qrrx_s
1110 SMLSL_vi 0.00 1111 01 .. .... 0110 . 0 ..... ..... @qrrx_h
1111 SMLSL_vi 0.00 1111 10 . ..... 0110 . 0 ..... ..... @qrrx_s
1112 UMLSL_vi 0.10 1111 01 .. .... 0110 . 0 ..... ..... @qrrx_h
1113 UMLSL_vi 0.10 1111 10 . ..... 0110 . 0 ..... ..... @qrrx_s
1115 SQDMULL_vi 0.00 1111 01 .. .... 1011 . 0 ..... ..... @qrrx_h
1116 SQDMULL_vi 0.00 1111 10 . ..... 1011 . 0 ..... ..... @qrrx_s
1118 SQDMLAL_vi 0.00 1111 01 .. .... 0011 . 0 ..... ..... @qrrx_h
1119 SQDMLAL_vi 0.00 1111 10 . ..... 0011 . 0 ..... ..... @qrrx_s
1121 SQDMLSL_vi 0.00 1111 01 .. .... 0111 . 0 ..... ..... @qrrx_h
1122 SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s
1124 # Floating-point conditional select
1126 FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
1128 # Floating-point data-processing (3 source)
1130 @rrrr_hsd .... .... .. . rm:5 . ra:5 rn:5 rd:5 &rrrr_e esz=%esz_hsd
1132 FMADD 0001 1111 .. 0 ..... 0 ..... ..... ..... @rrrr_hsd
1133 FMSUB 0001 1111 .. 0 ..... 1 ..... ..... ..... @rrrr_hsd
1134 FNMADD 0001 1111 .. 1 ..... 0 ..... ..... ..... @rrrr_hsd
1135 FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..... @rrrr_hsd