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os-posix: Add os_set_daemonize()
[qemu/armbru.git] / hw / arm / stellaris.c
blobb6c8a5d609837c0447ee343a439fbcc638a44c49
1 /*
2 * Luminary Micro Stellaris peripherals
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/sysbus.h"
13 #include "hw/sd/sd.h"
14 #include "hw/ssi/ssi.h"
15 #include "hw/arm/boot.h"
16 #include "qemu/timer.h"
17 #include "hw/i2c/i2c.h"
18 #include "net/net.h"
19 #include "hw/boards.h"
20 #include "qemu/log.h"
21 #include "exec/address-spaces.h"
22 #include "sysemu/sysemu.h"
23 #include "hw/arm/armv7m.h"
24 #include "hw/char/pl011.h"
25 #include "hw/input/gamepad.h"
26 #include "hw/irq.h"
27 #include "hw/watchdog/cmsdk-apb-watchdog.h"
28 #include "migration/vmstate.h"
29 #include "hw/misc/unimp.h"
30 #include "hw/timer/stellaris-gptm.h"
31 #include "hw/qdev-clock.h"
32 #include "qom/object.h"
33
34 #define GPIO_A 0
35 #define GPIO_B 1
36 #define GPIO_C 2
37 #define GPIO_D 3
38 #define GPIO_E 4
39 #define GPIO_F 5
40 #define GPIO_G 6
41
42 #define BP_OLED_I2C 0x01
43 #define BP_OLED_SSI 0x02
44 #define BP_GAMEPAD 0x04
45
46 #define NUM_IRQ_LINES 64
47
48 typedef const struct {
49 const char *name;
50 uint32_t did0;
51 uint32_t did1;
52 uint32_t dc0;
53 uint32_t dc1;
54 uint32_t dc2;
55 uint32_t dc3;
56 uint32_t dc4;
57 uint32_t peripherals;
58 } stellaris_board_info;
59
60 /* System controller. */
61
62 #define TYPE_STELLARIS_SYS "stellaris-sys"
63 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
64
65 struct ssys_state {
66 SysBusDevice parent_obj;
67
68 MemoryRegion iomem;
69 uint32_t pborctl;
70 uint32_t ldopctl;
71 uint32_t int_status;
72 uint32_t int_mask;
73 uint32_t resc;
74 uint32_t rcc;
75 uint32_t rcc2;
76 uint32_t rcgc[3];
77 uint32_t scgc[3];
78 uint32_t dcgc[3];
79 uint32_t clkvclr;
80 uint32_t ldoarst;
81 qemu_irq irq;
82 Clock *sysclk;
83 /* Properties (all read-only registers) */
84 uint32_t user0;
85 uint32_t user1;
86 uint32_t did0;
87 uint32_t did1;
88 uint32_t dc0;
89 uint32_t dc1;
90 uint32_t dc2;
91 uint32_t dc3;
92 uint32_t dc4;
93 };
94
95 static void ssys_update(ssys_state *s)
96 {
97 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
98 }
99
100 static uint32_t pllcfg_sandstorm[16] = {
101 0x31c0, /* 1 Mhz */
102 0x1ae0, /* 1.8432 Mhz */
103 0x18c0, /* 2 Mhz */
104 0xd573, /* 2.4576 Mhz */
105 0x37a6, /* 3.57954 Mhz */
106 0x1ae2, /* 3.6864 Mhz */
107 0x0c40, /* 4 Mhz */
108 0x98bc, /* 4.906 Mhz */
109 0x935b, /* 4.9152 Mhz */
110 0x09c0, /* 5 Mhz */
111 0x4dee, /* 5.12 Mhz */
112 0x0c41, /* 6 Mhz */
113 0x75db, /* 6.144 Mhz */
114 0x1ae6, /* 7.3728 Mhz */
115 0x0600, /* 8 Mhz */
116 0x585b /* 8.192 Mhz */
117 };
118
119 static uint32_t pllcfg_fury[16] = {
120 0x3200, /* 1 Mhz */
121 0x1b20, /* 1.8432 Mhz */
122 0x1900, /* 2 Mhz */
123 0xf42b, /* 2.4576 Mhz */
124 0x37e3, /* 3.57954 Mhz */
125 0x1b21, /* 3.6864 Mhz */
126 0x0c80, /* 4 Mhz */
127 0x98ee, /* 4.906 Mhz */
128 0xd5b4, /* 4.9152 Mhz */
129 0x0a00, /* 5 Mhz */
130 0x4e27, /* 5.12 Mhz */
131 0x1902, /* 6 Mhz */
132 0xec1c, /* 6.144 Mhz */
133 0x1b23, /* 7.3728 Mhz */
134 0x0640, /* 8 Mhz */
135 0xb11c /* 8.192 Mhz */
136 };
137
138 #define DID0_VER_MASK 0x70000000
139 #define DID0_VER_0 0x00000000
140 #define DID0_VER_1 0x10000000
141
142 #define DID0_CLASS_MASK 0x00FF0000
143 #define DID0_CLASS_SANDSTORM 0x00000000
144 #define DID0_CLASS_FURY 0x00010000
145
146 static int ssys_board_class(const ssys_state *s)
147 {
148 uint32_t did0 = s->did0;
149 switch (did0 & DID0_VER_MASK) {
150 case DID0_VER_0:
151 return DID0_CLASS_SANDSTORM;
152 case DID0_VER_1:
153 switch (did0 & DID0_CLASS_MASK) {
154 case DID0_CLASS_SANDSTORM:
155 case DID0_CLASS_FURY:
156 return did0 & DID0_CLASS_MASK;
157 }
158 /* for unknown classes, fall through */
159 default:
160 /* This can only happen if the hardwired constant did0 value
161 * in this board's stellaris_board_info struct is wrong.
162 */
163 g_assert_not_reached();
164 }
165 }
166
167 static uint64_t ssys_read(void *opaque, hwaddr offset,
168 unsigned size)
169 {
170 ssys_state *s = (ssys_state *)opaque;
171
172 switch (offset) {
173 case 0x000: /* DID0 */
174 return s->did0;
175 case 0x004: /* DID1 */
176 return s->did1;
177 case 0x008: /* DC0 */
178 return s->dc0;
179 case 0x010: /* DC1 */
180 return s->dc1;
181 case 0x014: /* DC2 */
182 return s->dc2;
183 case 0x018: /* DC3 */
184 return s->dc3;
185 case 0x01c: /* DC4 */
186 return s->dc4;
187 case 0x030: /* PBORCTL */
188 return s->pborctl;
189 case 0x034: /* LDOPCTL */
190 return s->ldopctl;
191 case 0x040: /* SRCR0 */
192 return 0;
193 case 0x044: /* SRCR1 */
194 return 0;
195 case 0x048: /* SRCR2 */
196 return 0;
197 case 0x050: /* RIS */
198 return s->int_status;
199 case 0x054: /* IMC */
200 return s->int_mask;
201 case 0x058: /* MISC */
202 return s->int_status & s->int_mask;
203 case 0x05c: /* RESC */
204 return s->resc;
205 case 0x060: /* RCC */
206 return s->rcc;
207 case 0x064: /* PLLCFG */
208 {
209 int xtal;
210 xtal = (s->rcc >> 6) & 0xf;
211 switch (ssys_board_class(s)) {
212 case DID0_CLASS_FURY:
213 return pllcfg_fury[xtal];
214 case DID0_CLASS_SANDSTORM:
215 return pllcfg_sandstorm[xtal];
216 default:
217 g_assert_not_reached();
218 }
219 }
220 case 0x070: /* RCC2 */
221 return s->rcc2;
222 case 0x100: /* RCGC0 */
223 return s->rcgc[0];
224 case 0x104: /* RCGC1 */
225 return s->rcgc[1];
226 case 0x108: /* RCGC2 */
227 return s->rcgc[2];
228 case 0x110: /* SCGC0 */
229 return s->scgc[0];
230 case 0x114: /* SCGC1 */
231 return s->scgc[1];
232 case 0x118: /* SCGC2 */
233 return s->scgc[2];
234 case 0x120: /* DCGC0 */
235 return s->dcgc[0];
236 case 0x124: /* DCGC1 */
237 return s->dcgc[1];
238 case 0x128: /* DCGC2 */
239 return s->dcgc[2];
240 case 0x150: /* CLKVCLR */
241 return s->clkvclr;
242 case 0x160: /* LDOARST */
243 return s->ldoarst;
244 case 0x1e0: /* USER0 */
245 return s->user0;
246 case 0x1e4: /* USER1 */
247 return s->user1;
248 default:
249 qemu_log_mask(LOG_GUEST_ERROR,
250 "SSYS: read at bad offset 0x%x\n", (int)offset);
251 return 0;
252 }
253 }
254
255 static bool ssys_use_rcc2(ssys_state *s)
256 {
257 return (s->rcc2 >> 31) & 0x1;
258 }
259
260 /*
261 * Calculate the system clock period. We only want to propagate
262 * this change to the rest of the system if we're not being called
263 * from migration post-load.
264 */
265 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
266 {
267 int period_ns;
268 /*
269 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
270 * clock is 200MHz, which is a period of 5 ns. Dividing the clock
271 * frequency by X is the same as multiplying the period by X.
272 */
273 if (ssys_use_rcc2(s)) {
274 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
275 } else {
276 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
277 }
278 clock_set_ns(s->sysclk, period_ns);
279 if (propagate_clock) {
280 clock_propagate(s->sysclk);
281 }
282 }
283
284 static void ssys_write(void *opaque, hwaddr offset,
285 uint64_t value, unsigned size)
286 {
287 ssys_state *s = (ssys_state *)opaque;
288
289 switch (offset) {
290 case 0x030: /* PBORCTL */
291 s->pborctl = value & 0xffff;
292 break;
293 case 0x034: /* LDOPCTL */
294 s->ldopctl = value & 0x1f;
295 break;
296 case 0x040: /* SRCR0 */
297 case 0x044: /* SRCR1 */
298 case 0x048: /* SRCR2 */
299 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
300 break;
301 case 0x054: /* IMC */
302 s->int_mask = value & 0x7f;
303 break;
304 case 0x058: /* MISC */
305 s->int_status &= ~value;
306 break;
307 case 0x05c: /* RESC */
308 s->resc = value & 0x3f;
309 break;
310 case 0x060: /* RCC */
311 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
312 /* PLL enable. */
313 s->int_status |= (1 << 6);
314 }
315 s->rcc = value;
316 ssys_calculate_system_clock(s, true);
317 break;
318 case 0x070: /* RCC2 */
319 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
320 break;
321 }
322
323 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
324 /* PLL enable. */
325 s->int_status |= (1 << 6);
326 }
327 s->rcc2 = value;
328 ssys_calculate_system_clock(s, true);
329 break;
330 case 0x100: /* RCGC0 */
331 s->rcgc[0] = value;
332 break;
333 case 0x104: /* RCGC1 */
334 s->rcgc[1] = value;
335 break;
336 case 0x108: /* RCGC2 */
337 s->rcgc[2] = value;
338 break;
339 case 0x110: /* SCGC0 */
340 s->scgc[0] = value;
341 break;
342 case 0x114: /* SCGC1 */
343 s->scgc[1] = value;
344 break;
345 case 0x118: /* SCGC2 */
346 s->scgc[2] = value;
347 break;
348 case 0x120: /* DCGC0 */
349 s->dcgc[0] = value;
350 break;
351 case 0x124: /* DCGC1 */
352 s->dcgc[1] = value;
353 break;
354 case 0x128: /* DCGC2 */
355 s->dcgc[2] = value;
356 break;
357 case 0x150: /* CLKVCLR */
358 s->clkvclr = value;
359 break;
360 case 0x160: /* LDOARST */
361 s->ldoarst = value;
362 break;
363 default:
364 qemu_log_mask(LOG_GUEST_ERROR,
365 "SSYS: write at bad offset 0x%x\n", (int)offset);
366 }
367 ssys_update(s);
368 }
369
370 static const MemoryRegionOps ssys_ops = {
371 .read = ssys_read,
372 .write = ssys_write,
373 .endianness = DEVICE_NATIVE_ENDIAN,
374 };
375
376 static void stellaris_sys_reset_enter(Object *obj, ResetType type)
377 {
378 ssys_state *s = STELLARIS_SYS(obj);
379
380 s->pborctl = 0x7ffd;
381 s->rcc = 0x078e3ac0;
382
383 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
384 s->rcc2 = 0;
385 } else {
386 s->rcc2 = 0x07802810;
387 }
388 s->rcgc[0] = 1;
389 s->scgc[0] = 1;
390 s->dcgc[0] = 1;
391 }
392
393 static void stellaris_sys_reset_hold(Object *obj)
394 {
395 ssys_state *s = STELLARIS_SYS(obj);
396
397 /* OK to propagate clocks from the hold phase */
398 ssys_calculate_system_clock(s, true);
399 }
400
401 static void stellaris_sys_reset_exit(Object *obj)
402 {
403 }
404
405 static int stellaris_sys_post_load(void *opaque, int version_id)
406 {
407 ssys_state *s = opaque;
408
409 ssys_calculate_system_clock(s, false);
410
411 return 0;
412 }
413
414 static const VMStateDescription vmstate_stellaris_sys = {
415 .name = "stellaris_sys",
416 .version_id = 2,
417 .minimum_version_id = 1,
418 .post_load = stellaris_sys_post_load,
419 .fields = (VMStateField[]) {
420 VMSTATE_UINT32(pborctl, ssys_state),
421 VMSTATE_UINT32(ldopctl, ssys_state),
422 VMSTATE_UINT32(int_mask, ssys_state),
423 VMSTATE_UINT32(int_status, ssys_state),
424 VMSTATE_UINT32(resc, ssys_state),
425 VMSTATE_UINT32(rcc, ssys_state),
426 VMSTATE_UINT32_V(rcc2, ssys_state, 2),
427 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
428 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
429 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
430 VMSTATE_UINT32(clkvclr, ssys_state),
431 VMSTATE_UINT32(ldoarst, ssys_state),
432 /* No field for sysclk -- handled in post-load instead */
433 VMSTATE_END_OF_LIST()
434 }
435 };
436
437 static Property stellaris_sys_properties[] = {
438 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
439 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
440 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
441 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
442 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
443 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
444 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
445 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
446 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
447 DEFINE_PROP_END_OF_LIST()
448 };
449
450 static void stellaris_sys_instance_init(Object *obj)
451 {
452 ssys_state *s = STELLARIS_SYS(obj);
453 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
454
455 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
456 sysbus_init_mmio(sbd, &s->iomem);
457 sysbus_init_irq(sbd, &s->irq);
458 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
459 }
460
461 /* I2C controller. */
462
463 #define TYPE_STELLARIS_I2C "stellaris-i2c"
464 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
465
466 struct stellaris_i2c_state {
467 SysBusDevice parent_obj;
468
469 I2CBus *bus;
470 qemu_irq irq;
471 MemoryRegion iomem;
472 uint32_t msa;
473 uint32_t mcs;
474 uint32_t mdr;
475 uint32_t mtpr;
476 uint32_t mimr;
477 uint32_t mris;
478 uint32_t mcr;
479 };
480
481 #define STELLARIS_I2C_MCS_BUSY 0x01
482 #define STELLARIS_I2C_MCS_ERROR 0x02
483 #define STELLARIS_I2C_MCS_ADRACK 0x04
484 #define STELLARIS_I2C_MCS_DATACK 0x08
485 #define STELLARIS_I2C_MCS_ARBLST 0x10
486 #define STELLARIS_I2C_MCS_IDLE 0x20
487 #define STELLARIS_I2C_MCS_BUSBSY 0x40
488
489 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
490 unsigned size)
491 {
492 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
493
494 switch (offset) {
495 case 0x00: /* MSA */
496 return s->msa;
497 case 0x04: /* MCS */
498 /* We don't emulate timing, so the controller is never busy. */
499 return s->mcs | STELLARIS_I2C_MCS_IDLE;
500 case 0x08: /* MDR */
501 return s->mdr;
502 case 0x0c: /* MTPR */
503 return s->mtpr;
504 case 0x10: /* MIMR */
505 return s->mimr;
506 case 0x14: /* MRIS */
507 return s->mris;
508 case 0x18: /* MMIS */
509 return s->mris & s->mimr;
510 case 0x20: /* MCR */
511 return s->mcr;
512 default:
513 qemu_log_mask(LOG_GUEST_ERROR,
514 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
515 return 0;
516 }
517 }
518
519 static void stellaris_i2c_update(stellaris_i2c_state *s)
520 {
521 int level;
522
523 level = (s->mris & s->mimr) != 0;
524 qemu_set_irq(s->irq, level);
525 }
526
527 static void stellaris_i2c_write(void *opaque, hwaddr offset,
528 uint64_t value, unsigned size)
529 {
530 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
531
532 switch (offset) {
533 case 0x00: /* MSA */
534 s->msa = value & 0xff;
535 break;
536 case 0x04: /* MCS */
537 if ((s->mcr & 0x10) == 0) {
538 /* Disabled. Do nothing. */
539 break;
540 }
541 /* Grab the bus if this is starting a transfer. */
542 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
543 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
544 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
545 } else {
546 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
547 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
548 }
549 }
550 /* If we don't have the bus then indicate an error. */
551 if (!i2c_bus_busy(s->bus)
552 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
553 s->mcs |= STELLARIS_I2C_MCS_ERROR;
554 break;
555 }
556 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
557 if (value & 1) {
558 /* Transfer a byte. */
559 /* TODO: Handle errors. */
560 if (s->msa & 1) {
561 /* Recv */
562 s->mdr = i2c_recv(s->bus);
563 } else {
564 /* Send */
565 i2c_send(s->bus, s->mdr);
566 }
567 /* Raise an interrupt. */
568 s->mris |= 1;
569 }
570 if (value & 4) {
571 /* Finish transfer. */
572 i2c_end_transfer(s->bus);
573 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
574 }
575 break;
576 case 0x08: /* MDR */
577 s->mdr = value & 0xff;
578 break;
579 case 0x0c: /* MTPR */
580 s->mtpr = value & 0xff;
581 break;
582 case 0x10: /* MIMR */
583 s->mimr = 1;
584 break;
585 case 0x1c: /* MICR */
586 s->mris &= ~value;
587 break;
588 case 0x20: /* MCR */
589 if (value & 1) {
590 qemu_log_mask(LOG_UNIMP,
591 "stellaris_i2c: Loopback not implemented\n");
592 }
593 if (value & 0x20) {
594 qemu_log_mask(LOG_UNIMP,
595 "stellaris_i2c: Slave mode not implemented\n");
596 }
597 s->mcr = value & 0x31;
598 break;
599 default:
600 qemu_log_mask(LOG_GUEST_ERROR,
601 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
602 }
603 stellaris_i2c_update(s);
604 }
605
606 static void stellaris_i2c_reset(stellaris_i2c_state *s)
607 {
608 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
609 i2c_end_transfer(s->bus);
610
611 s->msa = 0;
612 s->mcs = 0;
613 s->mdr = 0;
614 s->mtpr = 1;
615 s->mimr = 0;
616 s->mris = 0;
617 s->mcr = 0;
618 stellaris_i2c_update(s);
619 }
620
621 static const MemoryRegionOps stellaris_i2c_ops = {
622 .read = stellaris_i2c_read,
623 .write = stellaris_i2c_write,
624 .endianness = DEVICE_NATIVE_ENDIAN,
625 };
626
627 static const VMStateDescription vmstate_stellaris_i2c = {
628 .name = "stellaris_i2c",
629 .version_id = 1,
630 .minimum_version_id = 1,
631 .fields = (VMStateField[]) {
632 VMSTATE_UINT32(msa, stellaris_i2c_state),
633 VMSTATE_UINT32(mcs, stellaris_i2c_state),
634 VMSTATE_UINT32(mdr, stellaris_i2c_state),
635 VMSTATE_UINT32(mtpr, stellaris_i2c_state),
636 VMSTATE_UINT32(mimr, stellaris_i2c_state),
637 VMSTATE_UINT32(mris, stellaris_i2c_state),
638 VMSTATE_UINT32(mcr, stellaris_i2c_state),
639 VMSTATE_END_OF_LIST()
640 }
641 };
642
643 static void stellaris_i2c_init(Object *obj)
644 {
645 DeviceState *dev = DEVICE(obj);
646 stellaris_i2c_state *s = STELLARIS_I2C(obj);
647 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
648 I2CBus *bus;
649
650 sysbus_init_irq(sbd, &s->irq);
651 bus = i2c_init_bus(dev, "i2c");
652 s->bus = bus;
653
654 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
655 "i2c", 0x1000);
656 sysbus_init_mmio(sbd, &s->iomem);
657 /* ??? For now we only implement the master interface. */
658 stellaris_i2c_reset(s);
659 }
660
661 /* Analogue to Digital Converter. This is only partially implemented,
662 enough for applications that use a combined ADC and timer tick. */
663
664 #define STELLARIS_ADC_EM_CONTROLLER 0
665 #define STELLARIS_ADC_EM_COMP 1
666 #define STELLARIS_ADC_EM_EXTERNAL 4
667 #define STELLARIS_ADC_EM_TIMER 5
668 #define STELLARIS_ADC_EM_PWM0 6
669 #define STELLARIS_ADC_EM_PWM1 7
670 #define STELLARIS_ADC_EM_PWM2 8
671
672 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
673 #define STELLARIS_ADC_FIFO_FULL 0x1000
674
675 #define TYPE_STELLARIS_ADC "stellaris-adc"
676 typedef struct StellarisADCState stellaris_adc_state;
677 DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
678 TYPE_STELLARIS_ADC)
679
680 struct StellarisADCState {
681 SysBusDevice parent_obj;
682
683 MemoryRegion iomem;
684 uint32_t actss;
685 uint32_t ris;
686 uint32_t im;
687 uint32_t emux;
688 uint32_t ostat;
689 uint32_t ustat;
690 uint32_t sspri;
691 uint32_t sac;
692 struct {
693 uint32_t state;
694 uint32_t data[16];
695 } fifo[4];
696 uint32_t ssmux[4];
697 uint32_t ssctl[4];
698 uint32_t noise;
699 qemu_irq irq[4];
700 };
701
702 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
703 {
704 int tail;
705
706 tail = s->fifo[n].state & 0xf;
707 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
708 s->ustat |= 1 << n;
709 } else {
710 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
711 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
712 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
713 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
714 }
715 return s->fifo[n].data[tail];
716 }
717
718 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
719 uint32_t value)
720 {
721 int head;
722
723 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
724 FIFO fir each sequencer. */
725 head = (s->fifo[n].state >> 4) & 0xf;
726 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
727 s->ostat |= 1 << n;
728 return;
729 }
730 s->fifo[n].data[head] = value;
731 head = (head + 1) & 0xf;
732 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
733 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
734 if ((s->fifo[n].state & 0xf) == head)
735 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
736 }
737
738 static void stellaris_adc_update(stellaris_adc_state *s)
739 {
740 int level;
741 int n;
742
743 for (n = 0; n < 4; n++) {
744 level = (s->ris & s->im & (1 << n)) != 0;
745 qemu_set_irq(s->irq[n], level);
746 }
747 }
748
749 static void stellaris_adc_trigger(void *opaque, int irq, int level)
750 {
751 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
752 int n;
753
754 for (n = 0; n < 4; n++) {
755 if ((s->actss & (1 << n)) == 0) {
756 continue;
757 }
758
759 if (((s->emux >> (n * 4)) & 0xff) != 5) {
760 continue;
761 }
762
763 /* Some applications use the ADC as a random number source, so introduce
764 some variation into the signal. */
765 s->noise = s->noise * 314159 + 1;
766 /* ??? actual inputs not implemented. Return an arbitrary value. */
767 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
768 s->ris |= (1 << n);
769 stellaris_adc_update(s);
770 }
771 }
772
773 static void stellaris_adc_reset(stellaris_adc_state *s)
774 {
775 int n;
776
777 for (n = 0; n < 4; n++) {
778 s->ssmux[n] = 0;
779 s->ssctl[n] = 0;
780 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
781 }
782 }
783
784 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
785 unsigned size)
786 {
787 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
788
789 /* TODO: Implement this. */
790 if (offset >= 0x40 && offset < 0xc0) {
791 int n;
792 n = (offset - 0x40) >> 5;
793 switch (offset & 0x1f) {
794 case 0x00: /* SSMUX */
795 return s->ssmux[n];
796 case 0x04: /* SSCTL */
797 return s->ssctl[n];
798 case 0x08: /* SSFIFO */
799 return stellaris_adc_fifo_read(s, n);
800 case 0x0c: /* SSFSTAT */
801 return s->fifo[n].state;
802 default:
803 break;
804 }
805 }
806 switch (offset) {
807 case 0x00: /* ACTSS */
808 return s->actss;
809 case 0x04: /* RIS */
810 return s->ris;
811 case 0x08: /* IM */
812 return s->im;
813 case 0x0c: /* ISC */
814 return s->ris & s->im;
815 case 0x10: /* OSTAT */
816 return s->ostat;
817 case 0x14: /* EMUX */
818 return s->emux;
819 case 0x18: /* USTAT */
820 return s->ustat;
821 case 0x20: /* SSPRI */
822 return s->sspri;
823 case 0x30: /* SAC */
824 return s->sac;
825 default:
826 qemu_log_mask(LOG_GUEST_ERROR,
827 "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
828 return 0;
829 }
830 }
831
832 static void stellaris_adc_write(void *opaque, hwaddr offset,
833 uint64_t value, unsigned size)
834 {
835 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
836
837 /* TODO: Implement this. */
838 if (offset >= 0x40 && offset < 0xc0) {
839 int n;
840 n = (offset - 0x40) >> 5;
841 switch (offset & 0x1f) {
842 case 0x00: /* SSMUX */
843 s->ssmux[n] = value & 0x33333333;
844 return;
845 case 0x04: /* SSCTL */
846 if (value != 6) {
847 qemu_log_mask(LOG_UNIMP,
848 "ADC: Unimplemented sequence %" PRIx64 "\n",
849 value);
850 }
851 s->ssctl[n] = value;
852 return;
853 default:
854 break;
855 }
856 }
857 switch (offset) {
858 case 0x00: /* ACTSS */
859 s->actss = value & 0xf;
860 break;
861 case 0x08: /* IM */
862 s->im = value;
863 break;
864 case 0x0c: /* ISC */
865 s->ris &= ~value;
866 break;
867 case 0x10: /* OSTAT */
868 s->ostat &= ~value;
869 break;
870 case 0x14: /* EMUX */
871 s->emux = value;
872 break;
873 case 0x18: /* USTAT */
874 s->ustat &= ~value;
875 break;
876 case 0x20: /* SSPRI */
877 s->sspri = value;
878 break;
879 case 0x28: /* PSSI */
880 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
881 break;
882 case 0x30: /* SAC */
883 s->sac = value;
884 break;
885 default:
886 qemu_log_mask(LOG_GUEST_ERROR,
887 "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
888 }
889 stellaris_adc_update(s);
890 }
891
892 static const MemoryRegionOps stellaris_adc_ops = {
893 .read = stellaris_adc_read,
894 .write = stellaris_adc_write,
895 .endianness = DEVICE_NATIVE_ENDIAN,
896 };
897
898 static const VMStateDescription vmstate_stellaris_adc = {
899 .name = "stellaris_adc",
900 .version_id = 1,
901 .minimum_version_id = 1,
902 .fields = (VMStateField[]) {
903 VMSTATE_UINT32(actss, stellaris_adc_state),
904 VMSTATE_UINT32(ris, stellaris_adc_state),
905 VMSTATE_UINT32(im, stellaris_adc_state),
906 VMSTATE_UINT32(emux, stellaris_adc_state),
907 VMSTATE_UINT32(ostat, stellaris_adc_state),
908 VMSTATE_UINT32(ustat, stellaris_adc_state),
909 VMSTATE_UINT32(sspri, stellaris_adc_state),
910 VMSTATE_UINT32(sac, stellaris_adc_state),
911 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
912 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
913 VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
914 VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
915 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
916 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
917 VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
918 VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
919 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
920 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
921 VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
922 VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
923 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
924 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
925 VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
926 VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
927 VMSTATE_UINT32(noise, stellaris_adc_state),
928 VMSTATE_END_OF_LIST()
929 }
930 };
931
932 static void stellaris_adc_init(Object *obj)
933 {
934 DeviceState *dev = DEVICE(obj);
935 stellaris_adc_state *s = STELLARIS_ADC(obj);
936 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
937 int n;
938
939 for (n = 0; n < 4; n++) {
940 sysbus_init_irq(sbd, &s->irq[n]);
941 }
942
943 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
944 "adc", 0x1000);
945 sysbus_init_mmio(sbd, &s->iomem);
946 stellaris_adc_reset(s);
947 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
948 }
949
950 /* Board init. */
951 static stellaris_board_info stellaris_boards[] = {
952 { "LM3S811EVB",
953 0,
954 0x0032000e,
955 0x001f001f, /* dc0 */
956 0x001132bf,
957 0x01071013,
958 0x3f0f01ff,
959 0x0000001f,
960 BP_OLED_I2C
961 },
962 { "LM3S6965EVB",
963 0x10010002,
964 0x1073402e,
965 0x00ff007f, /* dc0 */
966 0x001133ff,
967 0x030f5317,
968 0x0f0f87ff,
969 0x5000007f,
970 BP_OLED_SSI | BP_GAMEPAD
971 }
972 };
973
974 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
975 {
976 static const int uart_irq[] = {5, 6, 33, 34};
977 static const int timer_irq[] = {19, 21, 23, 35};
978 static const uint32_t gpio_addr[7] =
979 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
980 0x40024000, 0x40025000, 0x40026000};
981 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
982
983 /* Memory map of SoC devices, from
984 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
985 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
986 *
987 * 40000000 wdtimer
988 * 40002000 i2c (unimplemented)
989 * 40004000 GPIO
990 * 40005000 GPIO
991 * 40006000 GPIO
992 * 40007000 GPIO
993 * 40008000 SSI
994 * 4000c000 UART
995 * 4000d000 UART
996 * 4000e000 UART
997 * 40020000 i2c
998 * 40021000 i2c (unimplemented)
999 * 40024000 GPIO
1000 * 40025000 GPIO
1001 * 40026000 GPIO
1002 * 40028000 PWM (unimplemented)
1003 * 4002c000 QEI (unimplemented)
1004 * 4002d000 QEI (unimplemented)
1005 * 40030000 gptimer
1006 * 40031000 gptimer
1007 * 40032000 gptimer
1008 * 40033000 gptimer
1009 * 40038000 ADC
1010 * 4003c000 analogue comparator (unimplemented)
1011 * 40048000 ethernet
1012 * 400fc000 hibernation module (unimplemented)
1013 * 400fd000 flash memory control (unimplemented)
1014 * 400fe000 system control
1015 */
1016
1017 DeviceState *gpio_dev[7], *nvic;
1018 qemu_irq gpio_in[7][8];
1019 qemu_irq gpio_out[7][8];
1020 qemu_irq adc;
1021 int sram_size;
1022 int flash_size;
1023 I2CBus *i2c;
1024 DeviceState *dev;
1025 DeviceState *ssys_dev;
1026 int i;
1027 int j;
1028 const uint8_t *macaddr;
1029
1030 MemoryRegion *sram = g_new(MemoryRegion, 1);
1031 MemoryRegion *flash = g_new(MemoryRegion, 1);
1032 MemoryRegion *system_memory = get_system_memory();
1033
1034 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1035 sram_size = ((board->dc0 >> 18) + 1) * 1024;
1036
1037 /* Flash programming is done via the SCU, so pretend it is ROM. */
1038 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1039 &error_fatal);
1040 memory_region_add_subregion(system_memory, 0, flash);
1041
1042 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1043 &error_fatal);
1044 memory_region_add_subregion(system_memory, 0x20000000, sram);
1045
1046 /*
1047 * Create the system-registers object early, because we will
1048 * need its sysclk output.
1049 */
1050 ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
1051 /* Most devices come preprogrammed with a MAC address in the user data. */
1052 macaddr = nd_table[0].macaddr.a;
1053 qdev_prop_set_uint32(ssys_dev, "user0",
1054 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
1055 qdev_prop_set_uint32(ssys_dev, "user1",
1056 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
1057 qdev_prop_set_uint32(ssys_dev, "did0", board->did0);
1058 qdev_prop_set_uint32(ssys_dev, "did1", board->did1);
1059 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0);
1060 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1);
1061 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2);
1062 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3);
1063 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
1064 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
1065
1066 nvic = qdev_new(TYPE_ARMV7M);
1067 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1068 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1069 qdev_prop_set_bit(nvic, "enable-bitband", true);
1070 qdev_connect_clock_in(nvic, "cpuclk",
1071 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1072 /* This SoC does not connect the systick reference clock */
1073 object_property_set_link(OBJECT(nvic), "memory",
1074 OBJECT(get_system_memory()), &error_abort);
1075 /* This will exit with an error if the user passed us a bad cpu_type */
1076 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1077
1078 /* Now we can wire up the IRQ and MMIO of the system registers */
1079 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
1080 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));
1081
1082 if (board->dc1 & (1 << 16)) {
1083 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1084 qdev_get_gpio_in(nvic, 14),
1085 qdev_get_gpio_in(nvic, 15),
1086 qdev_get_gpio_in(nvic, 16),
1087 qdev_get_gpio_in(nvic, 17),
1088 NULL);
1089 adc = qdev_get_gpio_in(dev, 0);
1090 } else {
1091 adc = NULL;
1092 }
1093 for (i = 0; i < 4; i++) {
1094 if (board->dc2 & (0x10000 << i)) {
1095 SysBusDevice *sbd;
1096
1097 dev = qdev_new(TYPE_STELLARIS_GPTM);
1098 sbd = SYS_BUS_DEVICE(dev);
1099 qdev_connect_clock_in(dev, "clk",
1100 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1101 sysbus_realize_and_unref(sbd, &error_fatal);
1102 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000);
1103 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
1104 /* TODO: This is incorrect, but we get away with it because
1105 the ADC output is only ever pulsed. */
1106 qdev_connect_gpio_out(dev, 0, adc);
1107 }
1108 }
1109
1110 if (board->dc1 & (1 << 3)) { /* watchdog present */
1111 dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1112
1113 qdev_connect_clock_in(dev, "WDOGCLK",
1114 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1115
1116 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1117 sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1118 0,
1119 0x40000000u);
1120 sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1121 0,
1122 qdev_get_gpio_in(nvic, 18));
1123 }
1124
1125
1126 for (i = 0; i < 7; i++) {
1127 if (board->dc4 & (1 << i)) {
1128 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1129 qdev_get_gpio_in(nvic,
1130 gpio_irq[i]));
1131 for (j = 0; j < 8; j++) {
1132 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1133 gpio_out[i][j] = NULL;
1134 }
1135 }
1136 }
1137
1138 if (board->dc2 & (1 << 12)) {
1139 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1140 qdev_get_gpio_in(nvic, 8));
1141 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1142 if (board->peripherals & BP_OLED_I2C) {
1143 i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1144 }
1145 }
1146
1147 for (i = 0; i < 4; i++) {
1148 if (board->dc2 & (1 << i)) {
1149 pl011_luminary_create(0x4000c000 + i * 0x1000,
1150 qdev_get_gpio_in(nvic, uart_irq[i]),
1151 serial_hd(i));
1152 }
1153 }
1154 if (board->dc2 & (1 << 4)) {
1155 dev = sysbus_create_simple("pl022", 0x40008000,
1156 qdev_get_gpio_in(nvic, 7));
1157 if (board->peripherals & BP_OLED_SSI) {
1158 void *bus;
1159 DeviceState *sddev;
1160 DeviceState *ssddev;
1161 DriveInfo *dinfo;
1162 DeviceState *carddev;
1163 BlockBackend *blk;
1164
1165 /*
1166 * Some boards have both an OLED controller and SD card connected to
1167 * the same SSI port, with the SD card chip select connected to a
1168 * GPIO pin. Technically the OLED chip select is connected to the
1169 * SSI Fss pin. We do not bother emulating that as both devices
1170 * should never be selected simultaneously, and our OLED controller
1171 * ignores stray 0xff commands that occur when deselecting the SD
1172 * card.
1173 *
1174 * The h/w wiring is:
1175 * - GPIO pin D0 is wired to the active-low SD card chip select
1176 * - GPIO pin A3 is wired to the active-low OLED chip select
1177 * - The SoC wiring of the PL061 "auxiliary function" for A3 is
1178 * SSI0Fss ("frame signal"), which is an output from the SoC's
1179 * SSI controller. The SSI controller takes SSI0Fss low when it
1180 * transmits a frame, so it can work as a chip-select signal.
1181 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
1182 * (the OLED never sends data to the CPU, so no wiring needed)
1183 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
1184 * and the OLED display-data-in
1185 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
1186 * serial-clock input
1187 * So a guest that wants to use the OLED can configure the PL061
1188 * to make pins A2, A3, A5 aux-function, so they are connected
1189 * directly to the SSI controller. When the SSI controller sends
1190 * data it asserts SSI0Fss which selects the OLED.
1191 * A guest that wants to use the SD card configures A2, A4 and A5
1192 * as aux-function, but leaves A3 as a software-controlled GPIO
1193 * line. It asserts the SD card chip-select by using the PL061
1194 * to control pin D0, and lets the SSI controller handle Clk, Tx
1195 * and Rx. (The SSI controller asserts Fss during tx cycles as
1196 * usual, but because A3 is not set to aux-function this is not
1197 * forwarded to the OLED, and so the OLED stays unselected.)
1198 *
1199 * The QEMU implementation instead is:
1200 * - GPIO pin D0 is wired to the active-low SD card chip select,
1201 * and also to the OLED chip-select which is implemented
1202 * as *active-high*
1203 * - SSI controller signals go to the devices regardless of
1204 * whether the guest programs A2, A4, A5 as aux-function or not
1205 *
1206 * The problem with this implementation is if the guest doesn't
1207 * care about the SD card and only uses the OLED. In that case it
1208 * may choose never to do anything with D0 (leaving it in its
1209 * default floating state, which reliably leaves the card disabled
1210 * because an SD card has a pullup on CS within the card itself),
1211 * and only set up A2, A3, A5. This for us would mean the OLED
1212 * never gets the chip-select assert it needs. We work around
1213 * this with a manual raise of D0 here (despite board creation
1214 * code being the wrong place to raise IRQ lines) to put the OLED
1215 * into an initially selected state.
1216 *
1217 * In theory the right way to model this would be:
1218 * - Implement aux-function support in the PL061, with an
1219 * extra set of AFIN and AFOUT GPIO lines (set up so that
1220 * if a GPIO line is in auxfn mode the main GPIO in and out
1221 * track the AFIN and AFOUT lines)
1222 * - Wire the AFOUT for D0 up to either a line from the
1223 * SSI controller that's pulled low around every transmit,
1224 * or at least to an always-0 line here on the board
1225 * - Make the ssd0323 OLED controller chipselect active-low
1226 */
1227 bus = qdev_get_child_bus(dev, "ssi");
1228 sddev = ssi_create_peripheral(bus, "ssi-sd");
1229
1230 dinfo = drive_get(IF_SD, 0, 0);
1231 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
1232 carddev = qdev_new(TYPE_SD_CARD);
1233 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
1234 qdev_prop_set_bit(carddev, "spi", true);
1235 qdev_realize_and_unref(carddev,
1236 qdev_get_child_bus(sddev, "sd-bus"),
1237 &error_fatal);
1238
1239 ssddev = ssi_create_peripheral(bus, "ssd0323");
1240 gpio_out[GPIO_D][0] = qemu_irq_split(
1241 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1242 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1243 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1244
1245 /* Make sure the select pin is high. */
1246 qemu_irq_raise(gpio_out[GPIO_D][0]);
1247 }
1248 }
1249 if (board->dc4 & (1 << 28)) {
1250 DeviceState *enet;
1251
1252 qemu_check_nic_model(&nd_table[0], "stellaris");
1253
1254 enet = qdev_new("stellaris_enet");
1255 qdev_set_nic_properties(enet, &nd_table[0]);
1256 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1257 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1258 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1259 }
1260 if (board->peripherals & BP_GAMEPAD) {
1261 qemu_irq gpad_irq[5];
1262 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1263
1264 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1265 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1266 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1267 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1268 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1269
1270 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1271 }
1272 for (i = 0; i < 7; i++) {
1273 if (board->dc4 & (1 << i)) {
1274 for (j = 0; j < 8; j++) {
1275 if (gpio_out[i][j]) {
1276 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1277 }
1278 }
1279 }
1280 }
1281
1282 /* Add dummy regions for the devices we don't implement yet,
1283 * so guest accesses don't cause unlogged crashes.
1284 */
1285 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1286 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1287 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1288 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1289 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1290 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1291 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1292 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1293
1294 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1295 }
1296
1297 /* FIXME: Figure out how to generate these from stellaris_boards. */
1298 static void lm3s811evb_init(MachineState *machine)
1299 {
1300 stellaris_init(machine, &stellaris_boards[0]);
1301 }
1302
1303 static void lm3s6965evb_init(MachineState *machine)
1304 {
1305 stellaris_init(machine, &stellaris_boards[1]);
1306 }
1307
1308 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1309 {
1310 MachineClass *mc = MACHINE_CLASS(oc);
1311
1312 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
1313 mc->init = lm3s811evb_init;
1314 mc->ignore_memory_transaction_failures = true;
1315 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1316 }
1317
1318 static const TypeInfo lm3s811evb_type = {
1319 .name = MACHINE_TYPE_NAME("lm3s811evb"),
1320 .parent = TYPE_MACHINE,
1321 .class_init = lm3s811evb_class_init,
1322 };
1323
1324 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1325 {
1326 MachineClass *mc = MACHINE_CLASS(oc);
1327
1328 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
1329 mc->init = lm3s6965evb_init;
1330 mc->ignore_memory_transaction_failures = true;
1331 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1332 }
1333
1334 static const TypeInfo lm3s6965evb_type = {
1335 .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1336 .parent = TYPE_MACHINE,
1337 .class_init = lm3s6965evb_class_init,
1338 };
1339
1340 static void stellaris_machine_init(void)
1341 {
1342 type_register_static(&lm3s811evb_type);
1343 type_register_static(&lm3s6965evb_type);
1344 }
1345
1346 type_init(stellaris_machine_init)
1347
1348 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1349 {
1350 DeviceClass *dc = DEVICE_CLASS(klass);
1351
1352 dc->vmsd = &vmstate_stellaris_i2c;
1353 }
1354
1355 static const TypeInfo stellaris_i2c_info = {
1356 .name = TYPE_STELLARIS_I2C,
1357 .parent = TYPE_SYS_BUS_DEVICE,
1358 .instance_size = sizeof(stellaris_i2c_state),
1359 .instance_init = stellaris_i2c_init,
1360 .class_init = stellaris_i2c_class_init,
1361 };
1362
1363 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1364 {
1365 DeviceClass *dc = DEVICE_CLASS(klass);
1366
1367 dc->vmsd = &vmstate_stellaris_adc;
1368 }
1369
1370 static const TypeInfo stellaris_adc_info = {
1371 .name = TYPE_STELLARIS_ADC,
1372 .parent = TYPE_SYS_BUS_DEVICE,
1373 .instance_size = sizeof(stellaris_adc_state),
1374 .instance_init = stellaris_adc_init,
1375 .class_init = stellaris_adc_class_init,
1376 };
1377
1378 static void stellaris_sys_class_init(ObjectClass *klass, void *data)
1379 {
1380 DeviceClass *dc = DEVICE_CLASS(klass);
1381 ResettableClass *rc = RESETTABLE_CLASS(klass);
1382
1383 dc->vmsd = &vmstate_stellaris_sys;
1384 rc->phases.enter = stellaris_sys_reset_enter;
1385 rc->phases.hold = stellaris_sys_reset_hold;
1386 rc->phases.exit = stellaris_sys_reset_exit;
1387 device_class_set_props(dc, stellaris_sys_properties);
1388 }
1389
1390 static const TypeInfo stellaris_sys_info = {
1391 .name = TYPE_STELLARIS_SYS,
1392 .parent = TYPE_SYS_BUS_DEVICE,
1393 .instance_size = sizeof(ssys_state),
1394 .instance_init = stellaris_sys_instance_init,
1395 .class_init = stellaris_sys_class_init,
1396 };
1397
1398 static void stellaris_register_types(void)
1399 {
1400 type_register_static(&stellaris_i2c_info);
1401 type_register_static(&stellaris_adc_info);
1402 type_register_static(&stellaris_sys_info);
1403 }
1404
1405 type_init(stellaris_register_types)
armbru's QEMU hackery