2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "kvm-consts.h"
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
29 # define ELF_MACHINE EM_AARCH64
31 # define TARGET_LONG_BITS 32
32 # define ELF_MACHINE EM_ARM
35 #define TARGET_IS_BIENDIAN 1
37 #define CPUArchState struct CPUARMState
39 #include "qemu-common.h"
40 #include "exec/cpu-defs.h"
42 #include "fpu/softfloat.h"
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
54 #define EXCP_HVC 11 /* HyperVisor Call */
55 #define EXCP_HYP_TRAP 12
56 #define EXCP_SMC 13 /* Secure Monitor Call */
60 #define ARMV7M_EXCP_RESET 1
61 #define ARMV7M_EXCP_NMI 2
62 #define ARMV7M_EXCP_HARD 3
63 #define ARMV7M_EXCP_MEM 4
64 #define ARMV7M_EXCP_BUS 5
65 #define ARMV7M_EXCP_USAGE 6
66 #define ARMV7M_EXCP_SVC 11
67 #define ARMV7M_EXCP_DEBUG 12
68 #define ARMV7M_EXCP_PENDSV 14
69 #define ARMV7M_EXCP_SYSTICK 15
71 /* ARM-specific interrupt pending bits. */
72 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
73 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
74 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
76 /* The usual mapping for an AArch64 system register to its AArch32
77 * counterpart is for the 32 bit world to have access to the lower
78 * half only (with writes leaving the upper half untouched). It's
79 * therefore useful to be able to pass TCG the offset of the least
80 * significant half of a uint64_t struct member.
82 #ifdef HOST_WORDS_BIGENDIAN
83 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
84 #define offsetofhigh32(S, M) offsetof(S, M)
86 #define offsetoflow32(S, M) offsetof(S, M)
87 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
90 /* Meanings of the ARMCPU object's four inbound GPIO lines */
93 #define ARM_CPU_VIRQ 2
94 #define ARM_CPU_VFIQ 3
98 #define NB_MMU_MODES 7
100 /* We currently assume float and double are IEEE single and double
101 precision respectively.
102 Doing runtime conversions is tricky because VFP registers may contain
103 integer values (eg. as the result of a FTOSI instruction).
104 s<2n> maps to the least significant half of d<n>
105 s<2n+1> maps to the most significant half of d<n>
108 /* CPU state for each instance of a generic timer (in cp15 c14) */
109 typedef struct ARMGenericTimer
{
110 uint64_t cval
; /* Timer CompareValue register */
111 uint64_t ctl
; /* Timer Control register */
114 #define GTIMER_PHYS 0
115 #define GTIMER_VIRT 1
116 #define NUM_GTIMERS 2
124 typedef struct CPUARMState
{
125 /* Regs for current mode. */
128 /* 32/64 switch only happens when taking and returning from
129 * exceptions so the overlap semantics are taken care of then
130 * instead of having a complicated union.
132 /* Regs for A64 mode. */
135 /* PSTATE isn't an architectural register for ARMv8. However, it is
136 * convenient for us to assemble the underlying state into a 32 bit format
137 * identical to the architectural format used for the SPSR. (This is also
138 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
139 * 'pstate' register are.) Of the PSTATE bits:
140 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
141 * semantics as for AArch32, as described in the comments on each field)
142 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
143 * DAIF (exception masks) are kept in env->daif
144 * all other bits are stored in their correct places in env->pstate
147 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
149 /* Frequently accessed CPSR bits are stored separately for efficiency.
150 This contains all the other bits. Use cpsr_{read,write} to access
152 uint32_t uncached_cpsr
;
155 /* Banked registers. */
156 uint64_t banked_spsr
[8];
157 uint32_t banked_r13
[8];
158 uint32_t banked_r14
[8];
160 /* These hold r8-r12. */
161 uint32_t usr_regs
[5];
162 uint32_t fiq_regs
[5];
164 /* cpsr flag cache for faster execution */
165 uint32_t CF
; /* 0 or 1 */
166 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
167 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
168 uint32_t ZF
; /* Z set if zero. */
169 uint32_t QF
; /* 0 or 1 */
170 uint32_t GE
; /* cpsr[19:16] */
171 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
172 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
173 uint64_t daif
; /* exception masks, in the bits they are in in PSTATE */
175 uint64_t elr_el
[4]; /* AArch64 exception link regs */
176 uint64_t sp_el
[4]; /* AArch64 banked stack pointers */
178 /* System control coprocessor (cp15) */
181 union { /* Cache size selection */
183 uint64_t _unused_csselr0
;
185 uint64_t _unused_csselr1
;
188 uint64_t csselr_el
[4];
190 union { /* System control register. */
192 uint64_t _unused_sctlr
;
197 uint64_t sctlr_el
[4];
199 uint64_t cpacr_el1
; /* Architectural feature access control register */
200 uint64_t cptr_el
[4]; /* ARMv8 feature trap registers */
201 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
202 uint64_t sder
; /* Secure debug enable register. */
203 uint32_t nsacr
; /* Non-secure access control register. */
204 union { /* MMU translation table base 0. */
206 uint64_t _unused_ttbr0_0
;
208 uint64_t _unused_ttbr0_1
;
211 uint64_t ttbr0_el
[4];
213 union { /* MMU translation table base 1. */
215 uint64_t _unused_ttbr1_0
;
217 uint64_t _unused_ttbr1_1
;
220 uint64_t ttbr1_el
[4];
222 /* MMU translation table base control. */
224 uint32_t c2_data
; /* MPU data cachable bits. */
225 uint32_t c2_insn
; /* MPU instruction cachable bits. */
226 union { /* MMU domain access control register
227 * MPU write buffer control.
237 uint32_t pmsav5_data_ap
; /* PMSAv5 MPU data access permissions */
238 uint32_t pmsav5_insn_ap
; /* PMSAv5 MPU insn access permissions */
239 uint64_t hcr_el2
; /* Hypervisor configuration register */
240 uint64_t scr_el3
; /* Secure configuration register. */
241 union { /* Fault status registers. */
252 uint64_t _unused_dfsr
;
259 uint32_t c6_region
[8]; /* MPU base/size registers. */
260 union { /* Fault address registers. */
262 uint64_t _unused_far0
;
263 #ifdef HOST_WORDS_BIGENDIAN
274 uint64_t _unused_far3
;
278 union { /* Translation result. */
280 uint64_t _unused_par_0
;
282 uint64_t _unused_par_1
;
290 uint32_t c9_insn
; /* Cache lockdown registers. */
292 uint64_t c9_pmcr
; /* performance monitor control register */
293 uint64_t c9_pmcnten
; /* perf monitor counter enables */
294 uint32_t c9_pmovsr
; /* perf monitor overflow status */
295 uint32_t c9_pmxevtyper
; /* perf monitor event type */
296 uint32_t c9_pmuserenr
; /* perf monitor user enable */
297 uint32_t c9_pminten
; /* perf monitor interrupt enables */
298 union { /* Memory attribute redirection */
300 #ifdef HOST_WORDS_BIGENDIAN
301 uint64_t _unused_mair_0
;
304 uint64_t _unused_mair_1
;
308 uint64_t _unused_mair_0
;
311 uint64_t _unused_mair_1
;
318 union { /* vector base address register */
320 uint64_t _unused_vbar
;
327 uint32_t mvbar
; /* (monitor) vector base address register */
328 struct { /* FCSE PID. */
332 union { /* Context ID. */
334 uint64_t _unused_contextidr_0
;
335 uint64_t contextidr_ns
;
336 uint64_t _unused_contextidr_1
;
337 uint64_t contextidr_s
;
339 uint64_t contextidr_el
[4];
341 union { /* User RW Thread register. */
343 uint64_t tpidrurw_ns
;
344 uint64_t tpidrprw_ns
;
348 uint64_t tpidr_el
[4];
350 /* The secure banks of these registers don't map anywhere */
355 union { /* User RO Thread register. */
356 uint64_t tpidruro_ns
;
357 uint64_t tpidrro_el
[1];
359 uint64_t c14_cntfrq
; /* Counter Frequency register */
360 uint64_t c14_cntkctl
; /* Timer Control register */
361 uint64_t cntvoff_el2
; /* Counter Virtual Offset register */
362 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
363 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
364 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
365 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
366 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
367 uint32_t c15_threadid
; /* TI debugger thread-ID. */
368 uint32_t c15_config_base_address
; /* SCU base address. */
369 uint32_t c15_diagnostic
; /* diagnostic register */
370 uint32_t c15_power_diagnostic
;
371 uint32_t c15_power_control
; /* power control */
372 uint64_t dbgbvr
[16]; /* breakpoint value registers */
373 uint64_t dbgbcr
[16]; /* breakpoint control registers */
374 uint64_t dbgwvr
[16]; /* watchpoint value registers */
375 uint64_t dbgwcr
[16]; /* watchpoint control registers */
377 /* If the counter is enabled, this stores the last time the counter
378 * was reset. Otherwise it stores the counter value
381 uint64_t pmccfiltr_el0
; /* Performance Monitor Filter Register */
393 /* Information associated with an exception about to be taken:
394 * code which raises an exception must set cs->exception_index and
395 * the relevant parts of this structure; the cpu_do_interrupt function
396 * will then set the guest-visible registers as part of the exception
400 uint32_t syndrome
; /* AArch64 format syndrome register */
401 uint32_t fsr
; /* AArch32 format fault status register info */
402 uint64_t vaddress
; /* virtual addr associated with exception, if any */
403 uint32_t target_el
; /* EL the exception should be targeted for */
404 /* If we implement EL2 we will also need to store information
405 * about the intermediate physical address for stage 2 faults.
409 /* Thumb-2 EE state. */
413 /* VFP coprocessor state. */
415 /* VFP/Neon register state. Note that the mapping between S, D and Q
416 * views of the register bank differs between AArch64 and AArch32:
418 * Qn = regs[2n+1]:regs[2n]
420 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
421 * (and regs[32] to regs[63] are inaccessible)
423 * Qn = regs[2n+1]:regs[2n]
425 * Sn = regs[2n] bits 31..0
426 * This corresponds to the architecturally defined mapping between
427 * the two execution states, and means we do not need to explicitly
428 * map these registers when changing states.
433 /* We store these fpcsr fields separately for convenience. */
437 /* scratch space when Tn are not sufficient. */
440 /* fp_status is the "normal" fp status. standard_fp_status retains
441 * values corresponding to the ARM "Standard FPSCR Value", ie
442 * default-NaN, flush-to-zero, round-to-nearest and is used by
443 * any operations (generally Neon) which the architecture defines
444 * as controlled by the standard FPSCR value rather than the FPSCR.
446 * To avoid having to transfer exception bits around, we simply
447 * say that the FPSCR cumulative exception flags are the logical
448 * OR of the flags in the two fp statuses. This relies on the
449 * only thing which needs to read the exception flags being
450 * an explicit FPSCR read.
452 float_status fp_status
;
453 float_status standard_fp_status
;
455 uint64_t exclusive_addr
;
456 uint64_t exclusive_val
;
457 uint64_t exclusive_high
;
458 #if defined(CONFIG_USER_ONLY)
459 uint64_t exclusive_test
;
460 uint32_t exclusive_info
;
463 /* iwMMXt coprocessor state. */
471 /* For mixed endian mode. */
474 #if defined(CONFIG_USER_ONLY)
475 /* For usermode syscall translation. */
479 struct CPUBreakpoint
*cpu_breakpoint
[16];
480 struct CPUWatchpoint
*cpu_watchpoint
[16];
484 /* These fields after the common ones so they are preserved on reset. */
486 /* Internal CPU feature flags. */
497 const struct arm_boot_info
*boot_info
;
502 ARMCPU
*cpu_arm_init(const char *cpu_model
);
503 int cpu_arm_exec(CPUState
*cpu
);
504 uint32_t do_arm_semihosting(CPUARMState
*env
);
505 void aarch64_sync_32_to_64(CPUARMState
*env
);
506 void aarch64_sync_64_to_32(CPUARMState
*env
);
508 static inline bool is_a64(CPUARMState
*env
)
513 /* you can call this signal handler from your SIGBUS and SIGSEGV
514 signal handlers to inform the virtual CPU of exceptions. non zero
515 is returned if the signal was handled by the virtual CPU. */
516 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
523 * Synchronises the counter in the PMCCNTR. This must always be called twice,
524 * once before any action that might affect the timer and again afterwards.
525 * The function is used to swap the state of the register if required.
526 * This only happens when not in user mode (!CONFIG_USER_ONLY)
528 void pmccntr_sync(CPUARMState
*env
);
530 /* SCTLR bit meanings. Several bits have been reused in newer
531 * versions of the architecture; in that case we define constants
532 * for both old and new bit meanings. Code which tests against those
533 * bits should probably check or otherwise arrange that the CPU
534 * is the architectural version it expects.
536 #define SCTLR_M (1U << 0)
537 #define SCTLR_A (1U << 1)
538 #define SCTLR_C (1U << 2)
539 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
540 #define SCTLR_SA (1U << 3)
541 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
542 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
543 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
544 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
545 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
546 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
547 #define SCTLR_ITD (1U << 7) /* v8 onward */
548 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
549 #define SCTLR_SED (1U << 8) /* v8 onward */
550 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
551 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
552 #define SCTLR_F (1U << 10) /* up to v6 */
553 #define SCTLR_SW (1U << 10) /* v7 onward */
554 #define SCTLR_Z (1U << 11)
555 #define SCTLR_I (1U << 12)
556 #define SCTLR_V (1U << 13)
557 #define SCTLR_RR (1U << 14) /* up to v7 */
558 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
559 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
560 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
561 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
562 #define SCTLR_nTWI (1U << 16) /* v8 onward */
563 #define SCTLR_HA (1U << 17)
564 #define SCTLR_BR (1U << 17) /* PMSA only */
565 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
566 #define SCTLR_nTWE (1U << 18) /* v8 onward */
567 #define SCTLR_WXN (1U << 19)
568 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
569 #define SCTLR_UWXN (1U << 20) /* v7 onward */
570 #define SCTLR_FI (1U << 21)
571 #define SCTLR_U (1U << 22)
572 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
573 #define SCTLR_VE (1U << 24) /* up to v7 */
574 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
575 #define SCTLR_EE (1U << 25)
576 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
577 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
578 #define SCTLR_NMFI (1U << 27)
579 #define SCTLR_TRE (1U << 28)
580 #define SCTLR_AFE (1U << 29)
581 #define SCTLR_TE (1U << 30)
583 #define CPTR_TCPAC (1U << 31)
584 #define CPTR_TTA (1U << 20)
585 #define CPTR_TFP (1U << 10)
587 #define CPSR_M (0x1fU)
588 #define CPSR_T (1U << 5)
589 #define CPSR_F (1U << 6)
590 #define CPSR_I (1U << 7)
591 #define CPSR_A (1U << 8)
592 #define CPSR_E (1U << 9)
593 #define CPSR_IT_2_7 (0xfc00U)
594 #define CPSR_GE (0xfU << 16)
595 #define CPSR_IL (1U << 20)
596 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
597 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
598 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
599 * where it is live state but not accessible to the AArch32 code.
601 #define CPSR_RESERVED (0x7U << 21)
602 #define CPSR_J (1U << 24)
603 #define CPSR_IT_0_1 (3U << 25)
604 #define CPSR_Q (1U << 27)
605 #define CPSR_V (1U << 28)
606 #define CPSR_C (1U << 29)
607 #define CPSR_Z (1U << 30)
608 #define CPSR_N (1U << 31)
609 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
610 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
612 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
613 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
615 /* Bits writable in user mode. */
616 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
617 /* Execution state bits. MRS read as zero, MSR writes ignored. */
618 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
619 /* Mask of bits which may be set by exception return copying them from SPSR */
620 #define CPSR_ERET_MASK (~CPSR_RESERVED)
622 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
623 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
624 #define TTBCR_PD0 (1U << 4)
625 #define TTBCR_PD1 (1U << 5)
626 #define TTBCR_EPD0 (1U << 7)
627 #define TTBCR_IRGN0 (3U << 8)
628 #define TTBCR_ORGN0 (3U << 10)
629 #define TTBCR_SH0 (3U << 12)
630 #define TTBCR_T1SZ (3U << 16)
631 #define TTBCR_A1 (1U << 22)
632 #define TTBCR_EPD1 (1U << 23)
633 #define TTBCR_IRGN1 (3U << 24)
634 #define TTBCR_ORGN1 (3U << 26)
635 #define TTBCR_SH1 (1U << 28)
636 #define TTBCR_EAE (1U << 31)
638 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
639 * Only these are valid when in AArch64 mode; in
640 * AArch32 mode SPSRs are basically CPSR-format.
642 #define PSTATE_SP (1U)
643 #define PSTATE_M (0xFU)
644 #define PSTATE_nRW (1U << 4)
645 #define PSTATE_F (1U << 6)
646 #define PSTATE_I (1U << 7)
647 #define PSTATE_A (1U << 8)
648 #define PSTATE_D (1U << 9)
649 #define PSTATE_IL (1U << 20)
650 #define PSTATE_SS (1U << 21)
651 #define PSTATE_V (1U << 28)
652 #define PSTATE_C (1U << 29)
653 #define PSTATE_Z (1U << 30)
654 #define PSTATE_N (1U << 31)
655 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
656 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
657 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
658 /* Mode values for AArch64 */
659 #define PSTATE_MODE_EL3h 13
660 #define PSTATE_MODE_EL3t 12
661 #define PSTATE_MODE_EL2h 9
662 #define PSTATE_MODE_EL2t 8
663 #define PSTATE_MODE_EL1h 5
664 #define PSTATE_MODE_EL1t 4
665 #define PSTATE_MODE_EL0t 0
667 /* Map EL and handler into a PSTATE_MODE. */
668 static inline unsigned int aarch64_pstate_mode(unsigned int el
, bool handler
)
670 return (el
<< 2) | handler
;
673 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
674 * interprocessing, so we don't attempt to sync with the cpsr state used by
675 * the 32 bit decoder.
677 static inline uint32_t pstate_read(CPUARMState
*env
)
682 return (env
->NF
& 0x80000000) | (ZF
<< 30)
683 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
684 | env
->pstate
| env
->daif
;
687 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
689 env
->ZF
= (~val
) & PSTATE_Z
;
691 env
->CF
= (val
>> 29) & 1;
692 env
->VF
= (val
<< 3) & 0x80000000;
693 env
->daif
= val
& PSTATE_DAIF
;
694 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
697 /* Return the current CPSR value. */
698 uint32_t cpsr_read(CPUARMState
*env
);
699 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
700 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
);
702 /* Return the current xPSR value. */
703 static inline uint32_t xpsr_read(CPUARMState
*env
)
707 return (env
->NF
& 0x80000000) | (ZF
<< 30)
708 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
709 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
710 | ((env
->condexec_bits
& 0xfc) << 8)
711 | env
->v7m
.exception
;
714 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
715 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
717 if (mask
& CPSR_NZCV
) {
718 env
->ZF
= (~val
) & CPSR_Z
;
720 env
->CF
= (val
>> 29) & 1;
721 env
->VF
= (val
<< 3) & 0x80000000;
724 env
->QF
= ((val
& CPSR_Q
) != 0);
725 if (mask
& (1 << 24))
726 env
->thumb
= ((val
& (1 << 24)) != 0);
727 if (mask
& CPSR_IT_0_1
) {
728 env
->condexec_bits
&= ~3;
729 env
->condexec_bits
|= (val
>> 25) & 3;
731 if (mask
& CPSR_IT_2_7
) {
732 env
->condexec_bits
&= 3;
733 env
->condexec_bits
|= (val
>> 8) & 0xfc;
736 env
->v7m
.exception
= val
& 0x1ff;
740 #define HCR_VM (1ULL << 0)
741 #define HCR_SWIO (1ULL << 1)
742 #define HCR_PTW (1ULL << 2)
743 #define HCR_FMO (1ULL << 3)
744 #define HCR_IMO (1ULL << 4)
745 #define HCR_AMO (1ULL << 5)
746 #define HCR_VF (1ULL << 6)
747 #define HCR_VI (1ULL << 7)
748 #define HCR_VSE (1ULL << 8)
749 #define HCR_FB (1ULL << 9)
750 #define HCR_BSU_MASK (3ULL << 10)
751 #define HCR_DC (1ULL << 12)
752 #define HCR_TWI (1ULL << 13)
753 #define HCR_TWE (1ULL << 14)
754 #define HCR_TID0 (1ULL << 15)
755 #define HCR_TID1 (1ULL << 16)
756 #define HCR_TID2 (1ULL << 17)
757 #define HCR_TID3 (1ULL << 18)
758 #define HCR_TSC (1ULL << 19)
759 #define HCR_TIDCP (1ULL << 20)
760 #define HCR_TACR (1ULL << 21)
761 #define HCR_TSW (1ULL << 22)
762 #define HCR_TPC (1ULL << 23)
763 #define HCR_TPU (1ULL << 24)
764 #define HCR_TTLB (1ULL << 25)
765 #define HCR_TVM (1ULL << 26)
766 #define HCR_TGE (1ULL << 27)
767 #define HCR_TDZ (1ULL << 28)
768 #define HCR_HCD (1ULL << 29)
769 #define HCR_TRVM (1ULL << 30)
770 #define HCR_RW (1ULL << 31)
771 #define HCR_CD (1ULL << 32)
772 #define HCR_ID (1ULL << 33)
773 #define HCR_MASK ((1ULL << 34) - 1)
775 #define SCR_NS (1U << 0)
776 #define SCR_IRQ (1U << 1)
777 #define SCR_FIQ (1U << 2)
778 #define SCR_EA (1U << 3)
779 #define SCR_FW (1U << 4)
780 #define SCR_AW (1U << 5)
781 #define SCR_NET (1U << 6)
782 #define SCR_SMD (1U << 7)
783 #define SCR_HCE (1U << 8)
784 #define SCR_SIF (1U << 9)
785 #define SCR_RW (1U << 10)
786 #define SCR_ST (1U << 11)
787 #define SCR_TWI (1U << 12)
788 #define SCR_TWE (1U << 13)
789 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
790 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
792 /* Return the current FPSCR value. */
793 uint32_t vfp_get_fpscr(CPUARMState
*env
);
794 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
796 /* For A64 the FPSCR is split into two logically distinct registers,
797 * FPCR and FPSR. However since they still use non-overlapping bits
798 * we store the underlying state in fpscr and just mask on read/write.
800 #define FPSR_MASK 0xf800009f
801 #define FPCR_MASK 0x07f79f00
802 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
804 return vfp_get_fpscr(env
) & FPSR_MASK
;
807 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
809 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
810 vfp_set_fpscr(env
, new_fpscr
);
813 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
815 return vfp_get_fpscr(env
) & FPCR_MASK
;
818 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
820 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
821 vfp_set_fpscr(env
, new_fpscr
);
825 ARM_CPU_MODE_USR
= 0x10,
826 ARM_CPU_MODE_FIQ
= 0x11,
827 ARM_CPU_MODE_IRQ
= 0x12,
828 ARM_CPU_MODE_SVC
= 0x13,
829 ARM_CPU_MODE_MON
= 0x16,
830 ARM_CPU_MODE_ABT
= 0x17,
831 ARM_CPU_MODE_HYP
= 0x1a,
832 ARM_CPU_MODE_UND
= 0x1b,
833 ARM_CPU_MODE_SYS
= 0x1f
836 /* VFP system registers. */
837 #define ARM_VFP_FPSID 0
838 #define ARM_VFP_FPSCR 1
839 #define ARM_VFP_MVFR2 5
840 #define ARM_VFP_MVFR1 6
841 #define ARM_VFP_MVFR0 7
842 #define ARM_VFP_FPEXC 8
843 #define ARM_VFP_FPINST 9
844 #define ARM_VFP_FPINST2 10
846 /* iwMMXt coprocessor control registers. */
847 #define ARM_IWMMXT_wCID 0
848 #define ARM_IWMMXT_wCon 1
849 #define ARM_IWMMXT_wCSSF 2
850 #define ARM_IWMMXT_wCASF 3
851 #define ARM_IWMMXT_wCGR0 8
852 #define ARM_IWMMXT_wCGR1 9
853 #define ARM_IWMMXT_wCGR2 10
854 #define ARM_IWMMXT_wCGR3 11
856 /* If adding a feature bit which corresponds to a Linux ELF
857 * HWCAP bit, remember to update the feature-bit-to-hwcap
858 * mapping in linux-user/elfload.c:get_elf_hwcap().
862 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
863 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
864 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
869 ARM_FEATURE_MPU
, /* Only has Memory Protection Unit, not full MMU. */
871 ARM_FEATURE_VFP_FP16
,
873 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
874 ARM_FEATURE_M
, /* Microcontroller profile. */
875 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
876 ARM_FEATURE_THUMB2EE
,
877 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
880 ARM_FEATURE_STRONGARM
,
881 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
882 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
883 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
884 ARM_FEATURE_GENERIC_TIMER
,
885 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
886 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
887 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
888 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
889 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
890 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
891 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
892 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
894 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
895 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
896 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
897 ARM_FEATURE_CRC
, /* ARMv8 CRC instructions */
898 ARM_FEATURE_CBAR_RO
, /* has cp15 CBAR and it is read-only */
899 ARM_FEATURE_EL2
, /* has EL2 Virtualization support */
900 ARM_FEATURE_EL3
, /* has EL3 Secure monitor support */
901 ARM_FEATURE_V8_SHA1
, /* implements SHA1 part of v8 Crypto Extensions */
902 ARM_FEATURE_V8_SHA256
, /* implements SHA256 part of v8 Crypto Extensions */
903 ARM_FEATURE_V8_PMULL
, /* implements PMULL part of v8 Crypto Extensions */
904 ARM_FEATURE_THUMB_DSP
, /* DSP insns supported in the Thumb encodings */
907 static inline int arm_feature(CPUARMState
*env
, int feature
)
909 return (env
->features
& (1ULL << feature
)) != 0;
912 #if !defined(CONFIG_USER_ONLY)
913 /* Return true if exception levels below EL3 are in secure state,
914 * or would be following an exception return to that level.
915 * Unlike arm_is_secure() (which is always a question about the
916 * _current_ state of the CPU) this doesn't care about the current
919 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
921 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
922 return !(env
->cp15
.scr_el3
& SCR_NS
);
924 /* If EL2 is not supported then the secure state is implementation
925 * defined, in which case QEMU defaults to non-secure.
931 /* Return true if the processor is in secure state */
932 static inline bool arm_is_secure(CPUARMState
*env
)
934 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
935 if (is_a64(env
) && extract32(env
->pstate
, 2, 2) == 3) {
936 /* CPU currently in AArch64 state and EL3 */
938 } else if (!is_a64(env
) &&
939 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
940 /* CPU currently in AArch32 state and monitor mode */
944 return arm_is_secure_below_el3(env
);
948 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
953 static inline bool arm_is_secure(CPUARMState
*env
)
959 /* Return true if the specified exception level is running in AArch64 state. */
960 static inline bool arm_el_is_aa64(CPUARMState
*env
, int el
)
962 /* We don't currently support EL2, and this isn't valid for EL0
963 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
964 * then the state of EL0 isn't well defined.)
966 assert(el
== 1 || el
== 3);
968 /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
969 * is a QEMU-imposed simplification which we may wish to change later.
970 * If we in future support EL2 and/or EL3, then the state of lower
971 * exception levels is controlled by the HCR.RW and SCR.RW bits.
973 return arm_feature(env
, ARM_FEATURE_AARCH64
);
976 /* Function for determing whether guest cp register reads and writes should
977 * access the secure or non-secure bank of a cp register. When EL3 is
978 * operating in AArch32 state, the NS-bit determines whether the secure
979 * instance of a cp register should be used. When EL3 is AArch64 (or if
980 * it doesn't exist at all) then there is no register banking, and all
981 * accesses are to the non-secure version.
983 static inline bool access_secure_reg(CPUARMState
*env
)
985 bool ret
= (arm_feature(env
, ARM_FEATURE_EL3
) &&
986 !arm_el_is_aa64(env
, 3) &&
987 !(env
->cp15
.scr_el3
& SCR_NS
));
992 /* Macros for accessing a specified CP register bank */
993 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
994 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
996 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
999 (_env)->cp15._regname##_s = (_val); \
1001 (_env)->cp15._regname##_ns = (_val); \
1005 /* Macros for automatically accessing a specific CP register bank depending on
1006 * the current secure state of the system. These macros are not intended for
1007 * supporting instruction translation reads/writes as these are dependent
1008 * solely on the SCR.NS bit and not the mode.
1010 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1011 A32_BANKED_REG_GET((_env), _regname, \
1012 ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))))
1014 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1015 A32_BANKED_REG_SET((_env), _regname, \
1016 ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \
1019 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
1020 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
1021 uint32_t cur_el
, bool secure
);
1023 /* Interface between CPU and Interrupt controller. */
1024 void armv7m_nvic_set_pending(void *opaque
, int irq
);
1025 int armv7m_nvic_acknowledge_irq(void *opaque
);
1026 void armv7m_nvic_complete_irq(void *opaque
, int irq
);
1028 /* Interface for defining coprocessor registers.
1029 * Registers are defined in tables of arm_cp_reginfo structs
1030 * which are passed to define_arm_cp_regs().
1033 /* When looking up a coprocessor register we look for it
1034 * via an integer which encodes all of:
1035 * coprocessor number
1036 * Crn, Crm, opc1, opc2 fields
1037 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1038 * or via MRRC/MCRR?)
1039 * non-secure/secure bank (AArch32 only)
1040 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1041 * (In this case crn and opc2 should be zero.)
1042 * For AArch64, there is no 32/64 bit size distinction;
1043 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1044 * and 4 bit CRn and CRm. The encoding patterns are chosen
1045 * to be easy to convert to and from the KVM encodings, and also
1046 * so that the hashtable can contain both AArch32 and AArch64
1047 * registers (to allow for interprocessing where we might run
1048 * 32 bit code on a 64 bit core).
1050 /* This bit is private to our hashtable cpreg; in KVM register
1051 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1052 * in the upper bits of the 64 bit ID.
1054 #define CP_REG_AA64_SHIFT 28
1055 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1057 /* To enable banking of coprocessor registers depending on ns-bit we
1058 * add a bit to distinguish between secure and non-secure cpregs in the
1061 #define CP_REG_NS_SHIFT 29
1062 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1064 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1065 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1066 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1068 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1069 (CP_REG_AA64_MASK | \
1070 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1071 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1072 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1073 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1074 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1075 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1077 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1078 * version used as a key for the coprocessor register hashtable
1080 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
1082 uint32_t cpregid
= kvmid
;
1083 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
1084 cpregid
|= CP_REG_AA64_MASK
;
1086 if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
1087 cpregid
|= (1 << 15);
1090 /* KVM is always non-secure so add the NS flag on AArch32 register
1093 cpregid
|= 1 << CP_REG_NS_SHIFT
;
1098 /* Convert a truncated 32 bit hashtable key into the full
1099 * 64 bit KVM register ID.
1101 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
1105 if (cpregid
& CP_REG_AA64_MASK
) {
1106 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
1107 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
1109 kvmid
= cpregid
& ~(1 << 15);
1110 if (cpregid
& (1 << 15)) {
1111 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
1113 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
1119 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1120 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1121 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1122 * TCG can assume the value to be constant (ie load at translate time)
1123 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1124 * indicates that the TB should not be ended after a write to this register
1125 * (the default is that the TB ends after cp writes). OVERRIDE permits
1126 * a register definition to override a previous definition for the
1127 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1128 * old must have the OVERRIDE bit set.
1129 * ALIAS indicates that this register is an alias view of some underlying
1130 * state which is also visible via another register, and that the other
1131 * register is handling migration and reset; registers marked ALIAS will not be
1132 * migrated but may have their state set by syncing of register state from KVM.
1133 * NO_RAW indicates that this register has no underlying state and does not
1134 * support raw access for state saving/loading; it will not be used for either
1135 * migration or KVM state synchronization. (Typically this is for "registers"
1136 * which are actually used as instructions for cache maintenance and so on.)
1137 * IO indicates that this register does I/O and therefore its accesses
1138 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1139 * registers which implement clocks or timers require this.
1141 #define ARM_CP_SPECIAL 1
1142 #define ARM_CP_CONST 2
1143 #define ARM_CP_64BIT 4
1144 #define ARM_CP_SUPPRESS_TB_END 8
1145 #define ARM_CP_OVERRIDE 16
1146 #define ARM_CP_ALIAS 32
1147 #define ARM_CP_IO 64
1148 #define ARM_CP_NO_RAW 128
1149 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1150 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1151 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1152 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1153 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1154 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1155 /* Used only as a terminator for ARMCPRegInfo lists */
1156 #define ARM_CP_SENTINEL 0xffff
1157 /* Mask of only the flag bits in a type field */
1158 #define ARM_CP_FLAG_MASK 0xff
1160 /* Valid values for ARMCPRegInfo state field, indicating which of
1161 * the AArch32 and AArch64 execution states this register is visible in.
1162 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1163 * If the reginfo is declared to be visible in both states then a second
1164 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1165 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1166 * Note that we rely on the values of these enums as we iterate through
1167 * the various states in some places.
1170 ARM_CP_STATE_AA32
= 0,
1171 ARM_CP_STATE_AA64
= 1,
1172 ARM_CP_STATE_BOTH
= 2,
1175 /* ARM CP register secure state flags. These flags identify security state
1176 * attributes for a given CP register entry.
1177 * The existence of both or neither secure and non-secure flags indicates that
1178 * the register has both a secure and non-secure hash entry. A single one of
1179 * these flags causes the register to only be hashed for the specified
1181 * Although definitions may have any combination of the S/NS bits, each
1182 * registered entry will only have one to identify whether the entry is secure
1186 ARM_CP_SECSTATE_S
= (1 << 0), /* bit[0]: Secure state register */
1187 ARM_CP_SECSTATE_NS
= (1 << 1), /* bit[1]: Non-secure state register */
1190 /* Return true if cptype is a valid type field. This is used to try to
1191 * catch errors where the sentinel has been accidentally left off the end
1192 * of a list of registers.
1194 static inline bool cptype_valid(int cptype
)
1196 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
1197 || ((cptype
& ARM_CP_SPECIAL
) &&
1198 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
1202 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1203 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1204 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1205 * (ie any of the privileged modes in Secure state, or Monitor mode).
1206 * If a register is accessible in one privilege level it's always accessible
1207 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1208 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1209 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1210 * terminology a little and call this PL3.
1211 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1212 * with the ELx exception levels.
1214 * If access permissions for a register are more complex than can be
1215 * described with these bits, then use a laxer set of restrictions, and
1216 * do the more restrictive/complex check inside a helper function.
1220 #define PL2_R (0x20 | PL3_R)
1221 #define PL2_W (0x10 | PL3_W)
1222 #define PL1_R (0x08 | PL2_R)
1223 #define PL1_W (0x04 | PL2_W)
1224 #define PL0_R (0x02 | PL1_R)
1225 #define PL0_W (0x01 | PL1_W)
1227 #define PL3_RW (PL3_R | PL3_W)
1228 #define PL2_RW (PL2_R | PL2_W)
1229 #define PL1_RW (PL1_R | PL1_W)
1230 #define PL0_RW (PL0_R | PL0_W)
1232 /* Return the current Exception Level (as per ARMv8; note that this differs
1233 * from the ARMv7 Privilege Level).
1235 static inline int arm_current_el(CPUARMState
*env
)
1237 if (arm_feature(env
, ARM_FEATURE_M
)) {
1238 return !((env
->v7m
.exception
== 0) && (env
->v7m
.control
& 1));
1242 return extract32(env
->pstate
, 2, 2);
1245 switch (env
->uncached_cpsr
& 0x1f) {
1246 case ARM_CPU_MODE_USR
:
1248 case ARM_CPU_MODE_HYP
:
1250 case ARM_CPU_MODE_MON
:
1253 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
1254 /* If EL3 is 32-bit then all secure privileged modes run in
1264 typedef struct ARMCPRegInfo ARMCPRegInfo
;
1266 typedef enum CPAccessResult
{
1267 /* Access is permitted */
1269 /* Access fails due to a configurable trap or enable which would
1270 * result in a categorized exception syndrome giving information about
1271 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1272 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1273 * PL1 if in EL0, otherwise to the current EL).
1276 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1277 * Note that this is not a catch-all case -- the set of cases which may
1278 * result in this failure is specifically defined by the architecture.
1280 CP_ACCESS_TRAP_UNCATEGORIZED
= 2,
1281 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1282 CP_ACCESS_TRAP_EL2
= 3,
1283 CP_ACCESS_TRAP_EL3
= 4,
1286 /* Access functions for coprocessor registers. These cannot fail and
1287 * may not raise exceptions.
1289 typedef uint64_t CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1290 typedef void CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
1292 /* Access permission check functions for coprocessor registers. */
1293 typedef CPAccessResult
CPAccessFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1294 /* Hook function for register reset */
1295 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1299 /* Definition of an ARM coprocessor register */
1300 struct ARMCPRegInfo
{
1301 /* Name of register (useful mainly for debugging, need not be unique) */
1303 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1304 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1305 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1306 * will be decoded to this register. The register read and write
1307 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1308 * used by the program, so it is possible to register a wildcard and
1309 * then behave differently on read/write if necessary.
1310 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1311 * must both be zero.
1312 * For AArch64-visible registers, opc0 is also used.
1313 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1314 * way to distinguish (for KVM's benefit) guest-visible system registers
1315 * from demuxed ones provided to preserve the "no side effects on
1316 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1317 * visible (to match KVM's encoding); cp==0 will be converted to
1318 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1326 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1328 /* Register type: ARM_CP_* bits/values */
1330 /* Access rights: PL*_[RW] */
1332 /* Security state: ARM_CP_SECSTATE_* bits/values */
1334 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1335 * this register was defined: can be used to hand data through to the
1336 * register read/write functions, since they are passed the ARMCPRegInfo*.
1339 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1340 * fieldoffset is non-zero, the reset value of the register.
1342 uint64_t resetvalue
;
1343 /* Offset of the field in CPUARMState for this register.
1345 * This is not needed if either:
1346 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1347 * 2. both readfn and writefn are specified
1349 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
1351 /* Offsets of the secure and non-secure fields in CPUARMState for the
1352 * register if it is banked. These fields are only used during the static
1353 * registration of a register. During hashing the bank associated
1354 * with a given security state is copied to fieldoffset which is used from
1357 * It is expected that register definitions use either fieldoffset or
1358 * bank_fieldoffsets in the definition but not both. It is also expected
1359 * that both bank offsets are set when defining a banked register. This
1360 * use indicates that a register is banked.
1362 ptrdiff_t bank_fieldoffsets
[2];
1364 /* Function for making any access checks for this register in addition to
1365 * those specified by the 'access' permissions bits. If NULL, no extra
1366 * checks required. The access check is performed at runtime, not at
1369 CPAccessFn
*accessfn
;
1370 /* Function for handling reads of this register. If NULL, then reads
1371 * will be done by loading from the offset into CPUARMState specified
1375 /* Function for handling writes of this register. If NULL, then writes
1376 * will be done by writing to the offset into CPUARMState specified
1380 /* Function for doing a "raw" read; used when we need to copy
1381 * coprocessor state to the kernel for KVM or out for
1382 * migration. This only needs to be provided if there is also a
1383 * readfn and it has side effects (for instance clear-on-read bits).
1385 CPReadFn
*raw_readfn
;
1386 /* Function for doing a "raw" write; used when we need to copy KVM
1387 * kernel coprocessor state into userspace, or for inbound
1388 * migration. This only needs to be provided if there is also a
1389 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1390 * or similar behaviour.
1392 CPWriteFn
*raw_writefn
;
1393 /* Function for resetting the register. If NULL, then reset will be done
1394 * by writing resetvalue to the field specified in fieldoffset. If
1395 * fieldoffset is 0 then no reset will be done.
1400 /* Macros which are lvalues for the field in CPUARMState for the
1403 #define CPREG_FIELD32(env, ri) \
1404 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1405 #define CPREG_FIELD64(env, ri) \
1406 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1408 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1410 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1411 const ARMCPRegInfo
*regs
, void *opaque
);
1412 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1413 const ARMCPRegInfo
*regs
, void *opaque
);
1414 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1416 define_arm_cp_regs_with_opaque(cpu
, regs
, 0);
1418 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1420 define_one_arm_cp_reg_with_opaque(cpu
, regs
, 0);
1422 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
1424 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1425 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1427 /* CPReadFn that can be used for read-as-zero behaviour */
1428 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1430 /* CPResetFn that does nothing, for use if no reset is required even
1431 * if fieldoffset is non zero.
1433 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1435 /* Return true if this reginfo struct's field in the cpu state struct
1438 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo
*ri
)
1440 return (ri
->state
== ARM_CP_STATE_AA64
) || (ri
->type
& ARM_CP_64BIT
);
1443 static inline bool cp_access_ok(int current_el
,
1444 const ARMCPRegInfo
*ri
, int isread
)
1446 return (ri
->access
>> ((current_el
* 2) + isread
)) & 1;
1450 * write_list_to_cpustate
1453 * For each register listed in the ARMCPU cpreg_indexes list, write
1454 * its value from the cpreg_values list into the ARMCPUState structure.
1455 * This updates TCG's working data structures from KVM data or
1456 * from incoming migration state.
1458 * Returns: true if all register values were updated correctly,
1459 * false if some register was unknown or could not be written.
1460 * Note that we do not stop early on failure -- we will attempt
1461 * writing all registers in the list.
1463 bool write_list_to_cpustate(ARMCPU
*cpu
);
1466 * write_cpustate_to_list:
1469 * For each register listed in the ARMCPU cpreg_indexes list, write
1470 * its value from the ARMCPUState structure into the cpreg_values list.
1471 * This is used to copy info from TCG's working data structures into
1472 * KVM or for outbound migration.
1474 * Returns: true if all register values were read correctly,
1475 * false if some register was unknown or could not be read.
1476 * Note that we do not stop early on failure -- we will attempt
1477 * reading all registers in the list.
1479 bool write_cpustate_to_list(ARMCPU
*cpu
);
1481 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
1482 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1483 conventional cores (ie. Application or Realtime profile). */
1485 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1487 #define ARM_CPUID_TI915T 0x54029152
1488 #define ARM_CPUID_TI925T 0x54029252
1490 #if defined(CONFIG_USER_ONLY)
1491 #define TARGET_PAGE_BITS 12
1493 /* The ARM MMU allows 1k pages. */
1494 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1495 architecture revisions. Maybe a configure option to disable them. */
1496 #define TARGET_PAGE_BITS 10
1499 #if defined(TARGET_AARCH64)
1500 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1501 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1503 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1504 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1507 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
1508 unsigned int target_el
)
1510 CPUARMState
*env
= cs
->env_ptr
;
1511 unsigned int cur_el
= arm_current_el(env
);
1512 bool secure
= arm_is_secure(env
);
1515 bool pstate_unmasked
;
1516 int8_t unmasked
= 0;
1518 /* Don't take exceptions if they target a lower EL.
1519 * This check should catch any exceptions that would not be taken but left
1522 if (cur_el
> target_el
) {
1528 /* If FIQs are routed to EL3 or EL2 then there are cases where we
1529 * override the CPSR.F in determining if the exception is masked or
1530 * not. If neither of these are set then we fall back to the CPSR.F
1531 * setting otherwise we further assess the state below.
1533 hcr
= (env
->cp15
.hcr_el2
& HCR_FMO
);
1534 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
1536 /* When EL3 is 32-bit, the SCR.FW bit controls whether the CPSR.F bit
1537 * masks FIQ interrupts when taken in non-secure state. If SCR.FW is
1538 * set then FIQs can be masked by CPSR.F when non-secure but only
1539 * when FIQs are only routed to EL3.
1541 scr
&= !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
1542 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
1546 /* When EL3 execution state is 32-bit, if HCR.IMO is set then we may
1547 * override the CPSR.I masking when in non-secure state. The SCR.IRQ
1548 * setting has already been taken into consideration when setting the
1549 * target EL, so it does not have a further affect here.
1551 hcr
= (env
->cp15
.hcr_el2
& HCR_IMO
);
1553 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
1557 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_FMO
)) {
1558 /* VFIQs are only taken when hypervized and non-secure. */
1561 return !(env
->daif
& PSTATE_F
);
1563 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_IMO
)) {
1564 /* VIRQs are only taken when hypervized and non-secure. */
1567 return !(env
->daif
& PSTATE_I
);
1569 g_assert_not_reached();
1572 /* Use the target EL, current execution state and SCR/HCR settings to
1573 * determine whether the corresponding CPSR bit is used to mask the
1576 if ((target_el
> cur_el
) && (target_el
!= 1)) {
1577 if (arm_el_is_aa64(env
, 3) || ((scr
|| hcr
) && (!secure
))) {
1582 /* The PSTATE bits only mask the interrupt if we have not overriden the
1585 return unmasked
|| pstate_unmasked
;
1588 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1590 #define cpu_exec cpu_arm_exec
1591 #define cpu_gen_code cpu_arm_gen_code
1592 #define cpu_signal_handler cpu_arm_signal_handler
1593 #define cpu_list arm_cpu_list
1595 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
1598 * + NonSecure EL1 & 0 stage 1
1599 * + NonSecure EL1 & 0 stage 2
1601 * + Secure EL1 & EL0
1604 * + NonSecure PL1 & 0 stage 1
1605 * + NonSecure PL1 & 0 stage 2
1607 * + Secure PL0 & PL1
1608 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
1610 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
1611 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
1612 * may differ in access permissions even if the VA->PA map is the same
1613 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
1614 * translation, which means that we have one mmu_idx that deals with two
1615 * concatenated translation regimes [this sort of combined s1+2 TLB is
1616 * architecturally permitted]
1617 * 3. we don't need to allocate an mmu_idx to translations that we won't be
1618 * handling via the TLB. The only way to do a stage 1 translation without
1619 * the immediate stage 2 translation is via the ATS or AT system insns,
1620 * which can be slow-pathed and always do a page table walk.
1621 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
1622 * translation regimes, because they map reasonably well to each other
1623 * and they can't both be active at the same time.
1624 * This gives us the following list of mmu_idx values:
1626 * NS EL0 (aka NS PL0) stage 1+2
1627 * NS EL1 (aka NS PL1) stage 1+2
1628 * NS EL2 (aka NS PL2)
1631 * S EL1 (not used if EL3 is 32 bit)
1634 * (The last of these is an mmu_idx because we want to be able to use the TLB
1635 * for the accesses done as part of a stage 1 page table walk, rather than
1636 * having to walk the stage 2 page table over and over.)
1638 * Our enumeration includes at the end some entries which are not "true"
1639 * mmu_idx values in that they don't have corresponding TLBs and are only
1640 * valid for doing slow path page table walks.
1642 * The constant names here are patterned after the general style of the names
1643 * of the AT/ATS operations.
1644 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
1646 typedef enum ARMMMUIdx
{
1647 ARMMMUIdx_S12NSE0
= 0,
1648 ARMMMUIdx_S12NSE1
= 1,
1651 ARMMMUIdx_S1SE0
= 4,
1652 ARMMMUIdx_S1SE1
= 5,
1654 /* Indexes below here don't have TLBs and are used only for AT system
1655 * instructions or for the first stage of an S12 page table walk.
1657 ARMMMUIdx_S1NSE0
= 7,
1658 ARMMMUIdx_S1NSE1
= 8,
1661 #define MMU_USER_IDX 0
1663 /* Return the exception level we're running at if this is our mmu_idx */
1664 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
1666 assert(mmu_idx
< ARMMMUIdx_S2NS
);
1670 /* Determine the current mmu_idx to use for normal loads/stores */
1671 static inline int cpu_mmu_index(CPUARMState
*env
)
1673 int el
= arm_current_el(env
);
1675 if (el
< 2 && arm_is_secure_below_el3(env
)) {
1676 return ARMMMUIdx_S1SE0
+ el
;
1681 /* Return the Exception Level targeted by debug exceptions;
1682 * currently always EL1 since we don't implement EL2 or EL3.
1684 static inline int arm_debug_target_el(CPUARMState
*env
)
1689 static inline bool aa64_generate_debug_exceptions(CPUARMState
*env
)
1691 if (arm_current_el(env
) == arm_debug_target_el(env
)) {
1692 if ((extract32(env
->cp15
.mdscr_el1
, 13, 1) == 0)
1693 || (env
->daif
& PSTATE_D
)) {
1700 static inline bool aa32_generate_debug_exceptions(CPUARMState
*env
)
1702 if (arm_current_el(env
) == 0 && arm_el_is_aa64(env
, 1)) {
1703 return aa64_generate_debug_exceptions(env
);
1705 return arm_current_el(env
) != 2;
1708 /* Return true if debugging exceptions are currently enabled.
1709 * This corresponds to what in ARM ARM pseudocode would be
1710 * if UsingAArch32() then
1711 * return AArch32.GenerateDebugExceptions()
1713 * return AArch64.GenerateDebugExceptions()
1714 * We choose to push the if() down into this function for clarity,
1715 * since the pseudocode has it at all callsites except for the one in
1716 * CheckSoftwareStep(), where it is elided because both branches would
1717 * always return the same value.
1719 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
1720 * don't yet implement those exception levels or their associated trap bits.
1722 static inline bool arm_generate_debug_exceptions(CPUARMState
*env
)
1725 return aa64_generate_debug_exceptions(env
);
1727 return aa32_generate_debug_exceptions(env
);
1731 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
1732 * implicitly means this always returns false in pre-v8 CPUs.)
1734 static inline bool arm_singlestep_active(CPUARMState
*env
)
1736 return extract32(env
->cp15
.mdscr_el1
, 0, 1)
1737 && arm_el_is_aa64(env
, arm_debug_target_el(env
))
1738 && arm_generate_debug_exceptions(env
);
1741 #include "exec/cpu-all.h"
1743 /* Bit usage in the TB flags field: bit 31 indicates whether we are
1744 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
1745 * We put flags which are shared between 32 and 64 bit mode at the top
1746 * of the word, and flags which apply to only one mode at the bottom.
1748 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1749 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1750 #define ARM_TBFLAG_MMUIDX_SHIFT 28
1751 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
1752 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
1753 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1754 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
1755 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1756 /* Target EL if we take a floating-point-disabled exception */
1757 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
1758 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
1760 /* Bit usage when in AArch32 state: */
1761 #define ARM_TBFLAG_THUMB_SHIFT 0
1762 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1763 #define ARM_TBFLAG_VECLEN_SHIFT 1
1764 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1765 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1766 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1767 #define ARM_TBFLAG_VFPEN_SHIFT 7
1768 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1769 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
1770 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1771 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1772 #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1773 /* We store the bottom two bits of the CPAR as TB flags and handle
1774 * checks on the other bits at runtime
1776 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
1777 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1778 /* Indicates whether cp register reads and writes by guest code should access
1779 * the secure or nonsecure bank of banked registers; note that this is not
1780 * the same thing as the current security state of the processor!
1782 #define ARM_TBFLAG_NS_SHIFT 19
1783 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
1785 /* Bit usage when in AArch64 state: currently we have no A64 specific bits */
1787 /* some convenience accessor macros */
1788 #define ARM_TBFLAG_AARCH64_STATE(F) \
1789 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1790 #define ARM_TBFLAG_MMUIDX(F) \
1791 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
1792 #define ARM_TBFLAG_SS_ACTIVE(F) \
1793 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1794 #define ARM_TBFLAG_PSTATE_SS(F) \
1795 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
1796 #define ARM_TBFLAG_FPEXC_EL(F) \
1797 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
1798 #define ARM_TBFLAG_THUMB(F) \
1799 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1800 #define ARM_TBFLAG_VECLEN(F) \
1801 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1802 #define ARM_TBFLAG_VECSTRIDE(F) \
1803 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1804 #define ARM_TBFLAG_VFPEN(F) \
1805 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1806 #define ARM_TBFLAG_CONDEXEC(F) \
1807 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1808 #define ARM_TBFLAG_BSWAP_CODE(F) \
1809 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1810 #define ARM_TBFLAG_XSCALE_CPAR(F) \
1811 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1812 #define ARM_TBFLAG_NS(F) \
1813 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
1815 /* Return the exception level to which FP-disabled exceptions should
1816 * be taken, or 0 if FP is enabled.
1818 static inline int fp_exception_el(CPUARMState
*env
)
1821 int cur_el
= arm_current_el(env
);
1823 /* CPACR and the CPTR registers don't exist before v6, so FP is
1826 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
1830 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1831 * 0, 2 : trap EL0 and EL1/PL1 accesses
1832 * 1 : trap only EL0 accesses
1833 * 3 : trap no accesses
1835 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
1839 if (cur_el
== 0 || cur_el
== 1) {
1840 /* Trap to PL1, which might be EL1 or EL3 */
1841 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
1846 if (cur_el
== 3 && !is_a64(env
)) {
1847 /* Secure PL1 running at EL3 */
1860 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
1861 * check because zero bits in the registers mean "don't trap".
1864 /* CPTR_EL2 : present in v7VE or v8 */
1865 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
1866 && !arm_is_secure_below_el3(env
)) {
1867 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
1871 /* CPTR_EL3 : present in v8 */
1872 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
1873 /* Trap all FP ops to EL3 */
1880 static inline void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
1881 target_ulong
*cs_base
, int *flags
)
1885 *flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
1887 *pc
= env
->regs
[15];
1888 *flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
1889 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
1890 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
1891 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
1892 | (env
->bswap_code
<< ARM_TBFLAG_BSWAP_CODE_SHIFT
);
1893 if (!(access_secure_reg(env
))) {
1894 *flags
|= ARM_TBFLAG_NS_MASK
;
1896 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
1897 || arm_el_is_aa64(env
, 1)) {
1898 *flags
|= ARM_TBFLAG_VFPEN_MASK
;
1900 *flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
1901 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
1904 *flags
|= (cpu_mmu_index(env
) << ARM_TBFLAG_MMUIDX_SHIFT
);
1905 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1906 * states defined in the ARM ARM for software singlestep:
1907 * SS_ACTIVE PSTATE.SS State
1908 * 0 x Inactive (the TB flag for SS is always 0)
1909 * 1 0 Active-pending
1910 * 1 1 Active-not-pending
1912 if (arm_singlestep_active(env
)) {
1913 *flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
1915 if (env
->pstate
& PSTATE_SS
) {
1916 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
1919 if (env
->uncached_cpsr
& PSTATE_SS
) {
1920 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
1924 *flags
|= fp_exception_el(env
) << ARM_TBFLAG_FPEXC_EL_SHIFT
;
1929 #include "exec/exec-all.h"
1932 QEMU_PSCI_CONDUIT_DISABLED
= 0,
1933 QEMU_PSCI_CONDUIT_SMC
= 1,
1934 QEMU_PSCI_CONDUIT_HVC
= 2,