| blob | 346c6143545d2eb2d9f3224bdc000b564c1e6770 |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
27 #include "../tcg-ldst.c.inc"
29 #if HOST_BIG_ENDIAN
30 # define MIPS_BE 1
31 #else
32 # define MIPS_BE 0
33 #endif
35 #if TCG_TARGET_REG_BITS == 32
36 # define LO_OFF (MIPS_BE * 4)
37 # define HI_OFF (4 - LO_OFF)
38 #else
39 /* To assert at compile-time that these values are never used
40 for TCG_TARGET_REG_BITS == 64. */
41 int link_error(void);
42 # define LO_OFF link_error()
43 # define HI_OFF link_error()
44 #endif
46 #ifdef CONFIG_DEBUG_TCG
47 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
48 "zero",
49 "at",
50 "v0",
51 "v1",
52 "a0",
53 "a1",
54 "a2",
55 "a3",
56 "t0",
57 "t1",
58 "t2",
59 "t3",
60 "t4",
61 "t5",
62 "t6",
63 "t7",
64 "s0",
65 "s1",
66 "s2",
67 "s3",
68 "s4",
69 "s5",
70 "s6",
71 "s7",
72 "t8",
73 "t9",
74 "k0",
75 "k1",
76 "gp",
77 "sp",
78 "s8",
79 "ra",
80 };
81 #endif
83 #define TCG_TMP0 TCG_REG_AT
84 #define TCG_TMP1 TCG_REG_T9
85 #define TCG_TMP2 TCG_REG_T8
86 #define TCG_TMP3 TCG_REG_T7
88 #ifndef CONFIG_SOFTMMU
89 #define TCG_GUEST_BASE_REG TCG_REG_S1
90 #endif
92 /* check if we really need so many registers :P */
93 static const int tcg_target_reg_alloc_order[] = {
94 /* Call saved registers. */
95 TCG_REG_S0,
96 TCG_REG_S1,
97 TCG_REG_S2,
98 TCG_REG_S3,
99 TCG_REG_S4,
100 TCG_REG_S5,
101 TCG_REG_S6,
102 TCG_REG_S7,
103 TCG_REG_S8,
105 /* Call clobbered registers. */
106 TCG_REG_T4,
107 TCG_REG_T5,
108 TCG_REG_T6,
109 TCG_REG_T7,
110 TCG_REG_T8,
111 TCG_REG_T9,
112 TCG_REG_V1,
113 TCG_REG_V0,
115 /* Argument registers, opposite order of allocation. */
116 TCG_REG_T3,
117 TCG_REG_T2,
118 TCG_REG_T1,
119 TCG_REG_T0,
120 TCG_REG_A3,
121 TCG_REG_A2,
122 TCG_REG_A1,
123 TCG_REG_A0,
124 };
126 static const TCGReg tcg_target_call_iarg_regs[] = {
127 TCG_REG_A0,
128 TCG_REG_A1,
129 TCG_REG_A2,
130 TCG_REG_A3,
131 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
132 TCG_REG_T0,
133 TCG_REG_T1,
134 TCG_REG_T2,
135 TCG_REG_T3,
136 #endif
137 };
139 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
140 {
141 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
142 tcg_debug_assert(slot >= 0 && slot <= 1);
143 return TCG_REG_V0 + slot;
144 }
146 static const tcg_insn_unit *tb_ret_addr;
147 static const tcg_insn_unit *bswap32_addr;
148 static const tcg_insn_unit *bswap32u_addr;
149 static const tcg_insn_unit *bswap64_addr;
151 static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
152 {
153 /* Let the compiler perform the right-shift as part of the arithmetic. */
154 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
155 ptrdiff_t disp = target - (src_rx + 1);
156 if (disp == (int16_t)disp) {
157 *src_rw = deposit32(*src_rw, 0, 16, disp);
158 return true;
159 }
160 return false;
161 }
163 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
164 intptr_t value, intptr_t addend)
165 {
166 tcg_debug_assert(type == R_MIPS_PC16);
167 tcg_debug_assert(addend == 0);
168 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
169 }
171 #define TCG_CT_CONST_ZERO 0x100
172 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
173 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
174 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
175 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
176 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
178 #define ALL_GENERAL_REGS 0xffffffffu
179 #define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
181 #ifdef CONFIG_SOFTMMU
182 #define ALL_QLOAD_REGS \
183 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
184 #define ALL_QSTORE_REGS \
185 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
186 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
187 : (1 << TCG_REG_A1)))
188 #else
189 #define ALL_QLOAD_REGS NOA0_REGS
190 #define ALL_QSTORE_REGS NOA0_REGS
191 #endif
194 static bool is_p2m1(tcg_target_long val)
195 {
196 return val && ((val + 1) & val) == 0;
197 }
199 /* test if a constant matches the constraint */
200 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
201 {
202 if (ct & TCG_CT_CONST) {
203 return 1;
204 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
205 return 1;
206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
207 return 1;
208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
209 return 1;
210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
211 return 1;
212 } else if ((ct & TCG_CT_CONST_P2M1)
213 && use_mips32r2_instructions && is_p2m1(val)) {
214 return 1;
215 } else if ((ct & TCG_CT_CONST_WSZ)
216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
217 return 1;
218 }
219 return 0;
220 }
222 /* instruction opcodes */
223 typedef enum {
224 OPC_J = 002 << 26,
225 OPC_JAL = 003 << 26,
226 OPC_BEQ = 004 << 26,
227 OPC_BNE = 005 << 26,
228 OPC_BLEZ = 006 << 26,
229 OPC_BGTZ = 007 << 26,
230 OPC_ADDIU = 011 << 26,
231 OPC_SLTI = 012 << 26,
232 OPC_SLTIU = 013 << 26,
233 OPC_ANDI = 014 << 26,
234 OPC_ORI = 015 << 26,
235 OPC_XORI = 016 << 26,
236 OPC_LUI = 017 << 26,
237 OPC_BNEL = 025 << 26,
238 OPC_BNEZALC_R6 = 030 << 26,
239 OPC_DADDIU = 031 << 26,
240 OPC_LDL = 032 << 26,
241 OPC_LDR = 033 << 26,
242 OPC_LB = 040 << 26,
243 OPC_LH = 041 << 26,
244 OPC_LWL = 042 << 26,
245 OPC_LW = 043 << 26,
246 OPC_LBU = 044 << 26,
247 OPC_LHU = 045 << 26,
248 OPC_LWR = 046 << 26,
249 OPC_LWU = 047 << 26,
250 OPC_SB = 050 << 26,
251 OPC_SH = 051 << 26,
252 OPC_SWL = 052 << 26,
253 OPC_SW = 053 << 26,
254 OPC_SDL = 054 << 26,
255 OPC_SDR = 055 << 26,
256 OPC_SWR = 056 << 26,
257 OPC_LD = 067 << 26,
258 OPC_SD = 077 << 26,
260 OPC_SPECIAL = 000 << 26,
261 OPC_SLL = OPC_SPECIAL | 000,
262 OPC_SRL = OPC_SPECIAL | 002,
263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
264 OPC_SRA = OPC_SPECIAL | 003,
265 OPC_SLLV = OPC_SPECIAL | 004,
266 OPC_SRLV = OPC_SPECIAL | 006,
267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
268 OPC_SRAV = OPC_SPECIAL | 007,
269 OPC_JR_R5 = OPC_SPECIAL | 010,
270 OPC_JALR = OPC_SPECIAL | 011,
271 OPC_MOVZ = OPC_SPECIAL | 012,
272 OPC_MOVN = OPC_SPECIAL | 013,
273 OPC_SYNC = OPC_SPECIAL | 017,
274 OPC_MFHI = OPC_SPECIAL | 020,
275 OPC_MFLO = OPC_SPECIAL | 022,
276 OPC_DSLLV = OPC_SPECIAL | 024,
277 OPC_DSRLV = OPC_SPECIAL | 026,
278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
279 OPC_DSRAV = OPC_SPECIAL | 027,
280 OPC_MULT = OPC_SPECIAL | 030,
281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
282 OPC_MUH = OPC_SPECIAL | 030 | 0300,
283 OPC_MULTU = OPC_SPECIAL | 031,
284 OPC_MULU = OPC_SPECIAL | 031 | 0200,
285 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
286 OPC_DIV = OPC_SPECIAL | 032,
287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
288 OPC_MOD = OPC_SPECIAL | 032 | 0300,
289 OPC_DIVU = OPC_SPECIAL | 033,
290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
291 OPC_MODU = OPC_SPECIAL | 033 | 0300,
292 OPC_DMULT = OPC_SPECIAL | 034,
293 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
294 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
295 OPC_DMULTU = OPC_SPECIAL | 035,
296 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
298 OPC_DDIV = OPC_SPECIAL | 036,
299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
300 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
301 OPC_DDIVU = OPC_SPECIAL | 037,
302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
303 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
304 OPC_ADDU = OPC_SPECIAL | 041,
305 OPC_SUBU = OPC_SPECIAL | 043,
306 OPC_AND = OPC_SPECIAL | 044,
307 OPC_OR = OPC_SPECIAL | 045,
308 OPC_XOR = OPC_SPECIAL | 046,
309 OPC_NOR = OPC_SPECIAL | 047,
310 OPC_SLT = OPC_SPECIAL | 052,
311 OPC_SLTU = OPC_SPECIAL | 053,
312 OPC_DADDU = OPC_SPECIAL | 055,
313 OPC_DSUBU = OPC_SPECIAL | 057,
314 OPC_SELEQZ = OPC_SPECIAL | 065,
315 OPC_SELNEZ = OPC_SPECIAL | 067,
316 OPC_DSLL = OPC_SPECIAL | 070,
317 OPC_DSRL = OPC_SPECIAL | 072,
318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
319 OPC_DSRA = OPC_SPECIAL | 073,
320 OPC_DSLL32 = OPC_SPECIAL | 074,
321 OPC_DSRL32 = OPC_SPECIAL | 076,
322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
323 OPC_DSRA32 = OPC_SPECIAL | 077,
324 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
327 OPC_REGIMM = 001 << 26,
328 OPC_BLTZ = OPC_REGIMM | (000 << 16),
329 OPC_BGEZ = OPC_REGIMM | (001 << 16),
331 OPC_SPECIAL2 = 034 << 26,
332 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
333 OPC_CLZ = OPC_SPECIAL2 | 040,
334 OPC_DCLZ = OPC_SPECIAL2 | 044,
336 OPC_SPECIAL3 = 037 << 26,
337 OPC_EXT = OPC_SPECIAL3 | 000,
338 OPC_DEXTM = OPC_SPECIAL3 | 001,
339 OPC_DEXTU = OPC_SPECIAL3 | 002,
340 OPC_DEXT = OPC_SPECIAL3 | 003,
341 OPC_INS = OPC_SPECIAL3 | 004,
342 OPC_DINSM = OPC_SPECIAL3 | 005,
343 OPC_DINSU = OPC_SPECIAL3 | 006,
344 OPC_DINS = OPC_SPECIAL3 | 007,
345 OPC_WSBH = OPC_SPECIAL3 | 00240,
346 OPC_DSBH = OPC_SPECIAL3 | 00244,
347 OPC_DSHD = OPC_SPECIAL3 | 00544,
348 OPC_SEB = OPC_SPECIAL3 | 02040,
349 OPC_SEH = OPC_SPECIAL3 | 03040,
351 /* MIPS r6 doesn't have JR, JALR should be used instead */
352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
354 /*
355 * MIPS r6 replaces MUL with an alternative encoding which is
356 * backwards-compatible at the assembly level.
357 */
358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
360 /* MIPS r6 introduced names for weaker variants of SYNC. These are
361 backward compatible to previous architecture revisions. */
362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
368 /* Aliases for convenience. */
369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
371 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
372 ? OPC_SRL : OPC_DSRL,
373 } MIPSInsn;
375 /*
376 * Type reg
377 */
378 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
379 TCGReg rd, TCGReg rs, TCGReg rt)
380 {
381 int32_t inst;
383 inst = opc;
384 inst |= (rs & 0x1F) << 21;
385 inst |= (rt & 0x1F) << 16;
386 inst |= (rd & 0x1F) << 11;
387 tcg_out32(s, inst);
388 }
390 /*
391 * Type immediate
392 */
393 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
394 TCGReg rt, TCGReg rs, TCGArg imm)
395 {
396 int32_t inst;
398 inst = opc;
399 inst |= (rs & 0x1F) << 21;
400 inst |= (rt & 0x1F) << 16;
401 inst |= (imm & 0xffff);
402 tcg_out32(s, inst);
403 }
405 /*
406 * Type bitfield
407 */
408 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
409 TCGReg rs, int msb, int lsb)
410 {
411 int32_t inst;
413 inst = opc;
414 inst |= (rs & 0x1F) << 21;
415 inst |= (rt & 0x1F) << 16;
416 inst |= (msb & 0x1F) << 11;
417 inst |= (lsb & 0x1F) << 6;
418 tcg_out32(s, inst);
419 }
421 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
422 MIPSInsn oph, TCGReg rt, TCGReg rs,
423 int msb, int lsb)
424 {
425 if (lsb >= 32) {
426 opc = oph;
427 msb -= 32;
428 lsb -= 32;
429 } else if (msb >= 32) {
430 opc = opm;
431 msb -= 32;
432 }
433 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
434 }
436 /*
437 * Type branch
438 */
439 static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
440 {
441 tcg_out_opc_imm(s, opc, rt, rs, 0);
442 }
444 /*
445 * Type sa
446 */
447 static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
448 TCGReg rd, TCGReg rt, TCGArg sa)
449 {
450 int32_t inst;
452 inst = opc;
453 inst |= (rt & 0x1F) << 16;
454 inst |= (rd & 0x1F) << 11;
455 inst |= (sa & 0x1F) << 6;
456 tcg_out32(s, inst);
458 }
460 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
461 TCGReg rd, TCGReg rt, TCGArg sa)
462 {
463 int32_t inst;
465 inst = (sa & 32 ? opc2 : opc1);
466 inst |= (rt & 0x1F) << 16;
467 inst |= (rd & 0x1F) << 11;
468 inst |= (sa & 0x1F) << 6;
469 tcg_out32(s, inst);
470 }
472 /*
473 * Type jump.
474 * Returns true if the branch was in range and the insn was emitted.
475 */
476 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
477 {
478 uintptr_t dest = (uintptr_t)target;
479 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
480 int32_t inst;
482 /* The pc-region branch happens within the 256MB region of
483 the delay slot (thus the +4). */
484 if ((from ^ dest) & -(1 << 28)) {
485 return false;
486 }
487 tcg_debug_assert((dest & 3) == 0);
489 inst = opc;
490 inst |= (dest >> 2) & 0x3ffffff;
491 tcg_out32(s, inst);
492 return true;
493 }
495 static void tcg_out_nop(TCGContext *s)
496 {
497 tcg_out32(s, 0);
498 }
500 static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
501 {
502 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
503 }
505 static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
506 {
507 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
508 }
510 static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
511 {
512 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
513 }
515 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
516 {
517 /* Simple reg-reg move, optimising out the 'do nothing' case */
518 if (ret != arg) {
519 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
520 }
521 return true;
522 }
524 static void tcg_out_movi(TCGContext *s, TCGType type,
525 TCGReg ret, tcg_target_long arg)
526 {
527 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
528 arg = (int32_t)arg;
529 }
530 if (arg == (int16_t)arg) {
531 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
532 return;
533 }
534 if (arg == (uint16_t)arg) {
535 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
536 return;
537 }
538 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
539 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
540 } else {
541 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
542 if (arg & 0xffff0000ull) {
543 tcg_out_dsll(s, ret, ret, 16);
544 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
545 tcg_out_dsll(s, ret, ret, 16);
546 } else {
547 tcg_out_dsll(s, ret, ret, 32);
548 }
549 }
550 if (arg & 0xffff) {
551 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
552 }
553 }
555 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
556 {
557 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
558 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs);
559 }
561 static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs)
562 {
563 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff);
564 }
566 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
567 {
568 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32);
569 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs);
570 }
572 static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs)
573 {
574 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff);
575 }
577 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs)
578 {
579 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
580 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0);
581 }
583 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
584 {
585 tcg_out_ext32s(s, rd, rs);
586 }
588 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
589 {
590 tcg_out_ext32u(s, rd, rs);
591 }
593 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
594 {
595 tcg_out_ext32s(s, rd, rs);
596 }
598 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
599 {
600 return false;
601 }
603 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
604 tcg_target_long imm)
605 {
606 /* This function is only used for passing structs by reference. */
607 g_assert_not_reached();
608 }
610 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
611 {
612 /* ret and arg can't be register tmp0 */
613 tcg_debug_assert(ret != TCG_TMP0);
614 tcg_debug_assert(arg != TCG_TMP0);
616 /* With arg = abcd: */
617 if (use_mips32r2_instructions) {
618 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
619 if (flags & TCG_BSWAP_OS) {
620 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
621 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
622 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
623 }
624 return;
625 }
627 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
628 if (!(flags & TCG_BSWAP_IZ)) {
629 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
630 }
631 if (flags & TCG_BSWAP_OS) {
632 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
633 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
634 } else {
635 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
636 if (flags & TCG_BSWAP_OZ) {
637 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
638 }
639 }
640 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
641 }
643 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
644 {
645 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
646 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
647 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
648 }
649 }
651 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
652 {
653 if (use_mips32r2_instructions) {
654 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
655 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
656 if (flags & TCG_BSWAP_OZ) {
657 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
658 }
659 } else {
660 if (flags & TCG_BSWAP_OZ) {
661 tcg_out_bswap_subr(s, bswap32u_addr);
662 } else {
663 tcg_out_bswap_subr(s, bswap32_addr);
664 }
665 /* delay slot -- never omit the insn, like tcg_out_mov might. */
666 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
667 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
668 }
669 }
671 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
672 {
673 if (use_mips32r2_instructions) {
674 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
675 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
676 } else {
677 tcg_out_bswap_subr(s, bswap64_addr);
678 /* delay slot -- never omit the insn, like tcg_out_mov might. */
679 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
680 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
681 }
682 }
684 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
685 {
686 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
687 if (use_mips32r2_instructions) {
688 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
689 } else {
690 tcg_out_dsll(s, ret, arg, 32);
691 tcg_out_dsrl(s, ret, ret, 32);
692 }
693 }
695 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
696 TCGReg addr, intptr_t ofs)
697 {
698 int16_t lo = ofs;
699 if (ofs != lo) {
700 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
701 if (addr != TCG_REG_ZERO) {
702 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
703 }
704 addr = TCG_TMP0;
705 }
706 tcg_out_opc_imm(s, opc, data, addr, lo);
707 }
709 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
710 TCGReg arg1, intptr_t arg2)
711 {
712 MIPSInsn opc = OPC_LD;
713 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
714 opc = OPC_LW;
715 }
716 tcg_out_ldst(s, opc, arg, arg1, arg2);
717 }
719 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
720 TCGReg arg1, intptr_t arg2)
721 {
722 MIPSInsn opc = OPC_SD;
723 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
724 opc = OPC_SW;
725 }
726 tcg_out_ldst(s, opc, arg, arg1, arg2);
727 }
729 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
730 TCGReg base, intptr_t ofs)
731 {
732 if (val == 0) {
733 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
734 return true;
735 }
736 return false;
737 }
739 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
740 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
741 bool cbh, bool is_sub)
742 {
743 TCGReg th = TCG_TMP1;
745 /* If we have a negative constant such that negating it would
746 make the high part zero, we can (usually) eliminate one insn. */
747 if (cbl && cbh && bh == -1 && bl != 0) {
748 bl = -bl;
749 bh = 0;
750 is_sub = !is_sub;
751 }
753 /* By operating on the high part first, we get to use the final
754 carry operation to move back from the temporary. */
755 if (!cbh) {
756 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
757 } else if (bh != 0 || ah == rl) {
758 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
759 } else {
760 th = ah;
761 }
763 /* Note that tcg optimization should eliminate the bl == 0 case. */
764 if (is_sub) {
765 if (cbl) {
766 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
767 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
768 } else {
769 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
770 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
771 }
772 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
773 } else {
774 if (cbl) {
775 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
776 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
777 } else if (rl == al && rl == bl) {
778 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
779 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
780 } else {
781 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
782 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
783 }
784 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
785 }
786 }
788 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
789 #define MIPS_CMP_INV 1
790 #define MIPS_CMP_SWAP 2
792 static const uint8_t mips_cmp_map[16] = {
793 [TCG_COND_LT] = 0,
794 [TCG_COND_LTU] = 0,
795 [TCG_COND_GE] = MIPS_CMP_INV,
796 [TCG_COND_GEU] = MIPS_CMP_INV,
797 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
798 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
799 [TCG_COND_GT] = MIPS_CMP_SWAP,
800 [TCG_COND_GTU] = MIPS_CMP_SWAP,
801 };
803 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
804 TCGReg arg1, TCGReg arg2)
805 {
806 MIPSInsn s_opc = OPC_SLTU;
807 int cmp_map;
809 switch (cond) {
810 case TCG_COND_EQ:
811 if (arg2 != 0) {
812 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
813 arg1 = ret;
814 }
815 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
816 break;
818 case TCG_COND_NE:
819 if (arg2 != 0) {
820 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
821 arg1 = ret;
822 }
823 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
824 break;
826 case TCG_COND_LT:
827 case TCG_COND_GE:
828 case TCG_COND_LE:
829 case TCG_COND_GT:
830 s_opc = OPC_SLT;
831 /* FALLTHRU */
833 case TCG_COND_LTU:
834 case TCG_COND_GEU:
835 case TCG_COND_LEU:
836 case TCG_COND_GTU:
837 cmp_map = mips_cmp_map[cond];
838 if (cmp_map & MIPS_CMP_SWAP) {
839 TCGReg t = arg1;
840 arg1 = arg2;
841 arg2 = t;
842 }
843 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
844 if (cmp_map & MIPS_CMP_INV) {
845 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
846 }
847 break;
849 default:
850 g_assert_not_reached();
851 break;
852 }
853 }
855 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
856 TCGReg arg2, TCGLabel *l)
857 {
858 static const MIPSInsn b_zero[16] = {
859 [TCG_COND_LT] = OPC_BLTZ,
860 [TCG_COND_GT] = OPC_BGTZ,
861 [TCG_COND_LE] = OPC_BLEZ,
862 [TCG_COND_GE] = OPC_BGEZ,
863 };
865 MIPSInsn s_opc = OPC_SLTU;
866 MIPSInsn b_opc;
867 int cmp_map;
869 switch (cond) {
870 case TCG_COND_EQ:
871 b_opc = OPC_BEQ;
872 break;
873 case TCG_COND_NE:
874 b_opc = OPC_BNE;
875 break;
877 case TCG_COND_LT:
878 case TCG_COND_GT:
879 case TCG_COND_LE:
880 case TCG_COND_GE:
881 if (arg2 == 0) {
882 b_opc = b_zero[cond];
883 arg2 = arg1;
884 arg1 = 0;
885 break;
886 }
887 s_opc = OPC_SLT;
888 /* FALLTHRU */
890 case TCG_COND_LTU:
891 case TCG_COND_GTU:
892 case TCG_COND_LEU:
893 case TCG_COND_GEU:
894 cmp_map = mips_cmp_map[cond];
895 if (cmp_map & MIPS_CMP_SWAP) {
896 TCGReg t = arg1;
897 arg1 = arg2;
898 arg2 = t;
899 }
900 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
901 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
902 arg1 = TCG_TMP0;
903 arg2 = TCG_REG_ZERO;
904 break;
906 default:
907 g_assert_not_reached();
908 break;
909 }
911 tcg_out_opc_br(s, b_opc, arg1, arg2);
912 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
913 tcg_out_nop(s);
914 }
916 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
917 TCGReg al, TCGReg ah,
918 TCGReg bl, TCGReg bh)
919 {
920 /* Merge highpart comparison into AH. */
921 if (bh != 0) {
922 if (ah != 0) {
923 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
924 ah = tmp0;
925 } else {
926 ah = bh;
927 }
928 }
929 /* Merge lowpart comparison into AL. */
930 if (bl != 0) {
931 if (al != 0) {
932 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
933 al = tmp1;
934 } else {
935 al = bl;
936 }
937 }
938 /* Merge high and low part comparisons into AL. */
939 if (ah != 0) {
940 if (al != 0) {
941 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
942 al = tmp0;
943 } else {
944 al = ah;
945 }
946 }
947 return al;
948 }
950 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
951 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
952 {
953 TCGReg tmp0 = TCG_TMP0;
954 TCGReg tmp1 = ret;
956 tcg_debug_assert(ret != TCG_TMP0);
957 if (ret == ah || ret == bh) {
958 tcg_debug_assert(ret != TCG_TMP1);
959 tmp1 = TCG_TMP1;
960 }
962 switch (cond) {
963 case TCG_COND_EQ:
964 case TCG_COND_NE:
965 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
966 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
967 break;
969 default:
970 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
971 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
972 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
973 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
974 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
975 break;
976 }
977 }
979 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
980 TCGReg bl, TCGReg bh, TCGLabel *l)
981 {
982 TCGCond b_cond = TCG_COND_NE;
983 TCGReg tmp = TCG_TMP1;
985 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
986 With setcond, we emit between 3 and 10 insns and only 1 branch,
987 which ought to get better branch prediction. */
988 switch (cond) {
989 case TCG_COND_EQ:
990 case TCG_COND_NE:
991 b_cond = cond;
992 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
993 break;
995 default:
996 /* Minimize code size by preferring a compare not requiring INV. */
997 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
998 cond = tcg_invert_cond(cond);
999 b_cond = TCG_COND_EQ;
1000 }
1001 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1002 break;
1003 }
1005 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
1006 }
1008 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1009 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1010 {
1011 bool eqz = false;
1013 /* If one of the values is zero, put it last to match SEL*Z instructions */
1014 if (use_mips32r6_instructions && v1 == 0) {
1015 v1 = v2;
1016 v2 = 0;
1017 cond = tcg_invert_cond(cond);
1018 }
1020 switch (cond) {
1021 case TCG_COND_EQ:
1022 eqz = true;
1023 /* FALLTHRU */
1024 case TCG_COND_NE:
1025 if (c2 != 0) {
1026 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
1027 c1 = TCG_TMP0;
1028 }
1029 break;
1031 default:
1032 /* Minimize code size by preferring a compare not requiring INV. */
1033 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1034 cond = tcg_invert_cond(cond);
1035 eqz = true;
1036 }
1037 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1038 c1 = TCG_TMP0;
1039 break;
1040 }
1042 if (use_mips32r6_instructions) {
1043 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1044 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1046 if (v2 != 0) {
1047 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1048 }
1049 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1050 if (v2 != 0) {
1051 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1052 }
1053 } else {
1054 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1056 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1058 /* This should be guaranteed via constraints */
1059 tcg_debug_assert(v2 == ret);
1060 }
1061 }
1063 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
1064 {
1065 /* Note that the ABI requires the called function's address to be
1066 loaded into T9, even if a direct branch is in range. */
1067 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1069 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1070 if (tail) {
1071 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1072 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1073 }
1074 } else {
1075 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1076 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1077 }
1078 }
1079 }
1081 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1082 const TCGHelperInfo *info)
1083 {
1084 tcg_out_call_int(s, arg, false);
1085 tcg_out_nop(s);
1086 }
1088 #if defined(CONFIG_SOFTMMU)
1089 static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
1090 [MO_UB] = helper_ret_ldub_mmu,
1091 [MO_SB] = helper_ret_ldsb_mmu,
1092 [MO_LEUW] = helper_le_lduw_mmu,
1093 [MO_LESW] = helper_le_ldsw_mmu,
1094 [MO_LEUL] = helper_le_ldul_mmu,
1095 [MO_LEUQ] = helper_le_ldq_mmu,
1096 [MO_BEUW] = helper_be_lduw_mmu,
1097 [MO_BESW] = helper_be_ldsw_mmu,
1098 [MO_BEUL] = helper_be_ldul_mmu,
1099 [MO_BEUQ] = helper_be_ldq_mmu,
1100 #if TCG_TARGET_REG_BITS == 64
1101 [MO_LESL] = helper_le_ldsl_mmu,
1102 [MO_BESL] = helper_be_ldsl_mmu,
1103 #endif
1104 };
1106 static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
1107 [MO_UB] = helper_ret_stb_mmu,
1108 [MO_LEUW] = helper_le_stw_mmu,
1109 [MO_LEUL] = helper_le_stl_mmu,
1110 [MO_LEUQ] = helper_le_stq_mmu,
1111 [MO_BEUW] = helper_be_stw_mmu,
1112 [MO_BEUL] = helper_be_stl_mmu,
1113 [MO_BEUQ] = helper_be_stq_mmu,
1114 };
1116 /* Helper routines for marshalling helper function arguments into
1117 * the correct registers and stack.
1118 * I is where we want to put this argument, and is updated and returned
1119 * for the next call. ARG is the argument itself.
1120 *
1121 * We provide routines for arguments which are: immediate, 32 bit
1122 * value in register, 16 and 8 bit values in register (which must be zero
1123 * extended before use) and 64 bit value in a lo:hi register pair.
1124 */
1126 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1127 {
1128 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1129 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1130 } else {
1131 /* For N32 and N64, the initial offset is different. But there
1132 we also have 8 argument register so we don't run out here. */
1133 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1134 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1135 }
1136 return i + 1;
1137 }
1139 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1140 {
1141 TCGReg tmp = TCG_TMP0;
1142 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1143 tmp = tcg_target_call_iarg_regs[i];
1144 }
1145 tcg_out_ext8u(s, tmp, arg);
1146 return tcg_out_call_iarg_reg(s, i, tmp);
1147 }
1149 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1150 {
1151 TCGReg tmp = TCG_TMP0;
1152 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1153 tmp = tcg_target_call_iarg_regs[i];
1154 }
1155 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1156 return tcg_out_call_iarg_reg(s, i, tmp);
1157 }
1159 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1160 {
1161 TCGReg tmp = TCG_TMP0;
1162 if (arg == 0) {
1163 tmp = TCG_REG_ZERO;
1164 } else {
1165 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1166 tmp = tcg_target_call_iarg_regs[i];
1167 }
1168 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1169 }
1170 return tcg_out_call_iarg_reg(s, i, tmp);
1171 }
1173 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1174 {
1175 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1176 i = (i + 1) & ~1;
1177 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1178 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1179 return i;
1180 }
1182 /* We expect to use a 16-bit negative offset from ENV. */
1183 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1184 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1186 /*
1187 * Perform the tlb comparison operation.
1188 * The complete host address is placed in BASE.
1189 * Clobbers TMP0, TMP1, TMP2, TMP3.
1190 */
1191 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1192 TCGReg addrh, MemOpIdx oi,
1193 tcg_insn_unit *label_ptr[2], bool is_load)
1194 {
1195 MemOp opc = get_memop(oi);
1196 unsigned a_bits = get_alignment_bits(opc);
1197 unsigned s_bits = opc & MO_SIZE;
1198 unsigned a_mask = (1 << a_bits) - 1;
1199 unsigned s_mask = (1 << s_bits) - 1;
1200 int mem_index = get_mmuidx(oi);
1201 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1202 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1203 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1204 int add_off = offsetof(CPUTLBEntry, addend);
1205 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1206 : offsetof(CPUTLBEntry, addr_write));
1207 target_ulong tlb_mask;
1209 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1210 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1211 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1213 /* Extract the TLB index from the address into TMP3. */
1214 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1215 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1216 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1218 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1219 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1221 /* Load the (low-half) tlb comparator. */
1222 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1223 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
1224 } else {
1225 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1226 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1227 TCG_TMP0, TCG_TMP3, cmp_off);
1228 }
1230 /* Zero extend a 32-bit guest address for a 64-bit host. */
1231 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1232 tcg_out_ext32u(s, base, addrl);
1233 addrl = base;
1234 }
1236 /*
1237 * Mask the page bits, keeping the alignment bits to compare against.
1238 * For unaligned accesses, compare against the end of the access to
1239 * verify that it does not cross a page boundary.
1240 */
1241 tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
1242 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask);
1243 if (a_mask >= s_mask) {
1244 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1245 } else {
1246 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask);
1247 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
1248 }
1250 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1251 /* Load the tlb addend for the fast path. */
1252 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1253 }
1255 label_ptr[0] = s->code_ptr;
1256 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1258 /* Load and test the high half tlb comparator. */
1259 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1260 /* delay slot */
1261 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1263 /* Load the tlb addend for the fast path. */
1264 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1266 label_ptr[1] = s->code_ptr;
1267 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1268 }
1270 /* delay slot */
1271 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1272 }
1274 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
1275 TCGType ext,
1276 TCGReg datalo, TCGReg datahi,
1277 TCGReg addrlo, TCGReg addrhi,
1278 void *raddr, tcg_insn_unit *label_ptr[2])
1279 {
1280 TCGLabelQemuLdst *label = new_ldst_label(s);
1282 label->is_ld = is_ld;
1283 label->oi = oi;
1284 label->type = ext;
1285 label->datalo_reg = datalo;
1286 label->datahi_reg = datahi;
1287 label->addrlo_reg = addrlo;
1288 label->addrhi_reg = addrhi;
1289 label->raddr = tcg_splitwx_to_rx(raddr);
1290 label->label_ptr[0] = label_ptr[0];
1291 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1292 label->label_ptr[1] = label_ptr[1];
1293 }
1294 }
1296 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1297 {
1298 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1299 MemOpIdx oi = l->oi;
1300 MemOp opc = get_memop(oi);
1301 TCGReg v0;
1302 int i;
1304 /* resolve label address */
1305 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1306 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1307 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1308 return false;
1309 }
1311 i = 1;
1312 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1313 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1314 } else {
1315 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1316 }
1317 i = tcg_out_call_iarg_imm(s, i, oi);
1318 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1319 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1320 /* delay slot */
1321 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1323 v0 = l->datalo_reg;
1324 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1325 /* We eliminated V0 from the possible output registers, so it
1326 cannot be clobbered here. So we must move V1 first. */
1327 if (MIPS_BE) {
1328 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1329 v0 = l->datahi_reg;
1330 } else {
1331 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1332 }
1333 }
1335 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1336 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1337 return false;
1338 }
1340 /* delay slot */
1341 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1342 /* we always sign-extend 32-bit loads */
1343 tcg_out_ext32s(s, v0, TCG_REG_V0);
1344 } else {
1345 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1346 }
1347 return true;
1348 }
1350 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1351 {
1352 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1353 MemOpIdx oi = l->oi;
1354 MemOp opc = get_memop(oi);
1355 MemOp s_bits = opc & MO_SIZE;
1356 int i;
1358 /* resolve label address */
1359 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1360 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1361 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1362 return false;
1363 }
1365 i = 1;
1366 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1367 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1368 } else {
1369 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1370 }
1371 switch (s_bits) {
1372 case MO_8:
1373 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1374 break;
1375 case MO_16:
1376 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1377 break;
1378 case MO_32:
1379 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1380 break;
1381 case MO_64:
1382 if (TCG_TARGET_REG_BITS == 32) {
1383 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1384 } else {
1385 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1386 }
1387 break;
1388 default:
1389 g_assert_not_reached();
1390 }
1391 i = tcg_out_call_iarg_imm(s, i, oi);
1393 /* Tail call to the store helper. Thus force the return address
1394 computation to take place in the return address register. */
1395 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1396 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1397 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1398 /* delay slot */
1399 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1400 return true;
1401 }
1403 #else
1405 static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
1406 TCGReg addrhi, unsigned a_bits)
1407 {
1408 unsigned a_mask = (1 << a_bits) - 1;
1409 TCGLabelQemuLdst *l = new_ldst_label(s);
1411 l->is_ld = is_ld;
1412 l->addrlo_reg = addrlo;
1413 l->addrhi_reg = addrhi;
1415 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
1416 tcg_debug_assert(a_bits < 16);
1417 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
1419 l->label_ptr[0] = s->code_ptr;
1420 if (use_mips32r6_instructions) {
1421 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
1422 } else {
1423 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
1424 tcg_out_nop(s);
1425 }
1427 l->raddr = tcg_splitwx_to_rx(s->code_ptr);
1428 }
1430 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
1431 {
1432 void *target;
1434 if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1435 return false;
1436 }
1438 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1439 /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */
1440 TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg;
1441 TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg;
1443 if (a3 != TCG_REG_A2) {
1444 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1445 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1446 } else if (a2 != TCG_REG_A3) {
1447 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1448 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1449 } else {
1450 tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2);
1451 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3);
1452 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0);
1453 }
1454 } else {
1455 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg);
1456 }
1457 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
1459 /*
1460 * Tail call to the helper, with the return address back inline.
1461 * We have arrived here via BNEL, so $31 is already set.
1462 */
1463 target = (l->is_ld ? helper_unaligned_ld : helper_unaligned_st);
1464 tcg_out_call_int(s, target, true);
1465 return true;
1466 }
1468 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1469 {
1470 return tcg_out_fail_alignment(s, l);
1471 }
1473 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1474 {
1475 return tcg_out_fail_alignment(s, l);
1476 }
1477 #endif /* SOFTMMU */
1479 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1480 TCGReg base, MemOp opc, bool is_64)
1481 {
1482 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1483 case MO_UB:
1484 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1485 break;
1486 case MO_SB:
1487 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1488 break;
1489 case MO_UW | MO_BSWAP:
1490 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1491 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1492 break;
1493 case MO_UW:
1494 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1495 break;
1496 case MO_SW | MO_BSWAP:
1497 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1498 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS);
1499 break;
1500 case MO_SW:
1501 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1502 break;
1503 case MO_UL | MO_BSWAP:
1504 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1505 if (use_mips32r2_instructions) {
1506 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1507 tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1508 } else {
1509 tcg_out_bswap_subr(s, bswap32u_addr);
1510 /* delay slot */
1511 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1512 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1513 }
1514 break;
1515 }
1516 /* FALLTHRU */
1517 case MO_SL | MO_BSWAP:
1518 if (use_mips32r2_instructions) {
1519 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1520 tcg_out_bswap32(s, lo, lo, 0);
1521 } else {
1522 tcg_out_bswap_subr(s, bswap32_addr);
1523 /* delay slot */
1524 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1525 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1526 }
1527 break;
1528 case MO_UL:
1529 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1530 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1531 break;
1532 }
1533 /* FALLTHRU */
1534 case MO_SL:
1535 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1536 break;
1537 case MO_UQ | MO_BSWAP:
1538 if (TCG_TARGET_REG_BITS == 64) {
1539 if (use_mips32r2_instructions) {
1540 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1541 tcg_out_bswap64(s, lo, lo);
1542 } else {
1543 tcg_out_bswap_subr(s, bswap64_addr);
1544 /* delay slot */
1545 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1546 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1547 }
1548 } else if (use_mips32r2_instructions) {
1549 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1550 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1551 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1552 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1553 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1554 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1555 } else {
1556 tcg_out_bswap_subr(s, bswap32_addr);
1557 /* delay slot */
1558 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1559 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1560 tcg_out_bswap_subr(s, bswap32_addr);
1561 /* delay slot */
1562 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1563 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1564 }
1565 break;
1566 case MO_UQ:
1567 /* Prefer to load from offset 0 first, but allow for overlap. */
1568 if (TCG_TARGET_REG_BITS == 64) {
1569 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1570 } else if (MIPS_BE ? hi != base : lo == base) {
1571 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1572 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1573 } else {
1574 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1575 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1576 }
1577 break;
1578 default:
1579 g_assert_not_reached();
1580 }
1581 }
1583 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1584 TCGReg base, MemOp opc, bool is_64)
1585 {
1586 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
1587 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
1588 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR;
1589 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL;
1591 bool sgn = (opc & MO_SIGN);
1593 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1594 case MO_SW | MO_BE:
1595 case MO_UW | MO_BE:
1596 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0);
1597 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1);
1598 if (use_mips32r2_instructions) {
1599 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1600 } else {
1601 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
1602 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1603 }
1604 break;
1606 case MO_SW | MO_LE:
1607 case MO_UW | MO_LE:
1608 if (use_mips32r2_instructions && lo != base) {
1609 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1610 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1);
1611 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1612 } else {
1613 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0);
1614 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1);
1615 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8);
1616 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1617 }
1618 break;
1620 case MO_SL:
1621 case MO_UL:
1622 tcg_out_opc_imm(s, lw1, lo, base, 0);
1623 tcg_out_opc_imm(s, lw2, lo, base, 3);
1624 if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) {
1625 tcg_out_ext32u(s, lo, lo);
1626 }
1627 break;
1629 case MO_UL | MO_BSWAP:
1630 case MO_SL | MO_BSWAP:
1631 if (use_mips32r2_instructions) {
1632 tcg_out_opc_imm(s, lw1, lo, base, 0);
1633 tcg_out_opc_imm(s, lw2, lo, base, 3);
1634 tcg_out_bswap32(s, lo, lo,
1635 TCG_TARGET_REG_BITS == 64 && is_64
1636 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0);
1637 } else {
1638 const tcg_insn_unit *subr =
1639 (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn
1640 ? bswap32u_addr : bswap32_addr);
1642 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0);
1643 tcg_out_bswap_subr(s, subr);
1644 /* delay slot */
1645 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3);
1646 tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3);
1647 }
1648 break;
1650 case MO_UQ:
1651 if (TCG_TARGET_REG_BITS == 64) {
1652 tcg_out_opc_imm(s, ld1, lo, base, 0);
1653 tcg_out_opc_imm(s, ld2, lo, base, 7);
1654 } else {
1655 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0);
1656 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3);
1657 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0);
1658 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3);
1659 }
1660 break;
1662 case MO_UQ | MO_BSWAP:
1663 if (TCG_TARGET_REG_BITS == 64) {
1664 if (use_mips32r2_instructions) {
1665 tcg_out_opc_imm(s, ld1, lo, base, 0);
1666 tcg_out_opc_imm(s, ld2, lo, base, 7);
1667 tcg_out_bswap64(s, lo, lo);
1668 } else {
1669 tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0);
1670 tcg_out_bswap_subr(s, bswap64_addr);
1671 /* delay slot */
1672 tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7);
1673 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1674 }
1675 } else if (use_mips32r2_instructions) {
1676 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0);
1677 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3);
1678 tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0);
1679 tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3);
1680 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1681 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1682 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1683 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1684 } else {
1685 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0);
1686 tcg_out_bswap_subr(s, bswap32_addr);
1687 /* delay slot */
1688 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3);
1689 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0);
1690 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1691 tcg_out_bswap_subr(s, bswap32_addr);
1692 /* delay slot */
1693 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3);
1694 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1695 }
1696 break;
1698 default:
1699 g_assert_not_reached();
1700 }
1701 }
1703 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1704 {
1705 TCGReg addr_regl, addr_regh __attribute__((unused));
1706 TCGReg data_regl, data_regh;
1707 MemOpIdx oi;
1708 MemOp opc;
1709 #if defined(CONFIG_SOFTMMU)
1710 tcg_insn_unit *label_ptr[2];
1711 #else
1712 #endif
1713 unsigned a_bits, s_bits;
1714 TCGReg base = TCG_REG_A0;
1716 data_regl = *args++;
1717 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1718 addr_regl = *args++;
1719 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1720 oi = *args++;
1721 opc = get_memop(oi);
1722 a_bits = get_alignment_bits(opc);
1723 s_bits = opc & MO_SIZE;
1725 /*
1726 * R6 removes the left/right instructions but requires the
1727 * system to support misaligned memory accesses.
1728 */
1729 #if defined(CONFIG_SOFTMMU)
1730 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1731 if (use_mips32r6_instructions || a_bits >= s_bits) {
1732 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1733 } else {
1734 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
1735 }
1736 add_qemu_ldst_label(s, 1, oi,
1737 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1738 data_regl, data_regh, addr_regl, addr_regh,
1739 s->code_ptr, label_ptr);
1740 #else
1741 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1742 tcg_out_ext32u(s, base, addr_regl);
1743 addr_regl = base;
1744 }
1745 if (guest_base == 0 && data_regl != addr_regl) {
1746 base = addr_regl;
1747 } else if (guest_base == (int16_t)guest_base) {
1748 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1749 } else {
1750 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1751 }
1752 if (use_mips32r6_instructions) {
1753 if (a_bits) {
1754 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1755 }
1756 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1757 } else {
1758 if (a_bits && a_bits != s_bits) {
1759 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1760 }
1761 if (a_bits >= s_bits) {
1762 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1763 } else {
1764 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
1765 }
1766 }
1767 #endif
1768 }
1770 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1771 TCGReg base, MemOp opc)
1772 {
1773 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1774 if ((lo | hi) == 0) {
1775 opc &= ~MO_BSWAP;
1776 }
1778 switch (opc & (MO_SIZE | MO_BSWAP)) {
1779 case MO_8:
1780 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1781 break;
1783 case MO_16 | MO_BSWAP:
1784 tcg_out_bswap16(s, TCG_TMP1, lo, 0);
1785 lo = TCG_TMP1;
1786 /* FALLTHRU */
1787 case MO_16:
1788 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1789 break;
1791 case MO_32 | MO_BSWAP:
1792 tcg_out_bswap32(s, TCG_TMP3, lo, 0);
1793 lo = TCG_TMP3;
1794 /* FALLTHRU */
1795 case MO_32:
1796 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1797 break;
1799 case MO_64 | MO_BSWAP:
1800 if (TCG_TARGET_REG_BITS == 64) {
1801 tcg_out_bswap64(s, TCG_TMP3, lo);
1802 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1803 } else if (use_mips32r2_instructions) {
1804 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1805 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1806 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1807 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1808 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1809 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1810 } else {
1811 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
1812 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1813 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
1814 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1815 }
1816 break;
1817 case MO_64:
1818 if (TCG_TARGET_REG_BITS == 64) {
1819 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1820 } else {
1821 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1822 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1823 }
1824 break;
1826 default:
1827 g_assert_not_reached();
1828 }
1829 }
1831 static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1832 TCGReg base, MemOp opc)
1833 {
1834 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR;
1835 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL;
1836 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR;
1837 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL;
1839 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1840 if ((lo | hi) == 0) {
1841 opc &= ~MO_BSWAP;
1842 }
1844 switch (opc & (MO_SIZE | MO_BSWAP)) {
1845 case MO_16 | MO_BE:
1846 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1847 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0);
1848 tcg_out_opc_imm(s, OPC_SB, lo, base, 1);
1849 break;
1851 case MO_16 | MO_LE:
1852 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1853 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1854 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1);
1855 break;
1857 case MO_32 | MO_BSWAP:
1858 tcg_out_bswap32(s, TCG_TMP3, lo, 0);
1859 lo = TCG_TMP3;
1860 /* fall through */
1861 case MO_32:
1862 tcg_out_opc_imm(s, sw1, lo, base, 0);
1863 tcg_out_opc_imm(s, sw2, lo, base, 3);
1864 break;
1866 case MO_64 | MO_BSWAP:
1867 if (TCG_TARGET_REG_BITS == 64) {
1868 tcg_out_bswap64(s, TCG_TMP3, lo);
1869 lo = TCG_TMP3;
1870 } else if (use_mips32r2_instructions) {
1871 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo);
1872 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi);
1873 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1874 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1875 hi = MIPS_BE ? TCG_TMP0 : TCG_TMP1;
1876 lo = MIPS_BE ? TCG_TMP1 : TCG_TMP0;
1877 } else {
1878 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
1879 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0);
1880 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3);
1881 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
1882 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0);
1883 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3);
1884 break;
1885 }
1886 /* fall through */
1887 case MO_64:
1888 if (TCG_TARGET_REG_BITS == 64) {
1889 tcg_out_opc_imm(s, sd1, lo, base, 0);
1890 tcg_out_opc_imm(s, sd2, lo, base, 7);
1891 } else {
1892 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0);
1893 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3);
1894 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0);
1895 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3);
1896 }
1897 break;
1899 default:
1900 g_assert_not_reached();
1901 }
1902 }
1903 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1904 {
1905 TCGReg addr_regl, addr_regh __attribute__((unused));
1906 TCGReg data_regl, data_regh;
1907 MemOpIdx oi;
1908 MemOp opc;
1909 #if defined(CONFIG_SOFTMMU)
1910 tcg_insn_unit *label_ptr[2];
1911 #endif
1912 unsigned a_bits, s_bits;
1913 TCGReg base = TCG_REG_A0;
1915 data_regl = *args++;
1916 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1917 addr_regl = *args++;
1918 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1919 oi = *args++;
1920 opc = get_memop(oi);
1921 a_bits = get_alignment_bits(opc);
1922 s_bits = opc & MO_SIZE;
1924 /*
1925 * R6 removes the left/right instructions but requires the
1926 * system to support misaligned memory accesses.
1927 */
1928 #if defined(CONFIG_SOFTMMU)
1929 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1930 if (use_mips32r6_instructions || a_bits >= s_bits) {
1931 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1932 } else {
1933 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
1934 }
1935 add_qemu_ldst_label(s, 0, oi,
1936 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1937 data_regl, data_regh, addr_regl, addr_regh,
1938 s->code_ptr, label_ptr);
1939 #else
1940 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1941 tcg_out_ext32u(s, base, addr_regl);
1942 addr_regl = base;
1943 }
1944 if (guest_base == 0) {
1945 base = addr_regl;
1946 } else if (guest_base == (int16_t)guest_base) {
1947 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1948 } else {
1949 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1950 }
1951 if (use_mips32r6_instructions) {
1952 if (a_bits) {
1953 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1954 }
1955 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1956 } else {
1957 if (a_bits && a_bits != s_bits) {
1958 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1959 }
1960 if (a_bits >= s_bits) {
1961 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1962 } else {
1963 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
1964 }
1965 }
1966 #endif
1967 }
1969 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1970 {
1971 static const MIPSInsn sync[] = {
1972 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1973 as the former is an ordering barrier and the latter
1974 is a completion barrier. */
1975 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1976 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1977 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1978 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1979 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1980 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1981 };
1982 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1983 }
1985 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1986 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1987 {
1988 if (use_mips32r6_instructions) {
1989 if (a2 == width) {
1990 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1991 } else {
1992 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1993 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1994 }
1995 } else {
1996 if (a2 == width) {
1997 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1998 } else if (a0 == a2) {
1999 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
2000 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
2001 } else if (a0 != a1) {
2002 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
2003 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
2004 } else {
2005 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
2006 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
2007 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
2008 }
2009 }
2010 }
2012 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
2013 {
2014 TCGReg b0 = TCG_REG_ZERO;
2016 if (a0 & ~0xffff) {
2017 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
2018 b0 = TCG_REG_V0;
2019 }
2020 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
2021 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
2022 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
2023 }
2024 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
2025 }
2027 static void tcg_out_goto_tb(TCGContext *s, int which)
2028 {
2029 /* indirect jump method */
2030 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
2031 get_jmp_target_addr(s, which));
2032 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
2033 tcg_out_nop(s);
2034 set_jmp_reset_offset(s, which);
2035 }
2037 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
2038 uintptr_t jmp_rx, uintptr_t jmp_rw)
2039 {
2040 /* Always indirect, nothing to do */
2041 }
2043 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
2044 const TCGArg args[TCG_MAX_OP_ARGS],
2045 const int const_args[TCG_MAX_OP_ARGS])
2046 {
2047 MIPSInsn i1, i2;
2048 TCGArg a0, a1, a2;
2049 int c2;
2051 /*
2052 * Note that many operands use the constraint set "rZ".
2053 * We make use of the fact that 0 is the ZERO register,
2054 * and hence such cases need not check for const_args.
2055 */
2056 a0 = args[0];
2057 a1 = args[1];
2058 a2 = args[2];
2059 c2 = const_args[2];
2061 switch (opc) {
2062 case INDEX_op_goto_ptr:
2063 /* jmp to the given host address (could be epilogue) */
2064 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
2065 tcg_out_nop(s);
2066 break;
2067 case INDEX_op_br:
2068 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
2069 arg_label(a0));
2070 break;
2072 case INDEX_op_ld8u_i32:
2073 case INDEX_op_ld8u_i64:
2074 i1 = OPC_LBU;
2075 goto do_ldst;
2076 case INDEX_op_ld8s_i32:
2077 case INDEX_op_ld8s_i64:
2078 i1 = OPC_LB;
2079 goto do_ldst;
2080 case INDEX_op_ld16u_i32:
2081 case INDEX_op_ld16u_i64:
2082 i1 = OPC_LHU;
2083 goto do_ldst;
2084 case INDEX_op_ld16s_i32:
2085 case INDEX_op_ld16s_i64:
2086 i1 = OPC_LH;
2087 goto do_ldst;
2088 case INDEX_op_ld_i32:
2089 case INDEX_op_ld32s_i64:
2090 i1 = OPC_LW;
2091 goto do_ldst;
2092 case INDEX_op_ld32u_i64:
2093 i1 = OPC_LWU;
2094 goto do_ldst;
2095 case INDEX_op_ld_i64:
2096 i1 = OPC_LD;
2097 goto do_ldst;
2098 case INDEX_op_st8_i32:
2099 case INDEX_op_st8_i64:
2100 i1 = OPC_SB;
2101 goto do_ldst;
2102 case INDEX_op_st16_i32:
2103 case INDEX_op_st16_i64:
2104 i1 = OPC_SH;
2105 goto do_ldst;
2106 case INDEX_op_st_i32:
2107 case INDEX_op_st32_i64:
2108 i1 = OPC_SW;
2109 goto do_ldst;
2110 case INDEX_op_st_i64:
2111 i1 = OPC_SD;
2112 do_ldst:
2113 tcg_out_ldst(s, i1, a0, a1, a2);
2114 break;
2116 case INDEX_op_add_i32:
2117 i1 = OPC_ADDU, i2 = OPC_ADDIU;
2118 goto do_binary;
2119 case INDEX_op_add_i64:
2120 i1 = OPC_DADDU, i2 = OPC_DADDIU;
2121 goto do_binary;
2122 case INDEX_op_or_i32:
2123 case INDEX_op_or_i64:
2124 i1 = OPC_OR, i2 = OPC_ORI;
2125 goto do_binary;
2126 case INDEX_op_xor_i32:
2127 case INDEX_op_xor_i64:
2128 i1 = OPC_XOR, i2 = OPC_XORI;
2129 do_binary:
2130 if (c2) {
2131 tcg_out_opc_imm(s, i2, a0, a1, a2);
2132 break;
2133 }
2134 do_binaryv:
2135 tcg_out_opc_reg(s, i1, a0, a1, a2);
2136 break;
2138 case INDEX_op_sub_i32:
2139 i1 = OPC_SUBU, i2 = OPC_ADDIU;
2140 goto do_subtract;
2141 case INDEX_op_sub_i64:
2142 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
2143 do_subtract:
2144 if (c2) {
2145 tcg_out_opc_imm(s, i2, a0, a1, -a2);
2146 break;
2147 }
2148 goto do_binaryv;
2149 case INDEX_op_and_i32:
2150 if (c2 && a2 != (uint16_t)a2) {
2151 int msb = ctz32(~a2) - 1;
2152 tcg_debug_assert(use_mips32r2_instructions);
2153 tcg_debug_assert(is_p2m1(a2));
2154 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
2155 break;
2156 }
2157 i1 = OPC_AND, i2 = OPC_ANDI;
2158 goto do_binary;
2159 case INDEX_op_and_i64:
2160 if (c2 && a2 != (uint16_t)a2) {
2161 int msb = ctz64(~a2) - 1;
2162 tcg_debug_assert(use_mips32r2_instructions);
2163 tcg_debug_assert(is_p2m1(a2));
2164 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
2165 break;
2166 }
2167 i1 = OPC_AND, i2 = OPC_ANDI;
2168 goto do_binary;
2169 case INDEX_op_nor_i32:
2170 case INDEX_op_nor_i64:
2171 i1 = OPC_NOR;
2172 goto do_binaryv;
2174 case INDEX_op_mul_i32:
2175 if (use_mips32_instructions) {
2176 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
2177 break;
2178 }
2179 i1 = OPC_MULT, i2 = OPC_MFLO;
2180 goto do_hilo1;
2181 case INDEX_op_mulsh_i32:
2182 if (use_mips32r6_instructions) {
2183 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
2184 break;
2185 }
2186 i1 = OPC_MULT, i2 = OPC_MFHI;
2187 goto do_hilo1;
2188 case INDEX_op_muluh_i32:
2189 if (use_mips32r6_instructions) {
2190 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
2191 break;
2192 }
2193 i1 = OPC_MULTU, i2 = OPC_MFHI;
2194 goto do_hilo1;
2195 case INDEX_op_div_i32:
2196 if (use_mips32r6_instructions) {
2197 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
2198 break;
2199 }
2200 i1 = OPC_DIV, i2 = OPC_MFLO;
2201 goto do_hilo1;
2202 case INDEX_op_divu_i32:
2203 if (use_mips32r6_instructions) {
2204 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
2205 break;
2206 }
2207 i1 = OPC_DIVU, i2 = OPC_MFLO;
2208 goto do_hilo1;
2209 case INDEX_op_rem_i32:
2210 if (use_mips32r6_instructions) {
2211 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
2212 break;
2213 }
2214 i1 = OPC_DIV, i2 = OPC_MFHI;
2215 goto do_hilo1;
2216 case INDEX_op_remu_i32:
2217 if (use_mips32r6_instructions) {
2218 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
2219 break;
2220 }
2221 i1 = OPC_DIVU, i2 = OPC_MFHI;
2222 goto do_hilo1;
2223 case INDEX_op_mul_i64:
2224 if (use_mips32r6_instructions) {
2225 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
2226 break;
2227 }
2228 i1 = OPC_DMULT, i2 = OPC_MFLO;
2229 goto do_hilo1;
2230 case INDEX_op_mulsh_i64:
2231 if (use_mips32r6_instructions) {
2232 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
2233 break;
2234 }
2235 i1 = OPC_DMULT, i2 = OPC_MFHI;
2236 goto do_hilo1;
2237 case INDEX_op_muluh_i64:
2238 if (use_mips32r6_instructions) {
2239 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
2240 break;
2241 }
2242 i1 = OPC_DMULTU, i2 = OPC_MFHI;
2243 goto do_hilo1;
2244 case INDEX_op_div_i64:
2245 if (use_mips32r6_instructions) {
2246 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
2247 break;
2248 }
2249 i1 = OPC_DDIV, i2 = OPC_MFLO;
2250 goto do_hilo1;
2251 case INDEX_op_divu_i64:
2252 if (use_mips32r6_instructions) {
2253 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
2254 break;
2255 }
2256 i1 = OPC_DDIVU, i2 = OPC_MFLO;
2257 goto do_hilo1;
2258 case INDEX_op_rem_i64:
2259 if (use_mips32r6_instructions) {
2260 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
2261 break;
2262 }
2263 i1 = OPC_DDIV, i2 = OPC_MFHI;
2264 goto do_hilo1;
2265 case INDEX_op_remu_i64:
2266 if (use_mips32r6_instructions) {
2267 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
2268 break;
2269 }
2270 i1 = OPC_DDIVU, i2 = OPC_MFHI;
2271 do_hilo1:
2272 tcg_out_opc_reg(s, i1, 0, a1, a2);
2273 tcg_out_opc_reg(s, i2, a0, 0, 0);
2274 break;
2276 case INDEX_op_muls2_i32:
2277 i1 = OPC_MULT;
2278 goto do_hilo2;
2279 case INDEX_op_mulu2_i32:
2280 i1 = OPC_MULTU;
2281 goto do_hilo2;
2282 case INDEX_op_muls2_i64:
2283 i1 = OPC_DMULT;
2284 goto do_hilo2;
2285 case INDEX_op_mulu2_i64:
2286 i1 = OPC_DMULTU;
2287 do_hilo2:
2288 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
2289 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
2290 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
2291 break;
2293 case INDEX_op_not_i32:
2294 case INDEX_op_not_i64:
2295 i1 = OPC_NOR;
2296 goto do_unary;
2297 do_unary:
2298 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
2299 break;
2301 case INDEX_op_bswap16_i32:
2302 case INDEX_op_bswap16_i64:
2303 tcg_out_bswap16(s, a0, a1, a2);
2304 break;
2305 case INDEX_op_bswap32_i32:
2306 tcg_out_bswap32(s, a0, a1, 0);
2307 break;
2308 case INDEX_op_bswap32_i64:
2309 tcg_out_bswap32(s, a0, a1, a2);
2310 break;
2311 case INDEX_op_bswap64_i64:
2312 tcg_out_bswap64(s, a0, a1);
2313 break;
2314 case INDEX_op_extrh_i64_i32:
2315 tcg_out_dsra(s, a0, a1, 32);
2316 break;
2318 case INDEX_op_sar_i32:
2319 i1 = OPC_SRAV, i2 = OPC_SRA;
2320 goto do_shift;
2321 case INDEX_op_shl_i32:
2322 i1 = OPC_SLLV, i2 = OPC_SLL;
2323 goto do_shift;
2324 case INDEX_op_shr_i32:
2325 i1 = OPC_SRLV, i2 = OPC_SRL;
2326 goto do_shift;
2327 case INDEX_op_rotr_i32:
2328 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2329 do_shift:
2330 if (c2) {
2331 tcg_out_opc_sa(s, i2, a0, a1, a2);
2332 break;
2333 }
2334 do_shiftv:
2335 tcg_out_opc_reg(s, i1, a0, a2, a1);
2336 break;
2337 case INDEX_op_rotl_i32:
2338 if (c2) {
2339 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
2340 } else {
2341 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2342 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
2343 }
2344 break;
2345 case INDEX_op_sar_i64:
2346 if (c2) {
2347 tcg_out_dsra(s, a0, a1, a2);
2348 break;
2349 }
2350 i1 = OPC_DSRAV;
2351 goto do_shiftv;
2352 case INDEX_op_shl_i64:
2353 if (c2) {
2354 tcg_out_dsll(s, a0, a1, a2);
2355 break;
2356 }
2357 i1 = OPC_DSLLV;
2358 goto do_shiftv;
2359 case INDEX_op_shr_i64:
2360 if (c2) {
2361 tcg_out_dsrl(s, a0, a1, a2);
2362 break;
2363 }
2364 i1 = OPC_DSRLV;
2365 goto do_shiftv;
2366 case INDEX_op_rotr_i64:
2367 if (c2) {
2368 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2369 break;
2370 }
2371 i1 = OPC_DROTRV;
2372 goto do_shiftv;
2373 case INDEX_op_rotl_i64:
2374 if (c2) {
2375 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2376 } else {
2377 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2378 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2379 }
2380 break;
2382 case INDEX_op_clz_i32:
2383 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2384 break;
2385 case INDEX_op_clz_i64:
2386 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2387 break;
2389 case INDEX_op_deposit_i32:
2390 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2391 break;
2392 case INDEX_op_deposit_i64:
2393 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2394 args[3] + args[4] - 1, args[3]);
2395 break;
2396 case INDEX_op_extract_i32:
2397 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2398 break;
2399 case INDEX_op_extract_i64:
2400 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2401 args[3] - 1, a2);
2402 break;
2404 case INDEX_op_brcond_i32:
2405 case INDEX_op_brcond_i64:
2406 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2407 break;
2408 case INDEX_op_brcond2_i32:
2409 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2410 break;
2412 case INDEX_op_movcond_i32:
2413 case INDEX_op_movcond_i64:
2414 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2415 break;
2417 case INDEX_op_setcond_i32:
2418 case INDEX_op_setcond_i64:
2419 tcg_out_setcond(s, args[3], a0, a1, a2);
2420 break;
2421 case INDEX_op_setcond2_i32:
2422 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2423 break;
2425 case INDEX_op_qemu_ld_i32:
2426 tcg_out_qemu_ld(s, args, false);
2427 break;
2428 case INDEX_op_qemu_ld_i64:
2429 tcg_out_qemu_ld(s, args, true);
2430 break;
2431 case INDEX_op_qemu_st_i32:
2432 tcg_out_qemu_st(s, args, false);
2433 break;
2434 case INDEX_op_qemu_st_i64:
2435 tcg_out_qemu_st(s, args, true);
2436 break;
2438 case INDEX_op_add2_i32:
2439 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2440 const_args[4], const_args[5], false);
2441 break;
2442 case INDEX_op_sub2_i32:
2443 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2444 const_args[4], const_args[5], true);
2445 break;
2447 case INDEX_op_mb:
2448 tcg_out_mb(s, a0);
2449 break;
2450 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2451 case INDEX_op_mov_i64:
2452 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2453 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
2454 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
2455 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2456 case INDEX_op_ext8s_i64:
2457 case INDEX_op_ext8u_i32:
2458 case INDEX_op_ext8u_i64:
2459 case INDEX_op_ext16s_i32:
2460 case INDEX_op_ext16s_i64:
2461 case INDEX_op_ext32s_i64:
2462 case INDEX_op_ext32u_i64:
2463 case INDEX_op_ext_i32_i64:
2464 case INDEX_op_extu_i32_i64:
2465 case INDEX_op_extrl_i64_i32:
2466 default:
2467 g_assert_not_reached();
2468 }
2469 }
2471 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2472 {
2473 switch (op) {
2474 case INDEX_op_goto_ptr:
2475 return C_O0_I1(r);
2477 case INDEX_op_ld8u_i32:
2478 case INDEX_op_ld8s_i32:
2479 case INDEX_op_ld16u_i32:
2480 case INDEX_op_ld16s_i32:
2481 case INDEX_op_ld_i32:
2482 case INDEX_op_not_i32:
2483 case INDEX_op_bswap16_i32:
2484 case INDEX_op_bswap32_i32:
2485 case INDEX_op_ext8s_i32:
2486 case INDEX_op_ext16s_i32:
2487 case INDEX_op_extract_i32:
2488 case INDEX_op_ld8u_i64:
2489 case INDEX_op_ld8s_i64:
2490 case INDEX_op_ld16u_i64:
2491 case INDEX_op_ld16s_i64:
2492 case INDEX_op_ld32s_i64:
2493 case INDEX_op_ld32u_i64:
2494 case INDEX_op_ld_i64:
2495 case INDEX_op_not_i64:
2496 case INDEX_op_bswap16_i64:
2497 case INDEX_op_bswap32_i64:
2498 case INDEX_op_bswap64_i64:
2499 case INDEX_op_ext8s_i64:
2500 case INDEX_op_ext16s_i64:
2501 case INDEX_op_ext32s_i64:
2502 case INDEX_op_ext32u_i64:
2503 case INDEX_op_ext_i32_i64:
2504 case INDEX_op_extu_i32_i64:
2505 case INDEX_op_extrl_i64_i32:
2506 case INDEX_op_extrh_i64_i32:
2507 case INDEX_op_extract_i64:
2508 return C_O1_I1(r, r);
2510 case INDEX_op_st8_i32:
2511 case INDEX_op_st16_i32:
2512 case INDEX_op_st_i32:
2513 case INDEX_op_st8_i64:
2514 case INDEX_op_st16_i64:
2515 case INDEX_op_st32_i64:
2516 case INDEX_op_st_i64:
2517 return C_O0_I2(rZ, r);
2519 case INDEX_op_add_i32:
2520 case INDEX_op_add_i64:
2521 return C_O1_I2(r, r, rJ);
2522 case INDEX_op_sub_i32:
2523 case INDEX_op_sub_i64:
2524 return C_O1_I2(r, rZ, rN);
2525 case INDEX_op_mul_i32:
2526 case INDEX_op_mulsh_i32:
2527 case INDEX_op_muluh_i32:
2528 case INDEX_op_div_i32:
2529 case INDEX_op_divu_i32:
2530 case INDEX_op_rem_i32:
2531 case INDEX_op_remu_i32:
2532 case INDEX_op_nor_i32:
2533 case INDEX_op_setcond_i32:
2534 case INDEX_op_mul_i64:
2535 case INDEX_op_mulsh_i64:
2536 case INDEX_op_muluh_i64:
2537 case INDEX_op_div_i64:
2538 case INDEX_op_divu_i64:
2539 case INDEX_op_rem_i64:
2540 case INDEX_op_remu_i64:
2541 case INDEX_op_nor_i64:
2542 case INDEX_op_setcond_i64:
2543 return C_O1_I2(r, rZ, rZ);
2544 case INDEX_op_muls2_i32:
2545 case INDEX_op_mulu2_i32:
2546 case INDEX_op_muls2_i64:
2547 case INDEX_op_mulu2_i64:
2548 return C_O2_I2(r, r, r, r);
2549 case INDEX_op_and_i32:
2550 case INDEX_op_and_i64:
2551 return C_O1_I2(r, r, rIK);
2552 case INDEX_op_or_i32:
2553 case INDEX_op_xor_i32:
2554 case INDEX_op_or_i64:
2555 case INDEX_op_xor_i64:
2556 return C_O1_I2(r, r, rI);
2557 case INDEX_op_shl_i32:
2558 case INDEX_op_shr_i32:
2559 case INDEX_op_sar_i32:
2560 case INDEX_op_rotr_i32:
2561 case INDEX_op_rotl_i32:
2562 case INDEX_op_shl_i64:
2563 case INDEX_op_shr_i64:
2564 case INDEX_op_sar_i64:
2565 case INDEX_op_rotr_i64:
2566 case INDEX_op_rotl_i64:
2567 return C_O1_I2(r, r, ri);
2568 case INDEX_op_clz_i32:
2569 case INDEX_op_clz_i64:
2570 return C_O1_I2(r, r, rWZ);
2572 case INDEX_op_deposit_i32:
2573 case INDEX_op_deposit_i64:
2574 return C_O1_I2(r, 0, rZ);
2575 case INDEX_op_brcond_i32:
2576 case INDEX_op_brcond_i64:
2577 return C_O0_I2(rZ, rZ);
2578 case INDEX_op_movcond_i32:
2579 case INDEX_op_movcond_i64:
2580 return (use_mips32r6_instructions
2581 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2582 : C_O1_I4(r, rZ, rZ, rZ, 0));
2583 case INDEX_op_add2_i32:
2584 case INDEX_op_sub2_i32:
2585 return C_O2_I4(r, r, rZ, rZ, rN, rN);
2586 case INDEX_op_setcond2_i32:
2587 return C_O1_I4(r, rZ, rZ, rZ, rZ);
2588 case INDEX_op_brcond2_i32:
2589 return C_O0_I4(rZ, rZ, rZ, rZ);
2591 case INDEX_op_qemu_ld_i32:
2592 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2593 ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
2594 case INDEX_op_qemu_st_i32:
2595 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2596 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
2597 case INDEX_op_qemu_ld_i64:
2598 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
2599 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
2600 : C_O2_I2(r, r, L, L));
2601 case INDEX_op_qemu_st_i64:
2602 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
2603 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
2604 : C_O0_I4(SZ, SZ, S, S));
2606 default:
2607 g_assert_not_reached();
2608 }
2609 }
2611 static const int tcg_target_callee_save_regs[] = {
2612 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2613 TCG_REG_S1,
2614 TCG_REG_S2,
2615 TCG_REG_S3,
2616 TCG_REG_S4,
2617 TCG_REG_S5,
2618 TCG_REG_S6,
2619 TCG_REG_S7,
2620 TCG_REG_S8,
2621 TCG_REG_RA, /* should be last for ABI compliance */
2622 };
2624 /* The Linux kernel doesn't provide any information about the available
2625 instruction set. Probe it using a signal handler. */
2628 #ifndef use_movnz_instructions
2629 bool use_movnz_instructions = false;
2630 #endif
2632 #ifndef use_mips32_instructions
2633 bool use_mips32_instructions = false;
2634 #endif
2636 #ifndef use_mips32r2_instructions
2637 bool use_mips32r2_instructions = false;
2638 #endif
2640 static volatile sig_atomic_t got_sigill;
2642 static void sigill_handler(int signo, siginfo_t *si, void *data)
2643 {
2644 /* Skip the faulty instruction */
2645 ucontext_t *uc = (ucontext_t *)data;
2646 uc->uc_mcontext.pc += 4;
2648 got_sigill = 1;
2649 }
2651 static void tcg_target_detect_isa(void)
2652 {
2653 struct sigaction sa_old, sa_new;
2655 memset(&sa_new, 0, sizeof(sa_new));
2656 sa_new.sa_flags = SA_SIGINFO;
2657 sa_new.sa_sigaction = sigill_handler;
2658 sigaction(SIGILL, &sa_new, &sa_old);
2660 /* Probe for movn/movz, necessary to implement movcond. */
2661 #ifndef use_movnz_instructions
2662 got_sigill = 0;
2663 asm volatile(".set push\n"
2664 ".set mips32\n"
2665 "movn $zero, $zero, $zero\n"
2666 "movz $zero, $zero, $zero\n"
2667 ".set pop\n"
2668 : : : );
2669 use_movnz_instructions = !got_sigill;
2670 #endif
2672 /* Probe for MIPS32 instructions. As no subsetting is allowed
2673 by the specification, it is only necessary to probe for one
2674 of the instructions. */
2675 #ifndef use_mips32_instructions
2676 got_sigill = 0;
2677 asm volatile(".set push\n"
2678 ".set mips32\n"
2679 "mul $zero, $zero\n"
2680 ".set pop\n"
2681 : : : );
2682 use_mips32_instructions = !got_sigill;
2683 #endif
2685 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2686 available. As no subsetting is allowed by the specification,
2687 it is only necessary to probe for one of the instructions. */
2688 #ifndef use_mips32r2_instructions
2689 if (use_mips32_instructions) {
2690 got_sigill = 0;
2691 asm volatile(".set push\n"
2692 ".set mips32r2\n"
2693 "seb $zero, $zero\n"
2694 ".set pop\n"
2695 : : : );
2696 use_mips32r2_instructions = !got_sigill;
2697 }
2698 #endif
2700 sigaction(SIGILL, &sa_old, NULL);
2701 }
2703 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2704 {
2705 uintptr_t p = (uintptr_t)s->code_ptr;
2706 if (p & 15) {
2707 p = (p + 15) & -16;
2708 s->code_ptr = (void *)p;
2709 }
2710 return s->code_ptr;
2711 }
2713 /* Stack frame parameters. */
2714 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2715 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2716 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2718 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2719 + TCG_TARGET_STACK_ALIGN - 1) \
2720 & -TCG_TARGET_STACK_ALIGN)
2721 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2723 /* We're expecting to be able to use an immediate for frame allocation. */
2724 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2726 /* Generate global QEMU prologue and epilogue code */
2727 static void tcg_target_qemu_prologue(TCGContext *s)
2728 {
2729 int i;
2731 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2733 /* TB prologue */
2734 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2735 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2736 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2737 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2738 }
2740 #ifndef CONFIG_SOFTMMU
2741 if (guest_base) {
2742 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2743 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2744 }
2745 #endif
2747 /* Call generated code */
2748 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2749 /* delay slot */
2750 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2752 /*
2753 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2754 * and fall through to the rest of the epilogue.
2755 */
2756 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2757 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2759 /* TB epilogue */
2760 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2761 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2762 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2763 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2764 }
2766 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2767 /* delay slot */
2768 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2770 if (use_mips32r2_instructions) {
2771 return;
2772 }
2774 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2775 clobbers TCG_TMP1, TCG_TMP2. */
2777 /*
2778 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2779 */
2780 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2781 /* t3 = (ssss)d000 */
2782 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2783 /* t1 = 000a */
2784 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2785 /* t2 = 00c0 */
2786 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2787 /* t3 = d00a */
2788 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2789 /* t1 = 0abc */
2790 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2791 /* t2 = 0c00 */
2792 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2793 /* t1 = 00b0 */
2794 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2795 /* t3 = dc0a */
2796 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2797 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2798 /* t3 = dcba -- delay slot */
2799 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2801 if (TCG_TARGET_REG_BITS == 32) {
2802 return;
2803 }
2805 /*
2806 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2807 */
2808 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2809 /* t1 = (0000)000d */
2810 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2811 /* t3 = 000a */
2812 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2813 /* t1 = (0000)d000 */
2814 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2815 /* t2 = 00c0 */
2816 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2817 /* t3 = d00a */
2818 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2819 /* t1 = 0abc */
2820 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2821 /* t2 = 0c00 */
2822 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2823 /* t1 = 00b0 */
2824 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2825 /* t3 = dc0a */
2826 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2827 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2828 /* t3 = dcba -- delay slot */
2829 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2831 /*
2832 * bswap64 -- 64-bit swap. a0 = abcdefgh
2833 */
2834 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2835 /* t3 = h0000000 */
2836 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2837 /* t1 = 0000000a */
2838 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2840 /* t2 = 000000g0 */
2841 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2842 /* t3 = h000000a */
2843 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2844 /* t1 = 00000abc */
2845 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2846 /* t2 = 0g000000 */
2847 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2848 /* t1 = 000000b0 */
2849 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2851 /* t3 = hg00000a */
2852 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2853 /* t2 = 0000abcd */
2854 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2855 /* t3 = hg0000ba */
2856 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2858 /* t1 = 000000c0 */
2859 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2860 /* t2 = 0000000d */
2861 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2862 /* t1 = 00000c00 */
2863 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2864 /* t2 = 0000d000 */
2865 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2867 /* t3 = hg000cba */
2868 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2869 /* t1 = 00abcdef */
2870 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2871 /* t3 = hg00dcba */
2872 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2874 /* t2 = 0000000f */
2875 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2876 /* t1 = 000000e0 */
2877 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2878 /* t2 = 00f00000 */
2879 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2880 /* t1 = 000e0000 */
2881 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2883 /* t3 = hgf0dcba */
2884 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2885 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2886 /* t3 = hgfedcba -- delay slot */
2887 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2888 }
2890 static void tcg_target_init(TCGContext *s)
2891 {
2892 tcg_target_detect_isa();
2893 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2894 if (TCG_TARGET_REG_BITS == 64) {
2895 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2896 }
2898 tcg_target_call_clobber_regs = 0;
2899 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2900 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2901 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2902 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2903 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2904 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2905 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2906 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2907 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2908 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2909 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2910 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2911 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2912 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2913 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2914 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2916 s->reserved_regs = 0;
2917 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2918 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2919 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2920 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2921 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2922 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2923 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2924 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2925 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2926 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2927 }
2929 typedef struct {
2930 DebugFrameHeader h;
2931 uint8_t fde_def_cfa[4];
2932 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2933 } DebugFrame;
2935 #define ELF_HOST_MACHINE EM_MIPS
2936 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2937 which is good because they're really quite complicated for MIPS. */
2939 static const DebugFrame debug_frame = {
2940 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2941 .h.cie.id = -1,
2942 .h.cie.version = 1,
2943 .h.cie.code_align = 1,
2944 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2945 .h.cie.return_column = TCG_REG_RA,
2947 /* Total FDE size does not include the "len" member. */
2948 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2950 .fde_def_cfa = {
2951 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2952 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2953 (FRAME_SIZE >> 7)
2954 },
2955 .fde_reg_ofs = {
2956 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2957 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2958 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2959 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2960 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2961 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2962 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2963 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2964 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2965 }
2966 };
2968 void tcg_register_jit(const void *buf, size_t buf_size)
2969 {
2970 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2971 }