2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * This source file covers the following FPGA images, for TrustZone cores:
17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
22 * Links to the TRM for the board itself and to the various Application
23 * Notes which document the FPGA images can be found here:
24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
27 * https://developer.arm.com/documentation/100112/latest/
28 * Application Note AN505:
29 * https://developer.arm.com/documentation/dai0505/latest/
30 * Application Note AN521:
31 * https://developer.arm.com/documentation/dai0521/latest/
32 * Application Note AN524:
33 * https://developer.arm.com/documentation/dai0524/latest/
34 * Application Note AN547:
35 * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
38 * (ARM ECM0601256) for the details of some of the device layout:
39 * https://developer.arm.com/documentation/ecm0601256/latest
40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
41 * most of the device layout:
42 * https://developer.arm.com/documentation/101104/latest/
43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
44 * https://developer.arm.com/documentation/101773/latest/
47 #include "qemu/osdep.h"
48 #include "qemu/units.h"
49 #include "qemu/cutils.h"
50 #include "qapi/error.h"
51 #include "qemu/error-report.h"
52 #include "hw/arm/boot.h"
53 #include "hw/arm/armv7m.h"
54 #include "hw/or-irq.h"
55 #include "hw/boards.h"
56 #include "exec/address-spaces.h"
57 #include "sysemu/sysemu.h"
58 #include "sysemu/reset.h"
59 #include "hw/misc/unimp.h"
60 #include "hw/char/cmsdk-apb-uart.h"
61 #include "hw/timer/cmsdk-apb-timer.h"
62 #include "hw/misc/mps2-scc.h"
63 #include "hw/misc/mps2-fpgaio.h"
64 #include "hw/misc/tz-mpc.h"
65 #include "hw/misc/tz-msc.h"
66 #include "hw/arm/armsse.h"
67 #include "hw/dma/pl080.h"
68 #include "hw/rtc/pl031.h"
69 #include "hw/ssi/pl022.h"
70 #include "hw/i2c/arm_sbcon_i2c.h"
71 #include "hw/net/lan9118.h"
73 #include "hw/core/split-irq.h"
74 #include "hw/qdev-clock.h"
75 #include "qom/object.h"
78 #define MPS2TZ_NUMIRQ_MAX 96
79 #define MPS2TZ_RAM_MAX 5
81 typedef enum MPS2TZFPGAType
{
89 * Define the layout of RAM in a board, including which parts are
91 * mrindex specifies the index into mms->ram[] to use for the backing RAM;
92 * -1 means "use the system RAM".
94 typedef struct RAMInfo
{
98 int mpc
; /* MPC number, -1 for "not behind an MPC" */
105 * IS_ALIAS: this RAM area is an alias to the upstream end of the
106 * MPC specified by its .mpc value
107 * IS_ROM: this RAM area is read-only
112 struct MPS2TZMachineClass
{
114 MPS2TZFPGAType fpga_type
;
116 uint32_t sysclk_frq
; /* Main SYSCLK frequency in Hz */
117 uint32_t apb_periph_frq
; /* APB peripheral frequency in Hz */
119 const uint32_t *oscclk
;
120 uint32_t fpgaio_num_leds
; /* Number of LEDs in FPGAIO LED0 register */
121 bool fpgaio_has_switches
; /* Does FPGAIO have SWITCH register? */
122 bool fpgaio_has_dbgctrl
; /* Does FPGAIO have DBGCTRL register? */
123 int numirq
; /* Number of external interrupts */
124 int uart_overflow_irq
; /* number of the combined UART overflow IRQ */
125 uint32_t init_svtor
; /* init-svtor setting for SSE */
126 uint32_t sram_addr_width
; /* SRAM_ADDR_WIDTH setting for SSE */
127 const RAMInfo
*raminfo
;
128 const char *armsse_type
;
129 uint32_t boot_ram_size
; /* size of ram at address 0; 0 == find in raminfo */
132 struct MPS2TZMachineState
{
136 MemoryRegion ram
[MPS2TZ_RAM_MAX
];
137 MemoryRegion eth_usb_container
;
144 ArmSbconI2CState i2c
[5];
145 UnimplementedDeviceState i2s_audio
;
146 UnimplementedDeviceState gpio
[4];
147 UnimplementedDeviceState gfx
;
148 UnimplementedDeviceState cldc
;
149 UnimplementedDeviceState usb
;
153 CMSDKAPBUART uart
[6];
154 SplitIRQ sec_resp_splitter
;
155 qemu_or_irq uart_irq_orgate
;
156 DeviceState
*lan9118
;
157 SplitIRQ cpu_irq_splitter
[MPS2TZ_NUMIRQ_MAX
];
165 #define TYPE_MPS2TZ_MACHINE "mps2tz"
166 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
167 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
168 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
169 #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547")
171 OBJECT_DECLARE_TYPE(MPS2TZMachineState
, MPS2TZMachineClass
, MPS2TZ_MACHINE
)
173 /* Slow 32Khz S32KCLK frequency in Hz */
174 #define S32KCLK_FRQ (32 * 1000)
177 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit
178 * emulation of that much guest RAM, so artificially make it smaller.
180 #if HOST_LONG_BITS == 32
181 #define MPS3_DDR_SIZE (1 * GiB)
183 #define MPS3_DDR_SIZE (2 * GiB)
186 static const uint32_t an505_oscclk
[] = {
192 static const uint32_t an524_oscclk
[] = {
201 static const RAMInfo an505_raminfo
[] = { {
220 .name
= "ssram-0-alias",
227 /* Use the largest bit of contiguous RAM as our "system memory" */
239 * Note that the addresses and MPC numbering here should match up
240 * with those used in remap_memory(), which can swap the BRAM and QSPI.
242 static const RAMInfo an524_raminfo
[] = { {
249 /* We don't model QSPI flash yet; for now expose it as simple ROM */
259 .size
= MPS3_DDR_SIZE
,
267 static const RAMInfo an547_raminfo
[] = { {
280 /* We don't model QSPI flash yet; for now expose it as simple ROM */
290 .size
= MPS3_DDR_SIZE
,
298 static const RAMInfo
*find_raminfo_for_mpc(MPS2TZMachineState
*mms
, int mpc
)
300 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
302 const RAMInfo
*found
= NULL
;
304 for (p
= mmc
->raminfo
; p
->name
; p
++) {
305 if (p
->mpc
== mpc
&& !(p
->flags
& IS_ALIAS
)) {
306 /* There should only be one entry in the array for this MPC */
311 /* if raminfo array doesn't have an entry for each MPC this is a bug */
316 static MemoryRegion
*mr_for_raminfo(MPS2TZMachineState
*mms
,
317 const RAMInfo
*raminfo
)
319 /* Return an initialized MemoryRegion for the RAMInfo. */
322 if (raminfo
->mrindex
< 0) {
323 /* Means this RAMInfo is for QEMU's "system memory" */
324 MachineState
*machine
= MACHINE(mms
);
325 assert(!(raminfo
->flags
& IS_ROM
));
329 assert(raminfo
->mrindex
< MPS2TZ_RAM_MAX
);
330 ram
= &mms
->ram
[raminfo
->mrindex
];
332 memory_region_init_ram(ram
, NULL
, raminfo
->name
,
333 raminfo
->size
, &error_fatal
);
334 if (raminfo
->flags
& IS_ROM
) {
335 memory_region_set_readonly(ram
, true);
340 /* Create an alias of an entire original MemoryRegion @orig
341 * located at @base in the memory map.
343 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
344 MemoryRegion
*orig
, hwaddr base
)
346 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
347 memory_region_size(orig
));
348 memory_region_add_subregion(get_system_memory(), base
, mr
);
351 static qemu_irq
get_sse_irq_in(MPS2TZMachineState
*mms
, int irqno
)
354 * Return a qemu_irq which will signal IRQ n to all CPUs in the
355 * SSE. The irqno should be as the CPU sees it, so the first
356 * external-to-the-SSE interrupt is 32.
358 MachineClass
*mc
= MACHINE_GET_CLASS(mms
);
359 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
361 assert(irqno
>= 32 && irqno
< (mmc
->numirq
+ 32));
364 * Convert from "CPU irq number" (as listed in the FPGA image
365 * documentation) to the SSE external-interrupt number.
369 if (mc
->max_cpus
> 1) {
370 return qdev_get_gpio_in(DEVICE(&mms
->cpu_irq_splitter
[irqno
]), 0);
372 return qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
), "EXP_IRQ", irqno
);
376 /* Union describing the device-specific extra data we pass to the devfn. */
377 typedef union PPCExtraData
{
380 /* Most of the devices in the AN505 FPGA image sit behind
381 * Peripheral Protection Controllers. These data structures
382 * define the layout of which devices sit behind which PPCs.
383 * The devfn for each port is a function which creates, configures
384 * and initializes the device, returning the MemoryRegion which
385 * needs to be plugged into the downstream end of the PPC port.
387 typedef MemoryRegion
*MakeDevFn(MPS2TZMachineState
*mms
, void *opaque
,
388 const char *name
, hwaddr size
,
390 const PPCExtraData
*extradata
);
392 typedef struct PPCPortInfo
{
398 int irqs
[3]; /* currently no device needs more IRQ lines than this */
399 PPCExtraData extradata
; /* to pass device-specific info to the devfn */
402 typedef struct PPCInfo
{
404 PPCPortInfo ports
[TZ_NUM_PORTS
];
407 static MemoryRegion
*make_unimp_dev(MPS2TZMachineState
*mms
,
409 const char *name
, hwaddr size
,
411 const PPCExtraData
*extradata
)
413 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
414 * and return a pointer to its MemoryRegion.
416 UnimplementedDeviceState
*uds
= opaque
;
418 object_initialize_child(OBJECT(mms
), name
, uds
, TYPE_UNIMPLEMENTED_DEVICE
);
419 qdev_prop_set_string(DEVICE(uds
), "name", name
);
420 qdev_prop_set_uint64(DEVICE(uds
), "size", size
);
421 sysbus_realize(SYS_BUS_DEVICE(uds
), &error_fatal
);
422 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds
), 0);
425 static MemoryRegion
*make_uart(MPS2TZMachineState
*mms
, void *opaque
,
426 const char *name
, hwaddr size
,
427 const int *irqs
, const PPCExtraData
*extradata
)
429 /* The irq[] array is tx, rx, combined, in that order */
430 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
431 CMSDKAPBUART
*uart
= opaque
;
432 int i
= uart
- &mms
->uart
[0];
434 DeviceState
*orgate_dev
= DEVICE(&mms
->uart_irq_orgate
);
436 object_initialize_child(OBJECT(mms
), name
, uart
, TYPE_CMSDK_APB_UART
);
437 qdev_prop_set_chr(DEVICE(uart
), "chardev", serial_hd(i
));
438 qdev_prop_set_uint32(DEVICE(uart
), "pclk-frq", mmc
->apb_periph_frq
);
439 sysbus_realize(SYS_BUS_DEVICE(uart
), &error_fatal
);
440 s
= SYS_BUS_DEVICE(uart
);
441 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
442 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
443 sysbus_connect_irq(s
, 2, qdev_get_gpio_in(orgate_dev
, i
* 2));
444 sysbus_connect_irq(s
, 3, qdev_get_gpio_in(orgate_dev
, i
* 2 + 1));
445 sysbus_connect_irq(s
, 4, get_sse_irq_in(mms
, irqs
[2]));
446 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart
), 0);
449 static MemoryRegion
*make_scc(MPS2TZMachineState
*mms
, void *opaque
,
450 const char *name
, hwaddr size
,
451 const int *irqs
, const PPCExtraData
*extradata
)
453 MPS2SCC
*scc
= opaque
;
455 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
458 object_initialize_child(OBJECT(mms
), "scc", scc
, TYPE_MPS2_SCC
);
459 sccdev
= DEVICE(scc
);
460 qdev_prop_set_uint32(sccdev
, "scc-cfg0", mms
->remap
? 1 : 0);
461 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
462 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
463 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
464 qdev_prop_set_uint32(sccdev
, "len-oscclk", mmc
->len_oscclk
);
465 for (i
= 0; i
< mmc
->len_oscclk
; i
++) {
466 g_autofree
char *propname
= g_strdup_printf("oscclk[%u]", i
);
467 qdev_prop_set_uint32(sccdev
, propname
, mmc
->oscclk
[i
]);
469 sysbus_realize(SYS_BUS_DEVICE(scc
), &error_fatal
);
470 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev
), 0);
473 static MemoryRegion
*make_fpgaio(MPS2TZMachineState
*mms
, void *opaque
,
474 const char *name
, hwaddr size
,
475 const int *irqs
, const PPCExtraData
*extradata
)
477 MPS2FPGAIO
*fpgaio
= opaque
;
478 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
480 object_initialize_child(OBJECT(mms
), "fpgaio", fpgaio
, TYPE_MPS2_FPGAIO
);
481 qdev_prop_set_uint32(DEVICE(fpgaio
), "num-leds", mmc
->fpgaio_num_leds
);
482 qdev_prop_set_bit(DEVICE(fpgaio
), "has-switches", mmc
->fpgaio_has_switches
);
483 qdev_prop_set_bit(DEVICE(fpgaio
), "has-dbgctrl", mmc
->fpgaio_has_dbgctrl
);
484 sysbus_realize(SYS_BUS_DEVICE(fpgaio
), &error_fatal
);
485 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio
), 0);
488 static MemoryRegion
*make_eth_dev(MPS2TZMachineState
*mms
, void *opaque
,
489 const char *name
, hwaddr size
,
491 const PPCExtraData
*extradata
)
494 NICInfo
*nd
= &nd_table
[0];
496 /* In hardware this is a LAN9220; the LAN9118 is software compatible
497 * except that it doesn't support the checksum-offload feature.
499 qemu_check_nic_model(nd
, "lan9118");
500 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
501 qdev_set_nic_properties(mms
->lan9118
, nd
);
503 s
= SYS_BUS_DEVICE(mms
->lan9118
);
504 sysbus_realize_and_unref(s
, &error_fatal
);
505 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
506 return sysbus_mmio_get_region(s
, 0);
509 static MemoryRegion
*make_eth_usb(MPS2TZMachineState
*mms
, void *opaque
,
510 const char *name
, hwaddr size
,
512 const PPCExtraData
*extradata
)
515 * The AN524 makes the ethernet and USB share a PPC port.
516 * irqs[] is the ethernet IRQ.
519 NICInfo
*nd
= &nd_table
[0];
521 memory_region_init(&mms
->eth_usb_container
, OBJECT(mms
),
522 "mps2-tz-eth-usb-container", 0x200000);
525 * In hardware this is a LAN9220; the LAN9118 is software compatible
526 * except that it doesn't support the checksum-offload feature.
528 qemu_check_nic_model(nd
, "lan9118");
529 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
530 qdev_set_nic_properties(mms
->lan9118
, nd
);
532 s
= SYS_BUS_DEVICE(mms
->lan9118
);
533 sysbus_realize_and_unref(s
, &error_fatal
);
534 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
536 memory_region_add_subregion(&mms
->eth_usb_container
,
537 0, sysbus_mmio_get_region(s
, 0));
539 /* The USB OTG controller is an ISP1763; we don't have a model of it. */
540 object_initialize_child(OBJECT(mms
), "usb-otg",
541 &mms
->usb
, TYPE_UNIMPLEMENTED_DEVICE
);
542 qdev_prop_set_string(DEVICE(&mms
->usb
), "name", "usb-otg");
543 qdev_prop_set_uint64(DEVICE(&mms
->usb
), "size", 0x100000);
544 s
= SYS_BUS_DEVICE(&mms
->usb
);
545 sysbus_realize(s
, &error_fatal
);
547 memory_region_add_subregion(&mms
->eth_usb_container
,
548 0x100000, sysbus_mmio_get_region(s
, 0));
550 return &mms
->eth_usb_container
;
553 static MemoryRegion
*make_mpc(MPS2TZMachineState
*mms
, void *opaque
,
554 const char *name
, hwaddr size
,
555 const int *irqs
, const PPCExtraData
*extradata
)
558 int i
= mpc
- &mms
->mpc
[0];
559 MemoryRegion
*upstream
;
560 const RAMInfo
*raminfo
= find_raminfo_for_mpc(mms
, i
);
561 MemoryRegion
*ram
= mr_for_raminfo(mms
, raminfo
);
563 object_initialize_child(OBJECT(mms
), name
, mpc
, TYPE_TZ_MPC
);
564 object_property_set_link(OBJECT(mpc
), "downstream", OBJECT(ram
),
566 sysbus_realize(SYS_BUS_DEVICE(mpc
), &error_fatal
);
567 /* Map the upstream end of the MPC into system memory */
568 upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 1);
569 memory_region_add_subregion(get_system_memory(), raminfo
->base
, upstream
);
570 /* and connect its interrupt to the IoTKit */
571 qdev_connect_gpio_out_named(DEVICE(mpc
), "irq", 0,
572 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
573 "mpcexp_status", i
));
575 /* Return the register interface MR for our caller to map behind the PPC */
576 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 0);
579 static hwaddr
boot_mem_base(MPS2TZMachineState
*mms
)
582 * Return the canonical address of the block which will be mapped
583 * at address 0x0 (i.e. where the vector table is).
584 * This is usually 0, but if the AN524 alternate memory map is
585 * enabled it will be the base address of the QSPI block.
587 return mms
->remap
? 0x28000000 : 0;
590 static void remap_memory(MPS2TZMachineState
*mms
, int map
)
593 * Remap the memory for the AN524. 'map' is the value of
594 * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1
595 * for the "option 1" mapping where QSPI is at address 0.
597 * Effectively we need to swap around the "upstream" ends of
600 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
603 if (mmc
->fpga_type
!= FPGA_AN524
) {
607 memory_region_transaction_begin();
608 for (i
= 0; i
< 2; i
++) {
609 TZMPC
*mpc
= &mms
->mpc
[i
];
610 MemoryRegion
*upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 1);
611 hwaddr addr
= (i
^ map
) ? 0x28000000 : 0;
613 memory_region_set_address(upstream
, addr
);
615 memory_region_transaction_commit();
618 static void remap_irq_fn(void *opaque
, int n
, int level
)
620 MPS2TZMachineState
*mms
= opaque
;
622 remap_memory(mms
, level
);
625 static MemoryRegion
*make_dma(MPS2TZMachineState
*mms
, void *opaque
,
626 const char *name
, hwaddr size
,
627 const int *irqs
, const PPCExtraData
*extradata
)
629 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */
630 PL080State
*dma
= opaque
;
631 int i
= dma
- &mms
->dma
[0];
633 char *mscname
= g_strdup_printf("%s-msc", name
);
634 TZMSC
*msc
= &mms
->msc
[i
];
635 DeviceState
*iotkitdev
= DEVICE(&mms
->iotkit
);
636 MemoryRegion
*msc_upstream
;
637 MemoryRegion
*msc_downstream
;
640 * Each DMA device is a PL081 whose transaction master interface
641 * is guarded by a Master Security Controller. The downstream end of
642 * the MSC connects to the IoTKit AHB Slave Expansion port, so the
643 * DMA devices can see all devices and memory that the CPU does.
645 object_initialize_child(OBJECT(mms
), mscname
, msc
, TYPE_TZ_MSC
);
646 msc_downstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms
->iotkit
), 0);
647 object_property_set_link(OBJECT(msc
), "downstream",
648 OBJECT(msc_downstream
), &error_fatal
);
649 object_property_set_link(OBJECT(msc
), "idau", OBJECT(mms
), &error_fatal
);
650 sysbus_realize(SYS_BUS_DEVICE(msc
), &error_fatal
);
652 qdev_connect_gpio_out_named(DEVICE(msc
), "irq", 0,
653 qdev_get_gpio_in_named(iotkitdev
,
654 "mscexp_status", i
));
655 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_clear", i
,
656 qdev_get_gpio_in_named(DEVICE(msc
),
658 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_ns", i
,
659 qdev_get_gpio_in_named(DEVICE(msc
),
661 qdev_connect_gpio_out(DEVICE(&mms
->sec_resp_splitter
),
662 ARRAY_SIZE(mms
->ppc
) + i
,
663 qdev_get_gpio_in_named(DEVICE(msc
),
665 msc_upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(msc
), 0);
667 object_initialize_child(OBJECT(mms
), name
, dma
, TYPE_PL081
);
668 object_property_set_link(OBJECT(dma
), "downstream", OBJECT(msc_upstream
),
670 sysbus_realize(SYS_BUS_DEVICE(dma
), &error_fatal
);
672 s
= SYS_BUS_DEVICE(dma
);
673 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
674 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
675 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
676 sysbus_connect_irq(s
, 2, get_sse_irq_in(mms
, irqs
[2]));
679 return sysbus_mmio_get_region(s
, 0);
682 static MemoryRegion
*make_spi(MPS2TZMachineState
*mms
, void *opaque
,
683 const char *name
, hwaddr size
,
684 const int *irqs
, const PPCExtraData
*extradata
)
687 * The AN505 has five PL022 SPI controllers.
688 * One of these should have the LCD controller behind it; the others
689 * are connected only to the FPGA's "general purpose SPI connector"
690 * or "shield" expansion connectors.
691 * Note that if we do implement devices behind SPI, the chip select
692 * lines are set via the "MISC" register in the MPS2 FPGAIO device.
694 PL022State
*spi
= opaque
;
697 object_initialize_child(OBJECT(mms
), name
, spi
, TYPE_PL022
);
698 sysbus_realize(SYS_BUS_DEVICE(spi
), &error_fatal
);
699 s
= SYS_BUS_DEVICE(spi
);
700 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
701 return sysbus_mmio_get_region(s
, 0);
704 static MemoryRegion
*make_i2c(MPS2TZMachineState
*mms
, void *opaque
,
705 const char *name
, hwaddr size
,
706 const int *irqs
, const PPCExtraData
*extradata
)
708 ArmSbconI2CState
*i2c
= opaque
;
711 object_initialize_child(OBJECT(mms
), name
, i2c
, TYPE_ARM_SBCON_I2C
);
712 s
= SYS_BUS_DEVICE(i2c
);
713 sysbus_realize(s
, &error_fatal
);
714 return sysbus_mmio_get_region(s
, 0);
717 static MemoryRegion
*make_rtc(MPS2TZMachineState
*mms
, void *opaque
,
718 const char *name
, hwaddr size
,
719 const int *irqs
, const PPCExtraData
*extradata
)
721 PL031State
*pl031
= opaque
;
724 object_initialize_child(OBJECT(mms
), name
, pl031
, TYPE_PL031
);
725 s
= SYS_BUS_DEVICE(pl031
);
726 sysbus_realize(s
, &error_fatal
);
728 * The board docs don't give an IRQ number for the PL031, so
729 * presumably it is not connected.
731 return sysbus_mmio_get_region(s
, 0);
734 static void create_non_mpc_ram(MPS2TZMachineState
*mms
)
737 * Handle the RAMs which are either not behind MPCs or which are
738 * aliases to another MPC.
741 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
743 for (p
= mmc
->raminfo
; p
->name
; p
++) {
744 if (p
->flags
& IS_ALIAS
) {
745 SysBusDevice
*mpc_sbd
= SYS_BUS_DEVICE(&mms
->mpc
[p
->mpc
]);
746 MemoryRegion
*upstream
= sysbus_mmio_get_region(mpc_sbd
, 1);
747 make_ram_alias(&mms
->ram
[p
->mrindex
], p
->name
, upstream
, p
->base
);
748 } else if (p
->mpc
== -1) {
749 /* RAM not behind an MPC */
750 MemoryRegion
*mr
= mr_for_raminfo(mms
, p
);
751 memory_region_add_subregion(get_system_memory(), p
->base
, mr
);
756 static uint32_t boot_ram_size(MPS2TZMachineState
*mms
)
758 /* Return the size of the RAM block at guest address zero */
760 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
763 * Use a per-board specification (for when the boot RAM is in
764 * the SSE and so doesn't have a RAMInfo list entry)
766 if (mmc
->boot_ram_size
) {
767 return mmc
->boot_ram_size
;
770 for (p
= mmc
->raminfo
; p
->name
; p
++) {
771 if (p
->base
== boot_mem_base(mms
)) {
775 g_assert_not_reached();
778 static void mps2tz_common_init(MachineState
*machine
)
780 MPS2TZMachineState
*mms
= MPS2TZ_MACHINE(machine
);
781 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
782 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
783 MemoryRegion
*system_memory
= get_system_memory();
784 DeviceState
*iotkitdev
;
785 DeviceState
*dev_splitter
;
790 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
791 error_report("This board can only be used with CPU %s",
792 mc
->default_cpu_type
);
796 if (machine
->ram_size
!= mc
->default_ram_size
) {
797 char *sz
= size_to_str(mc
->default_ram_size
);
798 error_report("Invalid RAM size, should be %s", sz
);
803 /* These clocks don't need migration because they are fixed-frequency */
804 mms
->sysclk
= clock_new(OBJECT(machine
), "SYSCLK");
805 clock_set_hz(mms
->sysclk
, mmc
->sysclk_frq
);
806 mms
->s32kclk
= clock_new(OBJECT(machine
), "S32KCLK");
807 clock_set_hz(mms
->s32kclk
, S32KCLK_FRQ
);
809 object_initialize_child(OBJECT(machine
), TYPE_IOTKIT
, &mms
->iotkit
,
811 iotkitdev
= DEVICE(&mms
->iotkit
);
812 object_property_set_link(OBJECT(&mms
->iotkit
), "memory",
813 OBJECT(system_memory
), &error_abort
);
814 qdev_prop_set_uint32(iotkitdev
, "EXP_NUMIRQ", mmc
->numirq
);
815 qdev_prop_set_uint32(iotkitdev
, "init-svtor", mmc
->init_svtor
);
816 qdev_prop_set_uint32(iotkitdev
, "SRAM_ADDR_WIDTH", mmc
->sram_addr_width
);
817 qdev_connect_clock_in(iotkitdev
, "MAINCLK", mms
->sysclk
);
818 qdev_connect_clock_in(iotkitdev
, "S32KCLK", mms
->s32kclk
);
819 sysbus_realize(SYS_BUS_DEVICE(&mms
->iotkit
), &error_fatal
);
822 * If this board has more than one CPU, then we need to create splitters
823 * to feed the IRQ inputs for each CPU in the SSE from each device in the
824 * board. If there is only one CPU, we can just wire the device IRQ
825 * directly to the SSE's IRQ input.
827 assert(mmc
->numirq
<= MPS2TZ_NUMIRQ_MAX
);
828 if (mc
->max_cpus
> 1) {
829 for (i
= 0; i
< mmc
->numirq
; i
++) {
830 char *name
= g_strdup_printf("mps2-irq-splitter%d", i
);
831 SplitIRQ
*splitter
= &mms
->cpu_irq_splitter
[i
];
833 object_initialize_child_with_props(OBJECT(machine
), name
,
834 splitter
, sizeof(*splitter
),
835 TYPE_SPLIT_IRQ
, &error_fatal
,
839 object_property_set_int(OBJECT(splitter
), "num-lines", 2,
841 qdev_realize(DEVICE(splitter
), NULL
, &error_fatal
);
842 qdev_connect_gpio_out(DEVICE(splitter
), 0,
843 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
845 qdev_connect_gpio_out(DEVICE(splitter
), 1,
846 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
851 /* The sec_resp_cfg output from the IoTKit must be split into multiple
852 * lines, one for each of the PPCs we create here, plus one per MSC.
854 object_initialize_child(OBJECT(machine
), "sec-resp-splitter",
855 &mms
->sec_resp_splitter
, TYPE_SPLIT_IRQ
);
856 object_property_set_int(OBJECT(&mms
->sec_resp_splitter
), "num-lines",
857 ARRAY_SIZE(mms
->ppc
) + ARRAY_SIZE(mms
->msc
),
859 qdev_realize(DEVICE(&mms
->sec_resp_splitter
), NULL
, &error_fatal
);
860 dev_splitter
= DEVICE(&mms
->sec_resp_splitter
);
861 qdev_connect_gpio_out_named(iotkitdev
, "sec_resp_cfg", 0,
862 qdev_get_gpio_in(dev_splitter
, 0));
865 * The IoTKit sets up much of the memory layout, including
866 * the aliases between secure and non-secure regions in the
867 * address space, and also most of the devices in the system.
868 * The FPGA itself contains various RAMs and some additional devices.
869 * The FPGA images have an odd combination of different RAMs,
870 * because in hardware they are different implementations and
871 * connected to different buses, giving varying performance/size
872 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
873 * call the largest lump our "system memory".
877 * The overflow IRQs for all UARTs are ORed together.
878 * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
879 * Create the OR gate for this: it has one input for the TX overflow
880 * and one for the RX overflow for each UART we might have.
881 * (If the board has fewer than the maximum possible number of UARTs
882 * those inputs are never wired up and are treated as always-zero.)
884 object_initialize_child(OBJECT(mms
), "uart-irq-orgate",
885 &mms
->uart_irq_orgate
, TYPE_OR_IRQ
);
886 object_property_set_int(OBJECT(&mms
->uart_irq_orgate
), "num-lines",
887 2 * ARRAY_SIZE(mms
->uart
),
889 qdev_realize(DEVICE(&mms
->uart_irq_orgate
), NULL
, &error_fatal
);
890 qdev_connect_gpio_out(DEVICE(&mms
->uart_irq_orgate
), 0,
891 get_sse_irq_in(mms
, mmc
->uart_overflow_irq
));
893 /* Most of the devices in the FPGA are behind Peripheral Protection
894 * Controllers. The required order for initializing things is:
895 * + initialize the PPC
896 * + initialize, configure and realize downstream devices
897 * + connect downstream device MemoryRegions to the PPC
899 * + map the PPC's MemoryRegions to the places in the address map
900 * where the downstream devices should appear
901 * + wire up the PPC's control lines to the IoTKit object
904 const PPCInfo an505_ppcs
[] = { {
905 .name
= "apb_ppcexp0",
907 { "ssram-0-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
908 { "ssram-1-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
909 { "ssram-2-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
912 .name
= "apb_ppcexp1",
914 { "spi0", make_spi
, &mms
->spi
[0], 0x40205000, 0x1000, { 51 } },
915 { "spi1", make_spi
, &mms
->spi
[1], 0x40206000, 0x1000, { 52 } },
916 { "spi2", make_spi
, &mms
->spi
[2], 0x40209000, 0x1000, { 53 } },
917 { "spi3", make_spi
, &mms
->spi
[3], 0x4020a000, 0x1000, { 54 } },
918 { "spi4", make_spi
, &mms
->spi
[4], 0x4020b000, 0x1000, { 55 } },
919 { "uart0", make_uart
, &mms
->uart
[0], 0x40200000, 0x1000, { 32, 33, 42 } },
920 { "uart1", make_uart
, &mms
->uart
[1], 0x40201000, 0x1000, { 34, 35, 43 } },
921 { "uart2", make_uart
, &mms
->uart
[2], 0x40202000, 0x1000, { 36, 37, 44 } },
922 { "uart3", make_uart
, &mms
->uart
[3], 0x40203000, 0x1000, { 38, 39, 45 } },
923 { "uart4", make_uart
, &mms
->uart
[4], 0x40204000, 0x1000, { 40, 41, 46 } },
924 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x40207000, 0x1000 },
925 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x40208000, 0x1000 },
926 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x4020c000, 0x1000 },
927 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x4020d000, 0x1000 },
930 .name
= "apb_ppcexp2",
932 { "scc", make_scc
, &mms
->scc
, 0x40300000, 0x1000 },
933 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
934 0x40301000, 0x1000 },
935 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x40302000, 0x1000 },
938 .name
= "ahb_ppcexp0",
940 { "gfx", make_unimp_dev
, &mms
->gfx
, 0x41000000, 0x140000 },
941 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x40100000, 0x1000 },
942 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x40101000, 0x1000 },
943 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x40102000, 0x1000 },
944 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x40103000, 0x1000 },
945 { "eth", make_eth_dev
, NULL
, 0x42000000, 0x100000, { 48 } },
948 .name
= "ahb_ppcexp1",
950 { "dma0", make_dma
, &mms
->dma
[0], 0x40110000, 0x1000, { 58, 56, 57 } },
951 { "dma1", make_dma
, &mms
->dma
[1], 0x40111000, 0x1000, { 61, 59, 60 } },
952 { "dma2", make_dma
, &mms
->dma
[2], 0x40112000, 0x1000, { 64, 62, 63 } },
953 { "dma3", make_dma
, &mms
->dma
[3], 0x40113000, 0x1000, { 67, 65, 66 } },
958 const PPCInfo an524_ppcs
[] = { {
959 .name
= "apb_ppcexp0",
961 { "bram-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
962 { "qspi-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
963 { "ddr-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
966 .name
= "apb_ppcexp1",
968 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x41200000, 0x1000 },
969 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x41201000, 0x1000 },
970 { "spi0", make_spi
, &mms
->spi
[0], 0x41202000, 0x1000, { 52 } },
971 { "spi1", make_spi
, &mms
->spi
[1], 0x41203000, 0x1000, { 53 } },
972 { "spi2", make_spi
, &mms
->spi
[2], 0x41204000, 0x1000, { 54 } },
973 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x41205000, 0x1000 },
974 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x41206000, 0x1000 },
975 { /* port 7 reserved */ },
976 { "i2c4", make_i2c
, &mms
->i2c
[4], 0x41208000, 0x1000 },
979 .name
= "apb_ppcexp2",
981 { "scc", make_scc
, &mms
->scc
, 0x41300000, 0x1000 },
982 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
983 0x41301000, 0x1000 },
984 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x41302000, 0x1000 },
985 { "uart0", make_uart
, &mms
->uart
[0], 0x41303000, 0x1000, { 32, 33, 42 } },
986 { "uart1", make_uart
, &mms
->uart
[1], 0x41304000, 0x1000, { 34, 35, 43 } },
987 { "uart2", make_uart
, &mms
->uart
[2], 0x41305000, 0x1000, { 36, 37, 44 } },
988 { "uart3", make_uart
, &mms
->uart
[3], 0x41306000, 0x1000, { 38, 39, 45 } },
989 { "uart4", make_uart
, &mms
->uart
[4], 0x41307000, 0x1000, { 40, 41, 46 } },
990 { "uart5", make_uart
, &mms
->uart
[5], 0x41308000, 0x1000, { 124, 125, 126 } },
992 { /* port 9 reserved */ },
993 { "clcd", make_unimp_dev
, &mms
->cldc
, 0x4130a000, 0x1000 },
994 { "rtc", make_rtc
, &mms
->rtc
, 0x4130b000, 0x1000 },
997 .name
= "ahb_ppcexp0",
999 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x41100000, 0x1000 },
1000 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x41101000, 0x1000 },
1001 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x41102000, 0x1000 },
1002 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x41103000, 0x1000 },
1003 { "eth-usb", make_eth_usb
, NULL
, 0x41400000, 0x200000, { 48 } },
1008 const PPCInfo an547_ppcs
[] = { {
1009 .name
= "apb_ppcexp0",
1011 { "ssram-mpc", make_mpc
, &mms
->mpc
[0], 0x57000000, 0x1000 },
1012 { "qspi-mpc", make_mpc
, &mms
->mpc
[1], 0x57001000, 0x1000 },
1013 { "ddr-mpc", make_mpc
, &mms
->mpc
[2], 0x57002000, 0x1000 },
1016 .name
= "apb_ppcexp1",
1018 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x49200000, 0x1000 },
1019 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x49201000, 0x1000 },
1020 { "spi0", make_spi
, &mms
->spi
[0], 0x49202000, 0x1000, { 53 } },
1021 { "spi1", make_spi
, &mms
->spi
[1], 0x49203000, 0x1000, { 54 } },
1022 { "spi2", make_spi
, &mms
->spi
[2], 0x49204000, 0x1000, { 55 } },
1023 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x49205000, 0x1000 },
1024 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x49206000, 0x1000 },
1025 { /* port 7 reserved */ },
1026 { "i2c4", make_i2c
, &mms
->i2c
[4], 0x49208000, 0x1000 },
1029 .name
= "apb_ppcexp2",
1031 { "scc", make_scc
, &mms
->scc
, 0x49300000, 0x1000 },
1032 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
, 0x49301000, 0x1000 },
1033 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x49302000, 0x1000 },
1034 { "uart0", make_uart
, &mms
->uart
[0], 0x49303000, 0x1000, { 33, 34, 43 } },
1035 { "uart1", make_uart
, &mms
->uart
[1], 0x49304000, 0x1000, { 35, 36, 44 } },
1036 { "uart2", make_uart
, &mms
->uart
[2], 0x49305000, 0x1000, { 37, 38, 45 } },
1037 { "uart3", make_uart
, &mms
->uart
[3], 0x49306000, 0x1000, { 39, 40, 46 } },
1038 { "uart4", make_uart
, &mms
->uart
[4], 0x49307000, 0x1000, { 41, 42, 47 } },
1039 { "uart5", make_uart
, &mms
->uart
[5], 0x49308000, 0x1000, { 125, 126, 127 } },
1041 { /* port 9 reserved */ },
1042 { "clcd", make_unimp_dev
, &mms
->cldc
, 0x4930a000, 0x1000 },
1043 { "rtc", make_rtc
, &mms
->rtc
, 0x4930b000, 0x1000 },
1046 .name
= "ahb_ppcexp0",
1048 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x41100000, 0x1000 },
1049 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x41101000, 0x1000 },
1050 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x41102000, 0x1000 },
1051 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x41103000, 0x1000 },
1052 { "eth-usb", make_eth_usb
, NULL
, 0x41400000, 0x200000, { 49 } },
1057 switch (mmc
->fpga_type
) {
1061 num_ppcs
= ARRAY_SIZE(an505_ppcs
);
1065 num_ppcs
= ARRAY_SIZE(an524_ppcs
);
1069 num_ppcs
= ARRAY_SIZE(an547_ppcs
);
1072 g_assert_not_reached();
1075 for (i
= 0; i
< num_ppcs
; i
++) {
1076 const PPCInfo
*ppcinfo
= &ppcs
[i
];
1077 TZPPC
*ppc
= &mms
->ppc
[i
];
1078 DeviceState
*ppcdev
;
1082 object_initialize_child(OBJECT(machine
), ppcinfo
->name
, ppc
,
1084 ppcdev
= DEVICE(ppc
);
1086 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
1087 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
1091 if (!pinfo
->devfn
) {
1095 mr
= pinfo
->devfn(mms
, pinfo
->opaque
, pinfo
->name
, pinfo
->size
,
1096 pinfo
->irqs
, &pinfo
->extradata
);
1097 portname
= g_strdup_printf("port[%d]", port
);
1098 object_property_set_link(OBJECT(ppc
), portname
, OBJECT(mr
),
1103 sysbus_realize(SYS_BUS_DEVICE(ppc
), &error_fatal
);
1105 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
1106 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
1108 if (!pinfo
->devfn
) {
1111 sysbus_mmio_map(SYS_BUS_DEVICE(ppc
), port
, pinfo
->addr
);
1113 gpioname
= g_strdup_printf("%s_nonsec", ppcinfo
->name
);
1114 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
1115 qdev_get_gpio_in_named(ppcdev
,
1119 gpioname
= g_strdup_printf("%s_ap", ppcinfo
->name
);
1120 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
1121 qdev_get_gpio_in_named(ppcdev
,
1126 gpioname
= g_strdup_printf("%s_irq_enable", ppcinfo
->name
);
1127 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
1128 qdev_get_gpio_in_named(ppcdev
,
1131 gpioname
= g_strdup_printf("%s_irq_clear", ppcinfo
->name
);
1132 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
1133 qdev_get_gpio_in_named(ppcdev
,
1136 gpioname
= g_strdup_printf("%s_irq_status", ppcinfo
->name
);
1137 qdev_connect_gpio_out_named(ppcdev
, "irq", 0,
1138 qdev_get_gpio_in_named(iotkitdev
,
1142 qdev_connect_gpio_out(dev_splitter
, i
,
1143 qdev_get_gpio_in_named(ppcdev
,
1144 "cfg_sec_resp", 0));
1147 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
1149 if (mmc
->fpga_type
== FPGA_AN547
) {
1150 create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000);
1151 create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000);
1154 create_non_mpc_ram(mms
);
1156 if (mmc
->fpga_type
== FPGA_AN524
) {
1158 * Connect the line from the SCC so that we can remap when the
1159 * guest updates that register.
1161 mms
->remap_irq
= qemu_allocate_irq(remap_irq_fn
, mms
, 0);
1162 qdev_connect_gpio_out_named(DEVICE(&mms
->scc
), "remap", 0,
1166 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
1167 boot_ram_size(mms
));
1170 static void mps2_tz_idau_check(IDAUInterface
*ii
, uint32_t address
,
1171 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
1174 * The MPS2 TZ FPGA images have IDAUs in them which are connected to
1175 * the Master Security Controllers. Thes have the same logic as
1176 * is used by the IoTKit for the IDAU connected to the CPU, except
1177 * that MSCs don't care about the NSC attribute.
1179 int region
= extract32(address
, 28, 4);
1181 *ns
= !(region
& 1);
1183 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1184 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1188 static char *mps2_get_remap(Object
*obj
, Error
**errp
)
1190 MPS2TZMachineState
*mms
= MPS2TZ_MACHINE(obj
);
1191 const char *val
= mms
->remap
? "QSPI" : "BRAM";
1192 return g_strdup(val
);
1195 static void mps2_set_remap(Object
*obj
, const char *value
, Error
**errp
)
1197 MPS2TZMachineState
*mms
= MPS2TZ_MACHINE(obj
);
1199 if (!strcmp(value
, "BRAM")) {
1201 } else if (!strcmp(value
, "QSPI")) {
1204 error_setg(errp
, "Invalid remap value");
1205 error_append_hint(errp
, "Valid values are BRAM and QSPI.\n");
1209 static void mps2_machine_reset(MachineState
*machine
)
1211 MPS2TZMachineState
*mms
= MPS2TZ_MACHINE(machine
);
1214 * Set the initial memory mapping before triggering the reset of
1215 * the rest of the system, so that the guest image loader and CPU
1216 * reset see the correct mapping.
1218 remap_memory(mms
, mms
->remap
);
1219 qemu_devices_reset();
1222 static void mps2tz_class_init(ObjectClass
*oc
, void *data
)
1224 MachineClass
*mc
= MACHINE_CLASS(oc
);
1225 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(oc
);
1227 mc
->init
= mps2tz_common_init
;
1228 mc
->reset
= mps2_machine_reset
;
1229 iic
->check
= mps2_tz_idau_check
;
1232 static void mps2tz_set_default_ram_info(MPS2TZMachineClass
*mmc
)
1235 * Set mc->default_ram_size and default_ram_id from the
1236 * information in mmc->raminfo.
1238 MachineClass
*mc
= MACHINE_CLASS(mmc
);
1241 for (p
= mmc
->raminfo
; p
->name
; p
++) {
1242 if (p
->mrindex
< 0) {
1243 /* Found the entry for "system memory" */
1244 mc
->default_ram_size
= p
->size
;
1245 mc
->default_ram_id
= p
->name
;
1249 g_assert_not_reached();
1252 static void mps2tz_an505_class_init(ObjectClass
*oc
, void *data
)
1254 MachineClass
*mc
= MACHINE_CLASS(oc
);
1255 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1257 mc
->desc
= "ARM MPS2 with AN505 FPGA image for Cortex-M33";
1258 mc
->default_cpus
= 1;
1259 mc
->min_cpus
= mc
->default_cpus
;
1260 mc
->max_cpus
= mc
->default_cpus
;
1261 mmc
->fpga_type
= FPGA_AN505
;
1262 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1263 mmc
->scc_id
= 0x41045050;
1264 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1265 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1266 mmc
->oscclk
= an505_oscclk
;
1267 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1268 mmc
->fpgaio_num_leds
= 2;
1269 mmc
->fpgaio_has_switches
= false;
1270 mmc
->fpgaio_has_dbgctrl
= false;
1272 mmc
->uart_overflow_irq
= 47;
1273 mmc
->init_svtor
= 0x10000000;
1274 mmc
->sram_addr_width
= 15;
1275 mmc
->raminfo
= an505_raminfo
;
1276 mmc
->armsse_type
= TYPE_IOTKIT
;
1277 mmc
->boot_ram_size
= 0;
1278 mps2tz_set_default_ram_info(mmc
);
1281 static void mps2tz_an521_class_init(ObjectClass
*oc
, void *data
)
1283 MachineClass
*mc
= MACHINE_CLASS(oc
);
1284 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1286 mc
->desc
= "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
1287 mc
->default_cpus
= 2;
1288 mc
->min_cpus
= mc
->default_cpus
;
1289 mc
->max_cpus
= mc
->default_cpus
;
1290 mmc
->fpga_type
= FPGA_AN521
;
1291 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1292 mmc
->scc_id
= 0x41045210;
1293 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1294 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1295 mmc
->oscclk
= an505_oscclk
; /* AN521 is the same as AN505 here */
1296 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1297 mmc
->fpgaio_num_leds
= 2;
1298 mmc
->fpgaio_has_switches
= false;
1299 mmc
->fpgaio_has_dbgctrl
= false;
1301 mmc
->uart_overflow_irq
= 47;
1302 mmc
->init_svtor
= 0x10000000;
1303 mmc
->sram_addr_width
= 15;
1304 mmc
->raminfo
= an505_raminfo
; /* AN521 is the same as AN505 here */
1305 mmc
->armsse_type
= TYPE_SSE200
;
1306 mmc
->boot_ram_size
= 0;
1307 mps2tz_set_default_ram_info(mmc
);
1310 static void mps3tz_an524_class_init(ObjectClass
*oc
, void *data
)
1312 MachineClass
*mc
= MACHINE_CLASS(oc
);
1313 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1315 mc
->desc
= "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
1316 mc
->default_cpus
= 2;
1317 mc
->min_cpus
= mc
->default_cpus
;
1318 mc
->max_cpus
= mc
->default_cpus
;
1319 mmc
->fpga_type
= FPGA_AN524
;
1320 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1321 mmc
->scc_id
= 0x41045240;
1322 mmc
->sysclk_frq
= 32 * 1000 * 1000; /* 32MHz */
1323 mmc
->apb_periph_frq
= mmc
->sysclk_frq
;
1324 mmc
->oscclk
= an524_oscclk
;
1325 mmc
->len_oscclk
= ARRAY_SIZE(an524_oscclk
);
1326 mmc
->fpgaio_num_leds
= 10;
1327 mmc
->fpgaio_has_switches
= true;
1328 mmc
->fpgaio_has_dbgctrl
= false;
1330 mmc
->uart_overflow_irq
= 47;
1331 mmc
->init_svtor
= 0x10000000;
1332 mmc
->sram_addr_width
= 15;
1333 mmc
->raminfo
= an524_raminfo
;
1334 mmc
->armsse_type
= TYPE_SSE200
;
1335 mmc
->boot_ram_size
= 0;
1336 mps2tz_set_default_ram_info(mmc
);
1338 object_class_property_add_str(oc
, "remap", mps2_get_remap
, mps2_set_remap
);
1339 object_class_property_set_description(oc
, "remap",
1340 "Set memory mapping. Valid values "
1341 "are BRAM (default) and QSPI.");
1344 static void mps3tz_an547_class_init(ObjectClass
*oc
, void *data
)
1346 MachineClass
*mc
= MACHINE_CLASS(oc
);
1347 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1349 mc
->desc
= "ARM MPS3 with AN547 FPGA image for Cortex-M55";
1350 mc
->default_cpus
= 1;
1351 mc
->min_cpus
= mc
->default_cpus
;
1352 mc
->max_cpus
= mc
->default_cpus
;
1353 mmc
->fpga_type
= FPGA_AN547
;
1354 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m55");
1355 mmc
->scc_id
= 0x41055470;
1356 mmc
->sysclk_frq
= 32 * 1000 * 1000; /* 32MHz */
1357 mmc
->apb_periph_frq
= 25 * 1000 * 1000; /* 25MHz */
1358 mmc
->oscclk
= an524_oscclk
; /* same as AN524 */
1359 mmc
->len_oscclk
= ARRAY_SIZE(an524_oscclk
);
1360 mmc
->fpgaio_num_leds
= 10;
1361 mmc
->fpgaio_has_switches
= true;
1362 mmc
->fpgaio_has_dbgctrl
= true;
1364 mmc
->uart_overflow_irq
= 48;
1365 mmc
->init_svtor
= 0x00000000;
1366 mmc
->sram_addr_width
= 21;
1367 mmc
->raminfo
= an547_raminfo
;
1368 mmc
->armsse_type
= TYPE_SSE300
;
1369 mmc
->boot_ram_size
= 512 * KiB
;
1370 mps2tz_set_default_ram_info(mmc
);
1373 static const TypeInfo mps2tz_info
= {
1374 .name
= TYPE_MPS2TZ_MACHINE
,
1375 .parent
= TYPE_MACHINE
,
1377 .instance_size
= sizeof(MPS2TZMachineState
),
1378 .class_size
= sizeof(MPS2TZMachineClass
),
1379 .class_init
= mps2tz_class_init
,
1380 .interfaces
= (InterfaceInfo
[]) {
1381 { TYPE_IDAU_INTERFACE
},
1386 static const TypeInfo mps2tz_an505_info
= {
1387 .name
= TYPE_MPS2TZ_AN505_MACHINE
,
1388 .parent
= TYPE_MPS2TZ_MACHINE
,
1389 .class_init
= mps2tz_an505_class_init
,
1392 static const TypeInfo mps2tz_an521_info
= {
1393 .name
= TYPE_MPS2TZ_AN521_MACHINE
,
1394 .parent
= TYPE_MPS2TZ_MACHINE
,
1395 .class_init
= mps2tz_an521_class_init
,
1398 static const TypeInfo mps3tz_an524_info
= {
1399 .name
= TYPE_MPS3TZ_AN524_MACHINE
,
1400 .parent
= TYPE_MPS2TZ_MACHINE
,
1401 .class_init
= mps3tz_an524_class_init
,
1404 static const TypeInfo mps3tz_an547_info
= {
1405 .name
= TYPE_MPS3TZ_AN547_MACHINE
,
1406 .parent
= TYPE_MPS2TZ_MACHINE
,
1407 .class_init
= mps3tz_an547_class_init
,
1410 static void mps2tz_machine_init(void)
1412 type_register_static(&mps2tz_info
);
1413 type_register_static(&mps2tz_an505_info
);
1414 type_register_static(&mps2tz_an521_info
);
1415 type_register_static(&mps3tz_an524_info
);
1416 type_register_static(&mps3tz_an547_info
);
1419 type_init(mps2tz_machine_init
);