target/loongarch/translate.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * LoongArch emulation for QEMU - main translation routines.
   4  *
   5  * Copyright (c) 2021 Loongson Technology Corporation Limited
   6  */
   7
   8 #include "qemu/osdep.h"
   9 #include "cpu.h"
  10 #include "tcg/tcg-op.h"
  11 #include "exec/translator.h"
  12 #include "exec/helper-proto.h"
  13 #include "exec/helper-gen.h"
  14
  15 #include "exec/translator.h"
  16 #include "exec/log.h"
  17 #include "qemu/qemu-print.h"
  18 #include "fpu/softfloat.h"
  19 #include "translate.h"
  20 #include "internals.h"
  21
  22 /* Global register indices */
  23 TCGv cpu_gpr[32], cpu_pc;
  24 static TCGv cpu_lladdr, cpu_llval;
  25 TCGv_i32 cpu_fcsr0;
  26 TCGv_i64 cpu_fpr[32];
  27
  28 #define DISAS_STOP       DISAS_TARGET_0
  29
  30 static inline int plus_1(DisasContext *ctx, int x)
  31 {
  32     return x + 1;
  33 }
  34
  35 static inline int shl_2(DisasContext *ctx, int x)
  36 {
  37     return x << 2;
  38 }
  39
  40 /*
  41  * LoongArch the upper 32 bits are undefined ("can be any value").
  42  * QEMU chooses to nanbox, because it is most likely to show guest bugs early.
  43  */
  44 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
  45 {
  46     tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
  47 }
  48
  49 void generate_exception(DisasContext *ctx, int excp)
  50 {
  51     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
  52     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
  53     ctx->base.is_jmp = DISAS_NORETURN;
  54 }
  55
  56 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
  57 {
  58     if (translator_use_goto_tb(&ctx->base, dest)) {
  59         tcg_gen_goto_tb(n);
  60         tcg_gen_movi_tl(cpu_pc, dest);
  61         tcg_gen_exit_tb(ctx->base.tb, n);
  62     } else {
  63         tcg_gen_movi_tl(cpu_pc, dest);
  64         tcg_gen_lookup_and_goto_ptr();
  65     }
  66 }
  67
  68 static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
  69                                             CPUState *cs)
  70 {
  71     int64_t bound;
  72     DisasContext *ctx = container_of(dcbase, DisasContext, base);
  73
  74     ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
  75     ctx->mem_idx = ctx->base.tb->flags;
  76
  77     /* Bound the number of insns to execute to those left on the page.  */
  78     bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
  79     ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
  80
  81     ctx->ntemp = 0;
  82     memset(ctx->temp, 0, sizeof(ctx->temp));
  83
  84     ctx->zero = tcg_constant_tl(0);
  85 }
  86
  87 static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
  88 {
  89 }
  90
  91 static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
  92 {
  93     DisasContext *ctx = container_of(dcbase, DisasContext, base);
  94
  95     tcg_gen_insn_start(ctx->base.pc_next);
  96 }
  97
  98 /*
  99  * Wrappers for getting reg values.
 100  *
 101  * The $zero register does not have cpu_gpr[0] allocated -- we supply the
 102  * constant zero as a source, and an uninitialized sink as destination.
 103  *
 104  * Further, we may provide an extension for word operations.
 105  */
 106 static TCGv temp_new(DisasContext *ctx)
 107 {
 108     assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
 109     return ctx->temp[ctx->ntemp++] = tcg_temp_new();
 110 }
 111
 112 static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
 113 {
 114     TCGv t;
 115
 116     if (reg_num == 0) {
 117         return ctx->zero;
 118     }
 119
 120     switch (src_ext) {
 121     case EXT_NONE:
 122         return cpu_gpr[reg_num];
 123     case EXT_SIGN:
 124         t = temp_new(ctx);
 125         tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
 126         return t;
 127     case EXT_ZERO:
 128         t = temp_new(ctx);
 129         tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
 130         return t;
 131     }
 132     g_assert_not_reached();
 133 }
 134
 135 static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext)
 136 {
 137     if (reg_num == 0 || dst_ext) {
 138         return temp_new(ctx);
 139     }
 140     return cpu_gpr[reg_num];
 141 }
 142
 143 static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
 144 {
 145     if (reg_num != 0) {
 146         switch (dst_ext) {
 147         case EXT_NONE:
 148             tcg_gen_mov_tl(cpu_gpr[reg_num], t);
 149             break;
 150         case EXT_SIGN:
 151             tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
 152             break;
 153         case EXT_ZERO:
 154             tcg_gen_ext32u_tl(cpu_gpr[reg_num], t);
 155             break;
 156         default:
 157             g_assert_not_reached();
 158         }
 159     }
 160 }
 161
 162 #include "decode-insns.c.inc"
 163 #include "insn_trans/trans_arith.c.inc"
 164 #include "insn_trans/trans_shift.c.inc"
 165 #include "insn_trans/trans_bit.c.inc"
 166 #include "insn_trans/trans_memory.c.inc"
 167 #include "insn_trans/trans_atomic.c.inc"
 168 #include "insn_trans/trans_extra.c.inc"
 169 #include "insn_trans/trans_farith.c.inc"
 170 #include "insn_trans/trans_fcmp.c.inc"
 171 #include "insn_trans/trans_fcnv.c.inc"
 172 #include "insn_trans/trans_fmov.c.inc"
 173 #include "insn_trans/trans_fmemory.c.inc"
 174
 175 static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 176 {
 177     CPULoongArchState *env = cs->env_ptr;
 178     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 179
 180     ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
 181
 182     if (!decode(ctx, ctx->opcode)) {
 183         qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
 184                       TARGET_FMT_lx ": 0x%x\n",
 185                       ctx->base.pc_next, ctx->opcode);
 186         generate_exception(ctx, EXCCODE_INE);
 187     }
 188
 189     for (int i = ctx->ntemp - 1; i >= 0; --i) {
 190         tcg_temp_free(ctx->temp[i]);
 191         ctx->temp[i] = NULL;
 192     }
 193     ctx->ntemp = 0;
 194
 195     ctx->base.pc_next += 4;
 196 }
 197
 198 static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
 199 {
 200     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 201
 202     switch (ctx->base.is_jmp) {
 203     case DISAS_STOP:
 204         tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 205         tcg_gen_lookup_and_goto_ptr();
 206         break;
 207     case DISAS_TOO_MANY:
 208         gen_goto_tb(ctx, 0, ctx->base.pc_next);
 209         break;
 210     case DISAS_NORETURN:
 211         break;
 212     default:
 213         g_assert_not_reached();
 214     }
 215 }
 216
 217 static void loongarch_tr_disas_log(const DisasContextBase *dcbase,
 218                                    CPUState *cpu, FILE *logfile)
 219 {
 220     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
 221     target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
 222 }
 223
 224 static const TranslatorOps loongarch_tr_ops = {
 225     .init_disas_context = loongarch_tr_init_disas_context,
 226     .tb_start           = loongarch_tr_tb_start,
 227     .insn_start         = loongarch_tr_insn_start,
 228     .translate_insn     = loongarch_tr_translate_insn,
 229     .tb_stop            = loongarch_tr_tb_stop,
 230     .disas_log          = loongarch_tr_disas_log,
 231 };
 232
 233 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
 234 {
 235     DisasContext ctx;
 236
 237     translator_loop(&loongarch_tr_ops, &ctx.base, cs, tb, max_insns);
 238 }
 239
 240 void loongarch_translate_init(void)
 241 {
 242     int i;
 243
 244     cpu_gpr[0] = NULL;
 245     for (i = 1; i < 32; i++) {
 246         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 247                                         offsetof(CPULoongArchState, gpr[i]),
 248                                         regnames[i]);
 249     }
 250
 251     for (i = 0; i < 32; i++) {
 252         int off = offsetof(CPULoongArchState, fpr[i]);
 253         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
 254     }
 255
 256     cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc), "pc");
 257     cpu_fcsr0 = tcg_global_mem_new_i32(cpu_env,
 258                     offsetof(CPULoongArchState, fcsr0), "fcsr0");
 259     cpu_lladdr = tcg_global_mem_new(cpu_env,
 260                     offsetof(CPULoongArchState, lladdr), "lladdr");
 261     cpu_llval = tcg_global_mem_new(cpu_env,
 262                     offsetof(CPULoongArchState, llval), "llval");
 263 }
 264
 265 void restore_state_to_opc(CPULoongArchState *env, TranslationBlock *tb,
 266                           target_ulong *data)
 267 {
 268     env->pc = data[0];
 269 }