hw/ppc/pnv_psi.c

   1 /*
   2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
   3  *
   4  * Copyright (c) 2015-2017, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "exec/address-spaces.h"
  22 #include "hw/irq.h"
  23 #include "target/ppc/cpu.h"
  24 #include "qemu/log.h"
  25 #include "qemu/module.h"
  26 #include "sysemu/reset.h"
  27 #include "qapi/error.h"
  28 #include "monitor/monitor.h"
  29
  30
  31 #include "hw/ppc/fdt.h"
  32 #include "hw/ppc/pnv.h"
  33 #include "hw/ppc/pnv_xscom.h"
  34 #include "hw/qdev-properties.h"
  35 #include "hw/ppc/pnv_psi.h"
  36
  37 #include <libfdt.h>
  38
  39 #define PSIHB_XSCOM_FIR_RW      0x00
  40 #define PSIHB_XSCOM_FIR_AND     0x01
  41 #define PSIHB_XSCOM_FIR_OR      0x02
  42 #define PSIHB_XSCOM_FIRMASK_RW  0x03
  43 #define PSIHB_XSCOM_FIRMASK_AND 0x04
  44 #define PSIHB_XSCOM_FIRMASK_OR  0x05
  45 #define PSIHB_XSCOM_FIRACT0     0x06
  46 #define PSIHB_XSCOM_FIRACT1     0x07
  47
  48 /* Host Bridge Base Address Register */
  49 #define PSIHB_XSCOM_BAR         0x0a
  50 #define   PSIHB_BAR_EN                  0x0000000000000001ull
  51
  52 /* FSP Base Address Register */
  53 #define PSIHB_XSCOM_FSPBAR      0x0b
  54
  55 /* PSI Host Bridge Control/Status Register */
  56 #define PSIHB_XSCOM_CR          0x0e
  57 #define   PSIHB_CR_FSP_CMD_ENABLE       0x8000000000000000ull
  58 #define   PSIHB_CR_FSP_MMIO_ENABLE      0x4000000000000000ull
  59 #define   PSIHB_CR_FSP_IRQ_ENABLE       0x1000000000000000ull
  60 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE   0x0800000000000000ull
  61 #define   PSIHB_CR_PSI_LINK_ENABLE      0x0400000000000000ull
  62 #define   PSIHB_CR_FSP_RESET            0x0200000000000000ull
  63 #define   PSIHB_CR_PSIHB_RESET          0x0100000000000000ull
  64 #define   PSIHB_CR_PSI_IRQ              0x0000800000000000ull
  65 #define   PSIHB_CR_FSP_IRQ              0x0000400000000000ull
  66 #define   PSIHB_CR_FSP_LINK_ACTIVE      0x0000200000000000ull
  67 #define   PSIHB_CR_IRQ_CMD_EXPECT       0x0000010000000000ull
  68           /* and more ... */
  69
  70 /* PSIHB Status / Error Mask Register */
  71 #define PSIHB_XSCOM_SEMR        0x0f
  72
  73 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
  74 #define PSIHB_XSCOM_XIVR_FSP    0x10
  75 #define   PSIHB_XIVR_SERVER_SH          40
  76 #define   PSIHB_XIVR_SERVER_MSK         (0xffffull << PSIHB_XIVR_SERVER_SH)
  77 #define   PSIHB_XIVR_PRIO_SH            32
  78 #define   PSIHB_XIVR_PRIO_MSK           (0xffull << PSIHB_XIVR_PRIO_SH)
  79 #define   PSIHB_XIVR_SRC_SH             29
  80 #define   PSIHB_XIVR_SRC_MSK            (0x7ull << PSIHB_XIVR_SRC_SH)
  81 #define   PSIHB_XIVR_PENDING            0x01000000ull
  82
  83 /* PSI Host Bridge Set Control/ Status Register */
  84 #define PSIHB_XSCOM_SCR         0x12
  85
  86 /* PSI Host Bridge Clear Control/ Status Register */
  87 #define PSIHB_XSCOM_CCR         0x13
  88
  89 /* DMA Upper Address Register */
  90 #define PSIHB_XSCOM_DMA_UPADD   0x14
  91
  92 /* Interrupt Status */
  93 #define PSIHB_XSCOM_IRQ_STAT    0x15
  94 #define   PSIHB_IRQ_STAT_OCC            0x0000001000000000ull
  95 #define   PSIHB_IRQ_STAT_FSI            0x0000000800000000ull
  96 #define   PSIHB_IRQ_STAT_LPCI2C         0x0000000400000000ull
  97 #define   PSIHB_IRQ_STAT_LOCERR         0x0000000200000000ull
  98 #define   PSIHB_IRQ_STAT_EXT            0x0000000100000000ull
  99
 100 /* remaining XIVR */
 101 #define PSIHB_XSCOM_XIVR_OCC    0x16
 102 #define PSIHB_XSCOM_XIVR_FSI    0x17
 103 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
 104 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
 105 #define PSIHB_XSCOM_XIVR_EXT    0x1a
 106
 107 /* Interrupt Requester Source Compare Register */
 108 #define PSIHB_XSCOM_IRSN        0x1b
 109 #define   PSIHB_IRSN_COMP_SH            45
 110 #define   PSIHB_IRSN_COMP_MSK           (0x7ffffull << PSIHB_IRSN_COMP_SH)
 111 #define   PSIHB_IRSN_IRQ_MUX            0x0000000800000000ull
 112 #define   PSIHB_IRSN_IRQ_RESET          0x0000000400000000ull
 113 #define   PSIHB_IRSN_DOWNSTREAM_EN      0x0000000200000000ull
 114 #define   PSIHB_IRSN_UPSTREAM_EN        0x0000000100000000ull
 115 #define   PSIHB_IRSN_COMPMASK_SH        13
 116 #define   PSIHB_IRSN_COMPMASK_MSK       (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
 117
 118 #define PSIHB_BAR_MASK                  0x0003fffffff00000ull
 119 #define PSIHB_FSPBAR_MASK               0x0003ffff00000000ull
 120
 121 #define PSIHB9_BAR_MASK                 0x00fffffffff00000ull
 122 #define PSIHB9_FSPBAR_MASK              0x00ffffff00000000ull
 123
 124 /* mmio address to xscom address */
 125 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
 126
 127 /* xscom address to mmio address */
 128 #define PSIHB_MMIO(reg) ((reg - PSIHB_XSCOM_BAR) << 3)
 129
 130 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
 131 {
 132     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
 133     MemoryRegion *sysmem = get_system_memory();
 134     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
 135
 136     psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
 137
 138     /* Update MR, always remove it first */
 139     if (old & PSIHB_BAR_EN) {
 140         memory_region_del_subregion(sysmem, &psi->regs_mr);
 141     }
 142
 143     /* Then add it back if needed */
 144     if (bar & PSIHB_BAR_EN) {
 145         uint64_t addr = bar & ppc->bar_mask;
 146         memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
 147     }
 148 }
 149
 150 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
 151 {
 152     /* TODO: Update FSP MR if/when we support FSP BAR */
 153 }
 154
 155 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
 156 {
 157     uint64_t old = psi->regs[PSIHB_XSCOM_CR];
 158
 159     psi->regs[PSIHB_XSCOM_CR] = cr;
 160
 161     /* Check some bit changes */
 162     if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
 163         pnv_psi_update_fsp_mr(psi);
 164     }
 165 }
 166
 167 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
 168 {
 169     ICSState *ics = &PNV8_PSI(psi)->ics;
 170
 171     /* In this model we ignore the up/down enable bits for now
 172      * as SW doesn't use them (other than setting them at boot).
 173      * We ignore IRQ_MUX, its meaning isn't clear and we don't use
 174      * it and finally we ignore reset (XXX fix that ?)
 175      */
 176     psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
 177                                          PSIHB_IRSN_IRQ_MUX |
 178                                          PSIHB_IRSN_IRQ_RESET |
 179                                          PSIHB_IRSN_DOWNSTREAM_EN |
 180                                          PSIHB_IRSN_UPSTREAM_EN);
 181
 182     /* We ignore the compare mask as well, our ICS emulation is too
 183      * simplistic to make any use if it, and we extract the offset
 184      * from the compare value
 185      */
 186     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
 187 }
 188
 189 /*
 190  * FSP and PSI interrupts are muxed under the same number.
 191  */
 192 static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = {
 193     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_XIVR_FSP,
 194     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_XIVR_OCC,
 195     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_XIVR_FSI,
 196     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_XIVR_LPCI2C,
 197     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
 198     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_XIVR_EXT,
 199 };
 200
 201 static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = {
 202     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_CR,
 203     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_IRQ_STAT,
 204     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_IRQ_STAT,
 205     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_IRQ_STAT,
 206     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
 207     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_IRQ_STAT,
 208 };
 209
 210 static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
 211     [PSIHB_IRQ_FSP]       = PSIHB_CR_FSP_IRQ,
 212     [PSIHB_IRQ_OCC]       = PSIHB_IRQ_STAT_OCC,
 213     [PSIHB_IRQ_FSI]       = PSIHB_IRQ_STAT_FSI,
 214     [PSIHB_IRQ_LPC_I2C]   = PSIHB_IRQ_STAT_LPCI2C,
 215     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
 216     [PSIHB_IRQ_EXTERNAL]  = PSIHB_IRQ_STAT_EXT,
 217 };
 218
 219 static void pnv_psi_power8_set_irq(void *opaque, int irq, int state)
 220 {
 221     PnvPsi *psi = opaque;
 222     uint32_t xivr_reg;
 223     uint32_t stat_reg;
 224     uint32_t src;
 225     bool masked;
 226
 227     xivr_reg = xivr_regs[irq];
 228     stat_reg = stat_regs[irq];
 229
 230     src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 231     if (state) {
 232         psi->regs[stat_reg] |= stat_bits[irq];
 233         /* TODO: optimization, check mask here. That means
 234          * re-evaluating when unmasking
 235          */
 236         qemu_irq_raise(psi->qirqs[src]);
 237     } else {
 238         psi->regs[stat_reg] &= ~stat_bits[irq];
 239
 240         /* FSP and PSI are muxed so don't lower if either is still set */
 241         if (stat_reg != PSIHB_XSCOM_CR ||
 242             !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
 243             qemu_irq_lower(psi->qirqs[src]);
 244         } else {
 245             state = true;
 246         }
 247     }
 248
 249     /* Note about the emulation of the pending bit: This isn't
 250      * entirely correct. The pending bit should be cleared when the
 251      * EOI has been received. However, we don't have callbacks on EOI
 252      * (especially not under KVM) so no way to emulate that properly,
 253      * so instead we just set that bit as the logical "output" of the
 254      * XIVR (ie pending & !masked)
 255      *
 256      * CLG: We could define a new ICS object with a custom eoi()
 257      * handler to clear the pending bit. But I am not sure this would
 258      * be useful for the software anyhow.
 259      */
 260     masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
 261     if (state && !masked) {
 262         psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
 263     } else {
 264         psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
 265     }
 266 }
 267
 268 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
 269 {
 270     ICSState *ics = &PNV8_PSI(psi)->ics;
 271     uint16_t server;
 272     uint8_t prio;
 273     uint8_t src;
 274
 275     psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
 276             (val & (PSIHB_XIVR_SERVER_MSK |
 277                     PSIHB_XIVR_PRIO_MSK |
 278                     PSIHB_XIVR_SRC_MSK));
 279     val = psi->regs[reg];
 280     server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
 281     prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
 282     src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
 283
 284     if (src >= PSI_NUM_INTERRUPTS) {
 285         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
 286         return;
 287     }
 288
 289     /* Remove pending bit if the IRQ is masked */
 290     if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
 291         psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
 292     }
 293
 294     /* The low order 2 bits are the link pointer (Type II interrupts).
 295      * Shift back to get a valid IRQ server.
 296      */
 297     server >>= 2;
 298
 299     /* Now because of source remapping, weird things can happen
 300      * if you change the source number dynamically, our simple ICS
 301      * doesn't deal with remapping. So we just poke a different
 302      * ICS entry based on what source number was written. This will
 303      * do for now but a more accurate implementation would instead
 304      * use a fixed server/prio and a remapper of the generated irq.
 305      */
 306     ics_write_xive(ics, src, server, prio, prio);
 307 }
 308
 309 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
 310 {
 311     uint64_t val = 0xffffffffffffffffull;
 312
 313     switch (offset) {
 314     case PSIHB_XSCOM_FIR_RW:
 315     case PSIHB_XSCOM_FIRACT0:
 316     case PSIHB_XSCOM_FIRACT1:
 317     case PSIHB_XSCOM_BAR:
 318     case PSIHB_XSCOM_FSPBAR:
 319     case PSIHB_XSCOM_CR:
 320     case PSIHB_XSCOM_XIVR_FSP:
 321     case PSIHB_XSCOM_XIVR_OCC:
 322     case PSIHB_XSCOM_XIVR_FSI:
 323     case PSIHB_XSCOM_XIVR_LPCI2C:
 324     case PSIHB_XSCOM_XIVR_LOCERR:
 325     case PSIHB_XSCOM_XIVR_EXT:
 326     case PSIHB_XSCOM_IRQ_STAT:
 327     case PSIHB_XSCOM_SEMR:
 328     case PSIHB_XSCOM_DMA_UPADD:
 329     case PSIHB_XSCOM_IRSN:
 330         val = psi->regs[offset];
 331         break;
 332     default:
 333         qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
 334     }
 335     return val;
 336 }
 337
 338 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
 339                               bool mmio)
 340 {
 341     switch (offset) {
 342     case PSIHB_XSCOM_FIR_RW:
 343     case PSIHB_XSCOM_FIRACT0:
 344     case PSIHB_XSCOM_FIRACT1:
 345     case PSIHB_XSCOM_SEMR:
 346     case PSIHB_XSCOM_DMA_UPADD:
 347         psi->regs[offset] = val;
 348         break;
 349     case PSIHB_XSCOM_FIR_OR:
 350         psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
 351         break;
 352     case PSIHB_XSCOM_FIR_AND:
 353         psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
 354         break;
 355     case PSIHB_XSCOM_BAR:
 356         /* Only XSCOM can write this one */
 357         if (!mmio) {
 358             pnv_psi_set_bar(psi, val);
 359         } else {
 360             qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
 361         }
 362         break;
 363     case PSIHB_XSCOM_FSPBAR:
 364         psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
 365         pnv_psi_update_fsp_mr(psi);
 366         break;
 367     case PSIHB_XSCOM_CR:
 368         pnv_psi_set_cr(psi, val);
 369         break;
 370     case PSIHB_XSCOM_SCR:
 371         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
 372         break;
 373     case PSIHB_XSCOM_CCR:
 374         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
 375         break;
 376     case PSIHB_XSCOM_XIVR_FSP:
 377     case PSIHB_XSCOM_XIVR_OCC:
 378     case PSIHB_XSCOM_XIVR_FSI:
 379     case PSIHB_XSCOM_XIVR_LPCI2C:
 380     case PSIHB_XSCOM_XIVR_LOCERR:
 381     case PSIHB_XSCOM_XIVR_EXT:
 382         pnv_psi_set_xivr(psi, offset, val);
 383         break;
 384     case PSIHB_XSCOM_IRQ_STAT:
 385         /* Read only */
 386         qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
 387         break;
 388     case PSIHB_XSCOM_IRSN:
 389         pnv_psi_set_irsn(psi, val);
 390         break;
 391     default:
 392         qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
 393     }
 394 }
 395
 396 /*
 397  * The values of the registers when accessed through the MMIO region
 398  * follow the relation : xscom = (mmio + 0x50) >> 3
 399  */
 400 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
 401 {
 402     return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
 403 }
 404
 405 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
 406                               uint64_t val, unsigned size)
 407 {
 408     pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
 409 }
 410
 411 static const MemoryRegionOps psi_mmio_ops = {
 412     .read = pnv_psi_mmio_read,
 413     .write = pnv_psi_mmio_write,
 414     .endianness = DEVICE_BIG_ENDIAN,
 415     .valid = {
 416         .min_access_size = 8,
 417         .max_access_size = 8,
 418     },
 419     .impl = {
 420         .min_access_size = 8,
 421         .max_access_size = 8,
 422     },
 423 };
 424
 425 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
 426 {
 427     return pnv_psi_reg_read(opaque, addr >> 3, false);
 428 }
 429
 430 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
 431                                 uint64_t val, unsigned size)
 432 {
 433     pnv_psi_reg_write(opaque, addr >> 3, val, false);
 434 }
 435
 436 static const MemoryRegionOps pnv_psi_xscom_ops = {
 437     .read = pnv_psi_xscom_read,
 438     .write = pnv_psi_xscom_write,
 439     .endianness = DEVICE_BIG_ENDIAN,
 440     .valid = {
 441         .min_access_size = 8,
 442         .max_access_size = 8,
 443     },
 444     .impl = {
 445         .min_access_size = 8,
 446         .max_access_size = 8,
 447     }
 448 };
 449
 450 static void pnv_psi_reset(DeviceState *dev)
 451 {
 452     PnvPsi *psi = PNV_PSI(dev);
 453
 454     memset(psi->regs, 0x0, sizeof(psi->regs));
 455
 456     psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
 457 }
 458
 459 static void pnv_psi_reset_handler(void *dev)
 460 {
 461     device_cold_reset(DEVICE(dev));
 462 }
 463
 464 static void pnv_psi_realize(DeviceState *dev, Error **errp)
 465 {
 466     PnvPsi *psi = PNV_PSI(dev);
 467
 468     /* Default BAR for MMIO region */
 469     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
 470
 471     qemu_register_reset(pnv_psi_reset_handler, dev);
 472 }
 473
 474 static void pnv_psi_power8_instance_init(Object *obj)
 475 {
 476     Pnv8Psi *psi8 = PNV8_PSI(obj);
 477
 478     object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS);
 479     object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics),
 480                               ICS_PROP_XICS);
 481 }
 482
 483 static const uint8_t irq_to_xivr[] = {
 484     PSIHB_XSCOM_XIVR_FSP,
 485     PSIHB_XSCOM_XIVR_OCC,
 486     PSIHB_XSCOM_XIVR_FSI,
 487     PSIHB_XSCOM_XIVR_LPCI2C,
 488     PSIHB_XSCOM_XIVR_LOCERR,
 489     PSIHB_XSCOM_XIVR_EXT,
 490 };
 491
 492 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
 493 {
 494     PnvPsi *psi = PNV_PSI(dev);
 495     ICSState *ics = &PNV8_PSI(psi)->ics;
 496     unsigned int i;
 497
 498     /* Create PSI interrupt control source */
 499     if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS,
 500                                  errp)) {
 501         return;
 502     }
 503     if (!qdev_realize(DEVICE(ics), NULL, errp)) {
 504         return;
 505     }
 506
 507     for (i = 0; i < ics->nr_irqs; i++) {
 508         ics_set_irq_type(ics, i, true);
 509     }
 510
 511     qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs);
 512
 513     psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
 514
 515     /* XSCOM region for PSI registers */
 516     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
 517                 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
 518
 519     /* Initialize MMIO region */
 520     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
 521                           "psihb", PNV_PSIHB_SIZE);
 522
 523     /* Default sources in XIVR */
 524     for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
 525         uint8_t xivr = irq_to_xivr[i];
 526         psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
 527             ((uint64_t) i << PSIHB_XIVR_SRC_SH);
 528     }
 529
 530     pnv_psi_realize(dev, errp);
 531 }
 532
 533 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 534 {
 535     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
 536     char *name;
 537     int offset;
 538     uint32_t reg[] = {
 539         cpu_to_be32(ppc->xscom_pcba),
 540         cpu_to_be32(ppc->xscom_size)
 541     };
 542
 543     name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
 544     offset = fdt_add_subnode(fdt, xscom_offset, name);
 545     _FDT(offset);
 546     g_free(name);
 547
 548     _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
 549     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
 550     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
 551     _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat,
 552                      ppc->compat_size));
 553     return 0;
 554 }
 555
 556 static Property pnv_psi_properties[] = {
 557     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
 558     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
 559     DEFINE_PROP_END_OF_LIST(),
 560 };
 561
 562 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
 563 {
 564     DeviceClass *dc = DEVICE_CLASS(klass);
 565     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 566     static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
 567
 568     dc->desc    = "PowerNV PSI Controller POWER8";
 569     dc->realize = pnv_psi_power8_realize;
 570
 571     ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
 572     ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
 573     ppc->bar_mask   = PSIHB_BAR_MASK;
 574     ppc->compat     = compat;
 575     ppc->compat_size = sizeof(compat);
 576 }
 577
 578 static const TypeInfo pnv_psi_power8_info = {
 579     .name          = TYPE_PNV8_PSI,
 580     .parent        = TYPE_PNV_PSI,
 581     .instance_size = sizeof(Pnv8Psi),
 582     .instance_init = pnv_psi_power8_instance_init,
 583     .class_init    = pnv_psi_power8_class_init,
 584 };
 585
 586
 587 /* Common registers */
 588
 589 #define PSIHB9_CR                       0x20
 590 #define PSIHB9_SEMR                     0x28
 591
 592 /* P9 registers */
 593
 594 #define PSIHB9_INTERRUPT_CONTROL        0x58
 595 #define   PSIHB9_IRQ_METHOD             PPC_BIT(0)
 596 #define   PSIHB9_IRQ_RESET              PPC_BIT(1)
 597 #define PSIHB9_ESB_CI_BASE              0x60
 598 #define   PSIHB9_ESB_CI_ADDR_MASK       PPC_BITMASK(8, 47)
 599 #define   PSIHB9_ESB_CI_VALID           PPC_BIT(63)
 600 #define PSIHB9_ESB_NOTIF_ADDR           0x68
 601 #define   PSIHB9_ESB_NOTIF_ADDR_MASK    PPC_BITMASK(8, 60)
 602 #define   PSIHB9_ESB_NOTIF_VALID        PPC_BIT(63)
 603 #define PSIHB9_IVT_OFFSET               0x70
 604 #define   PSIHB9_IVT_OFF_SHIFT          32
 605
 606 #define PSIHB9_IRQ_LEVEL                0x78 /* assertion */
 607 #define   PSIHB9_IRQ_LEVEL_PSI          PPC_BIT(0)
 608 #define   PSIHB9_IRQ_LEVEL_OCC          PPC_BIT(1)
 609 #define   PSIHB9_IRQ_LEVEL_FSI          PPC_BIT(2)
 610 #define   PSIHB9_IRQ_LEVEL_LPCHC        PPC_BIT(3)
 611 #define   PSIHB9_IRQ_LEVEL_LOCAL_ERR    PPC_BIT(4)
 612 #define   PSIHB9_IRQ_LEVEL_GLOBAL_ERR   PPC_BIT(5)
 613 #define   PSIHB9_IRQ_LEVEL_TPM          PPC_BIT(6)
 614 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ1    PPC_BIT(7)
 615 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ2    PPC_BIT(8)
 616 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ3    PPC_BIT(9)
 617 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ4    PPC_BIT(10)
 618 #define   PSIHB9_IRQ_LEVEL_SBE_I2C      PPC_BIT(11)
 619 #define   PSIHB9_IRQ_LEVEL_DIO          PPC_BIT(12)
 620 #define   PSIHB9_IRQ_LEVEL_PSU          PPC_BIT(13)
 621 #define   PSIHB9_IRQ_LEVEL_I2C_C        PPC_BIT(14)
 622 #define   PSIHB9_IRQ_LEVEL_I2C_D        PPC_BIT(15)
 623 #define   PSIHB9_IRQ_LEVEL_I2C_E        PPC_BIT(16)
 624 #define   PSIHB9_IRQ_LEVEL_SBE          PPC_BIT(19)
 625
 626 #define PSIHB9_IRQ_STAT                 0x80 /* P bit */
 627 #define   PSIHB9_IRQ_STAT_PSI           PPC_BIT(0)
 628 #define   PSIHB9_IRQ_STAT_OCC           PPC_BIT(1)
 629 #define   PSIHB9_IRQ_STAT_FSI           PPC_BIT(2)
 630 #define   PSIHB9_IRQ_STAT_LPCHC         PPC_BIT(3)
 631 #define   PSIHB9_IRQ_STAT_LOCAL_ERR     PPC_BIT(4)
 632 #define   PSIHB9_IRQ_STAT_GLOBAL_ERR    PPC_BIT(5)
 633 #define   PSIHB9_IRQ_STAT_TPM           PPC_BIT(6)
 634 #define   PSIHB9_IRQ_STAT_LPC_SIRQ1     PPC_BIT(7)
 635 #define   PSIHB9_IRQ_STAT_LPC_SIRQ2     PPC_BIT(8)
 636 #define   PSIHB9_IRQ_STAT_LPC_SIRQ3     PPC_BIT(9)
 637 #define   PSIHB9_IRQ_STAT_LPC_SIRQ4     PPC_BIT(10)
 638 #define   PSIHB9_IRQ_STAT_SBE_I2C       PPC_BIT(11)
 639 #define   PSIHB9_IRQ_STAT_DIO           PPC_BIT(12)
 640 #define   PSIHB9_IRQ_STAT_PSU           PPC_BIT(13)
 641
 642 /* P10 register extensions */
 643
 644 #define PSIHB10_CR                       PSIHB9_CR
 645 #define    PSIHB10_CR_STORE_EOI          PPC_BIT(12)
 646
 647 #define PSIHB10_ESB_CI_BASE              PSIHB9_ESB_CI_BASE
 648 #define   PSIHB10_ESB_CI_64K             PPC_BIT(1)
 649
 650 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno, bool pq_checked)
 651 {
 652     PnvPsi *psi = PNV_PSI(xf);
 653     uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
 654     bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
 655     uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
 656
 657     uint32_t offset =
 658         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 659     uint64_t data = offset | srcno;
 660     MemTxResult result;
 661
 662     if (pq_checked) {
 663         data |= XIVE_TRIGGER_PQ;
 664     }
 665
 666     if (!valid) {
 667         return;
 668     }
 669
 670     address_space_stq_be(&address_space_memory, notify_addr, data,
 671                          MEMTXATTRS_UNSPECIFIED, &result);
 672     if (result != MEMTX_OK) {
 673         qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
 674                       HWADDR_PRIx "\n", __func__, notif_port);
 675         return;
 676     }
 677 }
 678
 679 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
 680 {
 681     PnvPsi *psi = PNV_PSI(opaque);
 682     uint32_t reg = PSIHB_REG(addr);
 683     uint64_t val = -1;
 684
 685     switch (addr) {
 686     case PSIHB9_CR:
 687     case PSIHB9_SEMR:
 688         /* FSP stuff */
 689     case PSIHB9_INTERRUPT_CONTROL:
 690     case PSIHB9_ESB_CI_BASE:
 691     case PSIHB9_ESB_NOTIF_ADDR:
 692     case PSIHB9_IVT_OFFSET:
 693         val = psi->regs[reg];
 694         break;
 695     default:
 696         qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
 697     }
 698
 699     return val;
 700 }
 701
 702 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
 703                                   uint64_t val, unsigned size)
 704 {
 705     PnvPsi *psi = PNV_PSI(opaque);
 706     Pnv9Psi *psi9 = PNV9_PSI(psi);
 707     uint32_t reg = PSIHB_REG(addr);
 708     MemoryRegion *sysmem = get_system_memory();
 709
 710     switch (addr) {
 711     case PSIHB9_CR:
 712         if (val & PSIHB10_CR_STORE_EOI) {
 713             psi9->source.esb_flags |= XIVE_SRC_STORE_EOI;
 714         } else {
 715             psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI;
 716         }
 717         break;
 718
 719     case PSIHB9_SEMR:
 720         /* FSP stuff */
 721         break;
 722     case PSIHB9_INTERRUPT_CONTROL:
 723         if (val & PSIHB9_IRQ_RESET) {
 724             device_cold_reset(DEVICE(&psi9->source));
 725         }
 726         psi->regs[reg] = val;
 727         break;
 728
 729     case PSIHB9_ESB_CI_BASE:
 730         if (val & PSIHB10_ESB_CI_64K) {
 731             psi9->source.esb_shift = XIVE_ESB_64K;
 732         } else {
 733             psi9->source.esb_shift = XIVE_ESB_4K;
 734         }
 735         if (!(val & PSIHB9_ESB_CI_VALID)) {
 736             if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
 737                 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
 738             }
 739         } else {
 740             if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
 741                 hwaddr esb_addr =
 742                     val & ~(PSIHB9_ESB_CI_VALID | PSIHB10_ESB_CI_64K);
 743                 memory_region_add_subregion(sysmem, esb_addr,
 744                                             &psi9->source.esb_mmio);
 745             }
 746         }
 747         psi->regs[reg] = val;
 748         break;
 749
 750     case PSIHB9_ESB_NOTIF_ADDR:
 751         psi->regs[reg] = val;
 752         break;
 753     case PSIHB9_IVT_OFFSET:
 754         psi->regs[reg] = val;
 755         break;
 756     default:
 757         qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
 758     }
 759 }
 760
 761 static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
 762     .read = pnv_psi_p9_mmio_read,
 763     .write = pnv_psi_p9_mmio_write,
 764     .endianness = DEVICE_BIG_ENDIAN,
 765     .valid = {
 766         .min_access_size = 8,
 767         .max_access_size = 8,
 768     },
 769     .impl = {
 770         .min_access_size = 8,
 771         .max_access_size = 8,
 772     },
 773 };
 774
 775 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
 776 {
 777     uint32_t reg = addr >> 3;
 778     uint64_t val = -1;
 779
 780     if (reg < PSIHB_XSCOM_BAR) {
 781         /* FIR, not modeled */
 782         qemu_log_mask(LOG_UNIMP, "PSI: xscom read at 0x%08x\n", reg);
 783     } else {
 784         val = pnv_psi_p9_mmio_read(opaque, PSIHB_MMIO(reg), size);
 785     }
 786     return val;
 787 }
 788
 789 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
 790                                 uint64_t val, unsigned size)
 791 {
 792     PnvPsi *psi = PNV_PSI(opaque);
 793     uint32_t reg = addr >> 3;
 794
 795     if (reg < PSIHB_XSCOM_BAR) {
 796         /* FIR, not modeled */
 797         qemu_log_mask(LOG_UNIMP, "PSI: xscom write at 0x%08x\n", reg);
 798     } else if (reg == PSIHB_XSCOM_BAR) {
 799         pnv_psi_set_bar(psi, val);
 800     } else {
 801         pnv_psi_p9_mmio_write(opaque, PSIHB_MMIO(reg), val, size);
 802     }
 803 }
 804
 805 static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
 806     .read = pnv_psi_p9_xscom_read,
 807     .write = pnv_psi_p9_xscom_write,
 808     .endianness = DEVICE_BIG_ENDIAN,
 809     .valid = {
 810         .min_access_size = 8,
 811         .max_access_size = 8,
 812     },
 813     .impl = {
 814         .min_access_size = 8,
 815         .max_access_size = 8,
 816     }
 817 };
 818
 819 static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
 820 {
 821     PnvPsi *psi = opaque;
 822     uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
 823
 824     if (irq_method & PSIHB9_IRQ_METHOD) {
 825         qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
 826         return;
 827     }
 828
 829     /* Update LSI levels */
 830     if (state) {
 831         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
 832     } else {
 833         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
 834     }
 835
 836     qemu_set_irq(psi->qirqs[irq], state);
 837 }
 838
 839 static void pnv_psi_power9_reset(DeviceState *dev)
 840 {
 841     Pnv9Psi *psi = PNV9_PSI(dev);
 842
 843     pnv_psi_reset(dev);
 844
 845     if (memory_region_is_mapped(&psi->source.esb_mmio)) {
 846         memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
 847     }
 848 }
 849
 850 static void pnv_psi_power9_instance_init(Object *obj)
 851 {
 852     Pnv9Psi *psi = PNV9_PSI(obj);
 853
 854     object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE);
 855     object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift");
 856 }
 857
 858 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
 859 {
 860     PnvPsi *psi = PNV_PSI(dev);
 861     XiveSource *xsrc = &PNV9_PSI(psi)->source;
 862     int i;
 863
 864     object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS,
 865                             &error_fatal);
 866     object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort);
 867     object_property_set_int(OBJECT(xsrc), "reset-pq", XIVE_ESB_RESET,
 868                             &error_abort);
 869     if (!qdev_realize(DEVICE(xsrc), NULL, errp)) {
 870         return;
 871     }
 872
 873     for (i = 0; i < xsrc->nr_irqs; i++) {
 874         xive_source_irq_set_lsi(xsrc, i);
 875     }
 876
 877     psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
 878
 879     qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs);
 880
 881     /* XSCOM region for PSI registers */
 882     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
 883                 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
 884
 885     /* MMIO region for PSI registers */
 886     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
 887                           "psihb", PNV9_PSIHB_SIZE);
 888
 889     pnv_psi_realize(dev, errp);
 890 }
 891
 892 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
 893 {
 894     DeviceClass *dc = DEVICE_CLASS(klass);
 895     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 896     XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
 897     static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x";
 898
 899     dc->desc    = "PowerNV PSI Controller POWER9";
 900     dc->realize = pnv_psi_power9_realize;
 901     dc->reset   = pnv_psi_power9_reset;
 902
 903     ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
 904     ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
 905     ppc->bar_mask   = PSIHB9_BAR_MASK;
 906     ppc->compat     = compat;
 907     ppc->compat_size = sizeof(compat);
 908
 909     xfc->notify      = pnv_psi_notify;
 910 }
 911
 912 static const TypeInfo pnv_psi_power9_info = {
 913     .name          = TYPE_PNV9_PSI,
 914     .parent        = TYPE_PNV_PSI,
 915     .instance_size = sizeof(Pnv9Psi),
 916     .instance_init = pnv_psi_power9_instance_init,
 917     .class_init    = pnv_psi_power9_class_init,
 918     .interfaces = (InterfaceInfo[]) {
 919             { TYPE_XIVE_NOTIFIER },
 920             { },
 921     },
 922 };
 923
 924 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
 925 {
 926     DeviceClass *dc = DEVICE_CLASS(klass);
 927     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
 928     static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x";
 929
 930     dc->desc    = "PowerNV PSI Controller POWER10";
 931
 932     ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
 933     ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
 934     ppc->compat     = compat;
 935     ppc->compat_size = sizeof(compat);
 936 }
 937
 938 static const TypeInfo pnv_psi_power10_info = {
 939     .name          = TYPE_PNV10_PSI,
 940     .parent        = TYPE_PNV9_PSI,
 941     .class_init    = pnv_psi_power10_class_init,
 942 };
 943
 944 static void pnv_psi_class_init(ObjectClass *klass, void *data)
 945 {
 946     DeviceClass *dc = DEVICE_CLASS(klass);
 947     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 948
 949     xdc->dt_xscom = pnv_psi_dt_xscom;
 950
 951     dc->desc = "PowerNV PSI Controller";
 952     device_class_set_props(dc, pnv_psi_properties);
 953     dc->reset = pnv_psi_reset;
 954     dc->user_creatable = false;
 955 }
 956
 957 static const TypeInfo pnv_psi_info = {
 958     .name          = TYPE_PNV_PSI,
 959     .parent        = TYPE_DEVICE,
 960     .instance_size = sizeof(PnvPsi),
 961     .class_init    = pnv_psi_class_init,
 962     .class_size    = sizeof(PnvPsiClass),
 963     .abstract      = true,
 964     .interfaces    = (InterfaceInfo[]) {
 965         { TYPE_PNV_XSCOM_INTERFACE },
 966         { }
 967     }
 968 };
 969
 970 static void pnv_psi_register_types(void)
 971 {
 972     type_register_static(&pnv_psi_info);
 973     type_register_static(&pnv_psi_power8_info);
 974     type_register_static(&pnv_psi_power9_info);
 975     type_register_static(&pnv_psi_power10_info);
 976 }
 977
 978 type_init(pnv_psi_register_types);
 979
 980 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
 981 {
 982     PnvPsi *psi = PNV_PSI(psi9);
 983
 984     uint32_t offset =
 985         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
 986
 987     monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
 988                   offset, offset + psi9->source.nr_irqs - 1);
 989     xive_source_pic_print_info(&psi9->source, offset, mon);
 990 }