2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci-host/pnv_phb.h"
47 #include "hw/pci-host/pnv_phb3.h"
48 #include "hw/pci-host/pnv_phb4.h"
50 #include "hw/ppc/xics.h"
51 #include "hw/qdev-properties.h"
52 #include "hw/ppc/pnv_chip.h"
53 #include "hw/ppc/pnv_xscom.h"
54 #include "hw/ppc/pnv_pnor.h"
56 #include "hw/isa/isa.h"
57 #include "hw/char/serial.h"
58 #include "hw/rtc/mc146818rtc.h"
62 #define FDT_MAX_SIZE (1 * MiB)
64 #define FW_FILE_NAME "skiboot.lid"
65 #define FW_LOAD_ADDR 0x0
66 #define FW_MAX_SIZE (16 * MiB)
68 #define KERNEL_LOAD_ADDR 0x20000000
69 #define KERNEL_MAX_SIZE (128 * MiB)
70 #define INITRD_LOAD_ADDR 0x28000000
71 #define INITRD_MAX_SIZE (128 * MiB)
73 static const char *pnv_chip_core_typename(const PnvChip
*o
)
75 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
76 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
77 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
78 const char *core_type
= object_class_get_name(object_class_by_name(s
));
84 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
85 * 4 * 4 sockets * 12 cores * 8 threads = 1536
91 * Memory nodes are created by hostboot, one for each range of memory
92 * that has a different "affinity". In practice, it means one range
95 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
98 uint64_t mem_reg_property
[2];
101 mem_reg_property
[0] = cpu_to_be64(start
);
102 mem_reg_property
[1] = cpu_to_be64(size
);
104 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
105 off
= fdt_add_subnode(fdt
, 0, mem_name
);
108 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
109 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
110 sizeof(mem_reg_property
))));
111 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
114 static int get_cpus_node(void *fdt
)
116 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
118 if (cpus_offset
< 0) {
119 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
121 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
122 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
130 * The PowerNV cores (and threads) need to use real HW ids and not an
131 * incremental index like it has been done on other platforms. This HW
132 * id is stored in the CPU PIR, it is used to create cpu nodes in the
133 * device tree, used in XSCOM to address cores and in interrupt
136 static int pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
138 PowerPCCPU
*cpu
= pc
->threads
[0];
139 CPUState
*cs
= CPU(cpu
);
140 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
141 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
142 CPUPPCState
*env
= &cpu
->env
;
143 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
144 PnvChipClass
*pnv_cc
= PNV_CHIP_GET_CLASS(chip
);
145 g_autofree
uint32_t *servers_prop
= g_new(uint32_t, smt_threads
);
148 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
149 0xffffffff, 0xffffffff};
150 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
151 uint32_t cpufreq
= 1000000000;
152 uint32_t page_sizes_prop
[64];
153 size_t page_sizes_prop_size
;
156 int cpus_offset
= get_cpus_node(fdt
);
158 pir
= pnv_cc
->chip_pir(chip
, pc
->hwid
, 0);
160 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pir
);
161 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
165 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
167 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pir
)));
168 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pir
)));
169 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
171 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
172 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
173 env
->dcache_line_size
)));
174 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
175 env
->dcache_line_size
)));
176 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
177 env
->icache_line_size
)));
178 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
179 env
->icache_line_size
)));
181 if (pcc
->l1_dcache_size
) {
182 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
183 pcc
->l1_dcache_size
)));
185 warn_report("Unknown L1 dcache size for cpu");
187 if (pcc
->l1_icache_size
) {
188 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
189 pcc
->l1_icache_size
)));
191 warn_report("Unknown L1 icache size for cpu");
194 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
195 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
196 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
197 cpu
->hash64_opts
->slb_size
)));
198 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
199 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
201 if (ppc_has_spr(cpu
, SPR_PURR
)) {
202 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
205 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
206 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
207 segs
, sizeof(segs
))));
211 * Advertise VMX/VSX (vector extensions) if available
212 * 0 / no property == no vector extensions
213 * 1 == VMX / Altivec available
216 if (env
->insns_flags
& PPC_ALTIVEC
) {
217 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
219 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
223 * Advertise DFP (Decimal Floating Point) if available
224 * 0 / no property == no DFP
227 if (env
->insns_flags2
& PPC2_DFP
) {
228 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
231 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
232 sizeof(page_sizes_prop
));
233 if (page_sizes_prop_size
) {
234 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
235 page_sizes_prop
, page_sizes_prop_size
)));
238 /* Build interrupt servers properties */
239 for (i
= 0; i
< smt_threads
; i
++) {
240 servers_prop
[i
] = cpu_to_be32(pnv_cc
->chip_pir(chip
, pc
->hwid
, i
));
242 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
243 servers_prop
, sizeof(*servers_prop
) * smt_threads
)));
248 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t hwid
,
251 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
252 uint32_t pir
= pcc
->chip_pir(chip
, hwid
, 0);
253 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
255 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
256 uint32_t irange
[2], i
, rsize
;
260 irange
[0] = cpu_to_be32(pir
);
261 irange
[1] = cpu_to_be32(nr_threads
);
263 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
264 reg
= g_malloc(rsize
);
265 for (i
= 0; i
< nr_threads
; i
++) {
266 /* We know P8 PIR is linear with thread id */
267 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
268 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
271 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
272 offset
= fdt_add_subnode(fdt
, 0, name
);
276 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
277 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
278 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
279 "PowerPC-External-Interrupt-Presentation")));
280 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
281 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
282 irange
, sizeof(irange
))));
283 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
284 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
289 * Adds a PnvPHB to the chip on P8.
290 * Implemented here, like for defaults PHBs
292 PnvChip
*pnv_chip_add_phb(PnvChip
*chip
, PnvPHB
*phb
)
294 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
298 chip8
->phbs
[chip8
->num_phbs
] = phb
;
304 * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
305 * HTM is always enabled because TCG does implement HTM, it's just a
306 * degenerate implementation.
308 static const uint8_t pa_features_207
[] = { 24, 0,
309 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
310 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
311 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
312 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
314 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
316 static const char compat
[] = "ibm,power8-xscom\0ibm,xscom";
319 pnv_dt_xscom(chip
, fdt
, 0,
320 cpu_to_be64(PNV_XSCOM_BASE(chip
)),
321 cpu_to_be64(PNV_XSCOM_SIZE
),
322 compat
, sizeof(compat
));
324 for (i
= 0; i
< chip
->nr_cores
; i
++) {
325 PnvCore
*pnv_core
= chip
->cores
[i
];
328 offset
= pnv_dt_core(chip
, pnv_core
, fdt
);
330 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
331 pa_features_207
, sizeof(pa_features_207
))));
333 /* Interrupt Control Presenters (ICP). One per core. */
334 pnv_dt_icp(chip
, fdt
, pnv_core
->hwid
, CPU_CORE(pnv_core
)->nr_threads
);
337 if (chip
->ram_size
) {
338 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
343 * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
345 static const uint8_t pa_features_300
[] = { 66, 0,
346 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
347 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
348 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
350 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
352 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
353 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
354 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
355 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
356 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
357 /* 32: LE atomic, 34: EBB + ext EBB */
358 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
360 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
361 /* 42: PM, 44: PC RA, 46: SC vec'd */
362 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
363 /* 48: SIMD, 50: QP BFP, 52: String */
364 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
365 /* 54: DecFP, 56: DecI, 58: SHA */
366 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
367 /* 60: NM atomic, 62: RNG */
368 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
371 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
373 static const char compat
[] = "ibm,power9-xscom\0ibm,xscom";
376 pnv_dt_xscom(chip
, fdt
, 0,
377 cpu_to_be64(PNV9_XSCOM_BASE(chip
)),
378 cpu_to_be64(PNV9_XSCOM_SIZE
),
379 compat
, sizeof(compat
));
381 for (i
= 0; i
< chip
->nr_cores
; i
++) {
382 PnvCore
*pnv_core
= chip
->cores
[i
];
385 offset
= pnv_dt_core(chip
, pnv_core
, fdt
);
387 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
388 pa_features_300
, sizeof(pa_features_300
))));
391 if (chip
->ram_size
) {
392 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
395 pnv_dt_lpc(chip
, fdt
, 0, PNV9_LPCM_BASE(chip
), PNV9_LPCM_SIZE
);
399 * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
400 * always disables copy/paste.
402 static const uint8_t pa_features_31
[] = { 74, 0,
403 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
404 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
405 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
407 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
409 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
410 /* 18: Vec. Scalar, 20: Vec. XOR */
411 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
412 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
413 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
414 /* 32: LE atomic, 34: EBB + ext EBB */
415 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
417 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
418 /* 42: PM, 44: PC RA, 46: SC vec'd */
419 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
420 /* 48: SIMD, 50: QP BFP, 52: String */
421 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
422 /* 54: DecFP, 56: DecI, 58: SHA */
423 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
424 /* 60: NM atomic, 62: RNG */
425 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
426 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
427 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
428 /* 72: [P]HASHST/[P]HASHCHK */
429 0x80, 0x00, /* 72 - 73 */
432 static void pnv_chip_power10_dt_populate(PnvChip
*chip
, void *fdt
)
434 static const char compat
[] = "ibm,power10-xscom\0ibm,xscom";
437 pnv_dt_xscom(chip
, fdt
, 0,
438 cpu_to_be64(PNV10_XSCOM_BASE(chip
)),
439 cpu_to_be64(PNV10_XSCOM_SIZE
),
440 compat
, sizeof(compat
));
442 for (i
= 0; i
< chip
->nr_cores
; i
++) {
443 PnvCore
*pnv_core
= chip
->cores
[i
];
446 offset
= pnv_dt_core(chip
, pnv_core
, fdt
);
448 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
449 pa_features_31
, sizeof(pa_features_31
))));
452 if (chip
->ram_size
) {
453 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
456 pnv_dt_lpc(chip
, fdt
, 0, PNV10_LPCM_BASE(chip
), PNV10_LPCM_SIZE
);
459 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
461 uint32_t io_base
= d
->ioport_id
;
462 uint32_t io_regs
[] = {
464 cpu_to_be32(io_base
),
470 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
471 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
475 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
476 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
479 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
481 const char compatible
[] = "ns16550\0pnpPNP,501";
482 uint32_t io_base
= d
->ioport_id
;
483 uint32_t io_regs
[] = {
485 cpu_to_be32(io_base
),
492 irq
= object_property_get_uint(OBJECT(d
), "irq", &error_fatal
);
494 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
495 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
499 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
500 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
501 sizeof(compatible
))));
503 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
504 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
505 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
506 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
507 fdt_get_phandle(fdt
, lpc_off
))));
509 /* This is needed by Linux */
510 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
513 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
515 const char compatible
[] = "bt\0ipmi-bt";
517 uint32_t io_regs
[] = {
519 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
526 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
527 io_regs
[1] = cpu_to_be32(io_base
);
529 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
531 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
532 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
536 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
537 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
538 sizeof(compatible
))));
540 /* Mark it as reserved to avoid Linux trying to claim it */
541 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
542 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
543 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
544 fdt_get_phandle(fdt
, lpc_off
))));
547 typedef struct ForeachPopulateArgs
{
550 } ForeachPopulateArgs
;
552 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
554 ForeachPopulateArgs
*args
= opaque
;
555 ISADevice
*d
= ISA_DEVICE(dev
);
557 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
558 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
559 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
560 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
561 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
562 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
564 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
572 * The default LPC bus of a multichip system is on chip 0. It's
573 * recognized by the firmware (skiboot) using a "primary" property.
575 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
577 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
578 ForeachPopulateArgs args
= {
580 .offset
= isa_offset
,
584 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
586 phandle
= qemu_fdt_alloc_phandle(fdt
);
588 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
591 * ISA devices are not necessarily parented to the ISA bus so we
592 * can not use object_child_foreach()
594 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
598 static void pnv_dt_power_mgt(PnvMachineState
*pnv
, void *fdt
)
602 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
603 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
605 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
608 static void *pnv_dt_create(MachineState
*machine
)
610 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
611 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
617 fdt
= g_malloc0(FDT_MAX_SIZE
);
618 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
621 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
624 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
625 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
626 _FDT((fdt_setprop_string(fdt
, 0, "model",
627 "IBM PowerNV (emulated by qemu)")));
628 _FDT((fdt_setprop(fdt
, 0, "compatible", pmc
->compat
, pmc
->compat_size
)));
630 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
631 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
633 _FDT((fdt_setprop_string(fdt
, 0, "system-id", buf
)));
637 off
= fdt_add_subnode(fdt
, 0, "chosen");
638 if (machine
->kernel_cmdline
) {
639 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
640 machine
->kernel_cmdline
)));
643 if (pnv
->initrd_size
) {
644 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
645 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
647 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
648 &start_prop
, sizeof(start_prop
))));
649 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
650 &end_prop
, sizeof(end_prop
))));
653 /* Populate device tree for each chip */
654 for (i
= 0; i
< pnv
->num_chips
; i
++) {
655 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
658 /* Populate ISA devices on chip 0 */
659 pnv_dt_isa(pnv
, fdt
);
662 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
665 /* Create an extra node for power management on machines that support it */
666 if (pmc
->dt_power_mgt
) {
667 pmc
->dt_power_mgt(pnv
, fdt
);
673 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
675 PnvMachineState
*pnv
= container_of(n
, PnvMachineState
, powerdown_notifier
);
678 pnv_bmc_powerdown(pnv
->bmc
);
682 static void pnv_reset(MachineState
*machine
, ShutdownCause reason
)
684 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
688 qemu_devices_reset(reason
);
691 * The machine should provide by default an internal BMC simulator.
692 * If not, try to use the BMC device that was provided on the command
695 bmc
= pnv_bmc_find(&error_fatal
);
698 if (!qtest_enabled()) {
699 warn_report("machine has no BMC device. Use '-device "
700 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
704 pnv_bmc_set_pnor(bmc
, pnv
->pnor
);
709 fdt
= pnv_dt_create(machine
);
711 /* Pack resulting tree */
712 _FDT((fdt_pack(fdt
)));
714 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
715 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
718 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free
719 * the existing machine->fdt to avoid leaking it during
722 g_free(machine
->fdt
);
726 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
728 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
729 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_EXTERNAL
);
731 qdev_connect_gpio_out(DEVICE(&chip8
->lpc
), 0, irq
);
732 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
735 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
737 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
738 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_LPC_I2C
);
740 qdev_connect_gpio_out(DEVICE(&chip8
->lpc
), 0, irq
);
741 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
744 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
746 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
747 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip9
->psi
), PSIHB9_IRQ_LPCHC
);
749 qdev_connect_gpio_out(DEVICE(&chip9
->lpc
), 0, irq
);
750 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
753 static ISABus
*pnv_chip_power10_isa_create(PnvChip
*chip
, Error
**errp
)
755 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
756 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip10
->psi
), PSIHB9_IRQ_LPCHC
);
758 qdev_connect_gpio_out(DEVICE(&chip10
->lpc
), 0, irq
);
759 return pnv_lpc_isa_create(&chip10
->lpc
, false, errp
);
762 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
764 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
767 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
769 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
772 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
774 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
775 PnvPHB
*phb
= chip8
->phbs
[i
];
776 PnvPHB3
*phb3
= PNV_PHB3(phb
->backend
);
778 pnv_phb3_msi_pic_print_info(&phb3
->msis
, mon
);
779 ics_pic_print_info(&phb3
->lsis
, mon
);
783 static int pnv_chip_power9_pic_print_info_child(Object
*child
, void *opaque
)
785 Monitor
*mon
= opaque
;
786 PnvPHB
*phb
= (PnvPHB
*) object_dynamic_cast(child
, TYPE_PNV_PHB
);
792 pnv_phb4_pic_print_info(PNV_PHB4(phb
->backend
), mon
);
797 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
799 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
801 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
802 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
804 object_child_foreach_recursive(OBJECT(chip
),
805 pnv_chip_power9_pic_print_info_child
, mon
);
808 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip
*chip
,
811 return PNV_XSCOM_EX_BASE(core_id
);
814 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip
*chip
,
817 return PNV9_XSCOM_EC_BASE(core_id
);
820 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip
*chip
,
823 return PNV10_XSCOM_EC_BASE(core_id
);
826 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
828 PowerPCCPUClass
*ppc_default
=
829 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
830 PowerPCCPUClass
*ppc
=
831 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
833 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
, false);
836 static void pnv_ipmi_bt_init(ISABus
*bus
, IPMIBmc
*bmc
, uint32_t irq
)
838 ISADevice
*dev
= isa_new("isa-ipmi-bt");
840 object_property_set_link(OBJECT(dev
), "bmc", OBJECT(bmc
), &error_fatal
);
841 object_property_set_int(OBJECT(dev
), "irq", irq
, &error_fatal
);
842 isa_realize_and_unref(dev
, bus
, &error_fatal
);
845 static void pnv_chip_power10_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
847 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
849 pnv_xive2_pic_print_info(&chip10
->xive
, mon
);
850 pnv_psi_pic_print_info(&chip10
->psi
, mon
);
852 object_child_foreach_recursive(OBJECT(chip
),
853 pnv_chip_power9_pic_print_info_child
, mon
);
856 /* Always give the first 1GB to chip 0 else we won't boot */
857 static uint64_t pnv_chip_get_ram_size(PnvMachineState
*pnv
, int chip_id
)
859 MachineState
*machine
= MACHINE(pnv
);
860 uint64_t ram_per_chip
;
862 assert(machine
->ram_size
>= 1 * GiB
);
864 ram_per_chip
= machine
->ram_size
/ pnv
->num_chips
;
865 if (ram_per_chip
>= 1 * GiB
) {
866 return QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
869 assert(pnv
->num_chips
> 1);
871 ram_per_chip
= (machine
->ram_size
- 1 * GiB
) / (pnv
->num_chips
- 1);
872 return chip_id
== 0 ? 1 * GiB
: QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
875 static void pnv_init(MachineState
*machine
)
877 const char *bios_name
= machine
->firmware
?: FW_FILE_NAME
;
878 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
879 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
880 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
883 uint64_t chip_ram_start
= 0;
886 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
890 error_report("machine %s does not support the KVM accelerator",
896 if (machine
->ram_size
< mc
->default_ram_size
) {
897 char *sz
= size_to_str(mc
->default_ram_size
);
898 error_report("Invalid RAM size, should be bigger than %s", sz
);
902 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
905 * Create our simple PNOR device
907 dev
= qdev_new(TYPE_PNV_PNOR
);
909 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
));
911 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
912 pnv
->pnor
= PNV_PNOR(dev
);
914 /* load skiboot firmware */
915 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
917 error_report("Could not find OPAL firmware '%s'", bios_name
);
921 fw_size
= load_image_targphys(fw_filename
, pnv
->fw_load_addr
, FW_MAX_SIZE
);
923 error_report("Could not load OPAL firmware '%s'", fw_filename
);
929 if (machine
->kernel_filename
) {
932 kernel_size
= load_image_targphys(machine
->kernel_filename
,
933 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
934 if (kernel_size
< 0) {
935 error_report("Could not load kernel '%s'",
936 machine
->kernel_filename
);
942 if (machine
->initrd_filename
) {
943 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
944 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
945 pnv
->initrd_base
, INITRD_MAX_SIZE
);
946 if (pnv
->initrd_size
< 0) {
947 error_report("Could not load initial ram disk '%s'",
948 machine
->initrd_filename
);
953 /* MSIs are supported on this platform */
954 msi_nonbroken
= true;
957 * Check compatibility of the specified CPU with the machine
960 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
961 error_report("invalid CPU model '%s' for %s machine",
962 machine
->cpu_type
, mc
->name
);
966 /* Create the processor chips */
967 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
968 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
969 i
, machine
->cpu_type
);
970 if (!object_class_by_name(chip_typename
)) {
971 error_report("invalid chip model '%.*s' for %s machine",
972 i
, machine
->cpu_type
, mc
->name
);
977 machine
->smp
.max_cpus
/ (machine
->smp
.cores
* machine
->smp
.threads
);
979 if (machine
->smp
.threads
> 8) {
980 error_report("Cannot support more than 8 threads/core "
981 "on a powernv machine");
984 if (!is_power_of_2(machine
->smp
.threads
)) {
985 error_report("Cannot support %d threads/core on a powernv"
986 "machine because it must be a power of 2",
987 machine
->smp
.threads
);
991 * TODO: should we decide on how many chips we can create based
992 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
994 if (!is_power_of_2(pnv
->num_chips
) || pnv
->num_chips
> 16) {
995 error_report("invalid number of chips: '%d'", pnv
->num_chips
);
997 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
1001 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
1002 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1004 Object
*chip
= OBJECT(qdev_new(chip_typename
));
1005 uint64_t chip_ram_size
= pnv_chip_get_ram_size(pnv
, i
);
1007 pnv
->chips
[i
] = PNV_CHIP(chip
);
1009 /* Distribute RAM among the chips */
1010 object_property_set_int(chip
, "ram-start", chip_ram_start
,
1012 object_property_set_int(chip
, "ram-size", chip_ram_size
,
1014 chip_ram_start
+= chip_ram_size
;
1016 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", i
);
1017 object_property_add_child(OBJECT(pnv
), chip_name
, chip
);
1018 object_property_set_int(chip
, "chip-id", i
, &error_fatal
);
1019 object_property_set_int(chip
, "nr-cores", machine
->smp
.cores
,
1021 object_property_set_int(chip
, "nr-threads", machine
->smp
.threads
,
1024 * The POWER8 machine use the XICS interrupt interface.
1025 * Propagate the XICS fabric to the chip and its controllers.
1027 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XICS_FABRIC
)) {
1028 object_property_set_link(chip
, "xics", OBJECT(pnv
), &error_abort
);
1030 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XIVE_FABRIC
)) {
1031 object_property_set_link(chip
, "xive-fabric", OBJECT(pnv
),
1034 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip
), &error_fatal
);
1036 g_free(chip_typename
);
1038 /* Instantiate ISA bus on chip 0 */
1039 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
1041 /* Create serial port */
1042 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
1044 /* Create an RTC ISA device too */
1045 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
1048 * Create the machine BMC simulator and the IPMI BT device for
1049 * communication with the BMC
1051 if (defaults_enabled()) {
1052 pnv
->bmc
= pnv_bmc_create(pnv
->pnor
);
1053 pnv_ipmi_bt_init(pnv
->isa_bus
, pnv
->bmc
, 10);
1057 * The PNOR is mapped on the LPC FW address space by the BMC.
1058 * Since we can not reach the remote BMC machine with LPC memops,
1059 * map it always for now.
1061 memory_region_add_subregion(pnv
->chips
[0]->fw_mr
, PNOR_SPI_OFFSET
,
1065 * OpenPOWER systems use a IPMI SEL Event message to notify the
1068 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
1069 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
1072 * Create/Connect any machine-specific I2C devices
1074 if (pmc
->i2c_init
) {
1080 * 0:21 Reserved - Read as zeros
1085 static uint32_t pnv_chip_pir_p8(PnvChip
*chip
, uint32_t core_id
,
1088 return (chip
->chip_id
<< 7) | (core_id
<< 3) | thread_id
;
1091 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1094 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
1095 Error
*local_err
= NULL
;
1097 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1099 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, chip8
->xics
, &local_err
);
1101 error_propagate(errp
, local_err
);
1105 pnv_cpu
->intc
= obj
;
1109 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1111 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1113 icp_reset(ICP(pnv_cpu
->intc
));
1116 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1118 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1120 icp_destroy(ICP(pnv_cpu
->intc
));
1121 pnv_cpu
->intc
= NULL
;
1124 static void pnv_chip_power8_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1127 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
1131 * 0:48 Reserved - Read as zeroes
1134 * 56 Reserved - Read as zero
1138 * We only care about the lower bits. uint32_t is fine for the moment.
1140 static uint32_t pnv_chip_pir_p9(PnvChip
*chip
, uint32_t core_id
,
1143 if (chip
->nr_threads
== 8) {
1144 return (chip
->chip_id
<< 8) | ((thread_id
& 1) << 2) | (core_id
<< 3) |
1147 return (chip
->chip_id
<< 8) | (core_id
<< 2) | thread_id
;
1152 * 0:48 Reserved - Read as zeroes
1155 * 56 Reserved - Read as zero
1157 * 60 Core Chiplet Pair ID
1158 * 61:63 Thread/Core Chiplet ID t0-t2
1160 * We only care about the lower bits. uint32_t is fine for the moment.
1162 static uint32_t pnv_chip_pir_p10(PnvChip
*chip
, uint32_t core_id
,
1165 if (chip
->nr_threads
== 8) {
1166 return (chip
->chip_id
<< 8) | ((core_id
/ 4) << 4) |
1167 ((core_id
% 2) << 3) | thread_id
;
1169 return (chip
->chip_id
<< 8) | (core_id
<< 2) | thread_id
;
1173 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1176 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1177 Error
*local_err
= NULL
;
1179 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1182 * The core creates its interrupt presenter but the XIVE interrupt
1183 * controller object is initialized afterwards. Hopefully, it's
1184 * only used at runtime.
1186 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip9
->xive
),
1189 error_propagate(errp
, local_err
);
1193 pnv_cpu
->intc
= obj
;
1196 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1198 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1200 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
1203 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1205 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1207 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
1208 pnv_cpu
->intc
= NULL
;
1211 static void pnv_chip_power9_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1214 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1217 static void pnv_chip_power10_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1220 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
1221 Error
*local_err
= NULL
;
1223 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1226 * The core creates its interrupt presenter but the XIVE2 interrupt
1227 * controller object is initialized afterwards. Hopefully, it's
1228 * only used at runtime.
1230 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip10
->xive
),
1233 error_propagate(errp
, local_err
);
1237 pnv_cpu
->intc
= obj
;
1240 static void pnv_chip_power10_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1242 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1244 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
1247 static void pnv_chip_power10_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1249 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1251 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
1252 pnv_cpu
->intc
= NULL
;
1255 static void pnv_chip_power10_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1258 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1262 * Allowed core identifiers on a POWER8 Processor Chip :
1271 * <EX7,8 reserved> <reserved>
1273 * EX10 - Venice only
1274 * EX11 - Venice only
1280 #define POWER8E_CORE_MASK (0x7070ull)
1281 #define POWER8_CORE_MASK (0x7e7eull)
1284 * POWER9 has 24 cores, ids starting at 0x0
1286 #define POWER9_CORE_MASK (0xffffffffffffffull)
1289 #define POWER10_CORE_MASK (0xffffffffffffffull)
1291 static void pnv_chip_power8_instance_init(Object
*obj
)
1293 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
1294 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1297 object_property_add_link(obj
, "xics", TYPE_XICS_FABRIC
,
1298 (Object
**)&chip8
->xics
,
1299 object_property_allow_set_link
,
1300 OBJ_PROP_LINK_STRONG
);
1302 object_initialize_child(obj
, "psi", &chip8
->psi
, TYPE_PNV8_PSI
);
1304 object_initialize_child(obj
, "lpc", &chip8
->lpc
, TYPE_PNV8_LPC
);
1306 object_initialize_child(obj
, "occ", &chip8
->occ
, TYPE_PNV8_OCC
);
1308 object_initialize_child(obj
, "homer", &chip8
->homer
, TYPE_PNV8_HOMER
);
1310 if (defaults_enabled()) {
1311 chip8
->num_phbs
= pcc
->num_phbs
;
1313 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
1314 Object
*phb
= object_new(TYPE_PNV_PHB
);
1317 * We need the chip to parent the PHB to allow the DT
1318 * to build correctly (via pnv_xscom_dt()).
1320 * TODO: the PHB should be parented by a PEC device that, at
1321 * this moment, is not modelled powernv8/phb3.
1323 object_property_add_child(obj
, "phb[*]", phb
);
1324 chip8
->phbs
[i
] = PNV_PHB(phb
);
1330 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
1332 PnvChip
*chip
= PNV_CHIP(chip8
);
1333 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1337 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
1338 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
1340 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip
),
1343 /* Map the ICP registers for each thread */
1344 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1345 PnvCore
*pnv_core
= chip
->cores
[i
];
1346 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
1348 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
1349 uint32_t pir
= pcc
->chip_pir(chip
, core_hwid
, j
);
1350 PnvICPState
*icp
= PNV_ICP(xics_icp_get(chip8
->xics
, pir
));
1352 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
1358 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
1360 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1361 PnvChip
*chip
= PNV_CHIP(dev
);
1362 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
1363 Pnv8Psi
*psi8
= &chip8
->psi
;
1364 Error
*local_err
= NULL
;
1367 assert(chip8
->xics
);
1369 /* XSCOM bridge is first */
1370 pnv_xscom_init(chip
, PNV_XSCOM_SIZE
, PNV_XSCOM_BASE(chip
));
1372 pcc
->parent_realize(dev
, &local_err
);
1374 error_propagate(errp
, local_err
);
1378 /* Processor Service Interface (PSI) Host Bridge */
1379 object_property_set_int(OBJECT(psi8
), "bar", PNV_PSIHB_BASE(chip
),
1381 object_property_set_link(OBJECT(psi8
), ICS_PROP_XICS
,
1382 OBJECT(chip8
->xics
), &error_abort
);
1383 if (!qdev_realize(DEVICE(psi8
), NULL
, errp
)) {
1386 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
1387 &PNV_PSI(psi8
)->xscom_regs
);
1389 /* Create LPC controller */
1390 qdev_realize(DEVICE(&chip8
->lpc
), NULL
, &error_fatal
);
1391 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
1393 chip
->fw_mr
= &chip8
->lpc
.isa_fw
;
1394 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
1395 (uint64_t) PNV_XSCOM_BASE(chip
),
1396 PNV_XSCOM_LPC_BASE
);
1399 * Interrupt Management Area. This is the memory region holding
1400 * all the Interrupt Control Presenter (ICP) registers
1402 pnv_chip_icp_realize(chip8
, &local_err
);
1404 error_propagate(errp
, local_err
);
1408 /* Create the simplified OCC model */
1409 if (!qdev_realize(DEVICE(&chip8
->occ
), NULL
, errp
)) {
1412 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1413 qdev_connect_gpio_out(DEVICE(&chip8
->occ
), 0,
1414 qdev_get_gpio_in(DEVICE(psi8
), PSIHB_IRQ_OCC
));
1416 /* OCC SRAM model */
1417 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip
),
1418 &chip8
->occ
.sram_regs
);
1421 object_property_set_link(OBJECT(&chip8
->homer
), "chip", OBJECT(chip
),
1423 if (!qdev_realize(DEVICE(&chip8
->homer
), NULL
, errp
)) {
1426 /* Homer Xscom region */
1427 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PBA_BASE
, &chip8
->homer
.pba_regs
);
1429 /* Homer mmio region */
1430 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1431 &chip8
->homer
.regs
);
1433 /* PHB controllers */
1434 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
1435 PnvPHB
*phb
= chip8
->phbs
[i
];
1437 object_property_set_int(OBJECT(phb
), "index", i
, &error_fatal
);
1438 object_property_set_int(OBJECT(phb
), "chip-id", chip
->chip_id
,
1440 object_property_set_link(OBJECT(phb
), "chip", OBJECT(chip
),
1442 if (!sysbus_realize(SYS_BUS_DEVICE(phb
), errp
)) {
1448 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1450 addr
&= (PNV_XSCOM_SIZE
- 1);
1451 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
1454 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1456 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1457 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1459 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1460 k
->cores_mask
= POWER8E_CORE_MASK
;
1462 k
->chip_pir
= pnv_chip_pir_p8
;
1463 k
->intc_create
= pnv_chip_power8_intc_create
;
1464 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1465 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1466 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1467 k
->isa_create
= pnv_chip_power8_isa_create
;
1468 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1469 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1470 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1471 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1472 dc
->desc
= "PowerNV Chip POWER8E";
1474 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1475 &k
->parent_realize
);
1478 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1480 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1481 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1483 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1484 k
->cores_mask
= POWER8_CORE_MASK
;
1486 k
->chip_pir
= pnv_chip_pir_p8
;
1487 k
->intc_create
= pnv_chip_power8_intc_create
;
1488 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1489 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1490 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1491 k
->isa_create
= pnv_chip_power8_isa_create
;
1492 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1493 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1494 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1495 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1496 dc
->desc
= "PowerNV Chip POWER8";
1498 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1499 &k
->parent_realize
);
1502 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1504 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1505 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1507 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1508 k
->cores_mask
= POWER8_CORE_MASK
;
1510 k
->chip_pir
= pnv_chip_pir_p8
;
1511 k
->intc_create
= pnv_chip_power8_intc_create
;
1512 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1513 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1514 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1515 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1516 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1517 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1518 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1519 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1520 dc
->desc
= "PowerNV Chip POWER8NVL";
1522 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1523 &k
->parent_realize
);
1526 static void pnv_chip_power9_instance_init(Object
*obj
)
1528 PnvChip
*chip
= PNV_CHIP(obj
);
1529 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1530 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1533 object_initialize_child(obj
, "xive", &chip9
->xive
, TYPE_PNV_XIVE
);
1534 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip9
->xive
),
1537 object_initialize_child(obj
, "psi", &chip9
->psi
, TYPE_PNV9_PSI
);
1539 object_initialize_child(obj
, "lpc", &chip9
->lpc
, TYPE_PNV9_LPC
);
1541 object_initialize_child(obj
, "chiptod", &chip9
->chiptod
, TYPE_PNV9_CHIPTOD
);
1543 object_initialize_child(obj
, "occ", &chip9
->occ
, TYPE_PNV9_OCC
);
1545 object_initialize_child(obj
, "sbe", &chip9
->sbe
, TYPE_PNV9_SBE
);
1547 object_initialize_child(obj
, "homer", &chip9
->homer
, TYPE_PNV9_HOMER
);
1549 /* Number of PECs is the chip default */
1550 chip
->num_pecs
= pcc
->num_pecs
;
1552 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1553 object_initialize_child(obj
, "pec[*]", &chip9
->pecs
[i
],
1557 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
1558 object_initialize_child(obj
, "i2c[*]", &chip9
->i2c
[i
], TYPE_PNV_I2C
);
1562 static void pnv_chip_quad_realize_one(PnvChip
*chip
, PnvQuad
*eq
,
1567 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1569 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1570 object_initialize_child_with_props(OBJECT(chip
), eq_name
, eq
,
1572 &error_fatal
, NULL
);
1574 object_property_set_int(OBJECT(eq
), "quad-id", core_id
, &error_fatal
);
1575 qdev_realize(DEVICE(eq
), NULL
, &error_fatal
);
1578 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1580 PnvChip
*chip
= PNV_CHIP(chip9
);
1583 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1584 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1586 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1587 PnvQuad
*eq
= &chip9
->quads
[i
];
1589 pnv_chip_quad_realize_one(chip
, eq
, chip
->cores
[i
* 4],
1590 PNV_QUAD_TYPE_NAME("power9"));
1592 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->quad_id
),
1597 static void pnv_chip_power9_pec_realize(PnvChip
*chip
, Error
**errp
)
1599 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1602 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1603 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
1604 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1605 uint32_t pec_nest_base
;
1606 uint32_t pec_pci_base
;
1608 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1609 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1611 object_property_set_link(OBJECT(pec
), "chip", OBJECT(chip
),
1613 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1617 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1618 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1620 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1621 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1625 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1627 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1628 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1629 PnvChip
*chip
= PNV_CHIP(dev
);
1630 Pnv9Psi
*psi9
= &chip9
->psi
;
1631 Error
*local_err
= NULL
;
1634 /* XSCOM bridge is first */
1635 pnv_xscom_init(chip
, PNV9_XSCOM_SIZE
, PNV9_XSCOM_BASE(chip
));
1637 pcc
->parent_realize(dev
, &local_err
);
1639 error_propagate(errp
, local_err
);
1643 pnv_chip_quad_realize(chip9
, &local_err
);
1645 error_propagate(errp
, local_err
);
1649 /* XIVE interrupt controller (POWER9) */
1650 object_property_set_int(OBJECT(&chip9
->xive
), "ic-bar",
1651 PNV9_XIVE_IC_BASE(chip
), &error_fatal
);
1652 object_property_set_int(OBJECT(&chip9
->xive
), "vc-bar",
1653 PNV9_XIVE_VC_BASE(chip
), &error_fatal
);
1654 object_property_set_int(OBJECT(&chip9
->xive
), "pc-bar",
1655 PNV9_XIVE_PC_BASE(chip
), &error_fatal
);
1656 object_property_set_int(OBJECT(&chip9
->xive
), "tm-bar",
1657 PNV9_XIVE_TM_BASE(chip
), &error_fatal
);
1658 object_property_set_link(OBJECT(&chip9
->xive
), "chip", OBJECT(chip
),
1660 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9
->xive
), errp
)) {
1663 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1664 &chip9
->xive
.xscom_regs
);
1666 /* Processor Service Interface (PSI) Host Bridge */
1667 object_property_set_int(OBJECT(psi9
), "bar", PNV9_PSIHB_BASE(chip
),
1669 /* This is the only device with 4k ESB pages */
1670 object_property_set_int(OBJECT(psi9
), "shift", XIVE_ESB_4K
,
1672 if (!qdev_realize(DEVICE(psi9
), NULL
, errp
)) {
1675 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1676 &PNV_PSI(psi9
)->xscom_regs
);
1679 if (!qdev_realize(DEVICE(&chip9
->lpc
), NULL
, errp
)) {
1682 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1683 &chip9
->lpc
.xscom_regs
);
1685 chip
->fw_mr
= &chip9
->lpc
.isa_fw
;
1686 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1687 (uint64_t) PNV9_LPCM_BASE(chip
));
1690 object_property_set_bool(OBJECT(&chip9
->chiptod
), "primary",
1691 chip
->chip_id
== 0, &error_abort
);
1692 object_property_set_bool(OBJECT(&chip9
->chiptod
), "secondary",
1693 chip
->chip_id
== 1, &error_abort
);
1694 object_property_set_link(OBJECT(&chip9
->chiptod
), "chip", OBJECT(chip
),
1696 if (!qdev_realize(DEVICE(&chip9
->chiptod
), NULL
, errp
)) {
1699 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_CHIPTOD_BASE
,
1700 &chip9
->chiptod
.xscom_regs
);
1702 /* Create the simplified OCC model */
1703 if (!qdev_realize(DEVICE(&chip9
->occ
), NULL
, errp
)) {
1706 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1707 qdev_connect_gpio_out(DEVICE(&chip9
->occ
), 0, qdev_get_gpio_in(
1708 DEVICE(psi9
), PSIHB9_IRQ_OCC
));
1710 /* OCC SRAM model */
1711 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip
),
1712 &chip9
->occ
.sram_regs
);
1715 if (!qdev_realize(DEVICE(&chip9
->sbe
), NULL
, errp
)) {
1718 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_SBE_CTRL_BASE
,
1719 &chip9
->sbe
.xscom_ctrl_regs
);
1720 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_SBE_MBOX_BASE
,
1721 &chip9
->sbe
.xscom_mbox_regs
);
1722 qdev_connect_gpio_out(DEVICE(&chip9
->sbe
), 0, qdev_get_gpio_in(
1723 DEVICE(psi9
), PSIHB9_IRQ_PSU
));
1726 object_property_set_link(OBJECT(&chip9
->homer
), "chip", OBJECT(chip
),
1728 if (!qdev_realize(DEVICE(&chip9
->homer
), NULL
, errp
)) {
1731 /* Homer Xscom region */
1732 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PBA_BASE
, &chip9
->homer
.pba_regs
);
1734 /* Homer mmio region */
1735 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1736 &chip9
->homer
.regs
);
1739 pnv_chip_power9_pec_realize(chip
, &local_err
);
1741 error_propagate(errp
, local_err
);
1748 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
1749 Object
*obj
= OBJECT(&chip9
->i2c
[i
]);
1751 object_property_set_int(obj
, "engine", i
+ 1, &error_fatal
);
1752 object_property_set_int(obj
, "num-busses",
1753 pcc
->i2c_ports_per_engine
[i
],
1755 object_property_set_link(obj
, "chip", OBJECT(chip
), &error_abort
);
1756 if (!qdev_realize(DEVICE(obj
), NULL
, errp
)) {
1759 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_I2CM_BASE
+
1760 (chip9
->i2c
[i
].engine
- 1) *
1761 PNV9_XSCOM_I2CM_SIZE
,
1762 &chip9
->i2c
[i
].xscom_regs
);
1763 qdev_connect_gpio_out(DEVICE(&chip9
->i2c
[i
]), 0,
1764 qdev_get_gpio_in(DEVICE(psi9
),
1765 PSIHB9_IRQ_SBE_I2C
));
1769 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1771 addr
&= (PNV9_XSCOM_SIZE
- 1);
1775 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1777 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1778 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1779 static const int i2c_ports_per_engine
[PNV9_CHIP_MAX_I2C
] = {2, 13, 2, 2};
1781 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1782 k
->cores_mask
= POWER9_CORE_MASK
;
1783 k
->chip_pir
= pnv_chip_pir_p9
;
1784 k
->intc_create
= pnv_chip_power9_intc_create
;
1785 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1786 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1787 k
->intc_print_info
= pnv_chip_power9_intc_print_info
;
1788 k
->isa_create
= pnv_chip_power9_isa_create
;
1789 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1790 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1791 k
->xscom_core_base
= pnv_chip_power9_xscom_core_base
;
1792 k
->xscom_pcba
= pnv_chip_power9_xscom_pcba
;
1793 dc
->desc
= "PowerNV Chip POWER9";
1794 k
->num_pecs
= PNV9_CHIP_MAX_PEC
;
1795 k
->i2c_num_engines
= PNV9_CHIP_MAX_I2C
;
1796 k
->i2c_ports_per_engine
= i2c_ports_per_engine
;
1798 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1799 &k
->parent_realize
);
1802 static void pnv_chip_power10_instance_init(Object
*obj
)
1804 PnvChip
*chip
= PNV_CHIP(obj
);
1805 Pnv10Chip
*chip10
= PNV10_CHIP(obj
);
1806 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1809 object_initialize_child(obj
, "xive", &chip10
->xive
, TYPE_PNV_XIVE2
);
1810 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip10
->xive
),
1812 object_initialize_child(obj
, "psi", &chip10
->psi
, TYPE_PNV10_PSI
);
1813 object_initialize_child(obj
, "lpc", &chip10
->lpc
, TYPE_PNV10_LPC
);
1814 object_initialize_child(obj
, "chiptod", &chip10
->chiptod
,
1815 TYPE_PNV10_CHIPTOD
);
1816 object_initialize_child(obj
, "occ", &chip10
->occ
, TYPE_PNV10_OCC
);
1817 object_initialize_child(obj
, "sbe", &chip10
->sbe
, TYPE_PNV10_SBE
);
1818 object_initialize_child(obj
, "homer", &chip10
->homer
, TYPE_PNV10_HOMER
);
1819 object_initialize_child(obj
, "n1-chiplet", &chip10
->n1_chiplet
,
1820 TYPE_PNV_N1_CHIPLET
);
1822 chip
->num_pecs
= pcc
->num_pecs
;
1824 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1825 object_initialize_child(obj
, "pec[*]", &chip10
->pecs
[i
],
1829 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
1830 object_initialize_child(obj
, "i2c[*]", &chip10
->i2c
[i
], TYPE_PNV_I2C
);
1834 static void pnv_chip_power10_quad_realize(Pnv10Chip
*chip10
, Error
**errp
)
1836 PnvChip
*chip
= PNV_CHIP(chip10
);
1839 chip10
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1840 chip10
->quads
= g_new0(PnvQuad
, chip10
->nr_quads
);
1842 for (i
= 0; i
< chip10
->nr_quads
; i
++) {
1843 PnvQuad
*eq
= &chip10
->quads
[i
];
1845 pnv_chip_quad_realize_one(chip
, eq
, chip
->cores
[i
* 4],
1846 PNV_QUAD_TYPE_NAME("power10"));
1848 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_EQ_BASE(eq
->quad_id
),
1851 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_QME_BASE(eq
->quad_id
),
1852 &eq
->xscom_qme_regs
);
1856 static void pnv_chip_power10_phb_realize(PnvChip
*chip
, Error
**errp
)
1858 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
1861 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1862 PnvPhb4PecState
*pec
= &chip10
->pecs
[i
];
1863 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1864 uint32_t pec_nest_base
;
1865 uint32_t pec_pci_base
;
1867 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1868 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1870 object_property_set_link(OBJECT(pec
), "chip", OBJECT(chip
),
1872 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1876 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1877 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1879 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1880 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1884 static void pnv_chip_power10_realize(DeviceState
*dev
, Error
**errp
)
1886 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1887 PnvChip
*chip
= PNV_CHIP(dev
);
1888 Pnv10Chip
*chip10
= PNV10_CHIP(dev
);
1889 Error
*local_err
= NULL
;
1892 /* XSCOM bridge is first */
1893 pnv_xscom_init(chip
, PNV10_XSCOM_SIZE
, PNV10_XSCOM_BASE(chip
));
1895 pcc
->parent_realize(dev
, &local_err
);
1897 error_propagate(errp
, local_err
);
1901 pnv_chip_power10_quad_realize(chip10
, &local_err
);
1903 error_propagate(errp
, local_err
);
1907 /* XIVE2 interrupt controller (POWER10) */
1908 object_property_set_int(OBJECT(&chip10
->xive
), "ic-bar",
1909 PNV10_XIVE2_IC_BASE(chip
), &error_fatal
);
1910 object_property_set_int(OBJECT(&chip10
->xive
), "esb-bar",
1911 PNV10_XIVE2_ESB_BASE(chip
), &error_fatal
);
1912 object_property_set_int(OBJECT(&chip10
->xive
), "end-bar",
1913 PNV10_XIVE2_END_BASE(chip
), &error_fatal
);
1914 object_property_set_int(OBJECT(&chip10
->xive
), "nvpg-bar",
1915 PNV10_XIVE2_NVPG_BASE(chip
), &error_fatal
);
1916 object_property_set_int(OBJECT(&chip10
->xive
), "nvc-bar",
1917 PNV10_XIVE2_NVC_BASE(chip
), &error_fatal
);
1918 object_property_set_int(OBJECT(&chip10
->xive
), "tm-bar",
1919 PNV10_XIVE2_TM_BASE(chip
), &error_fatal
);
1920 object_property_set_link(OBJECT(&chip10
->xive
), "chip", OBJECT(chip
),
1922 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10
->xive
), errp
)) {
1925 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_XIVE2_BASE
,
1926 &chip10
->xive
.xscom_regs
);
1928 /* Processor Service Interface (PSI) Host Bridge */
1929 object_property_set_int(OBJECT(&chip10
->psi
), "bar",
1930 PNV10_PSIHB_BASE(chip
), &error_fatal
);
1931 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1932 object_property_set_int(OBJECT(&chip10
->psi
), "shift", XIVE_ESB_64K
,
1934 if (!qdev_realize(DEVICE(&chip10
->psi
), NULL
, errp
)) {
1937 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PSIHB_BASE
,
1938 &PNV_PSI(&chip10
->psi
)->xscom_regs
);
1941 if (!qdev_realize(DEVICE(&chip10
->lpc
), NULL
, errp
)) {
1944 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip
),
1945 &chip10
->lpc
.xscom_regs
);
1947 chip
->fw_mr
= &chip10
->lpc
.isa_fw
;
1948 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1949 (uint64_t) PNV10_LPCM_BASE(chip
));
1952 object_property_set_bool(OBJECT(&chip10
->chiptod
), "primary",
1953 chip
->chip_id
== 0, &error_abort
);
1954 object_property_set_bool(OBJECT(&chip10
->chiptod
), "secondary",
1955 chip
->chip_id
== 1, &error_abort
);
1956 object_property_set_link(OBJECT(&chip10
->chiptod
), "chip", OBJECT(chip
),
1958 if (!qdev_realize(DEVICE(&chip10
->chiptod
), NULL
, errp
)) {
1961 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_CHIPTOD_BASE
,
1962 &chip10
->chiptod
.xscom_regs
);
1964 /* Create the simplified OCC model */
1965 if (!qdev_realize(DEVICE(&chip10
->occ
), NULL
, errp
)) {
1968 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_OCC_BASE
,
1969 &chip10
->occ
.xscom_regs
);
1970 qdev_connect_gpio_out(DEVICE(&chip10
->occ
), 0, qdev_get_gpio_in(
1971 DEVICE(&chip10
->psi
), PSIHB9_IRQ_OCC
));
1973 /* OCC SRAM model */
1974 memory_region_add_subregion(get_system_memory(),
1975 PNV10_OCC_SENSOR_BASE(chip
),
1976 &chip10
->occ
.sram_regs
);
1979 if (!qdev_realize(DEVICE(&chip10
->sbe
), NULL
, errp
)) {
1982 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_SBE_CTRL_BASE
,
1983 &chip10
->sbe
.xscom_ctrl_regs
);
1984 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_SBE_MBOX_BASE
,
1985 &chip10
->sbe
.xscom_mbox_regs
);
1986 qdev_connect_gpio_out(DEVICE(&chip10
->sbe
), 0, qdev_get_gpio_in(
1987 DEVICE(&chip10
->psi
), PSIHB9_IRQ_PSU
));
1990 object_property_set_link(OBJECT(&chip10
->homer
), "chip", OBJECT(chip
),
1992 if (!qdev_realize(DEVICE(&chip10
->homer
), NULL
, errp
)) {
1995 /* Homer Xscom region */
1996 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PBA_BASE
,
1997 &chip10
->homer
.pba_regs
);
1999 /* Homer mmio region */
2000 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip
),
2001 &chip10
->homer
.regs
);
2004 if (!qdev_realize(DEVICE(&chip10
->n1_chiplet
), NULL
, errp
)) {
2007 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE
,
2008 &chip10
->n1_chiplet
.nest_pervasive
.xscom_ctrl_regs_mr
);
2010 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE
,
2011 &chip10
->n1_chiplet
.xscom_pb_eq_mr
);
2013 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_N1_PB_SCOM_ES_BASE
,
2014 &chip10
->n1_chiplet
.xscom_pb_es_mr
);
2017 pnv_chip_power10_phb_realize(chip
, &local_err
);
2019 error_propagate(errp
, local_err
);
2027 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
2028 Object
*obj
= OBJECT(&chip10
->i2c
[i
]);
2030 object_property_set_int(obj
, "engine", i
+ 1, &error_fatal
);
2031 object_property_set_int(obj
, "num-busses",
2032 pcc
->i2c_ports_per_engine
[i
],
2034 object_property_set_link(obj
, "chip", OBJECT(chip
), &error_abort
);
2035 if (!qdev_realize(DEVICE(obj
), NULL
, errp
)) {
2038 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_I2CM_BASE
+
2039 (chip10
->i2c
[i
].engine
- 1) *
2040 PNV10_XSCOM_I2CM_SIZE
,
2041 &chip10
->i2c
[i
].xscom_regs
);
2042 qdev_connect_gpio_out(DEVICE(&chip10
->i2c
[i
]), 0,
2043 qdev_get_gpio_in(DEVICE(&chip10
->psi
),
2044 PSIHB9_IRQ_SBE_I2C
));
2049 static void pnv_rainier_i2c_init(PnvMachineState
*pnv
)
2052 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2053 Pnv10Chip
*chip10
= PNV10_CHIP(pnv
->chips
[i
]);
2056 * Add a PCA9552 I2C device for PCIe hotplug control
2057 * to engine 2, bus 1, address 0x63
2059 I2CSlave
*dev
= i2c_slave_create_simple(chip10
->i2c
[2].busses
[1],
2063 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9
2064 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots
2065 * after hypervisor code sets a SLOTx_EN pin high.
2067 qdev_connect_gpio_out(DEVICE(dev
), 0, qdev_get_gpio_in(DEVICE(dev
), 5));
2068 qdev_connect_gpio_out(DEVICE(dev
), 1, qdev_get_gpio_in(DEVICE(dev
), 6));
2069 qdev_connect_gpio_out(DEVICE(dev
), 2, qdev_get_gpio_in(DEVICE(dev
), 7));
2070 qdev_connect_gpio_out(DEVICE(dev
), 3, qdev_get_gpio_in(DEVICE(dev
), 8));
2071 qdev_connect_gpio_out(DEVICE(dev
), 4, qdev_get_gpio_in(DEVICE(dev
), 9));
2074 * Add a PCA9554 I2C device for cable card presence detection
2075 * to engine 2, bus 1, address 0x25
2077 i2c_slave_create_simple(chip10
->i2c
[2].busses
[1], "pca9554", 0x25);
2081 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
2083 addr
&= (PNV10_XSCOM_SIZE
- 1);
2087 static void pnv_chip_power10_class_init(ObjectClass
*klass
, void *data
)
2089 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2090 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
2091 static const int i2c_ports_per_engine
[PNV10_CHIP_MAX_I2C
] = {14, 14, 2, 16};
2093 k
->chip_cfam_id
= 0x120da04900008000ull
; /* P10 DD1.0 (with NX) */
2094 k
->cores_mask
= POWER10_CORE_MASK
;
2095 k
->chip_pir
= pnv_chip_pir_p10
;
2096 k
->intc_create
= pnv_chip_power10_intc_create
;
2097 k
->intc_reset
= pnv_chip_power10_intc_reset
;
2098 k
->intc_destroy
= pnv_chip_power10_intc_destroy
;
2099 k
->intc_print_info
= pnv_chip_power10_intc_print_info
;
2100 k
->isa_create
= pnv_chip_power10_isa_create
;
2101 k
->dt_populate
= pnv_chip_power10_dt_populate
;
2102 k
->pic_print_info
= pnv_chip_power10_pic_print_info
;
2103 k
->xscom_core_base
= pnv_chip_power10_xscom_core_base
;
2104 k
->xscom_pcba
= pnv_chip_power10_xscom_pcba
;
2105 dc
->desc
= "PowerNV Chip POWER10";
2106 k
->num_pecs
= PNV10_CHIP_MAX_PEC
;
2107 k
->i2c_num_engines
= PNV10_CHIP_MAX_I2C
;
2108 k
->i2c_ports_per_engine
= i2c_ports_per_engine
;
2110 device_class_set_parent_realize(dc
, pnv_chip_power10_realize
,
2111 &k
->parent_realize
);
2114 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
2116 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
2120 * No custom mask for this chip, let's use the default one from *
2123 if (!chip
->cores_mask
) {
2124 chip
->cores_mask
= pcc
->cores_mask
;
2127 /* filter alien core ids ! some are reserved */
2128 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
2129 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
2133 chip
->cores_mask
&= pcc
->cores_mask
;
2135 /* now that we have a sane layout, let check the number of cores */
2136 cores_max
= ctpop64(chip
->cores_mask
);
2137 if (chip
->nr_cores
> cores_max
) {
2138 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
2144 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
2146 Error
*error
= NULL
;
2147 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
2148 const char *typename
= pnv_chip_core_typename(chip
);
2150 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
2152 if (!object_class_by_name(typename
)) {
2153 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
2158 pnv_chip_core_sanitize(chip
, &error
);
2160 error_propagate(errp
, error
);
2164 chip
->cores
= g_new0(PnvCore
*, chip
->nr_cores
);
2166 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
2167 && (i
< chip
->nr_cores
); core_hwid
++) {
2170 uint64_t xscom_core_base
;
2172 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
2176 pnv_core
= PNV_CORE(object_new(typename
));
2178 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
2179 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
));
2180 chip
->cores
[i
] = pnv_core
;
2181 object_property_set_int(OBJECT(pnv_core
), "nr-threads",
2182 chip
->nr_threads
, &error_fatal
);
2183 object_property_set_int(OBJECT(pnv_core
), CPU_CORE_PROP_CORE_ID
,
2184 core_hwid
, &error_fatal
);
2185 object_property_set_int(OBJECT(pnv_core
), "hwid", core_hwid
,
2187 object_property_set_int(OBJECT(pnv_core
), "hrmor", pnv
->fw_load_addr
,
2189 object_property_set_link(OBJECT(pnv_core
), "chip", OBJECT(chip
),
2191 qdev_realize(DEVICE(pnv_core
), NULL
, &error_fatal
);
2193 /* Each core has an XSCOM MMIO region */
2194 xscom_core_base
= pcc
->xscom_core_base(chip
, core_hwid
);
2196 pnv_xscom_add_subregion(chip
, xscom_core_base
,
2197 &pnv_core
->xscom_regs
);
2202 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
2204 PnvChip
*chip
= PNV_CHIP(dev
);
2205 Error
*error
= NULL
;
2208 pnv_chip_core_realize(chip
, &error
);
2210 error_propagate(errp
, error
);
2215 static Property pnv_chip_properties
[] = {
2216 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
2217 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
2218 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
2219 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
2220 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
2221 DEFINE_PROP_UINT32("nr-threads", PnvChip
, nr_threads
, 1),
2222 DEFINE_PROP_END_OF_LIST(),
2225 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
2227 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2229 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
2230 dc
->realize
= pnv_chip_realize
;
2231 device_class_set_props(dc
, pnv_chip_properties
);
2232 dc
->desc
= "PowerNV Chip";
2235 PnvCore
*pnv_chip_find_core(PnvChip
*chip
, uint32_t core_id
)
2239 for (i
= 0; i
< chip
->nr_cores
; i
++) {
2240 PnvCore
*pc
= chip
->cores
[i
];
2241 CPUCore
*cc
= CPU_CORE(pc
);
2243 if (cc
->core_id
== core_id
) {
2250 PowerPCCPU
*pnv_chip_find_cpu(PnvChip
*chip
, uint32_t pir
)
2254 for (i
= 0; i
< chip
->nr_cores
; i
++) {
2255 PnvCore
*pc
= chip
->cores
[i
];
2256 CPUCore
*cc
= CPU_CORE(pc
);
2258 for (j
= 0; j
< cc
->nr_threads
; j
++) {
2259 if (ppc_cpu_pir(pc
->threads
[j
]) == pir
) {
2260 return pc
->threads
[j
];
2267 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
2269 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
2272 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2273 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
2275 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
2276 return &chip8
->psi
.ics
;
2279 for (j
= 0; j
< chip8
->num_phbs
; j
++) {
2280 PnvPHB
*phb
= chip8
->phbs
[j
];
2281 PnvPHB3
*phb3
= PNV_PHB3(phb
->backend
);
2283 if (ics_valid_irq(&phb3
->lsis
, irq
)) {
2287 if (ics_valid_irq(ICS(&phb3
->msis
), irq
)) {
2288 return ICS(&phb3
->msis
);
2295 PnvChip
*pnv_get_chip(PnvMachineState
*pnv
, uint32_t chip_id
)
2299 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2300 PnvChip
*chip
= pnv
->chips
[i
];
2301 if (chip
->chip_id
== chip_id
) {
2308 static void pnv_ics_resend(XICSFabric
*xi
)
2310 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
2313 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2314 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
2316 ics_resend(&chip8
->psi
.ics
);
2318 for (j
= 0; j
< chip8
->num_phbs
; j
++) {
2319 PnvPHB
*phb
= chip8
->phbs
[j
];
2320 PnvPHB3
*phb3
= PNV_PHB3(phb
->backend
);
2322 ics_resend(&phb3
->lsis
);
2323 ics_resend(ICS(&phb3
->msis
));
2328 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
2330 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
2332 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
2335 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
2338 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2343 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2345 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2346 PNV_CHIP_GET_CLASS(pnv
->chips
[0])->intc_print_info(pnv
->chips
[0], cpu
,
2350 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2351 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
2355 static int pnv_match_nvt(XiveFabric
*xfb
, uint8_t format
,
2356 uint8_t nvt_blk
, uint32_t nvt_idx
,
2357 bool cam_ignore
, uint8_t priority
,
2358 uint32_t logic_serv
,
2359 XiveTCTXMatch
*match
)
2361 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
2362 int total_count
= 0;
2365 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2366 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
2367 XivePresenter
*xptr
= XIVE_PRESENTER(&chip9
->xive
);
2368 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
2371 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
2372 priority
, logic_serv
, match
);
2378 total_count
+= count
;
2384 static int pnv10_xive_match_nvt(XiveFabric
*xfb
, uint8_t format
,
2385 uint8_t nvt_blk
, uint32_t nvt_idx
,
2386 bool cam_ignore
, uint8_t priority
,
2387 uint32_t logic_serv
,
2388 XiveTCTXMatch
*match
)
2390 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
2391 int total_count
= 0;
2394 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2395 Pnv10Chip
*chip10
= PNV10_CHIP(pnv
->chips
[i
]);
2396 XivePresenter
*xptr
= XIVE_PRESENTER(&chip10
->xive
);
2397 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
2400 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
2401 priority
, logic_serv
, match
);
2407 total_count
+= count
;
2413 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
2415 MachineClass
*mc
= MACHINE_CLASS(oc
);
2416 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
2417 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2418 static const char compat
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2420 static GlobalProperty phb_compat
[] = {
2421 { TYPE_PNV_PHB
, "version", "3" },
2422 { TYPE_PNV_PHB_ROOT_PORT
, "version", "3" },
2425 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
2426 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
2427 compat_props_add(mc
->compat_props
, phb_compat
, G_N_ELEMENTS(phb_compat
));
2429 xic
->icp_get
= pnv_icp_get
;
2430 xic
->ics_get
= pnv_ics_get
;
2431 xic
->ics_resend
= pnv_ics_resend
;
2433 pmc
->compat
= compat
;
2434 pmc
->compat_size
= sizeof(compat
);
2436 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_PNV_PHB
);
2439 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
2441 MachineClass
*mc
= MACHINE_CLASS(oc
);
2442 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
2443 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2444 static const char compat
[] = "qemu,powernv9\0ibm,powernv";
2446 static GlobalProperty phb_compat
[] = {
2447 { TYPE_PNV_PHB
, "version", "4" },
2448 { TYPE_PNV_PHB_ROOT_PORT
, "version", "4" },
2451 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
2452 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.2");
2453 compat_props_add(mc
->compat_props
, phb_compat
, G_N_ELEMENTS(phb_compat
));
2455 xfc
->match_nvt
= pnv_match_nvt
;
2457 pmc
->compat
= compat
;
2458 pmc
->compat_size
= sizeof(compat
);
2459 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
2461 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_PNV_PHB
);
2464 static void pnv_machine_p10_common_class_init(ObjectClass
*oc
, void *data
)
2466 MachineClass
*mc
= MACHINE_CLASS(oc
);
2467 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2468 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
2469 static const char compat
[] = "qemu,powernv10\0ibm,powernv";
2471 static GlobalProperty phb_compat
[] = {
2472 { TYPE_PNV_PHB
, "version", "5" },
2473 { TYPE_PNV_PHB_ROOT_PORT
, "version", "5" },
2476 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power10_v2.0");
2477 compat_props_add(mc
->compat_props
, phb_compat
, G_N_ELEMENTS(phb_compat
));
2479 mc
->alias
= "powernv";
2481 pmc
->compat
= compat
;
2482 pmc
->compat_size
= sizeof(compat
);
2483 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
2485 xfc
->match_nvt
= pnv10_xive_match_nvt
;
2487 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_PNV_PHB
);
2490 static void pnv_machine_power10_class_init(ObjectClass
*oc
, void *data
)
2492 MachineClass
*mc
= MACHINE_CLASS(oc
);
2494 pnv_machine_p10_common_class_init(oc
, data
);
2495 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10";
2498 static void pnv_machine_p10_rainier_class_init(ObjectClass
*oc
, void *data
)
2500 MachineClass
*mc
= MACHINE_CLASS(oc
);
2501 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2503 pnv_machine_p10_common_class_init(oc
, data
);
2504 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10 Rainier";
2505 pmc
->i2c_init
= pnv_rainier_i2c_init
;
2508 static bool pnv_machine_get_hb(Object
*obj
, Error
**errp
)
2510 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2512 return !!pnv
->fw_load_addr
;
2515 static void pnv_machine_set_hb(Object
*obj
, bool value
, Error
**errp
)
2517 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2520 pnv
->fw_load_addr
= 0x8000000;
2524 static void pnv_cpu_do_nmi_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
2526 CPUPPCState
*env
= cpu_env(cs
);
2528 cpu_synchronize_state(cs
);
2529 ppc_cpu_do_system_reset(cs
);
2530 if (env
->spr
[SPR_SRR1
] & SRR1_WAKESTATE
) {
2532 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2533 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2536 if (!(env
->spr
[SPR_SRR1
] & SRR1_WAKERESET
)) {
2537 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2538 env
->spr
[SPR_SRR1
] |= SRR1_WAKERESET
;
2542 * For non-powersave system resets, SRR1[42:45] are defined to be
2543 * implementation-dependent. The POWER9 User Manual specifies that
2544 * an external (SCOM driven, which may come from a BMC nmi command or
2545 * another CPU requesting a NMI IPI) system reset exception should be
2546 * 0b0010 (PPC_BIT(44)).
2548 env
->spr
[SPR_SRR1
] |= SRR1_WAKESCOM
;
2552 static void pnv_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2557 async_run_on_cpu(cs
, pnv_cpu_do_nmi_on_cpu
, RUN_ON_CPU_NULL
);
2561 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
2563 MachineClass
*mc
= MACHINE_CLASS(oc
);
2564 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
2565 NMIClass
*nc
= NMI_CLASS(oc
);
2567 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
2568 mc
->init
= pnv_init
;
2569 mc
->reset
= pnv_reset
;
2570 mc
->max_cpus
= MAX_CPUS
;
2571 /* Pnv provides a AHCI device for storage */
2572 mc
->block_default_type
= IF_IDE
;
2573 mc
->no_parallel
= 1;
2574 mc
->default_boot_order
= NULL
;
2576 * RAM defaults to less than 2048 for 32-bit hosts, and large
2577 * enough to fit the maximum initrd size at it's load address
2579 mc
->default_ram_size
= 1 * GiB
;
2580 mc
->default_ram_id
= "pnv.ram";
2581 ispc
->print_info
= pnv_pic_print_info
;
2582 nc
->nmi_monitor_handler
= pnv_nmi
;
2584 object_class_property_add_bool(oc
, "hb-mode",
2585 pnv_machine_get_hb
, pnv_machine_set_hb
);
2586 object_class_property_set_description(oc
, "hb-mode",
2587 "Use a hostboot like boot loader");
2590 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2593 .class_init = class_initfn, \
2594 .parent = TYPE_PNV8_CHIP, \
2597 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2600 .class_init = class_initfn, \
2601 .parent = TYPE_PNV9_CHIP, \
2604 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2607 .class_init = class_initfn, \
2608 .parent = TYPE_PNV10_CHIP, \
2611 static const TypeInfo types
[] = {
2613 .name
= MACHINE_TYPE_NAME("powernv10-rainier"),
2614 .parent
= MACHINE_TYPE_NAME("powernv10"),
2615 .class_init
= pnv_machine_p10_rainier_class_init
,
2618 .name
= MACHINE_TYPE_NAME("powernv10"),
2619 .parent
= TYPE_PNV_MACHINE
,
2620 .class_init
= pnv_machine_power10_class_init
,
2621 .interfaces
= (InterfaceInfo
[]) {
2622 { TYPE_XIVE_FABRIC
},
2627 .name
= MACHINE_TYPE_NAME("powernv9"),
2628 .parent
= TYPE_PNV_MACHINE
,
2629 .class_init
= pnv_machine_power9_class_init
,
2630 .interfaces
= (InterfaceInfo
[]) {
2631 { TYPE_XIVE_FABRIC
},
2636 .name
= MACHINE_TYPE_NAME("powernv8"),
2637 .parent
= TYPE_PNV_MACHINE
,
2638 .class_init
= pnv_machine_power8_class_init
,
2639 .interfaces
= (InterfaceInfo
[]) {
2640 { TYPE_XICS_FABRIC
},
2645 .name
= TYPE_PNV_MACHINE
,
2646 .parent
= TYPE_MACHINE
,
2648 .instance_size
= sizeof(PnvMachineState
),
2649 .class_init
= pnv_machine_class_init
,
2650 .class_size
= sizeof(PnvMachineClass
),
2651 .interfaces
= (InterfaceInfo
[]) {
2652 { TYPE_INTERRUPT_STATS_PROVIDER
},
2658 .name
= TYPE_PNV_CHIP
,
2659 .parent
= TYPE_SYS_BUS_DEVICE
,
2660 .class_init
= pnv_chip_class_init
,
2661 .instance_size
= sizeof(PnvChip
),
2662 .class_size
= sizeof(PnvChipClass
),
2667 * P10 chip and variants
2670 .name
= TYPE_PNV10_CHIP
,
2671 .parent
= TYPE_PNV_CHIP
,
2672 .instance_init
= pnv_chip_power10_instance_init
,
2673 .instance_size
= sizeof(Pnv10Chip
),
2675 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10
, pnv_chip_power10_class_init
),
2678 * P9 chip and variants
2681 .name
= TYPE_PNV9_CHIP
,
2682 .parent
= TYPE_PNV_CHIP
,
2683 .instance_init
= pnv_chip_power9_instance_init
,
2684 .instance_size
= sizeof(Pnv9Chip
),
2686 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
2689 * P8 chip and variants
2692 .name
= TYPE_PNV8_CHIP
,
2693 .parent
= TYPE_PNV_CHIP
,
2694 .instance_init
= pnv_chip_power8_instance_init
,
2695 .instance_size
= sizeof(Pnv8Chip
),
2697 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
2698 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
2699 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
2700 pnv_chip_power8nvl_class_init
),