target/ppc/gdbstub.c

   1 /*
   2  * PowerPC gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/gdbstub.h"
  23 #include "gdbstub/helpers.h"
  24 #include "internal.h"
  25
  26 static int ppc_gdb_register_len_apple(int n)
  27 {
  28     switch (n) {
  29     case 0 ... 31:
  30         /* gprs */
  31         return 8;
  32     case 32 ... 63:
  33         /* fprs */
  34         return 8;
  35     case 64 ... 95:
  36         return 16;
  37     case 64 + 32: /* nip */
  38     case 65 + 32: /* msr */
  39     case 67 + 32: /* lr */
  40     case 68 + 32: /* ctr */
  41     case 70 + 32: /* fpscr */
  42         return 8;
  43     case 66 + 32: /* cr */
  44     case 69 + 32: /* xer */
  45         return 4;
  46     default:
  47         return 0;
  48     }
  49 }
  50
  51 static int ppc_gdb_register_len(int n)
  52 {
  53     switch (n) {
  54     case 0 ... 31:
  55         /* gprs */
  56         return sizeof(target_ulong);
  57     case 66:
  58         /* cr */
  59     case 69:
  60         /* xer */
  61         return 4;
  62     case 64:
  63         /* nip */
  64     case 65:
  65         /* msr */
  66     case 67:
  67         /* lr */
  68     case 68:
  69         /* ctr */
  70         return sizeof(target_ulong);
  71     default:
  72         return 0;
  73     }
  74 }
  75
  76 /*
  77  * We need to present the registers to gdb in the "current" memory
  78  * ordering.  For user-only mode we get this for free;
  79  * TARGET_BIG_ENDIAN is set to the proper ordering for the
  80  * binary, and cannot be changed.  For system mode,
  81  * TARGET_BIG_ENDIAN is always set, and we must check the current
  82  * mode of the chip to see if we're running in little-endian.
  83  */
  84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
  85 {
  86 #ifndef CONFIG_USER_ONLY
  87     if (!FIELD_EX64(env->msr, MSR, LE)) {
  88         /* do nothing */
  89     } else if (len == 4) {
  90         bswap32s((uint32_t *)mem_buf);
  91     } else if (len == 8) {
  92         bswap64s((uint64_t *)mem_buf);
  93     } else if (len == 16) {
  94         bswap128s((Int128 *)mem_buf);
  95     } else {
  96         g_assert_not_reached();
  97     }
  98 #endif
  99 }
 100
 101 /*
 102  * Old gdb always expects FP registers.  Newer (xml-aware) gdb only
 103  * expects whatever the target description contains.  Due to a
 104  * historical mishap the FP registers appear in between core integer
 105  * regs and PC, MSR, CR, and so forth.  We hack round this by giving
 106  * the FP regs zero size when talking to a newer gdb.
 107  */
 108
 109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
 110 {
 111     PowerPCCPU *cpu = POWERPC_CPU(cs);
 112     CPUPPCState *env = &cpu->env;
 113     uint8_t *mem_buf;
 114     int r = ppc_gdb_register_len(n);
 115
 116     if (!r) {
 117         return r;
 118     }
 119
 120     if (n < 32) {
 121         /* gprs */
 122         gdb_get_regl(buf, env->gpr[n]);
 123     } else {
 124         switch (n) {
 125         case 64:
 126             gdb_get_regl(buf, env->nip);
 127             break;
 128         case 65:
 129             gdb_get_regl(buf, env->msr);
 130             break;
 131         case 66:
 132             {
 133                 uint32_t cr = ppc_get_cr(env);
 134                 gdb_get_reg32(buf, cr);
 135                 break;
 136             }
 137         case 67:
 138             gdb_get_regl(buf, env->lr);
 139             break;
 140         case 68:
 141             gdb_get_regl(buf, env->ctr);
 142             break;
 143         case 69:
 144             gdb_get_reg32(buf, cpu_read_xer(env));
 145             break;
 146         }
 147     }
 148     mem_buf = buf->data + buf->len - r;
 149     ppc_maybe_bswap_register(env, mem_buf, r);
 150     return r;
 151 }
 152
 153 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
 154 {
 155     PowerPCCPU *cpu = POWERPC_CPU(cs);
 156     CPUPPCState *env = &cpu->env;
 157     uint8_t *mem_buf;
 158     int r = ppc_gdb_register_len_apple(n);
 159
 160     if (!r) {
 161         return r;
 162     }
 163
 164     if (n < 32) {
 165         /* gprs */
 166         gdb_get_reg64(buf, env->gpr[n]);
 167     } else if (n < 64) {
 168         /* fprs */
 169         gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
 170     } else if (n < 96) {
 171         /* Altivec */
 172         gdb_get_reg64(buf, n - 64);
 173         gdb_get_reg64(buf, 0);
 174     } else {
 175         switch (n) {
 176         case 64 + 32:
 177             gdb_get_reg64(buf, env->nip);
 178             break;
 179         case 65 + 32:
 180             gdb_get_reg64(buf, env->msr);
 181             break;
 182         case 66 + 32:
 183             {
 184                 uint32_t cr = ppc_get_cr(env);
 185                 gdb_get_reg32(buf, cr);
 186                 break;
 187             }
 188         case 67 + 32:
 189             gdb_get_reg64(buf, env->lr);
 190             break;
 191         case 68 + 32:
 192             gdb_get_reg64(buf, env->ctr);
 193             break;
 194         case 69 + 32:
 195             gdb_get_reg32(buf, cpu_read_xer(env));
 196             break;
 197         case 70 + 32:
 198             gdb_get_reg64(buf, env->fpscr);
 199             break;
 200         }
 201     }
 202     mem_buf = buf->data + buf->len - r;
 203     ppc_maybe_bswap_register(env, mem_buf, r);
 204     return r;
 205 }
 206
 207 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 208 {
 209     PowerPCCPU *cpu = POWERPC_CPU(cs);
 210     CPUPPCState *env = &cpu->env;
 211     int r = ppc_gdb_register_len(n);
 212
 213     if (!r) {
 214         return r;
 215     }
 216     ppc_maybe_bswap_register(env, mem_buf, r);
 217     if (n < 32) {
 218         /* gprs */
 219         env->gpr[n] = ldtul_p(mem_buf);
 220     } else if (n < 64) {
 221         /* fprs */
 222         *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
 223     } else {
 224         switch (n) {
 225         case 64:
 226             env->nip = ldtul_p(mem_buf);
 227             break;
 228         case 65:
 229             ppc_store_msr(env, ldtul_p(mem_buf));
 230             break;
 231         case 66:
 232             {
 233                 uint32_t cr = ldl_p(mem_buf);
 234                 ppc_set_cr(env, cr);
 235                 break;
 236             }
 237         case 67:
 238             env->lr = ldtul_p(mem_buf);
 239             break;
 240         case 68:
 241             env->ctr = ldtul_p(mem_buf);
 242             break;
 243         case 69:
 244             cpu_write_xer(env, ldl_p(mem_buf));
 245             break;
 246         case 70:
 247             /* fpscr */
 248             ppc_store_fpscr(env, ldtul_p(mem_buf));
 249             break;
 250         }
 251     }
 252     return r;
 253 }
 254 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
 255 {
 256     PowerPCCPU *cpu = POWERPC_CPU(cs);
 257     CPUPPCState *env = &cpu->env;
 258     int r = ppc_gdb_register_len_apple(n);
 259
 260     if (!r) {
 261         return r;
 262     }
 263     ppc_maybe_bswap_register(env, mem_buf, r);
 264     if (n < 32) {
 265         /* gprs */
 266         env->gpr[n] = ldq_p(mem_buf);
 267     } else if (n < 64) {
 268         /* fprs */
 269         *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
 270     } else {
 271         switch (n) {
 272         case 64 + 32:
 273             env->nip = ldq_p(mem_buf);
 274             break;
 275         case 65 + 32:
 276             ppc_store_msr(env, ldq_p(mem_buf));
 277             break;
 278         case 66 + 32:
 279             {
 280                 uint32_t cr = ldl_p(mem_buf);
 281                 ppc_set_cr(env, cr);
 282                 break;
 283             }
 284         case 67 + 32:
 285             env->lr = ldq_p(mem_buf);
 286             break;
 287         case 68 + 32:
 288             env->ctr = ldq_p(mem_buf);
 289             break;
 290         case 69 + 32:
 291             cpu_write_xer(env, ldl_p(mem_buf));
 292             break;
 293         case 70 + 32:
 294             /* fpscr */
 295             ppc_store_fpscr(env, ldq_p(mem_buf));
 296             break;
 297         }
 298     }
 299     return r;
 300 }
 301
 302 #ifndef CONFIG_USER_ONLY
 303 static void gdb_gen_spr_feature(CPUState *cs)
 304 {
 305     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
 306     PowerPCCPU *cpu = POWERPC_CPU(cs);
 307     CPUPPCState *env = &cpu->env;
 308     GDBFeatureBuilder builder;
 309     unsigned int num_regs = 0;
 310     int i;
 311
 312     if (pcc->gdb_spr.xml) {
 313         return;
 314     }
 315
 316     gdb_feature_builder_init(&builder, &pcc->gdb_spr,
 317                              "org.qemu.power.spr", "power-spr.xml",
 318                              cs->gdb_num_regs);
 319
 320     for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
 321         ppc_spr_t *spr = &env->spr_cb[i];
 322
 323         if (!spr->name) {
 324             continue;
 325         }
 326
 327         /*
 328          * GDB identifies registers based on the order they are
 329          * presented in the XML. These ids will not match QEMU's
 330          * representation (which follows the PowerISA).
 331          *
 332          * Store the position of the current register description so
 333          * we can make the correspondence later.
 334          */
 335         spr->gdb_id = num_regs;
 336         num_regs++;
 337
 338         gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
 339                                        TARGET_LONG_BITS, num_regs,
 340                                        "int", "spr");
 341     }
 342
 343     gdb_feature_builder_end(&builder);
 344 }
 345 #endif
 346
 347 #if !defined(CONFIG_USER_ONLY)
 348 static int gdb_find_spr_idx(CPUPPCState *env, int n)
 349 {
 350     int i;
 351
 352     for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
 353         ppc_spr_t *spr = &env->spr_cb[i];
 354
 355         if (spr->name && spr->gdb_id == n) {
 356             return i;
 357         }
 358     }
 359     return -1;
 360 }
 361
 362 static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n)
 363 {
 364     PowerPCCPU *cpu = POWERPC_CPU(cs);
 365     CPUPPCState *env = &cpu->env;
 366     int reg;
 367     int len;
 368
 369     reg = gdb_find_spr_idx(env, n);
 370     if (reg < 0) {
 371         return 0;
 372     }
 373
 374     len = TARGET_LONG_SIZE;
 375
 376     /* Handle those SPRs that are not part of the env->spr[] array */
 377     target_ulong val;
 378     switch (reg) {
 379 #if defined(TARGET_PPC64)
 380     case SPR_CFAR:
 381         val = env->cfar;
 382         break;
 383 #endif
 384     case SPR_HDEC:
 385         val = cpu_ppc_load_hdecr(env);
 386         break;
 387     case SPR_TBL:
 388         val = cpu_ppc_load_tbl(env);
 389         break;
 390     case SPR_TBU:
 391         val = cpu_ppc_load_tbu(env);
 392         break;
 393     case SPR_DECR:
 394         val = cpu_ppc_load_decr(env);
 395         break;
 396     default:
 397         val = env->spr[reg];
 398     }
 399     gdb_get_regl(buf, val);
 400
 401     ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
 402     return len;
 403 }
 404
 405 static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n)
 406 {
 407     PowerPCCPU *cpu = POWERPC_CPU(cs);
 408     CPUPPCState *env = &cpu->env;
 409     int reg;
 410     int len;
 411
 412     reg = gdb_find_spr_idx(env, n);
 413     if (reg < 0) {
 414         return 0;
 415     }
 416
 417     len = TARGET_LONG_SIZE;
 418     ppc_maybe_bswap_register(env, mem_buf, len);
 419
 420     /* Handle those SPRs that are not part of the env->spr[] array */
 421     target_ulong val = ldn_p(mem_buf, len);
 422     switch (reg) {
 423 #if defined(TARGET_PPC64)
 424     case SPR_CFAR:
 425         env->cfar = val;
 426         break;
 427 #endif
 428     default:
 429         env->spr[reg] = val;
 430     }
 431
 432     return len;
 433 }
 434 #endif
 435
 436 static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n)
 437 {
 438     PowerPCCPU *cpu = POWERPC_CPU(cs);
 439     CPUPPCState *env = &cpu->env;
 440     uint8_t *mem_buf;
 441     if (n < 32) {
 442         gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
 443         mem_buf = gdb_get_reg_ptr(buf, 8);
 444         ppc_maybe_bswap_register(env, mem_buf, 8);
 445         return 8;
 446     }
 447     if (n == 32) {
 448         gdb_get_reg32(buf, env->fpscr);
 449         mem_buf = gdb_get_reg_ptr(buf, 4);
 450         ppc_maybe_bswap_register(env, mem_buf, 4);
 451         return 4;
 452     }
 453     return 0;
 454 }
 455
 456 static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n)
 457 {
 458     PowerPCCPU *cpu = POWERPC_CPU(cs);
 459     CPUPPCState *env = &cpu->env;
 460
 461     if (n < 32) {
 462         ppc_maybe_bswap_register(env, mem_buf, 8);
 463         *cpu_fpr_ptr(env, n) = ldq_p(mem_buf);
 464         return 8;
 465     }
 466     if (n == 32) {
 467         ppc_maybe_bswap_register(env, mem_buf, 4);
 468         ppc_store_fpscr(env, ldl_p(mem_buf));
 469         return 4;
 470     }
 471     return 0;
 472 }
 473
 474 static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n)
 475 {
 476     PowerPCCPU *cpu = POWERPC_CPU(cs);
 477     CPUPPCState *env = &cpu->env;
 478     uint8_t *mem_buf;
 479
 480     if (n < 32) {
 481         ppc_avr_t *avr = cpu_avr_ptr(env, n);
 482         gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1));
 483         mem_buf = gdb_get_reg_ptr(buf, 16);
 484         ppc_maybe_bswap_register(env, mem_buf, 16);
 485         return 16;
 486     }
 487     if (n == 32) {
 488         gdb_get_reg32(buf, ppc_get_vscr(env));
 489         mem_buf = gdb_get_reg_ptr(buf, 4);
 490         ppc_maybe_bswap_register(env, mem_buf, 4);
 491         return 4;
 492     }
 493     if (n == 33) {
 494         gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
 495         mem_buf = gdb_get_reg_ptr(buf, 4);
 496         ppc_maybe_bswap_register(env, mem_buf, 4);
 497         return 4;
 498     }
 499     return 0;
 500 }
 501
 502 static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n)
 503 {
 504     PowerPCCPU *cpu = POWERPC_CPU(cs);
 505     CPUPPCState *env = &cpu->env;
 506
 507     if (n < 32) {
 508         ppc_avr_t *avr = cpu_avr_ptr(env, n);
 509         ppc_maybe_bswap_register(env, mem_buf, 16);
 510         avr->VsrD(0) = ldq_p(mem_buf);
 511         avr->VsrD(1) = ldq_p(mem_buf + 8);
 512         return 16;
 513     }
 514     if (n == 32) {
 515         ppc_maybe_bswap_register(env, mem_buf, 4);
 516         ppc_store_vscr(env, ldl_p(mem_buf));
 517         return 4;
 518     }
 519     if (n == 33) {
 520         ppc_maybe_bswap_register(env, mem_buf, 4);
 521         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
 522         return 4;
 523     }
 524     return 0;
 525 }
 526
 527 static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n)
 528 {
 529     PowerPCCPU *cpu = POWERPC_CPU(cs);
 530     CPUPPCState *env = &cpu->env;
 531
 532     if (n < 32) {
 533 #if defined(TARGET_PPC64)
 534         gdb_get_reg32(buf, env->gpr[n] >> 32);
 535         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
 536 #else
 537         gdb_get_reg32(buf, env->gprh[n]);
 538 #endif
 539         return 4;
 540     }
 541     if (n == 32) {
 542         gdb_get_reg64(buf, env->spe_acc);
 543         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
 544         return 8;
 545     }
 546     if (n == 33) {
 547         gdb_get_reg32(buf, env->spe_fscr);
 548         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
 549         return 4;
 550     }
 551     return 0;
 552 }
 553
 554 static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n)
 555 {
 556     PowerPCCPU *cpu = POWERPC_CPU(cs);
 557     CPUPPCState *env = &cpu->env;
 558
 559     if (n < 32) {
 560 #if defined(TARGET_PPC64)
 561         target_ulong lo = (uint32_t)env->gpr[n];
 562         target_ulong hi;
 563
 564         ppc_maybe_bswap_register(env, mem_buf, 4);
 565
 566         hi = (target_ulong)ldl_p(mem_buf) << 32;
 567         env->gpr[n] = lo | hi;
 568 #else
 569         env->gprh[n] = ldl_p(mem_buf);
 570 #endif
 571         return 4;
 572     }
 573     if (n == 32) {
 574         ppc_maybe_bswap_register(env, mem_buf, 8);
 575         env->spe_acc = ldq_p(mem_buf);
 576         return 8;
 577     }
 578     if (n == 33) {
 579         ppc_maybe_bswap_register(env, mem_buf, 4);
 580         env->spe_fscr = ldl_p(mem_buf);
 581         return 4;
 582     }
 583     return 0;
 584 }
 585
 586 static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n)
 587 {
 588     PowerPCCPU *cpu = POWERPC_CPU(cs);
 589     CPUPPCState *env = &cpu->env;
 590
 591     if (n < 32) {
 592         gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
 593         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
 594         return 8;
 595     }
 596     return 0;
 597 }
 598
 599 static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n)
 600 {
 601     PowerPCCPU *cpu = POWERPC_CPU(cs);
 602     CPUPPCState *env = &cpu->env;
 603
 604     if (n < 32) {
 605         ppc_maybe_bswap_register(env, mem_buf, 8);
 606         *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
 607         return 8;
 608     }
 609     return 0;
 610 }
 611
 612 const gchar *ppc_gdb_arch_name(CPUState *cs)
 613 {
 614 #if defined(TARGET_PPC64)
 615     return "powerpc:common64";
 616 #else
 617     return "powerpc:common";
 618 #endif
 619 }
 620
 621 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)
 622 {
 623     if (pcc->insns_flags & PPC_FLOAT) {
 624         gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
 625                                  gdb_find_static_feature("power-fpu.xml"), 0);
 626     }
 627     if (pcc->insns_flags & PPC_ALTIVEC) {
 628         gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
 629                                  gdb_find_static_feature("power-altivec.xml"),
 630                                  0);
 631     }
 632     if (pcc->insns_flags & PPC_SPE) {
 633         gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
 634                                  gdb_find_static_feature("power-spe.xml"), 0);
 635     }
 636     if (pcc->insns_flags2 & PPC2_VSX) {
 637         gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
 638                                  gdb_find_static_feature("power-vsx.xml"), 0);
 639     }
 640 #ifndef CONFIG_USER_ONLY
 641     gdb_gen_spr_feature(cs);
 642     gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
 643                              &pcc->gdb_spr, 0);
 644 #endif
 645 }