2 * Core code for QEMU igb emulation
5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
7 * Copyright (c) 2020-2023 Red Hat, Inc.
8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
9 * Developed by Daynix Computing LTD (http://www.daynix.com)
12 * Akihiko Odaki <akihiko.odaki@daynix.com>
13 * Gal Hammmer <gal.hammer@sap.com>
14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
15 * Dmitry Fleytman <dmitry@daynix.com>
16 * Leonid Bloch <leonid@daynix.com>
17 * Yan Vugenfirer <yan@daynix.com>
19 * Based on work done by:
20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
21 * Copyright (c) 2008 Qumranet
22 * Based on work done by:
23 * Copyright (c) 2007 Dan Aloni
24 * Copyright (c) 2004 Antony T Curtis
26 * This library is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU Lesser General Public
28 * License as published by the Free Software Foundation; either
29 * version 2.1 of the License, or (at your option) any later version.
31 * This library is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34 * Lesser General Public License for more details.
36 * You should have received a copy of the GNU Lesser General Public
37 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
40 #include "qemu/osdep.h"
44 #include "hw/net/mii.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "sysemu/runstate.h"
49 #include "net_tx_pkt.h"
50 #include "net_rx_pkt.h"
52 #include "igb_common.h"
53 #include "e1000x_common.h"
58 #define E1000E_MAX_TX_FRAGS (64)
60 union e1000_rx_desc_union
{
61 struct e1000_rx_desc legacy
;
62 union e1000_adv_rx_desc adv
;
65 typedef struct IGBTxPktVmdqCallbackContext
{
68 } IGBTxPktVmdqCallbackContext
;
71 igb_receive_internal(IGBCore
*core
, const struct iovec
*iov
, int iovcnt
,
72 bool has_vnet
, bool *external_tx
);
75 igb_set_interrupt_cause(IGBCore
*core
, uint32_t val
);
77 static void igb_update_interrupt_state(IGBCore
*core
);
78 static void igb_reset(IGBCore
*core
, bool sw
);
81 igb_raise_legacy_irq(IGBCore
*core
)
83 trace_e1000e_irq_legacy_notify(true);
84 e1000x_inc_reg_if_not_full(core
->mac
, IAC
);
85 pci_set_irq(core
->owner
, 1);
89 igb_lower_legacy_irq(IGBCore
*core
)
91 trace_e1000e_irq_legacy_notify(false);
92 pci_set_irq(core
->owner
, 0);
95 static void igb_msix_notify(IGBCore
*core
, unsigned int vector
)
97 PCIDevice
*dev
= core
->owner
;
100 vfn
= 8 - (vector
+ 2) / IGBVF_MSIX_VEC_NUM
;
101 if (vfn
< pcie_sriov_num_vfs(core
->owner
)) {
102 dev
= pcie_sriov_get_vf_at_index(core
->owner
, vfn
);
104 vector
= (vector
+ 2) % IGBVF_MSIX_VEC_NUM
;
105 } else if (vector
>= IGB_MSIX_VEC_NUM
) {
106 qemu_log_mask(LOG_GUEST_ERROR
,
107 "igb: Tried to use vector unavailable for PF");
111 msix_notify(dev
, vector
);
115 igb_intrmgr_rearm_timer(IGBIntrDelayTimer
*timer
)
117 int64_t delay_ns
= (int64_t) timer
->core
->mac
[timer
->delay_reg
] *
118 timer
->delay_resolution_ns
;
120 trace_e1000e_irq_rearm_timer(timer
->delay_reg
<< 2, delay_ns
);
122 timer_mod(timer
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + delay_ns
);
124 timer
->running
= true;
128 igb_intmgr_timer_resume(IGBIntrDelayTimer
*timer
)
130 if (timer
->running
) {
131 igb_intrmgr_rearm_timer(timer
);
136 igb_intmgr_timer_pause(IGBIntrDelayTimer
*timer
)
138 if (timer
->running
) {
139 timer_del(timer
->timer
);
144 igb_intrmgr_on_msix_throttling_timer(void *opaque
)
146 IGBIntrDelayTimer
*timer
= opaque
;
147 int idx
= timer
- &timer
->core
->eitr
[0];
149 timer
->running
= false;
151 trace_e1000e_irq_msix_notify_postponed_vec(idx
);
152 igb_msix_notify(timer
->core
, idx
);
156 igb_intrmgr_initialize_all_timers(IGBCore
*core
, bool create
)
160 for (i
= 0; i
< IGB_INTR_NUM
; i
++) {
161 core
->eitr
[i
].core
= core
;
162 core
->eitr
[i
].delay_reg
= EITR0
+ i
;
163 core
->eitr
[i
].delay_resolution_ns
= E1000_INTR_DELAY_NS_RES
;
170 for (i
= 0; i
< IGB_INTR_NUM
; i
++) {
171 core
->eitr
[i
].timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
172 igb_intrmgr_on_msix_throttling_timer
,
178 igb_intrmgr_resume(IGBCore
*core
)
182 for (i
= 0; i
< IGB_INTR_NUM
; i
++) {
183 igb_intmgr_timer_resume(&core
->eitr
[i
]);
188 igb_intrmgr_pause(IGBCore
*core
)
192 for (i
= 0; i
< IGB_INTR_NUM
; i
++) {
193 igb_intmgr_timer_pause(&core
->eitr
[i
]);
198 igb_intrmgr_reset(IGBCore
*core
)
202 for (i
= 0; i
< IGB_INTR_NUM
; i
++) {
203 if (core
->eitr
[i
].running
) {
204 timer_del(core
->eitr
[i
].timer
);
205 igb_intrmgr_on_msix_throttling_timer(&core
->eitr
[i
]);
211 igb_intrmgr_pci_unint(IGBCore
*core
)
215 for (i
= 0; i
< IGB_INTR_NUM
; i
++) {
216 timer_free(core
->eitr
[i
].timer
);
221 igb_intrmgr_pci_realize(IGBCore
*core
)
223 igb_intrmgr_initialize_all_timers(core
, true);
227 igb_rx_csum_enabled(IGBCore
*core
)
229 return (core
->mac
[RXCSUM
] & E1000_RXCSUM_PCSD
) ? false : true;
233 igb_rx_use_legacy_descriptor(IGBCore
*core
)
236 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx
243 igb_rss_enabled(IGBCore
*core
)
245 return (core
->mac
[MRQC
] & 3) == E1000_MRQC_ENABLE_RSS_MQ
&&
246 !igb_rx_csum_enabled(core
) &&
247 !igb_rx_use_legacy_descriptor(core
);
250 typedef struct E1000E_RSSInfo_st
{
258 igb_rss_get_hash_type(IGBCore
*core
, struct NetRxPkt
*pkt
)
261 EthL4HdrProto l4hdr_proto
;
263 assert(igb_rss_enabled(core
));
265 net_rx_pkt_get_protocols(pkt
, &hasip4
, &hasip6
, &l4hdr_proto
);
268 trace_e1000e_rx_rss_ip4(l4hdr_proto
, core
->mac
[MRQC
],
269 E1000_MRQC_EN_TCPIPV4(core
->mac
[MRQC
]),
270 E1000_MRQC_EN_IPV4(core
->mac
[MRQC
]));
272 if (l4hdr_proto
== ETH_L4_HDR_PROTO_TCP
&&
273 E1000_MRQC_EN_TCPIPV4(core
->mac
[MRQC
])) {
274 return E1000_MRQ_RSS_TYPE_IPV4TCP
;
277 if (E1000_MRQC_EN_IPV4(core
->mac
[MRQC
])) {
278 return E1000_MRQ_RSS_TYPE_IPV4
;
281 eth_ip6_hdr_info
*ip6info
= net_rx_pkt_get_ip6_info(pkt
);
283 bool ex_dis
= core
->mac
[RFCTL
] & E1000_RFCTL_IPV6_EX_DIS
;
284 bool new_ex_dis
= core
->mac
[RFCTL
] & E1000_RFCTL_NEW_IPV6_EXT_DIS
;
287 * Following two traces must not be combined because resulting
288 * event will have 11 arguments totally and some trace backends
289 * (at least "ust") have limitation of maximum 10 arguments per
290 * event. Events with more arguments fail to compile for
291 * backends like these.
293 trace_e1000e_rx_rss_ip6_rfctl(core
->mac
[RFCTL
]);
294 trace_e1000e_rx_rss_ip6(ex_dis
, new_ex_dis
, l4hdr_proto
,
295 ip6info
->has_ext_hdrs
,
296 ip6info
->rss_ex_dst_valid
,
297 ip6info
->rss_ex_src_valid
,
299 E1000_MRQC_EN_TCPIPV6(core
->mac
[MRQC
]),
300 E1000_MRQC_EN_IPV6EX(core
->mac
[MRQC
]),
301 E1000_MRQC_EN_IPV6(core
->mac
[MRQC
]));
303 if ((!ex_dis
|| !ip6info
->has_ext_hdrs
) &&
304 (!new_ex_dis
|| !(ip6info
->rss_ex_dst_valid
||
305 ip6info
->rss_ex_src_valid
))) {
307 if (l4hdr_proto
== ETH_L4_HDR_PROTO_TCP
&&
308 E1000_MRQC_EN_TCPIPV6(core
->mac
[MRQC
])) {
309 return E1000_MRQ_RSS_TYPE_IPV6TCP
;
312 if (E1000_MRQC_EN_IPV6EX(core
->mac
[MRQC
])) {
313 return E1000_MRQ_RSS_TYPE_IPV6EX
;
318 if (E1000_MRQC_EN_IPV6(core
->mac
[MRQC
])) {
319 return E1000_MRQ_RSS_TYPE_IPV6
;
324 return E1000_MRQ_RSS_TYPE_NONE
;
328 igb_rss_calc_hash(IGBCore
*core
, struct NetRxPkt
*pkt
, E1000E_RSSInfo
*info
)
330 NetRxPktRssType type
;
332 assert(igb_rss_enabled(core
));
334 switch (info
->type
) {
335 case E1000_MRQ_RSS_TYPE_IPV4
:
336 type
= NetPktRssIpV4
;
338 case E1000_MRQ_RSS_TYPE_IPV4TCP
:
339 type
= NetPktRssIpV4Tcp
;
341 case E1000_MRQ_RSS_TYPE_IPV6TCP
:
342 type
= NetPktRssIpV6TcpEx
;
344 case E1000_MRQ_RSS_TYPE_IPV6
:
345 type
= NetPktRssIpV6
;
347 case E1000_MRQ_RSS_TYPE_IPV6EX
:
348 type
= NetPktRssIpV6Ex
;
355 return net_rx_pkt_calc_rss_hash(pkt
, type
, (uint8_t *) &core
->mac
[RSSRK
]);
359 igb_rss_parse_packet(IGBCore
*core
, struct NetRxPkt
*pkt
, bool tx
,
360 E1000E_RSSInfo
*info
)
362 trace_e1000e_rx_rss_started();
364 if (tx
|| !igb_rss_enabled(core
)) {
365 info
->enabled
= false;
369 trace_e1000e_rx_rss_disabled();
373 info
->enabled
= true;
375 info
->type
= igb_rss_get_hash_type(core
, pkt
);
377 trace_e1000e_rx_rss_type(info
->type
);
379 if (info
->type
== E1000_MRQ_RSS_TYPE_NONE
) {
385 info
->hash
= igb_rss_calc_hash(core
, pkt
, info
);
386 info
->queue
= E1000_RSS_QUEUE(&core
->mac
[RETA
], info
->hash
);
390 igb_tx_insert_vlan(IGBCore
*core
, uint16_t qn
, struct igb_tx
*tx
,
391 uint16_t vlan
, bool insert_vlan
)
393 if (core
->mac
[MRQC
] & 1) {
394 uint16_t pool
= qn
% IGB_NUM_VM_POOLS
;
396 if (core
->mac
[VMVIR0
+ pool
] & E1000_VMVIR_VLANA_DEFAULT
) {
397 /* always insert default VLAN */
399 vlan
= core
->mac
[VMVIR0
+ pool
] & 0xffff;
400 } else if (core
->mac
[VMVIR0
+ pool
] & E1000_VMVIR_VLANA_NEVER
) {
406 net_tx_pkt_setup_vlan_header_ex(tx
->tx_pkt
, vlan
,
407 core
->mac
[VET
] & 0xffff);
412 igb_setup_tx_offloads(IGBCore
*core
, struct igb_tx
*tx
)
414 if (tx
->first_cmd_type_len
& E1000_ADVTXD_DCMD_TSE
) {
415 uint32_t idx
= (tx
->first_olinfo_status
>> 4) & 1;
416 uint32_t mss
= tx
->ctx
[idx
].mss_l4len_idx
>> 16;
417 if (!net_tx_pkt_build_vheader(tx
->tx_pkt
, true, true, mss
)) {
421 net_tx_pkt_update_ip_checksums(tx
->tx_pkt
);
422 e1000x_inc_reg_if_not_full(core
->mac
, TSCTC
);
426 if (tx
->first_olinfo_status
& E1000_ADVTXD_POTS_TXSM
) {
427 if (!net_tx_pkt_build_vheader(tx
->tx_pkt
, false, true, 0)) {
432 if (tx
->first_olinfo_status
& E1000_ADVTXD_POTS_IXSM
) {
433 net_tx_pkt_update_ip_hdr_checksum(tx
->tx_pkt
);
439 static void igb_tx_pkt_mac_callback(void *core
,
440 const struct iovec
*iov
,
442 const struct iovec
*virt_iov
,
445 igb_receive_internal(core
, virt_iov
, virt_iovcnt
, true, NULL
);
448 static void igb_tx_pkt_vmdq_callback(void *opaque
,
449 const struct iovec
*iov
,
451 const struct iovec
*virt_iov
,
454 IGBTxPktVmdqCallbackContext
*context
= opaque
;
457 igb_receive_internal(context
->core
, virt_iov
, virt_iovcnt
, true,
461 if (context
->core
->has_vnet
) {
462 qemu_sendv_packet(context
->nc
, virt_iov
, virt_iovcnt
);
464 qemu_sendv_packet(context
->nc
, iov
, iovcnt
);
469 /* TX Packets Switching (7.10.3.6) */
470 static bool igb_tx_pkt_switch(IGBCore
*core
, struct igb_tx
*tx
,
473 IGBTxPktVmdqCallbackContext context
;
475 /* TX switching is only used to serve VM to VM traffic. */
476 if (!(core
->mac
[MRQC
] & 1)) {
480 /* TX switching requires DTXSWC.Loopback_en bit enabled. */
481 if (!(core
->mac
[DTXSWC
] & E1000_DTXSWC_VMDQ_LOOPBACK_EN
)) {
488 return net_tx_pkt_send_custom(tx
->tx_pkt
, false,
489 igb_tx_pkt_vmdq_callback
, &context
);
492 return net_tx_pkt_send(tx
->tx_pkt
, nc
);
496 igb_tx_pkt_send(IGBCore
*core
, struct igb_tx
*tx
, int queue_index
)
498 int target_queue
= MIN(core
->max_queue_num
, queue_index
);
499 NetClientState
*queue
= qemu_get_subqueue(core
->owner_nic
, target_queue
);
501 if (!igb_setup_tx_offloads(core
, tx
)) {
505 net_tx_pkt_dump(tx
->tx_pkt
);
507 if ((core
->phy
[MII_BMCR
] & MII_BMCR_LOOPBACK
) ||
508 ((core
->mac
[RCTL
] & E1000_RCTL_LBM_MAC
) == E1000_RCTL_LBM_MAC
)) {
509 return net_tx_pkt_send_custom(tx
->tx_pkt
, false,
510 igb_tx_pkt_mac_callback
, core
);
512 return igb_tx_pkt_switch(core
, tx
, queue
);
517 igb_on_tx_done_update_stats(IGBCore
*core
, struct NetTxPkt
*tx_pkt
, int qn
)
519 static const int PTCregs
[6] = { PTC64
, PTC127
, PTC255
, PTC511
,
522 size_t tot_len
= net_tx_pkt_get_total_len(tx_pkt
) + 4;
524 e1000x_increase_size_stats(core
->mac
, PTCregs
, tot_len
);
525 e1000x_inc_reg_if_not_full(core
->mac
, TPT
);
526 e1000x_grow_8reg_if_not_full(core
->mac
, TOTL
, tot_len
);
528 switch (net_tx_pkt_get_packet_type(tx_pkt
)) {
530 e1000x_inc_reg_if_not_full(core
->mac
, BPTC
);
533 e1000x_inc_reg_if_not_full(core
->mac
, MPTC
);
538 g_assert_not_reached();
541 e1000x_inc_reg_if_not_full(core
->mac
, GPTC
);
542 e1000x_grow_8reg_if_not_full(core
->mac
, GOTCL
, tot_len
);
544 if (core
->mac
[MRQC
] & 1) {
545 uint16_t pool
= qn
% IGB_NUM_VM_POOLS
;
547 core
->mac
[PVFGOTC0
+ (pool
* 64)] += tot_len
;
548 core
->mac
[PVFGPTC0
+ (pool
* 64)]++;
553 igb_process_tx_desc(IGBCore
*core
,
556 union e1000_adv_tx_desc
*tx_desc
,
559 struct e1000_adv_tx_context_desc
*tx_ctx_desc
;
560 uint32_t cmd_type_len
;
562 uint64_t buffer_addr
;
565 cmd_type_len
= le32_to_cpu(tx_desc
->read
.cmd_type_len
);
567 if (cmd_type_len
& E1000_ADVTXD_DCMD_DEXT
) {
568 if ((cmd_type_len
& E1000_ADVTXD_DTYP_DATA
) ==
569 E1000_ADVTXD_DTYP_DATA
) {
570 /* advanced transmit data descriptor */
572 tx
->first_cmd_type_len
= cmd_type_len
;
573 tx
->first_olinfo_status
= le32_to_cpu(tx_desc
->read
.olinfo_status
);
576 } else if ((cmd_type_len
& E1000_ADVTXD_DTYP_CTXT
) ==
577 E1000_ADVTXD_DTYP_CTXT
) {
578 /* advanced transmit context descriptor */
579 tx_ctx_desc
= (struct e1000_adv_tx_context_desc
*)tx_desc
;
580 idx
= (le32_to_cpu(tx_ctx_desc
->mss_l4len_idx
) >> 4) & 1;
581 tx
->ctx
[idx
].vlan_macip_lens
= le32_to_cpu(tx_ctx_desc
->vlan_macip_lens
);
582 tx
->ctx
[idx
].seqnum_seed
= le32_to_cpu(tx_ctx_desc
->seqnum_seed
);
583 tx
->ctx
[idx
].type_tucmd_mlhl
= le32_to_cpu(tx_ctx_desc
->type_tucmd_mlhl
);
584 tx
->ctx
[idx
].mss_l4len_idx
= le32_to_cpu(tx_ctx_desc
->mss_l4len_idx
);
587 /* unknown descriptor type */
591 /* legacy descriptor */
593 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */
596 buffer_addr
= le64_to_cpu(tx_desc
->read
.buffer_addr
);
597 length
= cmd_type_len
& 0xFFFF;
600 if (!net_tx_pkt_add_raw_fragment_pci(tx
->tx_pkt
, dev
,
601 buffer_addr
, length
)) {
606 if (cmd_type_len
& E1000_TXD_CMD_EOP
) {
607 if (!tx
->skip_cp
&& net_tx_pkt_parse(tx
->tx_pkt
)) {
608 idx
= (tx
->first_olinfo_status
>> 4) & 1;
609 igb_tx_insert_vlan(core
, queue_index
, tx
,
610 tx
->ctx
[idx
].vlan_macip_lens
>> 16,
611 !!(cmd_type_len
& E1000_TXD_CMD_VLE
));
613 if (igb_tx_pkt_send(core
, tx
, queue_index
)) {
614 igb_on_tx_done_update_stats(core
, tx
->tx_pkt
, queue_index
);
620 net_tx_pkt_reset(tx
->tx_pkt
, net_tx_pkt_unmap_frag_pci
, dev
);
624 static uint32_t igb_tx_wb_eic(IGBCore
*core
, int queue_idx
)
628 n
= igb_ivar_entry_tx(queue_idx
);
629 ent
= (core
->mac
[IVAR0
+ n
/ 4] >> (8 * (n
% 4))) & 0xff;
631 return (ent
& E1000_IVAR_VALID
) ? BIT(ent
& 0x1f) : 0;
634 static uint32_t igb_rx_wb_eic(IGBCore
*core
, int queue_idx
)
638 n
= igb_ivar_entry_rx(queue_idx
);
639 ent
= (core
->mac
[IVAR0
+ n
/ 4] >> (8 * (n
% 4))) & 0xff;
641 return (ent
& E1000_IVAR_VALID
) ? BIT(ent
& 0x1f) : 0;
644 typedef struct E1000E_RingInfo_st
{
654 igb_ring_empty(IGBCore
*core
, const E1000E_RingInfo
*r
)
656 return core
->mac
[r
->dh
] == core
->mac
[r
->dt
] ||
657 core
->mac
[r
->dt
] >= core
->mac
[r
->dlen
] / E1000_RING_DESC_LEN
;
660 static inline uint64_t
661 igb_ring_base(IGBCore
*core
, const E1000E_RingInfo
*r
)
663 uint64_t bah
= core
->mac
[r
->dbah
];
664 uint64_t bal
= core
->mac
[r
->dbal
];
666 return (bah
<< 32) + bal
;
669 static inline uint64_t
670 igb_ring_head_descr(IGBCore
*core
, const E1000E_RingInfo
*r
)
672 return igb_ring_base(core
, r
) + E1000_RING_DESC_LEN
* core
->mac
[r
->dh
];
676 igb_ring_advance(IGBCore
*core
, const E1000E_RingInfo
*r
, uint32_t count
)
678 core
->mac
[r
->dh
] += count
;
680 if (core
->mac
[r
->dh
] * E1000_RING_DESC_LEN
>= core
->mac
[r
->dlen
]) {
681 core
->mac
[r
->dh
] = 0;
685 static inline uint32_t
686 igb_ring_free_descr_num(IGBCore
*core
, const E1000E_RingInfo
*r
)
688 trace_e1000e_ring_free_space(r
->idx
, core
->mac
[r
->dlen
],
689 core
->mac
[r
->dh
], core
->mac
[r
->dt
]);
691 if (core
->mac
[r
->dh
] <= core
->mac
[r
->dt
]) {
692 return core
->mac
[r
->dt
] - core
->mac
[r
->dh
];
695 if (core
->mac
[r
->dh
] > core
->mac
[r
->dt
]) {
696 return core
->mac
[r
->dlen
] / E1000_RING_DESC_LEN
+
697 core
->mac
[r
->dt
] - core
->mac
[r
->dh
];
700 g_assert_not_reached();
705 igb_ring_enabled(IGBCore
*core
, const E1000E_RingInfo
*r
)
707 return core
->mac
[r
->dlen
] > 0;
710 typedef struct IGB_TxRing_st
{
711 const E1000E_RingInfo
*i
;
716 igb_mq_queue_idx(int base_reg_idx
, int reg_idx
)
718 return (reg_idx
- base_reg_idx
) / 16;
722 igb_tx_ring_init(IGBCore
*core
, IGB_TxRing
*txr
, int idx
)
724 static const E1000E_RingInfo i
[IGB_NUM_QUEUES
] = {
725 { TDBAH0
, TDBAL0
, TDLEN0
, TDH0
, TDT0
, 0 },
726 { TDBAH1
, TDBAL1
, TDLEN1
, TDH1
, TDT1
, 1 },
727 { TDBAH2
, TDBAL2
, TDLEN2
, TDH2
, TDT2
, 2 },
728 { TDBAH3
, TDBAL3
, TDLEN3
, TDH3
, TDT3
, 3 },
729 { TDBAH4
, TDBAL4
, TDLEN4
, TDH4
, TDT4
, 4 },
730 { TDBAH5
, TDBAL5
, TDLEN5
, TDH5
, TDT5
, 5 },
731 { TDBAH6
, TDBAL6
, TDLEN6
, TDH6
, TDT6
, 6 },
732 { TDBAH7
, TDBAL7
, TDLEN7
, TDH7
, TDT7
, 7 },
733 { TDBAH8
, TDBAL8
, TDLEN8
, TDH8
, TDT8
, 8 },
734 { TDBAH9
, TDBAL9
, TDLEN9
, TDH9
, TDT9
, 9 },
735 { TDBAH10
, TDBAL10
, TDLEN10
, TDH10
, TDT10
, 10 },
736 { TDBAH11
, TDBAL11
, TDLEN11
, TDH11
, TDT11
, 11 },
737 { TDBAH12
, TDBAL12
, TDLEN12
, TDH12
, TDT12
, 12 },
738 { TDBAH13
, TDBAL13
, TDLEN13
, TDH13
, TDT13
, 13 },
739 { TDBAH14
, TDBAL14
, TDLEN14
, TDH14
, TDT14
, 14 },
740 { TDBAH15
, TDBAL15
, TDLEN15
, TDH15
, TDT15
, 15 }
743 assert(idx
< ARRAY_SIZE(i
));
746 txr
->tx
= &core
->tx
[idx
];
749 typedef struct E1000E_RxRing_st
{
750 const E1000E_RingInfo
*i
;
754 igb_rx_ring_init(IGBCore
*core
, E1000E_RxRing
*rxr
, int idx
)
756 static const E1000E_RingInfo i
[IGB_NUM_QUEUES
] = {
757 { RDBAH0
, RDBAL0
, RDLEN0
, RDH0
, RDT0
, 0 },
758 { RDBAH1
, RDBAL1
, RDLEN1
, RDH1
, RDT1
, 1 },
759 { RDBAH2
, RDBAL2
, RDLEN2
, RDH2
, RDT2
, 2 },
760 { RDBAH3
, RDBAL3
, RDLEN3
, RDH3
, RDT3
, 3 },
761 { RDBAH4
, RDBAL4
, RDLEN4
, RDH4
, RDT4
, 4 },
762 { RDBAH5
, RDBAL5
, RDLEN5
, RDH5
, RDT5
, 5 },
763 { RDBAH6
, RDBAL6
, RDLEN6
, RDH6
, RDT6
, 6 },
764 { RDBAH7
, RDBAL7
, RDLEN7
, RDH7
, RDT7
, 7 },
765 { RDBAH8
, RDBAL8
, RDLEN8
, RDH8
, RDT8
, 8 },
766 { RDBAH9
, RDBAL9
, RDLEN9
, RDH9
, RDT9
, 9 },
767 { RDBAH10
, RDBAL10
, RDLEN10
, RDH10
, RDT10
, 10 },
768 { RDBAH11
, RDBAL11
, RDLEN11
, RDH11
, RDT11
, 11 },
769 { RDBAH12
, RDBAL12
, RDLEN12
, RDH12
, RDT12
, 12 },
770 { RDBAH13
, RDBAL13
, RDLEN13
, RDH13
, RDT13
, 13 },
771 { RDBAH14
, RDBAL14
, RDLEN14
, RDH14
, RDT14
, 14 },
772 { RDBAH15
, RDBAL15
, RDLEN15
, RDH15
, RDT15
, 15 }
775 assert(idx
< ARRAY_SIZE(i
));
781 igb_txdesc_writeback(IGBCore
*core
, dma_addr_t base
,
782 union e1000_adv_tx_desc
*tx_desc
,
783 const E1000E_RingInfo
*txi
)
786 uint32_t cmd_type_len
= le32_to_cpu(tx_desc
->read
.cmd_type_len
);
789 tdwba
= core
->mac
[E1000_TDWBAL(txi
->idx
) >> 2];
790 tdwba
|= (uint64_t)core
->mac
[E1000_TDWBAH(txi
->idx
) >> 2] << 32;
792 if (!(cmd_type_len
& E1000_TXD_CMD_RS
)) {
796 d
= pcie_sriov_get_vf_at_index(core
->owner
, txi
->idx
% 8);
802 uint32_t buffer
= cpu_to_le32(core
->mac
[txi
->dh
]);
803 pci_dma_write(d
, tdwba
& ~3, &buffer
, sizeof(buffer
));
805 uint32_t status
= le32_to_cpu(tx_desc
->wb
.status
) | E1000_TXD_STAT_DD
;
807 tx_desc
->wb
.status
= cpu_to_le32(status
);
808 pci_dma_write(d
, base
+ offsetof(union e1000_adv_tx_desc
, wb
),
809 &tx_desc
->wb
, sizeof(tx_desc
->wb
));
812 return igb_tx_wb_eic(core
, txi
->idx
);
816 igb_tx_enabled(IGBCore
*core
, const E1000E_RingInfo
*txi
)
818 bool vmdq
= core
->mac
[MRQC
] & 1;
819 uint16_t qn
= txi
->idx
;
820 uint16_t pool
= qn
% IGB_NUM_VM_POOLS
;
822 return (core
->mac
[TCTL
] & E1000_TCTL_EN
) &&
823 (!vmdq
|| core
->mac
[VFTE
] & BIT(pool
)) &&
824 (core
->mac
[TXDCTL0
+ (qn
* 16)] & E1000_TXDCTL_QUEUE_ENABLE
);
828 igb_start_xmit(IGBCore
*core
, const IGB_TxRing
*txr
)
832 union e1000_adv_tx_desc desc
;
833 const E1000E_RingInfo
*txi
= txr
->i
;
836 if (!igb_tx_enabled(core
, txi
)) {
837 trace_e1000e_tx_disabled();
841 d
= pcie_sriov_get_vf_at_index(core
->owner
, txi
->idx
% 8);
846 while (!igb_ring_empty(core
, txi
)) {
847 base
= igb_ring_head_descr(core
, txi
);
849 pci_dma_read(d
, base
, &desc
, sizeof(desc
));
851 trace_e1000e_tx_descr((void *)(intptr_t)desc
.read
.buffer_addr
,
852 desc
.read
.cmd_type_len
, desc
.wb
.status
);
854 igb_process_tx_desc(core
, d
, txr
->tx
, &desc
, txi
->idx
);
855 igb_ring_advance(core
, txi
, 1);
856 eic
|= igb_txdesc_writeback(core
, base
, &desc
, txi
);
860 core
->mac
[EICR
] |= eic
;
861 igb_set_interrupt_cause(core
, E1000_ICR_TXDW
);
864 net_tx_pkt_reset(txr
->tx
->tx_pkt
, net_tx_pkt_unmap_frag_pci
, d
);
868 igb_rxbufsize(IGBCore
*core
, const E1000E_RingInfo
*r
)
870 uint32_t srrctl
= core
->mac
[E1000_SRRCTL(r
->idx
) >> 2];
871 uint32_t bsizepkt
= srrctl
& E1000_SRRCTL_BSIZEPKT_MASK
;
873 return bsizepkt
<< E1000_SRRCTL_BSIZEPKT_SHIFT
;
876 return e1000x_rxbufsize(core
->mac
[RCTL
]);
880 igb_has_rxbufs(IGBCore
*core
, const E1000E_RingInfo
*r
, size_t total_size
)
882 uint32_t bufs
= igb_ring_free_descr_num(core
, r
);
883 uint32_t bufsize
= igb_rxbufsize(core
, r
);
885 trace_e1000e_rx_has_buffers(r
->idx
, bufs
, total_size
, bufsize
);
887 return total_size
<= bufs
/ (core
->rx_desc_len
/ E1000_MIN_RX_DESC_LEN
) *
892 igb_start_recv(IGBCore
*core
)
896 trace_e1000e_rx_start_recv();
898 for (i
= 0; i
<= core
->max_queue_num
; i
++) {
899 qemu_flush_queued_packets(qemu_get_subqueue(core
->owner_nic
, i
));
904 igb_can_receive(IGBCore
*core
)
908 if (!e1000x_rx_ready(core
->owner
, core
->mac
)) {
912 for (i
= 0; i
< IGB_NUM_QUEUES
; i
++) {
914 if (!(core
->mac
[RXDCTL0
+ (i
* 16)] & E1000_RXDCTL_QUEUE_ENABLE
)) {
918 igb_rx_ring_init(core
, &rxr
, i
);
919 if (igb_ring_enabled(core
, rxr
.i
) && igb_has_rxbufs(core
, rxr
.i
, 1)) {
920 trace_e1000e_rx_can_recv();
925 trace_e1000e_rx_can_recv_rings_full();
930 igb_receive(IGBCore
*core
, const uint8_t *buf
, size_t size
)
932 const struct iovec iov
= {
933 .iov_base
= (uint8_t *)buf
,
937 return igb_receive_iov(core
, &iov
, 1);
941 igb_rx_l3_cso_enabled(IGBCore
*core
)
943 return !!(core
->mac
[RXCSUM
] & E1000_RXCSUM_IPOFLD
);
947 igb_rx_l4_cso_enabled(IGBCore
*core
)
949 return !!(core
->mac
[RXCSUM
] & E1000_RXCSUM_TUOFLD
);
953 igb_rx_is_oversized(IGBCore
*core
, uint16_t qn
, size_t size
)
955 uint16_t pool
= qn
% IGB_NUM_VM_POOLS
;
956 bool lpe
= !!(core
->mac
[VMOLR0
+ pool
] & E1000_VMOLR_LPE
);
957 int max_ethernet_lpe_size
=
958 core
->mac
[VMOLR0
+ pool
] & E1000_VMOLR_RLPML_MASK
;
959 int max_ethernet_vlan_size
= 1522;
961 return size
> (lpe
? max_ethernet_lpe_size
: max_ethernet_vlan_size
);
964 static uint16_t igb_receive_assign(IGBCore
*core
, const struct eth_header
*ehdr
,
965 size_t size
, E1000E_RSSInfo
*rss_info
,
968 static const int ta_shift
[] = { 4, 3, 2, 0 };
969 uint32_t f
, ra
[2], *macp
, rctl
= core
->mac
[RCTL
];
971 uint16_t oversized
= 0;
972 uint16_t vid
= lduw_be_p(&PKT_GET_VLAN_HDR(ehdr
)->h_tci
) & VLAN_VID_MASK
;
973 bool accepted
= false;
976 memset(rss_info
, 0, sizeof(E1000E_RSSInfo
));
982 if (e1000x_is_vlan_packet(ehdr
, core
->mac
[VET
] & 0xffff) &&
983 e1000x_vlan_rx_filter_enabled(core
->mac
)) {
985 ldl_le_p((uint32_t *)(core
->mac
+ VFTA
) +
986 ((vid
>> E1000_VFTA_ENTRY_SHIFT
) & E1000_VFTA_ENTRY_MASK
));
987 if ((vfta
& (1 << (vid
& E1000_VFTA_ENTRY_BIT_SHIFT_MASK
))) == 0) {
988 trace_e1000e_rx_flt_vlan_mismatch(vid
);
991 trace_e1000e_rx_flt_vlan_match(vid
);
995 if (core
->mac
[MRQC
] & 1) {
996 if (is_broadcast_ether_addr(ehdr
->h_dest
)) {
997 for (i
= 0; i
< IGB_NUM_VM_POOLS
; i
++) {
998 if (core
->mac
[VMOLR0
+ i
] & E1000_VMOLR_BAM
) {
1003 for (macp
= core
->mac
+ RA
; macp
< core
->mac
+ RA
+ 32; macp
+= 2) {
1004 if (!(macp
[1] & E1000_RAH_AV
)) {
1007 ra
[0] = cpu_to_le32(macp
[0]);
1008 ra
[1] = cpu_to_le32(macp
[1]);
1009 if (!memcmp(ehdr
->h_dest
, (uint8_t *)ra
, ETH_ALEN
)) {
1010 queues
|= (macp
[1] & E1000_RAH_POOL_MASK
) / E1000_RAH_POOL_1
;
1014 for (macp
= core
->mac
+ RA2
; macp
< core
->mac
+ RA2
+ 16; macp
+= 2) {
1015 if (!(macp
[1] & E1000_RAH_AV
)) {
1018 ra
[0] = cpu_to_le32(macp
[0]);
1019 ra
[1] = cpu_to_le32(macp
[1]);
1020 if (!memcmp(ehdr
->h_dest
, (uint8_t *)ra
, ETH_ALEN
)) {
1021 queues
|= (macp
[1] & E1000_RAH_POOL_MASK
) / E1000_RAH_POOL_1
;
1026 macp
= core
->mac
+ (is_multicast_ether_addr(ehdr
->h_dest
) ? MTA
: UTA
);
1028 f
= ta_shift
[(rctl
>> E1000_RCTL_MO_SHIFT
) & 3];
1029 f
= (((ehdr
->h_dest
[5] << 8) | ehdr
->h_dest
[4]) >> f
) & 0xfff;
1030 if (macp
[f
>> 5] & (1 << (f
& 0x1f))) {
1031 for (i
= 0; i
< IGB_NUM_VM_POOLS
; i
++) {
1032 if (core
->mac
[VMOLR0
+ i
] & E1000_VMOLR_ROMPE
) {
1037 } else if (is_unicast_ether_addr(ehdr
->h_dest
) && external_tx
) {
1038 *external_tx
= false;
1042 if (e1000x_vlan_rx_filter_enabled(core
->mac
)) {
1045 if (e1000x_is_vlan_packet(ehdr
, core
->mac
[VET
] & 0xffff)) {
1046 for (i
= 0; i
< E1000_VLVF_ARRAY_SIZE
; i
++) {
1047 if ((core
->mac
[VLVF0
+ i
] & E1000_VLVF_VLANID_MASK
) == vid
&&
1048 (core
->mac
[VLVF0
+ i
] & E1000_VLVF_VLANID_ENABLE
)) {
1049 uint32_t poolsel
= core
->mac
[VLVF0
+ i
] & E1000_VLVF_POOLSEL_MASK
;
1050 mask
|= poolsel
>> E1000_VLVF_POOLSEL_SHIFT
;
1054 for (i
= 0; i
< IGB_NUM_VM_POOLS
; i
++) {
1055 if (core
->mac
[VMOLR0
+ i
] & E1000_VMOLR_AUPE
) {
1064 if (is_unicast_ether_addr(ehdr
->h_dest
) && !queues
&& !external_tx
&&
1065 !(core
->mac
[VT_CTL
] & E1000_VT_CTL_DISABLE_DEF_POOL
)) {
1066 uint32_t def_pl
= core
->mac
[VT_CTL
] & E1000_VT_CTL_DEFAULT_POOL_MASK
;
1067 queues
= BIT(def_pl
>> E1000_VT_CTL_DEFAULT_POOL_SHIFT
);
1070 queues
&= core
->mac
[VFRE
];
1072 for (i
= 0; i
< IGB_NUM_VM_POOLS
; i
++) {
1073 if ((queues
& BIT(i
)) && igb_rx_is_oversized(core
, i
, size
)) {
1074 oversized
|= BIT(i
);
1077 /* 8.19.37 increment ROC if packet is oversized for all queues */
1078 if (oversized
== queues
) {
1079 trace_e1000x_rx_oversized(size
);
1080 e1000x_inc_reg_if_not_full(core
->mac
, ROC
);
1082 queues
&= ~oversized
;
1086 igb_rss_parse_packet(core
, core
->rx_pkt
,
1087 external_tx
!= NULL
, rss_info
);
1088 /* Sec 8.26.1: PQn = VFn + VQn*8 */
1089 if (rss_info
->queue
& 1) {
1090 for (i
= 0; i
< IGB_NUM_VM_POOLS
; i
++) {
1091 if ((queues
& BIT(i
)) &&
1092 (core
->mac
[VMOLR0
+ i
] & E1000_VMOLR_RSSE
)) {
1093 queues
|= BIT(i
+ IGB_NUM_VM_POOLS
);
1100 switch (net_rx_pkt_get_packet_type(core
->rx_pkt
)) {
1102 if (rctl
& E1000_RCTL_UPE
) {
1103 accepted
= true; /* promiscuous ucast */
1108 if (rctl
& E1000_RCTL_BAM
) {
1109 accepted
= true; /* broadcast enabled */
1114 if (rctl
& E1000_RCTL_MPE
) {
1115 accepted
= true; /* promiscuous mcast */
1120 g_assert_not_reached();
1124 accepted
= e1000x_rx_group_filter(core
->mac
, ehdr
->h_dest
);
1128 for (macp
= core
->mac
+ RA2
; macp
< core
->mac
+ RA2
+ 16; macp
+= 2) {
1129 if (!(macp
[1] & E1000_RAH_AV
)) {
1132 ra
[0] = cpu_to_le32(macp
[0]);
1133 ra
[1] = cpu_to_le32(macp
[1]);
1134 if (!memcmp(ehdr
->h_dest
, (uint8_t *)ra
, ETH_ALEN
)) {
1135 trace_e1000x_rx_flt_ucast_match((int)(macp
- core
->mac
- RA2
) / 2,
1136 MAC_ARG(ehdr
->h_dest
));
1145 igb_rss_parse_packet(core
, core
->rx_pkt
, false, rss_info
);
1146 queues
= BIT(rss_info
->queue
);
1154 igb_read_lgcy_rx_descr(IGBCore
*core
, struct e1000_rx_desc
*desc
,
1157 *buff_addr
= le64_to_cpu(desc
->buffer_addr
);
1161 igb_read_adv_rx_descr(IGBCore
*core
, union e1000_adv_rx_desc
*desc
,
1164 *buff_addr
= le64_to_cpu(desc
->read
.pkt_addr
);
1168 igb_read_rx_descr(IGBCore
*core
, union e1000_rx_desc_union
*desc
,
1171 if (igb_rx_use_legacy_descriptor(core
)) {
1172 igb_read_lgcy_rx_descr(core
, &desc
->legacy
, buff_addr
);
1174 igb_read_adv_rx_descr(core
, &desc
->adv
, buff_addr
);
1179 igb_verify_csum_in_sw(IGBCore
*core
,
1180 struct NetRxPkt
*pkt
,
1181 uint32_t *status_flags
,
1182 EthL4HdrProto l4hdr_proto
)
1185 uint32_t csum_error
;
1187 if (igb_rx_l3_cso_enabled(core
)) {
1188 if (!net_rx_pkt_validate_l3_csum(pkt
, &csum_valid
)) {
1189 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1191 csum_error
= csum_valid
? 0 : E1000_RXDEXT_STATERR_IPE
;
1192 *status_flags
|= E1000_RXD_STAT_IPCS
| csum_error
;
1195 trace_e1000e_rx_metadata_l3_cso_disabled();
1198 if (!igb_rx_l4_cso_enabled(core
)) {
1199 trace_e1000e_rx_metadata_l4_cso_disabled();
1203 if (!net_rx_pkt_validate_l4_csum(pkt
, &csum_valid
)) {
1204 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1208 csum_error
= csum_valid
? 0 : E1000_RXDEXT_STATERR_TCPE
;
1209 *status_flags
|= E1000_RXD_STAT_TCPCS
| csum_error
;
1211 if (l4hdr_proto
== ETH_L4_HDR_PROTO_UDP
) {
1212 *status_flags
|= E1000_RXD_STAT_UDPCS
;
1217 igb_build_rx_metadata(IGBCore
*core
,
1218 struct NetRxPkt
*pkt
,
1220 const E1000E_RSSInfo
*rss_info
,
1221 uint16_t *pkt_info
, uint16_t *hdr_info
,
1223 uint32_t *status_flags
,
1227 struct virtio_net_hdr
*vhdr
;
1228 bool hasip4
, hasip6
;
1229 EthL4HdrProto l4hdr_proto
;
1231 *status_flags
= E1000_RXD_STAT_DD
;
1233 /* No additional metadata needed for non-EOP descriptors */
1234 /* TODO: EOP apply only to status so don't skip whole function. */
1239 *status_flags
|= E1000_RXD_STAT_EOP
;
1241 net_rx_pkt_get_protocols(pkt
, &hasip4
, &hasip6
, &l4hdr_proto
);
1242 trace_e1000e_rx_metadata_protocols(hasip4
, hasip6
, l4hdr_proto
);
1245 if (net_rx_pkt_is_vlan_stripped(pkt
)) {
1246 *status_flags
|= E1000_RXD_STAT_VP
;
1247 *vlan_tag
= cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt
));
1248 trace_e1000e_rx_metadata_vlan(*vlan_tag
);
1251 /* Packet parsing results */
1252 if ((core
->mac
[RXCSUM
] & E1000_RXCSUM_PCSD
) != 0) {
1253 if (rss_info
->enabled
) {
1254 *rss
= cpu_to_le32(rss_info
->hash
);
1255 trace_igb_rx_metadata_rss(*rss
);
1257 } else if (hasip4
) {
1258 *status_flags
|= E1000_RXD_STAT_IPIDV
;
1259 *ip_id
= cpu_to_le16(net_rx_pkt_get_ip_id(pkt
));
1260 trace_e1000e_rx_metadata_ip_id(*ip_id
);
1263 if (l4hdr_proto
== ETH_L4_HDR_PROTO_TCP
&& net_rx_pkt_is_tcp_ack(pkt
)) {
1264 *status_flags
|= E1000_RXD_STAT_ACK
;
1265 trace_e1000e_rx_metadata_ack();
1269 *pkt_info
= rss_info
->enabled
? rss_info
->type
: 0;
1272 *pkt_info
|= E1000_ADVRXD_PKT_IP4
;
1276 *pkt_info
|= E1000_ADVRXD_PKT_IP6
;
1279 switch (l4hdr_proto
) {
1280 case ETH_L4_HDR_PROTO_TCP
:
1281 *pkt_info
|= E1000_ADVRXD_PKT_TCP
;
1284 case ETH_L4_HDR_PROTO_UDP
:
1285 *pkt_info
|= E1000_ADVRXD_PKT_UDP
;
1297 /* RX CSO information */
1298 if (hasip6
&& (core
->mac
[RFCTL
] & E1000_RFCTL_IPV6_XSUM_DIS
)) {
1299 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1303 vhdr
= net_rx_pkt_get_vhdr(pkt
);
1305 if (!(vhdr
->flags
& VIRTIO_NET_HDR_F_DATA_VALID
) &&
1306 !(vhdr
->flags
& VIRTIO_NET_HDR_F_NEEDS_CSUM
)) {
1307 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1308 igb_verify_csum_in_sw(core
, pkt
, status_flags
, l4hdr_proto
);
1312 if (igb_rx_l3_cso_enabled(core
)) {
1313 *status_flags
|= hasip4
? E1000_RXD_STAT_IPCS
: 0;
1315 trace_e1000e_rx_metadata_l3_cso_disabled();
1318 if (igb_rx_l4_cso_enabled(core
)) {
1319 switch (l4hdr_proto
) {
1320 case ETH_L4_HDR_PROTO_TCP
:
1321 *status_flags
|= E1000_RXD_STAT_TCPCS
;
1324 case ETH_L4_HDR_PROTO_UDP
:
1325 *status_flags
|= E1000_RXD_STAT_TCPCS
| E1000_RXD_STAT_UDPCS
;
1332 trace_e1000e_rx_metadata_l4_cso_disabled();
1335 trace_e1000e_rx_metadata_status_flags(*status_flags
);
1338 *status_flags
= cpu_to_le32(*status_flags
);
1342 igb_write_lgcy_rx_descr(IGBCore
*core
, struct e1000_rx_desc
*desc
,
1343 struct NetRxPkt
*pkt
,
1344 const E1000E_RSSInfo
*rss_info
,
1347 uint32_t status_flags
, rss
;
1350 assert(!rss_info
->enabled
);
1351 desc
->length
= cpu_to_le16(length
);
1354 igb_build_rx_metadata(core
, pkt
, pkt
!= NULL
,
1357 &status_flags
, &ip_id
,
1359 desc
->errors
= (uint8_t) (le32_to_cpu(status_flags
) >> 24);
1360 desc
->status
= (uint8_t) le32_to_cpu(status_flags
);
1364 igb_write_adv_rx_descr(IGBCore
*core
, union e1000_adv_rx_desc
*desc
,
1365 struct NetRxPkt
*pkt
,
1366 const E1000E_RSSInfo
*rss_info
,
1369 memset(&desc
->wb
, 0, sizeof(desc
->wb
));
1371 desc
->wb
.upper
.length
= cpu_to_le16(length
);
1373 igb_build_rx_metadata(core
, pkt
, pkt
!= NULL
,
1375 &desc
->wb
.lower
.lo_dword
.pkt_info
,
1376 &desc
->wb
.lower
.lo_dword
.hdr_info
,
1377 &desc
->wb
.lower
.hi_dword
.rss
,
1378 &desc
->wb
.upper
.status_error
,
1379 &desc
->wb
.lower
.hi_dword
.csum_ip
.ip_id
,
1380 &desc
->wb
.upper
.vlan
);
1384 igb_write_rx_descr(IGBCore
*core
, union e1000_rx_desc_union
*desc
,
1385 struct NetRxPkt
*pkt
, const E1000E_RSSInfo
*rss_info
, uint16_t length
)
1387 if (igb_rx_use_legacy_descriptor(core
)) {
1388 igb_write_lgcy_rx_descr(core
, &desc
->legacy
, pkt
, rss_info
, length
);
1390 igb_write_adv_rx_descr(core
, &desc
->adv
, pkt
, rss_info
, length
);
1395 igb_pci_dma_write_rx_desc(IGBCore
*core
, PCIDevice
*dev
, dma_addr_t addr
,
1396 union e1000_rx_desc_union
*desc
, dma_addr_t len
)
1398 if (igb_rx_use_legacy_descriptor(core
)) {
1399 struct e1000_rx_desc
*d
= &desc
->legacy
;
1400 size_t offset
= offsetof(struct e1000_rx_desc
, status
);
1401 uint8_t status
= d
->status
;
1403 d
->status
&= ~E1000_RXD_STAT_DD
;
1404 pci_dma_write(dev
, addr
, desc
, len
);
1406 if (status
& E1000_RXD_STAT_DD
) {
1408 pci_dma_write(dev
, addr
+ offset
, &status
, sizeof(status
));
1411 union e1000_adv_rx_desc
*d
= &desc
->adv
;
1413 offsetof(union e1000_adv_rx_desc
, wb
.upper
.status_error
);
1414 uint32_t status
= d
->wb
.upper
.status_error
;
1416 d
->wb
.upper
.status_error
&= ~E1000_RXD_STAT_DD
;
1417 pci_dma_write(dev
, addr
, desc
, len
);
1419 if (status
& E1000_RXD_STAT_DD
) {
1420 d
->wb
.upper
.status_error
= status
;
1421 pci_dma_write(dev
, addr
+ offset
, &status
, sizeof(status
));
1427 igb_write_to_rx_buffers(IGBCore
*core
,
1432 dma_addr_t data_len
)
1434 trace_igb_rx_desc_buff_write(ba
, *written
, data
, data_len
);
1435 pci_dma_write(d
, ba
+ *written
, data
, data_len
);
1436 *written
+= data_len
;
1440 igb_update_rx_stats(IGBCore
*core
, const E1000E_RingInfo
*rxi
,
1441 size_t pkt_size
, size_t pkt_fcs_size
)
1443 eth_pkt_types_e pkt_type
= net_rx_pkt_get_packet_type(core
->rx_pkt
);
1444 e1000x_update_rx_total_stats(core
->mac
, pkt_type
, pkt_size
, pkt_fcs_size
);
1446 if (core
->mac
[MRQC
] & 1) {
1447 uint16_t pool
= rxi
->idx
% IGB_NUM_VM_POOLS
;
1449 core
->mac
[PVFGORC0
+ (pool
* 64)] += pkt_size
+ 4;
1450 core
->mac
[PVFGPRC0
+ (pool
* 64)]++;
1451 if (pkt_type
== ETH_PKT_MCAST
) {
1452 core
->mac
[PVFMPRC0
+ (pool
* 64)]++;
1458 igb_rx_descr_threshold_hit(IGBCore
*core
, const E1000E_RingInfo
*rxi
)
1460 return igb_ring_free_descr_num(core
, rxi
) ==
1461 ((core
->mac
[E1000_SRRCTL(rxi
->idx
) >> 2] >> 20) & 31) * 16;
1465 igb_write_packet_to_guest(IGBCore
*core
, struct NetRxPkt
*pkt
,
1466 const E1000E_RxRing
*rxr
,
1467 const E1000E_RSSInfo
*rss_info
)
1471 union e1000_rx_desc_union desc
;
1473 size_t desc_offset
= 0;
1476 struct iovec
*iov
= net_rx_pkt_get_iovec(pkt
);
1477 size_t size
= net_rx_pkt_get_total_len(pkt
);
1478 size_t total_size
= size
+ e1000x_fcs_len(core
->mac
);
1479 const E1000E_RingInfo
*rxi
= rxr
->i
;
1480 size_t bufsize
= igb_rxbufsize(core
, rxi
);
1482 d
= pcie_sriov_get_vf_at_index(core
->owner
, rxi
->idx
% 8);
1489 uint16_t written
= 0;
1490 bool is_last
= false;
1492 desc_size
= total_size
- desc_offset
;
1494 if (desc_size
> bufsize
) {
1495 desc_size
= bufsize
;
1498 if (igb_ring_empty(core
, rxi
)) {
1502 base
= igb_ring_head_descr(core
, rxi
);
1504 pci_dma_read(d
, base
, &desc
, core
->rx_desc_len
);
1506 trace_e1000e_rx_descr(rxi
->idx
, base
, core
->rx_desc_len
);
1508 igb_read_rx_descr(core
, &desc
, &ba
);
1511 if (desc_offset
< size
) {
1512 static const uint32_t fcs_pad
;
1514 size_t copy_size
= size
- desc_offset
;
1515 if (copy_size
> bufsize
) {
1516 copy_size
= bufsize
;
1519 /* Copy packet payload */
1521 iov_copy
= MIN(copy_size
, iov
->iov_len
- iov_ofs
);
1523 igb_write_to_rx_buffers(core
, d
, ba
, &written
,
1524 iov
->iov_base
+ iov_ofs
, iov_copy
);
1526 copy_size
-= iov_copy
;
1527 iov_ofs
+= iov_copy
;
1528 if (iov_ofs
== iov
->iov_len
) {
1534 if (desc_offset
+ desc_size
>= total_size
) {
1535 /* Simulate FCS checksum presence in the last descriptor */
1536 igb_write_to_rx_buffers(core
, d
, ba
, &written
,
1537 (const char *) &fcs_pad
, e1000x_fcs_len(core
->mac
));
1540 } else { /* as per intel docs; skip descriptors with null buf addr */
1541 trace_e1000e_rx_null_descriptor();
1543 desc_offset
+= desc_size
;
1544 if (desc_offset
>= total_size
) {
1548 igb_write_rx_descr(core
, &desc
, is_last
? core
->rx_pkt
: NULL
,
1550 igb_pci_dma_write_rx_desc(core
, d
, base
, &desc
, core
->rx_desc_len
);
1552 igb_ring_advance(core
, rxi
, core
->rx_desc_len
/ E1000_MIN_RX_DESC_LEN
);
1554 } while (desc_offset
< total_size
);
1556 igb_update_rx_stats(core
, rxi
, size
, total_size
);
1560 igb_rx_strip_vlan(IGBCore
*core
, const E1000E_RingInfo
*rxi
)
1562 if (core
->mac
[MRQC
] & 1) {
1563 uint16_t pool
= rxi
->idx
% IGB_NUM_VM_POOLS
;
1564 /* Sec 7.10.3.8: CTRL.VME is ignored, only VMOLR/RPLOLR is used */
1565 return (net_rx_pkt_get_packet_type(core
->rx_pkt
) == ETH_PKT_MCAST
) ?
1566 core
->mac
[RPLOLR
] & E1000_RPLOLR_STRVLAN
:
1567 core
->mac
[VMOLR0
+ pool
] & E1000_VMOLR_STRVLAN
;
1570 return e1000x_vlan_enabled(core
->mac
);
1574 igb_rx_fix_l4_csum(IGBCore
*core
, struct NetRxPkt
*pkt
)
1576 struct virtio_net_hdr
*vhdr
= net_rx_pkt_get_vhdr(pkt
);
1578 if (vhdr
->flags
& VIRTIO_NET_HDR_F_NEEDS_CSUM
) {
1579 net_rx_pkt_fix_l4_csum(pkt
);
1584 igb_receive_iov(IGBCore
*core
, const struct iovec
*iov
, int iovcnt
)
1586 return igb_receive_internal(core
, iov
, iovcnt
, core
->has_vnet
, NULL
);
1590 igb_receive_internal(IGBCore
*core
, const struct iovec
*iov
, int iovcnt
,
1591 bool has_vnet
, bool *external_tx
)
1593 static const int maximum_ethernet_hdr_len
= (ETH_HLEN
+ 4);
1595 uint16_t queues
= 0;
1597 uint8_t min_buf
[ETH_ZLEN
];
1598 struct iovec min_iov
;
1599 struct eth_header
*ehdr
;
1600 uint8_t *filter_buf
;
1601 size_t size
, orig_size
;
1604 E1000E_RSSInfo rss_info
;
1608 trace_e1000e_rx_receive_iov(iovcnt
);
1611 *external_tx
= true;
1614 if (!e1000x_hw_rx_enabled(core
->mac
)) {
1618 /* Pull virtio header in */
1620 net_rx_pkt_set_vhdr_iovec(core
->rx_pkt
, iov
, iovcnt
);
1621 iov_ofs
= sizeof(struct virtio_net_hdr
);
1623 net_rx_pkt_unset_vhdr(core
->rx_pkt
);
1626 filter_buf
= iov
->iov_base
+ iov_ofs
;
1627 orig_size
= iov_size(iov
, iovcnt
);
1628 size
= orig_size
- iov_ofs
;
1630 /* Pad to minimum Ethernet frame length */
1631 if (size
< sizeof(min_buf
)) {
1632 iov_to_buf(iov
, iovcnt
, iov_ofs
, min_buf
, size
);
1633 memset(&min_buf
[size
], 0, sizeof(min_buf
) - size
);
1634 e1000x_inc_reg_if_not_full(core
->mac
, RUC
);
1635 min_iov
.iov_base
= filter_buf
= min_buf
;
1636 min_iov
.iov_len
= size
= sizeof(min_buf
);
1640 } else if (iov
->iov_len
< maximum_ethernet_hdr_len
) {
1641 /* This is very unlikely, but may happen. */
1642 iov_to_buf(iov
, iovcnt
, iov_ofs
, min_buf
, maximum_ethernet_hdr_len
);
1643 filter_buf
= min_buf
;
1646 /* Discard oversized packets if !LPE and !SBP. */
1647 if (e1000x_is_oversized(core
->mac
, size
)) {
1651 ehdr
= PKT_GET_ETH_HDR(filter_buf
);
1652 net_rx_pkt_set_packet_type(core
->rx_pkt
, get_eth_packet_type(ehdr
));
1653 net_rx_pkt_set_protocols(core
->rx_pkt
, filter_buf
, size
);
1655 queues
= igb_receive_assign(core
, ehdr
, size
, &rss_info
, external_tx
);
1657 trace_e1000e_rx_flt_dropped();
1661 for (i
= 0; i
< IGB_NUM_QUEUES
; i
++) {
1662 if (!(queues
& BIT(i
)) ||
1663 !(core
->mac
[RXDCTL0
+ (i
* 16)] & E1000_RXDCTL_QUEUE_ENABLE
)) {
1667 igb_rx_ring_init(core
, &rxr
, i
);
1669 net_rx_pkt_attach_iovec_ex(core
->rx_pkt
, iov
, iovcnt
, iov_ofs
,
1670 igb_rx_strip_vlan(core
, rxr
.i
),
1671 core
->mac
[VET
] & 0xffff);
1673 total_size
= net_rx_pkt_get_total_len(core
->rx_pkt
) +
1674 e1000x_fcs_len(core
->mac
);
1676 if (!igb_has_rxbufs(core
, rxr
.i
, total_size
)) {
1678 trace_e1000e_rx_not_written_to_guest(rxr
.i
->idx
);
1682 n
|= E1000_ICR_RXDW
;
1684 igb_rx_fix_l4_csum(core
, core
->rx_pkt
);
1685 igb_write_packet_to_guest(core
, core
->rx_pkt
, &rxr
, &rss_info
);
1687 /* Check if receive descriptor minimum threshold hit */
1688 if (igb_rx_descr_threshold_hit(core
, rxr
.i
)) {
1689 n
|= E1000_ICS_RXDMT0
;
1692 core
->mac
[EICR
] |= igb_rx_wb_eic(core
, rxr
.i
->idx
);
1694 trace_e1000e_rx_written_to_guest(rxr
.i
->idx
);
1697 trace_e1000e_rx_interrupt_set(n
);
1698 igb_set_interrupt_cause(core
, n
);
1704 igb_have_autoneg(IGBCore
*core
)
1706 return core
->phy
[MII_BMCR
] & MII_BMCR_AUTOEN
;
1709 static void igb_update_flowctl_status(IGBCore
*core
)
1711 if (igb_have_autoneg(core
) && core
->phy
[MII_BMSR
] & MII_BMSR_AN_COMP
) {
1712 trace_e1000e_link_autoneg_flowctl(true);
1713 core
->mac
[CTRL
] |= E1000_CTRL_TFCE
| E1000_CTRL_RFCE
;
1715 trace_e1000e_link_autoneg_flowctl(false);
1720 igb_link_down(IGBCore
*core
)
1722 e1000x_update_regs_on_link_down(core
->mac
, core
->phy
);
1723 igb_update_flowctl_status(core
);
1727 igb_set_phy_ctrl(IGBCore
*core
, uint16_t val
)
1729 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1730 core
->phy
[MII_BMCR
] = val
& ~(0x3f | MII_BMCR_RESET
| MII_BMCR_ANRESTART
);
1732 if ((val
& MII_BMCR_ANRESTART
) && igb_have_autoneg(core
)) {
1733 e1000x_restart_autoneg(core
->mac
, core
->phy
, core
->autoneg_timer
);
1737 void igb_core_set_link_status(IGBCore
*core
)
1739 NetClientState
*nc
= qemu_get_queue(core
->owner_nic
);
1740 uint32_t old_status
= core
->mac
[STATUS
];
1742 trace_e1000e_link_status_changed(nc
->link_down
? false : true);
1744 if (nc
->link_down
) {
1745 e1000x_update_regs_on_link_down(core
->mac
, core
->phy
);
1747 if (igb_have_autoneg(core
) &&
1748 !(core
->phy
[MII_BMSR
] & MII_BMSR_AN_COMP
)) {
1749 e1000x_restart_autoneg(core
->mac
, core
->phy
,
1750 core
->autoneg_timer
);
1752 e1000x_update_regs_on_link_up(core
->mac
, core
->phy
);
1753 igb_start_recv(core
);
1757 if (core
->mac
[STATUS
] != old_status
) {
1758 igb_set_interrupt_cause(core
, E1000_ICR_LSC
);
1763 igb_set_ctrl(IGBCore
*core
, int index
, uint32_t val
)
1765 trace_e1000e_core_ctrl_write(index
, val
);
1767 /* RST is self clearing */
1768 core
->mac
[CTRL
] = val
& ~E1000_CTRL_RST
;
1769 core
->mac
[CTRL_DUP
] = core
->mac
[CTRL
];
1771 trace_e1000e_link_set_params(
1772 !!(val
& E1000_CTRL_ASDE
),
1773 (val
& E1000_CTRL_SPD_SEL
) >> E1000_CTRL_SPD_SHIFT
,
1774 !!(val
& E1000_CTRL_FRCSPD
),
1775 !!(val
& E1000_CTRL_FRCDPX
),
1776 !!(val
& E1000_CTRL_RFCE
),
1777 !!(val
& E1000_CTRL_TFCE
));
1779 if (val
& E1000_CTRL_RST
) {
1780 trace_e1000e_core_ctrl_sw_reset();
1781 igb_reset(core
, true);
1784 if (val
& E1000_CTRL_PHY_RST
) {
1785 trace_e1000e_core_ctrl_phy_reset();
1786 core
->mac
[STATUS
] |= E1000_STATUS_PHYRA
;
1791 igb_set_rfctl(IGBCore
*core
, int index
, uint32_t val
)
1793 trace_e1000e_rx_set_rfctl(val
);
1795 if (!(val
& E1000_RFCTL_ISCSI_DIS
)) {
1796 trace_e1000e_wrn_iscsi_filtering_not_supported();
1799 if (!(val
& E1000_RFCTL_NFSW_DIS
)) {
1800 trace_e1000e_wrn_nfsw_filtering_not_supported();
1803 if (!(val
& E1000_RFCTL_NFSR_DIS
)) {
1804 trace_e1000e_wrn_nfsr_filtering_not_supported();
1807 core
->mac
[RFCTL
] = val
;
1811 igb_calc_rxdesclen(IGBCore
*core
)
1813 if (igb_rx_use_legacy_descriptor(core
)) {
1814 core
->rx_desc_len
= sizeof(struct e1000_rx_desc
);
1816 core
->rx_desc_len
= sizeof(union e1000_adv_rx_desc
);
1818 trace_e1000e_rx_desc_len(core
->rx_desc_len
);
1822 igb_set_rx_control(IGBCore
*core
, int index
, uint32_t val
)
1824 core
->mac
[RCTL
] = val
;
1825 trace_e1000e_rx_set_rctl(core
->mac
[RCTL
]);
1827 if (val
& E1000_RCTL_DTYP_MASK
) {
1828 qemu_log_mask(LOG_GUEST_ERROR
,
1829 "igb: RCTL.DTYP must be zero for compatibility");
1832 if (val
& E1000_RCTL_EN
) {
1833 igb_calc_rxdesclen(core
);
1834 igb_start_recv(core
);
1839 igb_clear_ims_bits(IGBCore
*core
, uint32_t bits
)
1841 trace_e1000e_irq_clear_ims(bits
, core
->mac
[IMS
], core
->mac
[IMS
] & ~bits
);
1842 core
->mac
[IMS
] &= ~bits
;
1846 igb_postpone_interrupt(IGBIntrDelayTimer
*timer
)
1848 if (timer
->running
) {
1849 trace_e1000e_irq_postponed_by_xitr(timer
->delay_reg
<< 2);
1854 if (timer
->core
->mac
[timer
->delay_reg
] != 0) {
1855 igb_intrmgr_rearm_timer(timer
);
1862 igb_eitr_should_postpone(IGBCore
*core
, int idx
)
1864 return igb_postpone_interrupt(&core
->eitr
[idx
]);
1867 static void igb_send_msix(IGBCore
*core
)
1869 uint32_t causes
= core
->mac
[EICR
] & core
->mac
[EIMS
];
1870 uint32_t effective_eiac
;
1873 for (vector
= 0; vector
< IGB_INTR_NUM
; ++vector
) {
1874 if ((causes
& BIT(vector
)) && !igb_eitr_should_postpone(core
, vector
)) {
1876 trace_e1000e_irq_msix_notify_vec(vector
);
1877 igb_msix_notify(core
, vector
);
1879 trace_e1000e_irq_icr_clear_eiac(core
->mac
[EICR
], core
->mac
[EIAC
]);
1880 effective_eiac
= core
->mac
[EIAC
] & BIT(vector
);
1881 core
->mac
[EICR
] &= ~effective_eiac
;
1887 igb_fix_icr_asserted(IGBCore
*core
)
1889 core
->mac
[ICR
] &= ~E1000_ICR_ASSERTED
;
1890 if (core
->mac
[ICR
]) {
1891 core
->mac
[ICR
] |= E1000_ICR_ASSERTED
;
1894 trace_e1000e_irq_fix_icr_asserted(core
->mac
[ICR
]);
1898 igb_update_interrupt_state(IGBCore
*core
)
1904 icr
= core
->mac
[ICR
] & core
->mac
[IMS
];
1906 if (msix_enabled(core
->owner
)) {
1909 if (icr
& E1000_ICR_DRSTA
) {
1910 int_alloc
= core
->mac
[IVAR_MISC
] & 0xff;
1911 if (int_alloc
& E1000_IVAR_VALID
) {
1912 causes
|= BIT(int_alloc
& 0x1f);
1915 /* Check if other bits (excluding the TCP Timer) are enabled. */
1916 if (icr
& ~E1000_ICR_DRSTA
) {
1917 int_alloc
= (core
->mac
[IVAR_MISC
] >> 8) & 0xff;
1918 if (int_alloc
& E1000_IVAR_VALID
) {
1919 causes
|= BIT(int_alloc
& 0x1f);
1921 trace_e1000e_irq_add_msi_other(core
->mac
[EICR
]);
1923 core
->mac
[EICR
] |= causes
;
1926 if ((core
->mac
[EICR
] & core
->mac
[EIMS
])) {
1927 igb_send_msix(core
);
1930 igb_fix_icr_asserted(core
);
1933 core
->mac
[EICR
] |= (icr
& E1000_ICR_DRSTA
) | E1000_EICR_OTHER
;
1935 core
->mac
[EICR
] &= ~E1000_EICR_OTHER
;
1938 trace_e1000e_irq_pending_interrupts(core
->mac
[ICR
] & core
->mac
[IMS
],
1939 core
->mac
[ICR
], core
->mac
[IMS
]);
1941 if (msi_enabled(core
->owner
)) {
1943 msi_notify(core
->owner
, 0);
1947 igb_raise_legacy_irq(core
);
1949 igb_lower_legacy_irq(core
);
1956 igb_set_interrupt_cause(IGBCore
*core
, uint32_t val
)
1958 trace_e1000e_irq_set_cause_entry(val
, core
->mac
[ICR
]);
1960 core
->mac
[ICR
] |= val
;
1962 trace_e1000e_irq_set_cause_exit(val
, core
->mac
[ICR
]);
1964 igb_update_interrupt_state(core
);
1967 static void igb_set_eics(IGBCore
*core
, int index
, uint32_t val
)
1969 bool msix
= !!(core
->mac
[GPIE
] & E1000_GPIE_MSIX_MODE
);
1971 trace_igb_irq_write_eics(val
, msix
);
1974 val
& (msix
? E1000_EICR_MSIX_MASK
: E1000_EICR_LEGACY_MASK
);
1977 * TODO: Move to igb_update_interrupt_state if EICS is modified in other
1980 core
->mac
[EICR
] = core
->mac
[EICS
];
1982 igb_update_interrupt_state(core
);
1985 static void igb_set_eims(IGBCore
*core
, int index
, uint32_t val
)
1987 bool msix
= !!(core
->mac
[GPIE
] & E1000_GPIE_MSIX_MODE
);
1989 trace_igb_irq_write_eims(val
, msix
);
1992 val
& (msix
? E1000_EICR_MSIX_MASK
: E1000_EICR_LEGACY_MASK
);
1994 igb_update_interrupt_state(core
);
1997 static void mailbox_interrupt_to_vf(IGBCore
*core
, uint16_t vfn
)
1999 uint32_t ent
= core
->mac
[VTIVAR_MISC
+ vfn
];
2001 if ((ent
& E1000_IVAR_VALID
)) {
2002 core
->mac
[EICR
] |= (ent
& 0x3) << (22 - vfn
* IGBVF_MSIX_VEC_NUM
);
2003 igb_update_interrupt_state(core
);
2007 static void mailbox_interrupt_to_pf(IGBCore
*core
)
2009 igb_set_interrupt_cause(core
, E1000_ICR_VMMB
);
2012 static void igb_set_pfmailbox(IGBCore
*core
, int index
, uint32_t val
)
2014 uint16_t vfn
= index
- P2VMAILBOX0
;
2016 trace_igb_set_pfmailbox(vfn
, val
);
2018 if (val
& E1000_P2VMAILBOX_STS
) {
2019 core
->mac
[V2PMAILBOX0
+ vfn
] |= E1000_V2PMAILBOX_PFSTS
;
2020 mailbox_interrupt_to_vf(core
, vfn
);
2023 if (val
& E1000_P2VMAILBOX_ACK
) {
2024 core
->mac
[V2PMAILBOX0
+ vfn
] |= E1000_V2PMAILBOX_PFACK
;
2025 mailbox_interrupt_to_vf(core
, vfn
);
2028 /* Buffer Taken by PF (can be set only if the VFU is cleared). */
2029 if (val
& E1000_P2VMAILBOX_PFU
) {
2030 if (!(core
->mac
[index
] & E1000_P2VMAILBOX_VFU
)) {
2031 core
->mac
[index
] |= E1000_P2VMAILBOX_PFU
;
2032 core
->mac
[V2PMAILBOX0
+ vfn
] |= E1000_V2PMAILBOX_PFU
;
2035 core
->mac
[index
] &= ~E1000_P2VMAILBOX_PFU
;
2036 core
->mac
[V2PMAILBOX0
+ vfn
] &= ~E1000_V2PMAILBOX_PFU
;
2039 if (val
& E1000_P2VMAILBOX_RVFU
) {
2040 core
->mac
[V2PMAILBOX0
+ vfn
] &= ~E1000_V2PMAILBOX_VFU
;
2041 core
->mac
[MBVFICR
] &= ~((E1000_MBVFICR_VFACK_VF1
<< vfn
) |
2042 (E1000_MBVFICR_VFREQ_VF1
<< vfn
));
2046 static void igb_set_vfmailbox(IGBCore
*core
, int index
, uint32_t val
)
2048 uint16_t vfn
= index
- V2PMAILBOX0
;
2050 trace_igb_set_vfmailbox(vfn
, val
);
2052 if (val
& E1000_V2PMAILBOX_REQ
) {
2053 core
->mac
[MBVFICR
] |= E1000_MBVFICR_VFREQ_VF1
<< vfn
;
2054 mailbox_interrupt_to_pf(core
);
2057 if (val
& E1000_V2PMAILBOX_ACK
) {
2058 core
->mac
[MBVFICR
] |= E1000_MBVFICR_VFACK_VF1
<< vfn
;
2059 mailbox_interrupt_to_pf(core
);
2062 /* Buffer Taken by VF (can be set only if the PFU is cleared). */
2063 if (val
& E1000_V2PMAILBOX_VFU
) {
2064 if (!(core
->mac
[index
] & E1000_V2PMAILBOX_PFU
)) {
2065 core
->mac
[index
] |= E1000_V2PMAILBOX_VFU
;
2066 core
->mac
[P2VMAILBOX0
+ vfn
] |= E1000_P2VMAILBOX_VFU
;
2069 core
->mac
[index
] &= ~E1000_V2PMAILBOX_VFU
;
2070 core
->mac
[P2VMAILBOX0
+ vfn
] &= ~E1000_P2VMAILBOX_VFU
;
2074 static void igb_vf_reset(IGBCore
*core
, uint16_t vfn
)
2077 uint16_t qn1
= vfn
+ IGB_NUM_VM_POOLS
;
2079 /* disable Rx and Tx for the VF*/
2080 core
->mac
[RXDCTL0
+ (qn0
* 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE
;
2081 core
->mac
[RXDCTL0
+ (qn1
* 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE
;
2082 core
->mac
[TXDCTL0
+ (qn0
* 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE
;
2083 core
->mac
[TXDCTL0
+ (qn1
* 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE
;
2084 core
->mac
[VFRE
] &= ~BIT(vfn
);
2085 core
->mac
[VFTE
] &= ~BIT(vfn
);
2086 /* indicate VF reset to PF */
2087 core
->mac
[VFLRE
] |= BIT(vfn
);
2088 /* VFLRE and mailbox use the same interrupt cause */
2089 mailbox_interrupt_to_pf(core
);
2092 static void igb_w1c(IGBCore
*core
, int index
, uint32_t val
)
2094 core
->mac
[index
] &= ~val
;
2097 static void igb_set_eimc(IGBCore
*core
, int index
, uint32_t val
)
2099 bool msix
= !!(core
->mac
[GPIE
] & E1000_GPIE_MSIX_MODE
);
2101 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */
2103 ~(val
& (msix
? E1000_EICR_MSIX_MASK
: E1000_EICR_LEGACY_MASK
));
2105 trace_igb_irq_write_eimc(val
, core
->mac
[EIMS
], msix
);
2106 igb_update_interrupt_state(core
);
2109 static void igb_set_eiac(IGBCore
*core
, int index
, uint32_t val
)
2111 bool msix
= !!(core
->mac
[GPIE
] & E1000_GPIE_MSIX_MODE
);
2114 trace_igb_irq_write_eiac(val
);
2117 * TODO: When using IOV, the bits that correspond to MSI-X vectors
2118 * that are assigned to a VF are read-only.
2120 core
->mac
[EIAC
] |= (val
& E1000_EICR_MSIX_MASK
);
2124 static void igb_set_eiam(IGBCore
*core
, int index
, uint32_t val
)
2126 bool msix
= !!(core
->mac
[GPIE
] & E1000_GPIE_MSIX_MODE
);
2129 * TODO: When using IOV, the bits that correspond to MSI-X vectors that
2130 * are assigned to a VF are read-only.
2133 ~(val
& (msix
? E1000_EICR_MSIX_MASK
: E1000_EICR_LEGACY_MASK
));
2135 trace_igb_irq_write_eiam(val
, msix
);
2138 static void igb_set_eicr(IGBCore
*core
, int index
, uint32_t val
)
2140 bool msix
= !!(core
->mac
[GPIE
] & E1000_GPIE_MSIX_MODE
);
2143 * TODO: In IOV mode, only bit zero of this vector is available for the PF
2147 ~(val
& (msix
? E1000_EICR_MSIX_MASK
: E1000_EICR_LEGACY_MASK
));
2149 trace_igb_irq_write_eicr(val
, msix
);
2150 igb_update_interrupt_state(core
);
2153 static void igb_set_vtctrl(IGBCore
*core
, int index
, uint32_t val
)
2157 if (val
& E1000_CTRL_RST
) {
2158 vfn
= (index
- PVTCTRL0
) / 0x40;
2159 igb_vf_reset(core
, vfn
);
2163 static void igb_set_vteics(IGBCore
*core
, int index
, uint32_t val
)
2165 uint16_t vfn
= (index
- PVTEICS0
) / 0x40;
2167 core
->mac
[index
] = val
;
2168 igb_set_eics(core
, EICS
, (val
& 0x7) << (22 - vfn
* IGBVF_MSIX_VEC_NUM
));
2171 static void igb_set_vteims(IGBCore
*core
, int index
, uint32_t val
)
2173 uint16_t vfn
= (index
- PVTEIMS0
) / 0x40;
2175 core
->mac
[index
] = val
;
2176 igb_set_eims(core
, EIMS
, (val
& 0x7) << (22 - vfn
* IGBVF_MSIX_VEC_NUM
));
2179 static void igb_set_vteimc(IGBCore
*core
, int index
, uint32_t val
)
2181 uint16_t vfn
= (index
- PVTEIMC0
) / 0x40;
2183 core
->mac
[index
] = val
;
2184 igb_set_eimc(core
, EIMC
, (val
& 0x7) << (22 - vfn
* IGBVF_MSIX_VEC_NUM
));
2187 static void igb_set_vteiac(IGBCore
*core
, int index
, uint32_t val
)
2189 uint16_t vfn
= (index
- PVTEIAC0
) / 0x40;
2191 core
->mac
[index
] = val
;
2192 igb_set_eiac(core
, EIAC
, (val
& 0x7) << (22 - vfn
* IGBVF_MSIX_VEC_NUM
));
2195 static void igb_set_vteiam(IGBCore
*core
, int index
, uint32_t val
)
2197 uint16_t vfn
= (index
- PVTEIAM0
) / 0x40;
2199 core
->mac
[index
] = val
;
2200 igb_set_eiam(core
, EIAM
, (val
& 0x7) << (22 - vfn
* IGBVF_MSIX_VEC_NUM
));
2203 static void igb_set_vteicr(IGBCore
*core
, int index
, uint32_t val
)
2205 uint16_t vfn
= (index
- PVTEICR0
) / 0x40;
2207 core
->mac
[index
] = val
;
2208 igb_set_eicr(core
, EICR
, (val
& 0x7) << (22 - vfn
* IGBVF_MSIX_VEC_NUM
));
2211 static void igb_set_vtivar(IGBCore
*core
, int index
, uint32_t val
)
2213 uint16_t vfn
= (index
- VTIVAR
);
2218 core
->mac
[index
] = val
;
2220 /* Get assigned vector associated with queue Rx#0. */
2221 if ((val
& E1000_IVAR_VALID
)) {
2222 n
= igb_ivar_entry_rx(qn
);
2223 ent
= E1000_IVAR_VALID
| (24 - vfn
* IGBVF_MSIX_VEC_NUM
- (2 - (val
& 0x7)));
2224 core
->mac
[IVAR0
+ n
/ 4] |= ent
<< 8 * (n
% 4);
2227 /* Get assigned vector associated with queue Tx#0 */
2229 if ((ent
& E1000_IVAR_VALID
)) {
2230 n
= igb_ivar_entry_tx(qn
);
2231 ent
= E1000_IVAR_VALID
| (24 - vfn
* IGBVF_MSIX_VEC_NUM
- (2 - (ent
& 0x7)));
2232 core
->mac
[IVAR0
+ n
/ 4] |= ent
<< 8 * (n
% 4);
2236 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now.
2241 igb_autoneg_timer(void *opaque
)
2243 IGBCore
*core
= opaque
;
2244 if (!qemu_get_queue(core
->owner_nic
)->link_down
) {
2245 e1000x_update_regs_on_autoneg_done(core
->mac
, core
->phy
);
2246 igb_start_recv(core
);
2248 igb_update_flowctl_status(core
);
2249 /* signal link status change to the guest */
2250 igb_set_interrupt_cause(core
, E1000_ICR_LSC
);
2254 static inline uint16_t
2255 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access
, hwaddr addr
)
2257 uint16_t index
= (addr
& 0x1ffff) >> 2;
2258 return index
+ (mac_reg_access
[index
] & 0xfffe);
2261 static const char igb_phy_regcap
[MAX_PHY_REG_ADDRESS
+ 1] = {
2262 [MII_BMCR
] = PHY_RW
,
2264 [MII_PHYID1
] = PHY_R
,
2265 [MII_PHYID2
] = PHY_R
,
2266 [MII_ANAR
] = PHY_RW
,
2267 [MII_ANLPAR
] = PHY_R
,
2269 [MII_ANNP
] = PHY_RW
,
2270 [MII_ANLPRNP
] = PHY_R
,
2271 [MII_CTRL1000
] = PHY_RW
,
2272 [MII_STAT1000
] = PHY_R
,
2273 [MII_EXTSTAT
] = PHY_R
,
2275 [IGP01E1000_PHY_PORT_CONFIG
] = PHY_RW
,
2276 [IGP01E1000_PHY_PORT_STATUS
] = PHY_R
,
2277 [IGP01E1000_PHY_PORT_CTRL
] = PHY_RW
,
2278 [IGP01E1000_PHY_LINK_HEALTH
] = PHY_R
,
2279 [IGP02E1000_PHY_POWER_MGMT
] = PHY_RW
,
2280 [IGP01E1000_PHY_PAGE_SELECT
] = PHY_W
2284 igb_phy_reg_write(IGBCore
*core
, uint32_t addr
, uint16_t data
)
2286 assert(addr
<= MAX_PHY_REG_ADDRESS
);
2288 if (addr
== MII_BMCR
) {
2289 igb_set_phy_ctrl(core
, data
);
2291 core
->phy
[addr
] = data
;
2296 igb_set_mdic(IGBCore
*core
, int index
, uint32_t val
)
2298 uint32_t data
= val
& E1000_MDIC_DATA_MASK
;
2299 uint32_t addr
= ((val
& E1000_MDIC_REG_MASK
) >> E1000_MDIC_REG_SHIFT
);
2301 if ((val
& E1000_MDIC_PHY_MASK
) >> E1000_MDIC_PHY_SHIFT
!= 1) { /* phy # */
2302 val
= core
->mac
[MDIC
] | E1000_MDIC_ERROR
;
2303 } else if (val
& E1000_MDIC_OP_READ
) {
2304 if (!(igb_phy_regcap
[addr
] & PHY_R
)) {
2305 trace_igb_core_mdic_read_unhandled(addr
);
2306 val
|= E1000_MDIC_ERROR
;
2308 val
= (val
^ data
) | core
->phy
[addr
];
2309 trace_igb_core_mdic_read(addr
, val
);
2311 } else if (val
& E1000_MDIC_OP_WRITE
) {
2312 if (!(igb_phy_regcap
[addr
] & PHY_W
)) {
2313 trace_igb_core_mdic_write_unhandled(addr
);
2314 val
|= E1000_MDIC_ERROR
;
2316 trace_igb_core_mdic_write(addr
, data
);
2317 igb_phy_reg_write(core
, addr
, data
);
2320 core
->mac
[MDIC
] = val
| E1000_MDIC_READY
;
2322 if (val
& E1000_MDIC_INT_EN
) {
2323 igb_set_interrupt_cause(core
, E1000_ICR_MDAC
);
2328 igb_set_rdt(IGBCore
*core
, int index
, uint32_t val
)
2330 core
->mac
[index
] = val
& 0xffff;
2331 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0
, index
), val
);
2332 igb_start_recv(core
);
2336 igb_set_status(IGBCore
*core
, int index
, uint32_t val
)
2338 if ((val
& E1000_STATUS_PHYRA
) == 0) {
2339 core
->mac
[index
] &= ~E1000_STATUS_PHYRA
;
2344 igb_set_ctrlext(IGBCore
*core
, int index
, uint32_t val
)
2346 trace_igb_link_set_ext_params(!!(val
& E1000_CTRL_EXT_ASDCHK
),
2347 !!(val
& E1000_CTRL_EXT_SPD_BYPS
),
2348 !!(val
& E1000_CTRL_EXT_PFRSTD
));
2350 /* Zero self-clearing bits */
2351 val
&= ~(E1000_CTRL_EXT_ASDCHK
| E1000_CTRL_EXT_EE_RST
);
2352 core
->mac
[CTRL_EXT
] = val
;
2354 if (core
->mac
[CTRL_EXT
] & E1000_CTRL_EXT_PFRSTD
) {
2355 for (int vfn
= 0; vfn
< IGB_MAX_VF_FUNCTIONS
; vfn
++) {
2356 core
->mac
[V2PMAILBOX0
+ vfn
] &= ~E1000_V2PMAILBOX_RSTI
;
2357 core
->mac
[V2PMAILBOX0
+ vfn
] |= E1000_V2PMAILBOX_RSTD
;
2363 igb_set_pbaclr(IGBCore
*core
, int index
, uint32_t val
)
2367 core
->mac
[PBACLR
] = val
& E1000_PBACLR_VALID_MASK
;
2369 if (!msix_enabled(core
->owner
)) {
2373 for (i
= 0; i
< IGB_INTR_NUM
; i
++) {
2374 if (core
->mac
[PBACLR
] & BIT(i
)) {
2375 msix_clr_pending(core
->owner
, i
);
2381 igb_set_fcrth(IGBCore
*core
, int index
, uint32_t val
)
2383 core
->mac
[FCRTH
] = val
& 0xFFF8;
2387 igb_set_fcrtl(IGBCore
*core
, int index
, uint32_t val
)
2389 core
->mac
[FCRTL
] = val
& 0x8000FFF8;
2392 #define IGB_LOW_BITS_SET_FUNC(num) \
2394 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \
2396 core->mac[index] = val & (BIT(num) - 1); \
2399 IGB_LOW_BITS_SET_FUNC(4)
2400 IGB_LOW_BITS_SET_FUNC(13)
2401 IGB_LOW_BITS_SET_FUNC(16)
2404 igb_set_dlen(IGBCore
*core
, int index
, uint32_t val
)
2406 core
->mac
[index
] = val
& 0xffff0;
2410 igb_set_dbal(IGBCore
*core
, int index
, uint32_t val
)
2412 core
->mac
[index
] = val
& E1000_XDBAL_MASK
;
2416 igb_set_tdt(IGBCore
*core
, int index
, uint32_t val
)
2419 int qn
= igb_mq_queue_idx(TDT0
, index
);
2421 core
->mac
[index
] = val
& 0xffff;
2423 igb_tx_ring_init(core
, &txr
, qn
);
2424 igb_start_xmit(core
, &txr
);
2428 igb_set_ics(IGBCore
*core
, int index
, uint32_t val
)
2430 trace_e1000e_irq_write_ics(val
);
2431 igb_set_interrupt_cause(core
, val
);
2435 igb_set_imc(IGBCore
*core
, int index
, uint32_t val
)
2437 trace_e1000e_irq_ims_clear_set_imc(val
);
2438 igb_clear_ims_bits(core
, val
);
2439 igb_update_interrupt_state(core
);
2443 igb_set_ims(IGBCore
*core
, int index
, uint32_t val
)
2445 uint32_t valid_val
= val
& 0x77D4FBFD;
2447 trace_e1000e_irq_set_ims(val
, core
->mac
[IMS
], core
->mac
[IMS
] | valid_val
);
2448 core
->mac
[IMS
] |= valid_val
;
2449 igb_update_interrupt_state(core
);
2452 static void igb_commit_icr(IGBCore
*core
)
2455 * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at
2456 * least one bit is set in the IMS and there is a true interrupt as
2457 * reflected in ICR.INTA.
2459 if ((core
->mac
[GPIE
] & E1000_GPIE_NSICR
) ||
2460 (core
->mac
[IMS
] && (core
->mac
[ICR
] & E1000_ICR_INT_ASSERTED
))) {
2461 igb_set_ims(core
, IMS
, core
->mac
[IAM
]);
2463 igb_update_interrupt_state(core
);
2467 static void igb_set_icr(IGBCore
*core
, int index
, uint32_t val
)
2469 uint32_t icr
= core
->mac
[ICR
] & ~val
;
2471 trace_igb_irq_icr_write(val
, core
->mac
[ICR
], icr
);
2472 core
->mac
[ICR
] = icr
;
2473 igb_commit_icr(core
);
2477 igb_mac_readreg(IGBCore
*core
, int index
)
2479 return core
->mac
[index
];
2483 igb_mac_ics_read(IGBCore
*core
, int index
)
2485 trace_e1000e_irq_read_ics(core
->mac
[ICS
]);
2486 return core
->mac
[ICS
];
2490 igb_mac_ims_read(IGBCore
*core
, int index
)
2492 trace_e1000e_irq_read_ims(core
->mac
[IMS
]);
2493 return core
->mac
[IMS
];
2497 igb_mac_swsm_read(IGBCore
*core
, int index
)
2499 uint32_t val
= core
->mac
[SWSM
];
2500 core
->mac
[SWSM
] = val
| E1000_SWSM_SMBI
;
2505 igb_mac_eitr_read(IGBCore
*core
, int index
)
2507 return core
->eitr_guest_value
[index
- EITR0
];
2510 static uint32_t igb_mac_vfmailbox_read(IGBCore
*core
, int index
)
2512 uint32_t val
= core
->mac
[index
];
2514 core
->mac
[index
] &= ~(E1000_V2PMAILBOX_PFSTS
| E1000_V2PMAILBOX_PFACK
|
2515 E1000_V2PMAILBOX_RSTD
);
2521 igb_mac_icr_read(IGBCore
*core
, int index
)
2523 uint32_t ret
= core
->mac
[ICR
];
2524 trace_e1000e_irq_icr_read_entry(ret
);
2526 if (core
->mac
[GPIE
] & E1000_GPIE_NSICR
) {
2527 trace_igb_irq_icr_clear_gpie_nsicr();
2529 } else if (core
->mac
[IMS
] == 0) {
2530 trace_e1000e_irq_icr_clear_zero_ims();
2532 } else if (!msix_enabled(core
->owner
)) {
2533 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2537 trace_e1000e_irq_icr_read_exit(core
->mac
[ICR
]);
2538 igb_commit_icr(core
);
2543 igb_mac_read_clr4(IGBCore
*core
, int index
)
2545 uint32_t ret
= core
->mac
[index
];
2547 core
->mac
[index
] = 0;
2552 igb_mac_read_clr8(IGBCore
*core
, int index
)
2554 uint32_t ret
= core
->mac
[index
];
2556 core
->mac
[index
] = 0;
2557 core
->mac
[index
- 1] = 0;
2562 igb_get_ctrl(IGBCore
*core
, int index
)
2564 uint32_t val
= core
->mac
[CTRL
];
2566 trace_e1000e_link_read_params(
2567 !!(val
& E1000_CTRL_ASDE
),
2568 (val
& E1000_CTRL_SPD_SEL
) >> E1000_CTRL_SPD_SHIFT
,
2569 !!(val
& E1000_CTRL_FRCSPD
),
2570 !!(val
& E1000_CTRL_FRCDPX
),
2571 !!(val
& E1000_CTRL_RFCE
),
2572 !!(val
& E1000_CTRL_TFCE
));
2577 static uint32_t igb_get_status(IGBCore
*core
, int index
)
2579 uint32_t res
= core
->mac
[STATUS
];
2580 uint16_t num_vfs
= pcie_sriov_num_vfs(core
->owner
);
2582 if (core
->mac
[CTRL
] & E1000_CTRL_FRCDPX
) {
2583 res
|= (core
->mac
[CTRL
] & E1000_CTRL_FD
) ? E1000_STATUS_FD
: 0;
2585 res
|= E1000_STATUS_FD
;
2588 if ((core
->mac
[CTRL
] & E1000_CTRL_FRCSPD
) ||
2589 (core
->mac
[CTRL_EXT
] & E1000_CTRL_EXT_SPD_BYPS
)) {
2590 switch (core
->mac
[CTRL
] & E1000_CTRL_SPD_SEL
) {
2591 case E1000_CTRL_SPD_10
:
2592 res
|= E1000_STATUS_SPEED_10
;
2594 case E1000_CTRL_SPD_100
:
2595 res
|= E1000_STATUS_SPEED_100
;
2597 case E1000_CTRL_SPD_1000
:
2599 res
|= E1000_STATUS_SPEED_1000
;
2603 res
|= E1000_STATUS_SPEED_1000
;
2607 res
|= num_vfs
<< E1000_STATUS_NUM_VFS_SHIFT
;
2608 res
|= E1000_STATUS_IOV_MODE
;
2612 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is
2613 * left set after E1000_CTRL_LRST is set.
2615 if (!(core
->mac
[CTRL
] & E1000_CTRL_GIO_MASTER_DISABLE
) &&
2616 !(core
->mac
[CTRL
] & E1000_CTRL_LRST
)) {
2617 res
|= E1000_STATUS_GIO_MASTER_ENABLE
;
2624 igb_mac_writereg(IGBCore
*core
, int index
, uint32_t val
)
2626 core
->mac
[index
] = val
;
2630 igb_mac_setmacaddr(IGBCore
*core
, int index
, uint32_t val
)
2632 uint32_t macaddr
[2];
2634 core
->mac
[index
] = val
;
2636 macaddr
[0] = cpu_to_le32(core
->mac
[RA
]);
2637 macaddr
[1] = cpu_to_le32(core
->mac
[RA
+ 1]);
2638 qemu_format_nic_info_str(qemu_get_queue(core
->owner_nic
),
2639 (uint8_t *) macaddr
);
2641 trace_e1000e_mac_set_sw(MAC_ARG(macaddr
));
2645 igb_set_eecd(IGBCore
*core
, int index
, uint32_t val
)
2647 static const uint32_t ro_bits
= E1000_EECD_PRES
|
2648 E1000_EECD_AUTO_RD
|
2649 E1000_EECD_SIZE_EX_MASK
;
2651 core
->mac
[EECD
] = (core
->mac
[EECD
] & ro_bits
) | (val
& ~ro_bits
);
2655 igb_set_eerd(IGBCore
*core
, int index
, uint32_t val
)
2657 uint32_t addr
= (val
>> E1000_EERW_ADDR_SHIFT
) & E1000_EERW_ADDR_MASK
;
2661 if ((addr
< IGB_EEPROM_SIZE
) && (val
& E1000_EERW_START
)) {
2662 data
= core
->eeprom
[addr
];
2663 flags
= E1000_EERW_DONE
;
2666 core
->mac
[EERD
] = flags
|
2667 (addr
<< E1000_EERW_ADDR_SHIFT
) |
2668 (data
<< E1000_EERW_DATA_SHIFT
);
2672 igb_set_eitr(IGBCore
*core
, int index
, uint32_t val
)
2674 uint32_t eitr_num
= index
- EITR0
;
2676 trace_igb_irq_eitr_set(eitr_num
, val
);
2678 core
->eitr_guest_value
[eitr_num
] = val
& ~E1000_EITR_CNT_IGNR
;
2679 core
->mac
[index
] = val
& 0x7FFE;
2683 igb_update_rx_offloads(IGBCore
*core
)
2685 int cso_state
= igb_rx_l4_cso_enabled(core
);
2687 trace_e1000e_rx_set_cso(cso_state
);
2689 if (core
->has_vnet
) {
2690 qemu_set_offload(qemu_get_queue(core
->owner_nic
)->peer
,
2691 cso_state
, 0, 0, 0, 0);
2696 igb_set_rxcsum(IGBCore
*core
, int index
, uint32_t val
)
2698 core
->mac
[RXCSUM
] = val
;
2699 igb_update_rx_offloads(core
);
2703 igb_set_gcr(IGBCore
*core
, int index
, uint32_t val
)
2705 uint32_t ro_bits
= core
->mac
[GCR
] & E1000_GCR_RO_BITS
;
2706 core
->mac
[GCR
] = (val
& ~E1000_GCR_RO_BITS
) | ro_bits
;
2709 static uint32_t igb_get_systiml(IGBCore
*core
, int index
)
2711 e1000x_timestamp(core
->mac
, core
->timadj
, SYSTIML
, SYSTIMH
);
2712 return core
->mac
[SYSTIML
];
2715 static uint32_t igb_get_rxsatrh(IGBCore
*core
, int index
)
2717 core
->mac
[TSYNCRXCTL
] &= ~E1000_TSYNCRXCTL_VALID
;
2718 return core
->mac
[RXSATRH
];
2721 static uint32_t igb_get_txstmph(IGBCore
*core
, int index
)
2723 core
->mac
[TSYNCTXCTL
] &= ~E1000_TSYNCTXCTL_VALID
;
2724 return core
->mac
[TXSTMPH
];
2727 static void igb_set_timinca(IGBCore
*core
, int index
, uint32_t val
)
2729 e1000x_set_timinca(core
->mac
, &core
->timadj
, val
);
2732 static void igb_set_timadjh(IGBCore
*core
, int index
, uint32_t val
)
2734 core
->mac
[TIMADJH
] = val
;
2735 core
->timadj
+= core
->mac
[TIMADJL
] | ((int64_t)core
->mac
[TIMADJH
] << 32);
2738 #define igb_getreg(x) [x] = igb_mac_readreg
2739 typedef uint32_t (*readops
)(IGBCore
*, int);
2740 static const readops igb_macreg_readops
[] = {
2770 igb_getreg(RDBAH10
),
2771 igb_getreg(RDBAH11
),
2772 igb_getreg(RDBAH12
),
2773 igb_getreg(RDBAH13
),
2774 igb_getreg(RDBAH14
),
2775 igb_getreg(RDBAH15
),
2786 igb_getreg(TDBAL10
),
2787 igb_getreg(TDBAL11
),
2788 igb_getreg(TDBAL12
),
2789 igb_getreg(TDBAL13
),
2790 igb_getreg(TDBAL14
),
2791 igb_getreg(TDBAL15
),
2802 igb_getreg(RDLEN10
),
2803 igb_getreg(RDLEN11
),
2804 igb_getreg(RDLEN12
),
2805 igb_getreg(RDLEN13
),
2806 igb_getreg(RDLEN14
),
2807 igb_getreg(RDLEN15
),
2808 igb_getreg(SRRCTL0
),
2809 igb_getreg(SRRCTL1
),
2810 igb_getreg(SRRCTL2
),
2811 igb_getreg(SRRCTL3
),
2812 igb_getreg(SRRCTL4
),
2813 igb_getreg(SRRCTL5
),
2814 igb_getreg(SRRCTL6
),
2815 igb_getreg(SRRCTL7
),
2816 igb_getreg(SRRCTL8
),
2817 igb_getreg(SRRCTL9
),
2818 igb_getreg(SRRCTL10
),
2819 igb_getreg(SRRCTL11
),
2820 igb_getreg(SRRCTL12
),
2821 igb_getreg(SRRCTL13
),
2822 igb_getreg(SRRCTL14
),
2823 igb_getreg(SRRCTL15
),
2824 igb_getreg(LATECOL
),
2848 igb_getreg(RXSTMPH
),
2849 igb_getreg(TXSTMPL
),
2850 igb_getreg(TIMADJL
),
2888 igb_getreg(FLMNGCTL
),
2889 igb_getreg(FLMNGCNT
),
2890 igb_getreg(TSYNCTXCTL
),
2891 igb_getreg(EEMNGDATA
),
2892 igb_getreg(CTRL_EXT
),
2893 igb_getreg(SYSTIMH
),
2894 igb_getreg(EEMNGCTL
),
2895 igb_getreg(FLMNGDATA
),
2896 igb_getreg(TSYNCRXCTL
),
2899 igb_getreg(TCTL_EXT
),
2921 igb_getreg(XOFFTXC
),
2925 igb_getreg(TIMINCA
),
2931 igb_getreg(RXSATRL
),
2943 igb_getreg(TDLEN10
),
2944 igb_getreg(TDLEN11
),
2945 igb_getreg(TDLEN12
),
2946 igb_getreg(TDLEN13
),
2947 igb_getreg(TDLEN14
),
2948 igb_getreg(TDLEN15
),
2953 igb_getreg(TXDCTL0
),
2954 igb_getreg(TXDCTL1
),
2955 igb_getreg(TXDCTL2
),
2956 igb_getreg(TXDCTL3
),
2957 igb_getreg(TXDCTL4
),
2958 igb_getreg(TXDCTL5
),
2959 igb_getreg(TXDCTL6
),
2960 igb_getreg(TXDCTL7
),
2961 igb_getreg(TXDCTL8
),
2962 igb_getreg(TXDCTL9
),
2963 igb_getreg(TXDCTL10
),
2964 igb_getreg(TXDCTL11
),
2965 igb_getreg(TXDCTL12
),
2966 igb_getreg(TXDCTL13
),
2967 igb_getreg(TXDCTL14
),
2968 igb_getreg(TXDCTL15
),
2979 igb_getreg(TXCTL10
),
2980 igb_getreg(TXCTL11
),
2981 igb_getreg(TXCTL12
),
2982 igb_getreg(TXCTL13
),
2983 igb_getreg(TXCTL14
),
2984 igb_getreg(TXCTL15
),
2985 igb_getreg(TDWBAL0
),
2986 igb_getreg(TDWBAL1
),
2987 igb_getreg(TDWBAL2
),
2988 igb_getreg(TDWBAL3
),
2989 igb_getreg(TDWBAL4
),
2990 igb_getreg(TDWBAL5
),
2991 igb_getreg(TDWBAL6
),
2992 igb_getreg(TDWBAL7
),
2993 igb_getreg(TDWBAL8
),
2994 igb_getreg(TDWBAL9
),
2995 igb_getreg(TDWBAL10
),
2996 igb_getreg(TDWBAL11
),
2997 igb_getreg(TDWBAL12
),
2998 igb_getreg(TDWBAL13
),
2999 igb_getreg(TDWBAL14
),
3000 igb_getreg(TDWBAL15
),
3001 igb_getreg(TDWBAH0
),
3002 igb_getreg(TDWBAH1
),
3003 igb_getreg(TDWBAH2
),
3004 igb_getreg(TDWBAH3
),
3005 igb_getreg(TDWBAH4
),
3006 igb_getreg(TDWBAH5
),
3007 igb_getreg(TDWBAH6
),
3008 igb_getreg(TDWBAH7
),
3009 igb_getreg(TDWBAH8
),
3010 igb_getreg(TDWBAH9
),
3011 igb_getreg(TDWBAH10
),
3012 igb_getreg(TDWBAH11
),
3013 igb_getreg(TDWBAH12
),
3014 igb_getreg(TDWBAH13
),
3015 igb_getreg(TDWBAH14
),
3016 igb_getreg(TDWBAH15
),
3017 igb_getreg(PVTCTRL0
),
3018 igb_getreg(PVTCTRL1
),
3019 igb_getreg(PVTCTRL2
),
3020 igb_getreg(PVTCTRL3
),
3021 igb_getreg(PVTCTRL4
),
3022 igb_getreg(PVTCTRL5
),
3023 igb_getreg(PVTCTRL6
),
3024 igb_getreg(PVTCTRL7
),
3025 igb_getreg(PVTEIMS0
),
3026 igb_getreg(PVTEIMS1
),
3027 igb_getreg(PVTEIMS2
),
3028 igb_getreg(PVTEIMS3
),
3029 igb_getreg(PVTEIMS4
),
3030 igb_getreg(PVTEIMS5
),
3031 igb_getreg(PVTEIMS6
),
3032 igb_getreg(PVTEIMS7
),
3033 igb_getreg(PVTEIAC0
),
3034 igb_getreg(PVTEIAC1
),
3035 igb_getreg(PVTEIAC2
),
3036 igb_getreg(PVTEIAC3
),
3037 igb_getreg(PVTEIAC4
),
3038 igb_getreg(PVTEIAC5
),
3039 igb_getreg(PVTEIAC6
),
3040 igb_getreg(PVTEIAC7
),
3041 igb_getreg(PVTEIAM0
),
3042 igb_getreg(PVTEIAM1
),
3043 igb_getreg(PVTEIAM2
),
3044 igb_getreg(PVTEIAM3
),
3045 igb_getreg(PVTEIAM4
),
3046 igb_getreg(PVTEIAM5
),
3047 igb_getreg(PVTEIAM6
),
3048 igb_getreg(PVTEIAM7
),
3049 igb_getreg(PVFGPRC0
),
3050 igb_getreg(PVFGPRC1
),
3051 igb_getreg(PVFGPRC2
),
3052 igb_getreg(PVFGPRC3
),
3053 igb_getreg(PVFGPRC4
),
3054 igb_getreg(PVFGPRC5
),
3055 igb_getreg(PVFGPRC6
),
3056 igb_getreg(PVFGPRC7
),
3057 igb_getreg(PVFGPTC0
),
3058 igb_getreg(PVFGPTC1
),
3059 igb_getreg(PVFGPTC2
),
3060 igb_getreg(PVFGPTC3
),
3061 igb_getreg(PVFGPTC4
),
3062 igb_getreg(PVFGPTC5
),
3063 igb_getreg(PVFGPTC6
),
3064 igb_getreg(PVFGPTC7
),
3065 igb_getreg(PVFGORC0
),
3066 igb_getreg(PVFGORC1
),
3067 igb_getreg(PVFGORC2
),
3068 igb_getreg(PVFGORC3
),
3069 igb_getreg(PVFGORC4
),
3070 igb_getreg(PVFGORC5
),
3071 igb_getreg(PVFGORC6
),
3072 igb_getreg(PVFGORC7
),
3073 igb_getreg(PVFGOTC0
),
3074 igb_getreg(PVFGOTC1
),
3075 igb_getreg(PVFGOTC2
),
3076 igb_getreg(PVFGOTC3
),
3077 igb_getreg(PVFGOTC4
),
3078 igb_getreg(PVFGOTC5
),
3079 igb_getreg(PVFGOTC6
),
3080 igb_getreg(PVFGOTC7
),
3081 igb_getreg(PVFMPRC0
),
3082 igb_getreg(PVFMPRC1
),
3083 igb_getreg(PVFMPRC2
),
3084 igb_getreg(PVFMPRC3
),
3085 igb_getreg(PVFMPRC4
),
3086 igb_getreg(PVFMPRC5
),
3087 igb_getreg(PVFMPRC6
),
3088 igb_getreg(PVFMPRC7
),
3089 igb_getreg(PVFGPRLBC0
),
3090 igb_getreg(PVFGPRLBC1
),
3091 igb_getreg(PVFGPRLBC2
),
3092 igb_getreg(PVFGPRLBC3
),
3093 igb_getreg(PVFGPRLBC4
),
3094 igb_getreg(PVFGPRLBC5
),
3095 igb_getreg(PVFGPRLBC6
),
3096 igb_getreg(PVFGPRLBC7
),
3097 igb_getreg(PVFGPTLBC0
),
3098 igb_getreg(PVFGPTLBC1
),
3099 igb_getreg(PVFGPTLBC2
),
3100 igb_getreg(PVFGPTLBC3
),
3101 igb_getreg(PVFGPTLBC4
),
3102 igb_getreg(PVFGPTLBC5
),
3103 igb_getreg(PVFGPTLBC6
),
3104 igb_getreg(PVFGPTLBC7
),
3105 igb_getreg(PVFGORLBC0
),
3106 igb_getreg(PVFGORLBC1
),
3107 igb_getreg(PVFGORLBC2
),
3108 igb_getreg(PVFGORLBC3
),
3109 igb_getreg(PVFGORLBC4
),
3110 igb_getreg(PVFGORLBC5
),
3111 igb_getreg(PVFGORLBC6
),
3112 igb_getreg(PVFGORLBC7
),
3113 igb_getreg(PVFGOTLBC0
),
3114 igb_getreg(PVFGOTLBC1
),
3115 igb_getreg(PVFGOTLBC2
),
3116 igb_getreg(PVFGOTLBC3
),
3117 igb_getreg(PVFGOTLBC4
),
3118 igb_getreg(PVFGOTLBC5
),
3119 igb_getreg(PVFGOTLBC6
),
3120 igb_getreg(PVFGOTLBC7
),
3135 igb_getreg(RDBAL10
),
3136 igb_getreg(RDBAL11
),
3137 igb_getreg(RDBAL12
),
3138 igb_getreg(RDBAL13
),
3139 igb_getreg(RDBAL14
),
3140 igb_getreg(RDBAL15
),
3151 igb_getreg(TDBAH10
),
3152 igb_getreg(TDBAH11
),
3153 igb_getreg(TDBAH12
),
3154 igb_getreg(TDBAH13
),
3155 igb_getreg(TDBAH14
),
3156 igb_getreg(TDBAH15
),
3159 igb_getreg(XOFFRXC
),
3165 igb_getreg(FUNCTAG
),
3171 igb_getreg(RXDCTL0
),
3172 igb_getreg(RXDCTL1
),
3173 igb_getreg(RXDCTL2
),
3174 igb_getreg(RXDCTL3
),
3175 igb_getreg(RXDCTL4
),
3176 igb_getreg(RXDCTL5
),
3177 igb_getreg(RXDCTL6
),
3178 igb_getreg(RXDCTL7
),
3179 igb_getreg(RXDCTL8
),
3180 igb_getreg(RXDCTL9
),
3181 igb_getreg(RXDCTL10
),
3182 igb_getreg(RXDCTL11
),
3183 igb_getreg(RXDCTL12
),
3184 igb_getreg(RXDCTL13
),
3185 igb_getreg(RXDCTL14
),
3186 igb_getreg(RXDCTL15
),
3187 igb_getreg(RXSTMPL
),
3188 igb_getreg(TIMADJH
),
3198 [TOTH
] = igb_mac_read_clr8
,
3199 [GOTCH
] = igb_mac_read_clr8
,
3200 [PRC64
] = igb_mac_read_clr4
,
3201 [PRC255
] = igb_mac_read_clr4
,
3202 [PRC1023
] = igb_mac_read_clr4
,
3203 [PTC64
] = igb_mac_read_clr4
,
3204 [PTC255
] = igb_mac_read_clr4
,
3205 [PTC1023
] = igb_mac_read_clr4
,
3206 [GPRC
] = igb_mac_read_clr4
,
3207 [TPT
] = igb_mac_read_clr4
,
3208 [RUC
] = igb_mac_read_clr4
,
3209 [BPRC
] = igb_mac_read_clr4
,
3210 [MPTC
] = igb_mac_read_clr4
,
3211 [IAC
] = igb_mac_read_clr4
,
3212 [ICR
] = igb_mac_icr_read
,
3213 [STATUS
] = igb_get_status
,
3214 [ICS
] = igb_mac_ics_read
,
3216 * 8.8.10: Reading the IMC register returns the value of the IMS register.
3218 [IMC
] = igb_mac_ims_read
,
3219 [TORH
] = igb_mac_read_clr8
,
3220 [GORCH
] = igb_mac_read_clr8
,
3221 [PRC127
] = igb_mac_read_clr4
,
3222 [PRC511
] = igb_mac_read_clr4
,
3223 [PRC1522
] = igb_mac_read_clr4
,
3224 [PTC127
] = igb_mac_read_clr4
,
3225 [PTC511
] = igb_mac_read_clr4
,
3226 [PTC1522
] = igb_mac_read_clr4
,
3227 [GPTC
] = igb_mac_read_clr4
,
3228 [TPR
] = igb_mac_read_clr4
,
3229 [ROC
] = igb_mac_read_clr4
,
3230 [MPRC
] = igb_mac_read_clr4
,
3231 [BPTC
] = igb_mac_read_clr4
,
3232 [TSCTC
] = igb_mac_read_clr4
,
3233 [CTRL
] = igb_get_ctrl
,
3234 [SWSM
] = igb_mac_swsm_read
,
3235 [IMS
] = igb_mac_ims_read
,
3236 [SYSTIML
] = igb_get_systiml
,
3237 [RXSATRH
] = igb_get_rxsatrh
,
3238 [TXSTMPH
] = igb_get_txstmph
,
3240 [CRCERRS
... MPC
] = igb_mac_readreg
,
3241 [IP6AT
... IP6AT
+ 3] = igb_mac_readreg
,
3242 [IP4AT
... IP4AT
+ 6] = igb_mac_readreg
,
3243 [RA
... RA
+ 31] = igb_mac_readreg
,
3244 [RA2
... RA2
+ 31] = igb_mac_readreg
,
3245 [WUPM
... WUPM
+ 31] = igb_mac_readreg
,
3246 [MTA
... MTA
+ E1000_MC_TBL_SIZE
- 1] = igb_mac_readreg
,
3247 [VFTA
... VFTA
+ E1000_VLAN_FILTER_TBL_SIZE
- 1] = igb_mac_readreg
,
3248 [FFMT
... FFMT
+ 254] = igb_mac_readreg
,
3249 [MDEF
... MDEF
+ 7] = igb_mac_readreg
,
3250 [FTFT
... FTFT
+ 254] = igb_mac_readreg
,
3251 [RETA
... RETA
+ 31] = igb_mac_readreg
,
3252 [RSSRK
... RSSRK
+ 9] = igb_mac_readreg
,
3253 [MAVTV0
... MAVTV3
] = igb_mac_readreg
,
3254 [EITR0
... EITR0
+ IGB_INTR_NUM
- 1] = igb_mac_eitr_read
,
3255 [PVTEICR0
] = igb_mac_read_clr4
,
3256 [PVTEICR1
] = igb_mac_read_clr4
,
3257 [PVTEICR2
] = igb_mac_read_clr4
,
3258 [PVTEICR3
] = igb_mac_read_clr4
,
3259 [PVTEICR4
] = igb_mac_read_clr4
,
3260 [PVTEICR5
] = igb_mac_read_clr4
,
3261 [PVTEICR6
] = igb_mac_read_clr4
,
3262 [PVTEICR7
] = igb_mac_read_clr4
,
3265 [FWSM
] = igb_mac_readreg
,
3266 [SW_FW_SYNC
] = igb_mac_readreg
,
3267 [HTCBDPC
] = igb_mac_read_clr4
,
3268 [EICR
] = igb_mac_read_clr4
,
3269 [EIMS
] = igb_mac_readreg
,
3270 [EIAM
] = igb_mac_readreg
,
3271 [IVAR0
... IVAR0
+ 7] = igb_mac_readreg
,
3272 igb_getreg(IVAR_MISC
),
3274 [P2VMAILBOX0
... P2VMAILBOX7
] = igb_mac_readreg
,
3275 [V2PMAILBOX0
... V2PMAILBOX7
] = igb_mac_vfmailbox_read
,
3276 igb_getreg(MBVFICR
),
3277 [VMBMEM0
... VMBMEM0
+ 127] = igb_mac_readreg
,
3278 igb_getreg(MBVFIMR
),
3285 [VLVF0
... VLVF0
+ E1000_VLVF_ARRAY_SIZE
- 1] = igb_mac_readreg
,
3286 [VMVIR0
... VMVIR7
] = igb_mac_readreg
,
3287 [VMOLR0
... VMOLR7
] = igb_mac_readreg
,
3288 [WVBR
] = igb_mac_read_clr4
,
3289 [RQDPC0
] = igb_mac_read_clr4
,
3290 [RQDPC1
] = igb_mac_read_clr4
,
3291 [RQDPC2
] = igb_mac_read_clr4
,
3292 [RQDPC3
] = igb_mac_read_clr4
,
3293 [RQDPC4
] = igb_mac_read_clr4
,
3294 [RQDPC5
] = igb_mac_read_clr4
,
3295 [RQDPC6
] = igb_mac_read_clr4
,
3296 [RQDPC7
] = igb_mac_read_clr4
,
3297 [RQDPC8
] = igb_mac_read_clr4
,
3298 [RQDPC9
] = igb_mac_read_clr4
,
3299 [RQDPC10
] = igb_mac_read_clr4
,
3300 [RQDPC11
] = igb_mac_read_clr4
,
3301 [RQDPC12
] = igb_mac_read_clr4
,
3302 [RQDPC13
] = igb_mac_read_clr4
,
3303 [RQDPC14
] = igb_mac_read_clr4
,
3304 [RQDPC15
] = igb_mac_read_clr4
,
3305 [VTIVAR
... VTIVAR
+ 7] = igb_mac_readreg
,
3306 [VTIVAR_MISC
... VTIVAR_MISC
+ 7] = igb_mac_readreg
,
3308 enum { IGB_NREADOPS
= ARRAY_SIZE(igb_macreg_readops
) };
3310 #define igb_putreg(x) [x] = igb_mac_writereg
3311 typedef void (*writeops
)(IGBCore
*, int, uint32_t);
3312 static const writeops igb_macreg_writeops
[] = {
3325 igb_putreg(RDBAH10
),
3326 igb_putreg(RDBAH11
),
3327 igb_putreg(RDBAH12
),
3328 igb_putreg(RDBAH13
),
3329 igb_putreg(RDBAH14
),
3330 igb_putreg(RDBAH15
),
3331 igb_putreg(SRRCTL0
),
3332 igb_putreg(SRRCTL1
),
3333 igb_putreg(SRRCTL2
),
3334 igb_putreg(SRRCTL3
),
3335 igb_putreg(SRRCTL4
),
3336 igb_putreg(SRRCTL5
),
3337 igb_putreg(SRRCTL6
),
3338 igb_putreg(SRRCTL7
),
3339 igb_putreg(SRRCTL8
),
3340 igb_putreg(SRRCTL9
),
3341 igb_putreg(SRRCTL10
),
3342 igb_putreg(SRRCTL11
),
3343 igb_putreg(SRRCTL12
),
3344 igb_putreg(SRRCTL13
),
3345 igb_putreg(SRRCTL14
),
3346 igb_putreg(SRRCTL15
),
3347 igb_putreg(RXDCTL0
),
3348 igb_putreg(RXDCTL1
),
3349 igb_putreg(RXDCTL2
),
3350 igb_putreg(RXDCTL3
),
3351 igb_putreg(RXDCTL4
),
3352 igb_putreg(RXDCTL5
),
3353 igb_putreg(RXDCTL6
),
3354 igb_putreg(RXDCTL7
),
3355 igb_putreg(RXDCTL8
),
3356 igb_putreg(RXDCTL9
),
3357 igb_putreg(RXDCTL10
),
3358 igb_putreg(RXDCTL11
),
3359 igb_putreg(RXDCTL12
),
3360 igb_putreg(RXDCTL13
),
3361 igb_putreg(RXDCTL14
),
3362 igb_putreg(RXDCTL15
),
3365 igb_putreg(TCTL_EXT
),
3384 igb_putreg(TDBAH10
),
3385 igb_putreg(TDBAH11
),
3386 igb_putreg(TDBAH12
),
3387 igb_putreg(TDBAH13
),
3388 igb_putreg(TDBAH14
),
3389 igb_putreg(TDBAH15
),
3395 igb_putreg(FUNCTAG
),
3407 igb_putreg(TXDCTL0
),
3408 igb_putreg(TXDCTL1
),
3409 igb_putreg(TXDCTL2
),
3410 igb_putreg(TXDCTL3
),
3411 igb_putreg(TXDCTL4
),
3412 igb_putreg(TXDCTL5
),
3413 igb_putreg(TXDCTL6
),
3414 igb_putreg(TXDCTL7
),
3415 igb_putreg(TXDCTL8
),
3416 igb_putreg(TXDCTL9
),
3417 igb_putreg(TXDCTL10
),
3418 igb_putreg(TXDCTL11
),
3419 igb_putreg(TXDCTL12
),
3420 igb_putreg(TXDCTL13
),
3421 igb_putreg(TXDCTL14
),
3422 igb_putreg(TXDCTL15
),
3433 igb_putreg(TXCTL10
),
3434 igb_putreg(TXCTL11
),
3435 igb_putreg(TXCTL12
),
3436 igb_putreg(TXCTL13
),
3437 igb_putreg(TXCTL14
),
3438 igb_putreg(TXCTL15
),
3439 igb_putreg(TDWBAL0
),
3440 igb_putreg(TDWBAL1
),
3441 igb_putreg(TDWBAL2
),
3442 igb_putreg(TDWBAL3
),
3443 igb_putreg(TDWBAL4
),
3444 igb_putreg(TDWBAL5
),
3445 igb_putreg(TDWBAL6
),
3446 igb_putreg(TDWBAL7
),
3447 igb_putreg(TDWBAL8
),
3448 igb_putreg(TDWBAL9
),
3449 igb_putreg(TDWBAL10
),
3450 igb_putreg(TDWBAL11
),
3451 igb_putreg(TDWBAL12
),
3452 igb_putreg(TDWBAL13
),
3453 igb_putreg(TDWBAL14
),
3454 igb_putreg(TDWBAL15
),
3455 igb_putreg(TDWBAH0
),
3456 igb_putreg(TDWBAH1
),
3457 igb_putreg(TDWBAH2
),
3458 igb_putreg(TDWBAH3
),
3459 igb_putreg(TDWBAH4
),
3460 igb_putreg(TDWBAH5
),
3461 igb_putreg(TDWBAH6
),
3462 igb_putreg(TDWBAH7
),
3463 igb_putreg(TDWBAH8
),
3464 igb_putreg(TDWBAH9
),
3465 igb_putreg(TDWBAH10
),
3466 igb_putreg(TDWBAH11
),
3467 igb_putreg(TDWBAH12
),
3468 igb_putreg(TDWBAH13
),
3469 igb_putreg(TDWBAH14
),
3470 igb_putreg(TDWBAH15
),
3472 igb_putreg(RXSTMPH
),
3473 igb_putreg(RXSTMPL
),
3474 igb_putreg(RXSATRL
),
3475 igb_putreg(RXSATRH
),
3476 igb_putreg(TXSTMPL
),
3477 igb_putreg(TXSTMPH
),
3478 igb_putreg(SYSTIML
),
3479 igb_putreg(SYSTIMH
),
3480 igb_putreg(TIMADJL
),
3481 igb_putreg(TSYNCRXCTL
),
3482 igb_putreg(TSYNCTXCTL
),
3483 igb_putreg(EEMNGCTL
),
3489 [TDH0
] = igb_set_16bit
,
3490 [TDH1
] = igb_set_16bit
,
3491 [TDH2
] = igb_set_16bit
,
3492 [TDH3
] = igb_set_16bit
,
3493 [TDH4
] = igb_set_16bit
,
3494 [TDH5
] = igb_set_16bit
,
3495 [TDH6
] = igb_set_16bit
,
3496 [TDH7
] = igb_set_16bit
,
3497 [TDH8
] = igb_set_16bit
,
3498 [TDH9
] = igb_set_16bit
,
3499 [TDH10
] = igb_set_16bit
,
3500 [TDH11
] = igb_set_16bit
,
3501 [TDH12
] = igb_set_16bit
,
3502 [TDH13
] = igb_set_16bit
,
3503 [TDH14
] = igb_set_16bit
,
3504 [TDH15
] = igb_set_16bit
,
3505 [TDT0
] = igb_set_tdt
,
3506 [TDT1
] = igb_set_tdt
,
3507 [TDT2
] = igb_set_tdt
,
3508 [TDT3
] = igb_set_tdt
,
3509 [TDT4
] = igb_set_tdt
,
3510 [TDT5
] = igb_set_tdt
,
3511 [TDT6
] = igb_set_tdt
,
3512 [TDT7
] = igb_set_tdt
,
3513 [TDT8
] = igb_set_tdt
,
3514 [TDT9
] = igb_set_tdt
,
3515 [TDT10
] = igb_set_tdt
,
3516 [TDT11
] = igb_set_tdt
,
3517 [TDT12
] = igb_set_tdt
,
3518 [TDT13
] = igb_set_tdt
,
3519 [TDT14
] = igb_set_tdt
,
3520 [TDT15
] = igb_set_tdt
,
3521 [MDIC
] = igb_set_mdic
,
3522 [ICS
] = igb_set_ics
,
3523 [RDH0
] = igb_set_16bit
,
3524 [RDH1
] = igb_set_16bit
,
3525 [RDH2
] = igb_set_16bit
,
3526 [RDH3
] = igb_set_16bit
,
3527 [RDH4
] = igb_set_16bit
,
3528 [RDH5
] = igb_set_16bit
,
3529 [RDH6
] = igb_set_16bit
,
3530 [RDH7
] = igb_set_16bit
,
3531 [RDH8
] = igb_set_16bit
,
3532 [RDH9
] = igb_set_16bit
,
3533 [RDH10
] = igb_set_16bit
,
3534 [RDH11
] = igb_set_16bit
,
3535 [RDH12
] = igb_set_16bit
,
3536 [RDH13
] = igb_set_16bit
,
3537 [RDH14
] = igb_set_16bit
,
3538 [RDH15
] = igb_set_16bit
,
3539 [RDT0
] = igb_set_rdt
,
3540 [RDT1
] = igb_set_rdt
,
3541 [RDT2
] = igb_set_rdt
,
3542 [RDT3
] = igb_set_rdt
,
3543 [RDT4
] = igb_set_rdt
,
3544 [RDT5
] = igb_set_rdt
,
3545 [RDT6
] = igb_set_rdt
,
3546 [RDT7
] = igb_set_rdt
,
3547 [RDT8
] = igb_set_rdt
,
3548 [RDT9
] = igb_set_rdt
,
3549 [RDT10
] = igb_set_rdt
,
3550 [RDT11
] = igb_set_rdt
,
3551 [RDT12
] = igb_set_rdt
,
3552 [RDT13
] = igb_set_rdt
,
3553 [RDT14
] = igb_set_rdt
,
3554 [RDT15
] = igb_set_rdt
,
3555 [IMC
] = igb_set_imc
,
3556 [IMS
] = igb_set_ims
,
3557 [ICR
] = igb_set_icr
,
3558 [EECD
] = igb_set_eecd
,
3559 [RCTL
] = igb_set_rx_control
,
3560 [CTRL
] = igb_set_ctrl
,
3561 [EERD
] = igb_set_eerd
,
3562 [TDFH
] = igb_set_13bit
,
3563 [TDFT
] = igb_set_13bit
,
3564 [TDFHS
] = igb_set_13bit
,
3565 [TDFTS
] = igb_set_13bit
,
3566 [TDFPC
] = igb_set_13bit
,
3567 [RDFH
] = igb_set_13bit
,
3568 [RDFT
] = igb_set_13bit
,
3569 [RDFHS
] = igb_set_13bit
,
3570 [RDFTS
] = igb_set_13bit
,
3571 [RDFPC
] = igb_set_13bit
,
3572 [GCR
] = igb_set_gcr
,
3573 [RXCSUM
] = igb_set_rxcsum
,
3574 [TDLEN0
] = igb_set_dlen
,
3575 [TDLEN1
] = igb_set_dlen
,
3576 [TDLEN2
] = igb_set_dlen
,
3577 [TDLEN3
] = igb_set_dlen
,
3578 [TDLEN4
] = igb_set_dlen
,
3579 [TDLEN5
] = igb_set_dlen
,
3580 [TDLEN6
] = igb_set_dlen
,
3581 [TDLEN7
] = igb_set_dlen
,
3582 [TDLEN8
] = igb_set_dlen
,
3583 [TDLEN9
] = igb_set_dlen
,
3584 [TDLEN10
] = igb_set_dlen
,
3585 [TDLEN11
] = igb_set_dlen
,
3586 [TDLEN12
] = igb_set_dlen
,
3587 [TDLEN13
] = igb_set_dlen
,
3588 [TDLEN14
] = igb_set_dlen
,
3589 [TDLEN15
] = igb_set_dlen
,
3590 [RDLEN0
] = igb_set_dlen
,
3591 [RDLEN1
] = igb_set_dlen
,
3592 [RDLEN2
] = igb_set_dlen
,
3593 [RDLEN3
] = igb_set_dlen
,
3594 [RDLEN4
] = igb_set_dlen
,
3595 [RDLEN5
] = igb_set_dlen
,
3596 [RDLEN6
] = igb_set_dlen
,
3597 [RDLEN7
] = igb_set_dlen
,
3598 [RDLEN8
] = igb_set_dlen
,
3599 [RDLEN9
] = igb_set_dlen
,
3600 [RDLEN10
] = igb_set_dlen
,
3601 [RDLEN11
] = igb_set_dlen
,
3602 [RDLEN12
] = igb_set_dlen
,
3603 [RDLEN13
] = igb_set_dlen
,
3604 [RDLEN14
] = igb_set_dlen
,
3605 [RDLEN15
] = igb_set_dlen
,
3606 [TDBAL0
] = igb_set_dbal
,
3607 [TDBAL1
] = igb_set_dbal
,
3608 [TDBAL2
] = igb_set_dbal
,
3609 [TDBAL3
] = igb_set_dbal
,
3610 [TDBAL4
] = igb_set_dbal
,
3611 [TDBAL5
] = igb_set_dbal
,
3612 [TDBAL6
] = igb_set_dbal
,
3613 [TDBAL7
] = igb_set_dbal
,
3614 [TDBAL8
] = igb_set_dbal
,
3615 [TDBAL9
] = igb_set_dbal
,
3616 [TDBAL10
] = igb_set_dbal
,
3617 [TDBAL11
] = igb_set_dbal
,
3618 [TDBAL12
] = igb_set_dbal
,
3619 [TDBAL13
] = igb_set_dbal
,
3620 [TDBAL14
] = igb_set_dbal
,
3621 [TDBAL15
] = igb_set_dbal
,
3622 [RDBAL0
] = igb_set_dbal
,
3623 [RDBAL1
] = igb_set_dbal
,
3624 [RDBAL2
] = igb_set_dbal
,
3625 [RDBAL3
] = igb_set_dbal
,
3626 [RDBAL4
] = igb_set_dbal
,
3627 [RDBAL5
] = igb_set_dbal
,
3628 [RDBAL6
] = igb_set_dbal
,
3629 [RDBAL7
] = igb_set_dbal
,
3630 [RDBAL8
] = igb_set_dbal
,
3631 [RDBAL9
] = igb_set_dbal
,
3632 [RDBAL10
] = igb_set_dbal
,
3633 [RDBAL11
] = igb_set_dbal
,
3634 [RDBAL12
] = igb_set_dbal
,
3635 [RDBAL13
] = igb_set_dbal
,
3636 [RDBAL14
] = igb_set_dbal
,
3637 [RDBAL15
] = igb_set_dbal
,
3638 [STATUS
] = igb_set_status
,
3639 [PBACLR
] = igb_set_pbaclr
,
3640 [CTRL_EXT
] = igb_set_ctrlext
,
3641 [FCAH
] = igb_set_16bit
,
3642 [FCT
] = igb_set_16bit
,
3643 [FCTTV
] = igb_set_16bit
,
3644 [FCRTV
] = igb_set_16bit
,
3645 [FCRTH
] = igb_set_fcrth
,
3646 [FCRTL
] = igb_set_fcrtl
,
3647 [CTRL_DUP
] = igb_set_ctrl
,
3648 [RFCTL
] = igb_set_rfctl
,
3649 [TIMINCA
] = igb_set_timinca
,
3650 [TIMADJH
] = igb_set_timadjh
,
3652 [IP6AT
... IP6AT
+ 3] = igb_mac_writereg
,
3653 [IP4AT
... IP4AT
+ 6] = igb_mac_writereg
,
3654 [RA
] = igb_mac_writereg
,
3655 [RA
+ 1] = igb_mac_setmacaddr
,
3656 [RA
+ 2 ... RA
+ 31] = igb_mac_writereg
,
3657 [RA2
... RA2
+ 31] = igb_mac_writereg
,
3658 [WUPM
... WUPM
+ 31] = igb_mac_writereg
,
3659 [MTA
... MTA
+ E1000_MC_TBL_SIZE
- 1] = igb_mac_writereg
,
3660 [VFTA
... VFTA
+ E1000_VLAN_FILTER_TBL_SIZE
- 1] = igb_mac_writereg
,
3661 [FFMT
... FFMT
+ 254] = igb_set_4bit
,
3662 [MDEF
... MDEF
+ 7] = igb_mac_writereg
,
3663 [FTFT
... FTFT
+ 254] = igb_mac_writereg
,
3664 [RETA
... RETA
+ 31] = igb_mac_writereg
,
3665 [RSSRK
... RSSRK
+ 9] = igb_mac_writereg
,
3666 [MAVTV0
... MAVTV3
] = igb_mac_writereg
,
3667 [EITR0
... EITR0
+ IGB_INTR_NUM
- 1] = igb_set_eitr
,
3670 [FWSM
] = igb_mac_writereg
,
3671 [SW_FW_SYNC
] = igb_mac_writereg
,
3672 [EICR
] = igb_set_eicr
,
3673 [EICS
] = igb_set_eics
,
3674 [EIAC
] = igb_set_eiac
,
3675 [EIAM
] = igb_set_eiam
,
3676 [EIMC
] = igb_set_eimc
,
3677 [EIMS
] = igb_set_eims
,
3678 [IVAR0
... IVAR0
+ 7] = igb_mac_writereg
,
3679 igb_putreg(IVAR_MISC
),
3681 [P2VMAILBOX0
... P2VMAILBOX7
] = igb_set_pfmailbox
,
3682 [V2PMAILBOX0
... V2PMAILBOX7
] = igb_set_vfmailbox
,
3683 [MBVFICR
] = igb_w1c
,
3684 [VMBMEM0
... VMBMEM0
+ 127] = igb_mac_writereg
,
3685 igb_putreg(MBVFIMR
),
3692 [VLVF0
... VLVF0
+ E1000_VLVF_ARRAY_SIZE
- 1] = igb_mac_writereg
,
3693 [VMVIR0
... VMVIR7
] = igb_mac_writereg
,
3694 [VMOLR0
... VMOLR7
] = igb_mac_writereg
,
3695 [UTA
... UTA
+ E1000_MC_TBL_SIZE
- 1] = igb_mac_writereg
,
3696 [PVTCTRL0
] = igb_set_vtctrl
,
3697 [PVTCTRL1
] = igb_set_vtctrl
,
3698 [PVTCTRL2
] = igb_set_vtctrl
,
3699 [PVTCTRL3
] = igb_set_vtctrl
,
3700 [PVTCTRL4
] = igb_set_vtctrl
,
3701 [PVTCTRL5
] = igb_set_vtctrl
,
3702 [PVTCTRL6
] = igb_set_vtctrl
,
3703 [PVTCTRL7
] = igb_set_vtctrl
,
3704 [PVTEICS0
] = igb_set_vteics
,
3705 [PVTEICS1
] = igb_set_vteics
,
3706 [PVTEICS2
] = igb_set_vteics
,
3707 [PVTEICS3
] = igb_set_vteics
,
3708 [PVTEICS4
] = igb_set_vteics
,
3709 [PVTEICS5
] = igb_set_vteics
,
3710 [PVTEICS6
] = igb_set_vteics
,
3711 [PVTEICS7
] = igb_set_vteics
,
3712 [PVTEIMS0
] = igb_set_vteims
,
3713 [PVTEIMS1
] = igb_set_vteims
,
3714 [PVTEIMS2
] = igb_set_vteims
,
3715 [PVTEIMS3
] = igb_set_vteims
,
3716 [PVTEIMS4
] = igb_set_vteims
,
3717 [PVTEIMS5
] = igb_set_vteims
,
3718 [PVTEIMS6
] = igb_set_vteims
,
3719 [PVTEIMS7
] = igb_set_vteims
,
3720 [PVTEIMC0
] = igb_set_vteimc
,
3721 [PVTEIMC1
] = igb_set_vteimc
,
3722 [PVTEIMC2
] = igb_set_vteimc
,
3723 [PVTEIMC3
] = igb_set_vteimc
,
3724 [PVTEIMC4
] = igb_set_vteimc
,
3725 [PVTEIMC5
] = igb_set_vteimc
,
3726 [PVTEIMC6
] = igb_set_vteimc
,
3727 [PVTEIMC7
] = igb_set_vteimc
,
3728 [PVTEIAC0
] = igb_set_vteiac
,
3729 [PVTEIAC1
] = igb_set_vteiac
,
3730 [PVTEIAC2
] = igb_set_vteiac
,
3731 [PVTEIAC3
] = igb_set_vteiac
,
3732 [PVTEIAC4
] = igb_set_vteiac
,
3733 [PVTEIAC5
] = igb_set_vteiac
,
3734 [PVTEIAC6
] = igb_set_vteiac
,
3735 [PVTEIAC7
] = igb_set_vteiac
,
3736 [PVTEIAM0
] = igb_set_vteiam
,
3737 [PVTEIAM1
] = igb_set_vteiam
,
3738 [PVTEIAM2
] = igb_set_vteiam
,
3739 [PVTEIAM3
] = igb_set_vteiam
,
3740 [PVTEIAM4
] = igb_set_vteiam
,
3741 [PVTEIAM5
] = igb_set_vteiam
,
3742 [PVTEIAM6
] = igb_set_vteiam
,
3743 [PVTEIAM7
] = igb_set_vteiam
,
3744 [PVTEICR0
] = igb_set_vteicr
,
3745 [PVTEICR1
] = igb_set_vteicr
,
3746 [PVTEICR2
] = igb_set_vteicr
,
3747 [PVTEICR3
] = igb_set_vteicr
,
3748 [PVTEICR4
] = igb_set_vteicr
,
3749 [PVTEICR5
] = igb_set_vteicr
,
3750 [PVTEICR6
] = igb_set_vteicr
,
3751 [PVTEICR7
] = igb_set_vteicr
,
3752 [VTIVAR
... VTIVAR
+ 7] = igb_set_vtivar
,
3753 [VTIVAR_MISC
... VTIVAR_MISC
+ 7] = igb_mac_writereg
3755 enum { IGB_NWRITEOPS
= ARRAY_SIZE(igb_macreg_writeops
) };
3757 enum { MAC_ACCESS_PARTIAL
= 1 };
3760 * The array below combines alias offsets of the index values for the
3761 * MAC registers that have aliases, with the indication of not fully
3762 * implemented registers (lowest bit). This combination is possible
3763 * because all of the offsets are even.
3765 static const uint16_t mac_reg_access
[E1000E_MAC_SIZE
] = {
3766 /* Alias index offsets */
3768 [RDFH_A
] = 0xe904, [RDFT_A
] = 0xe904,
3769 [TDFH_A
] = 0xed00, [TDFT_A
] = 0xed00,
3770 [RA_A
... RA_A
+ 31] = 0x14f0,
3771 [VFTA_A
... VFTA_A
+ E1000_VLAN_FILTER_TBL_SIZE
- 1] = 0x1400,
3773 [RDBAL0_A
] = 0x2600,
3774 [RDBAH0_A
] = 0x2600,
3775 [RDLEN0_A
] = 0x2600,
3776 [SRRCTL0_A
] = 0x2600,
3779 [RXDCTL0_A
] = 0x2600,
3780 [RXCTL0_A
] = 0x2600,
3781 [RQDPC0_A
] = 0x2600,
3782 [RDBAL1_A
] = 0x25D0,
3783 [RDBAL2_A
] = 0x25A0,
3784 [RDBAL3_A
] = 0x2570,
3785 [RDBAH1_A
] = 0x25D0,
3786 [RDBAH2_A
] = 0x25A0,
3787 [RDBAH3_A
] = 0x2570,
3788 [RDLEN1_A
] = 0x25D0,
3789 [RDLEN2_A
] = 0x25A0,
3790 [RDLEN3_A
] = 0x2570,
3791 [SRRCTL1_A
] = 0x25D0,
3792 [SRRCTL2_A
] = 0x25A0,
3793 [SRRCTL3_A
] = 0x2570,
3800 [RXDCTL1_A
] = 0x25D0,
3801 [RXDCTL2_A
] = 0x25A0,
3802 [RXDCTL3_A
] = 0x2570,
3803 [RXCTL1_A
] = 0x25D0,
3804 [RXCTL2_A
] = 0x25A0,
3805 [RXCTL3_A
] = 0x2570,
3806 [RQDPC1_A
] = 0x25D0,
3807 [RQDPC2_A
] = 0x25A0,
3808 [RQDPC3_A
] = 0x2570,
3809 [TDBAL0_A
] = 0x2A00,
3810 [TDBAH0_A
] = 0x2A00,
3811 [TDLEN0_A
] = 0x2A00,
3814 [TXCTL0_A
] = 0x2A00,
3815 [TDWBAL0_A
] = 0x2A00,
3816 [TDWBAH0_A
] = 0x2A00,
3817 [TDBAL1_A
] = 0x29D0,
3818 [TDBAL2_A
] = 0x29A0,
3819 [TDBAL3_A
] = 0x2970,
3820 [TDBAH1_A
] = 0x29D0,
3821 [TDBAH2_A
] = 0x29A0,
3822 [TDBAH3_A
] = 0x2970,
3823 [TDLEN1_A
] = 0x29D0,
3824 [TDLEN2_A
] = 0x29A0,
3825 [TDLEN3_A
] = 0x2970,
3832 [TXDCTL0_A
] = 0x2A00,
3833 [TXDCTL1_A
] = 0x29D0,
3834 [TXDCTL2_A
] = 0x29A0,
3835 [TXDCTL3_A
] = 0x2970,
3836 [TXCTL1_A
] = 0x29D0,
3837 [TXCTL2_A
] = 0x29A0,
3838 [TXCTL3_A
] = 0x29D0,
3839 [TDWBAL1_A
] = 0x29D0,
3840 [TDWBAL2_A
] = 0x29A0,
3841 [TDWBAL3_A
] = 0x2970,
3842 [TDWBAH1_A
] = 0x29D0,
3843 [TDWBAH2_A
] = 0x29A0,
3844 [TDWBAH3_A
] = 0x2970,
3846 /* Access options */
3847 [RDFH
] = MAC_ACCESS_PARTIAL
, [RDFT
] = MAC_ACCESS_PARTIAL
,
3848 [RDFHS
] = MAC_ACCESS_PARTIAL
, [RDFTS
] = MAC_ACCESS_PARTIAL
,
3849 [RDFPC
] = MAC_ACCESS_PARTIAL
,
3850 [TDFH
] = MAC_ACCESS_PARTIAL
, [TDFT
] = MAC_ACCESS_PARTIAL
,
3851 [TDFHS
] = MAC_ACCESS_PARTIAL
, [TDFTS
] = MAC_ACCESS_PARTIAL
,
3852 [TDFPC
] = MAC_ACCESS_PARTIAL
, [EECD
] = MAC_ACCESS_PARTIAL
,
3853 [FLA
] = MAC_ACCESS_PARTIAL
,
3854 [FCAL
] = MAC_ACCESS_PARTIAL
, [FCAH
] = MAC_ACCESS_PARTIAL
,
3855 [FCT
] = MAC_ACCESS_PARTIAL
, [FCTTV
] = MAC_ACCESS_PARTIAL
,
3856 [FCRTV
] = MAC_ACCESS_PARTIAL
, [FCRTL
] = MAC_ACCESS_PARTIAL
,
3857 [FCRTH
] = MAC_ACCESS_PARTIAL
,
3858 [MAVTV0
... MAVTV3
] = MAC_ACCESS_PARTIAL
3862 igb_core_write(IGBCore
*core
, hwaddr addr
, uint64_t val
, unsigned size
)
3864 uint16_t index
= igb_get_reg_index_with_offset(mac_reg_access
, addr
);
3866 if (index
< IGB_NWRITEOPS
&& igb_macreg_writeops
[index
]) {
3867 if (mac_reg_access
[index
] & MAC_ACCESS_PARTIAL
) {
3868 trace_e1000e_wrn_regs_write_trivial(index
<< 2);
3870 trace_e1000e_core_write(index
<< 2, size
, val
);
3871 igb_macreg_writeops
[index
](core
, index
, val
);
3872 } else if (index
< IGB_NREADOPS
&& igb_macreg_readops
[index
]) {
3873 trace_e1000e_wrn_regs_write_ro(index
<< 2, size
, val
);
3875 trace_e1000e_wrn_regs_write_unknown(index
<< 2, size
, val
);
3880 igb_core_read(IGBCore
*core
, hwaddr addr
, unsigned size
)
3883 uint16_t index
= igb_get_reg_index_with_offset(mac_reg_access
, addr
);
3885 if (index
< IGB_NREADOPS
&& igb_macreg_readops
[index
]) {
3886 if (mac_reg_access
[index
] & MAC_ACCESS_PARTIAL
) {
3887 trace_e1000e_wrn_regs_read_trivial(index
<< 2);
3889 val
= igb_macreg_readops
[index
](core
, index
);
3890 trace_e1000e_core_read(index
<< 2, size
, val
);
3893 trace_e1000e_wrn_regs_read_unknown(index
<< 2, size
);
3899 igb_autoneg_pause(IGBCore
*core
)
3901 timer_del(core
->autoneg_timer
);
3905 igb_autoneg_resume(IGBCore
*core
)
3907 if (igb_have_autoneg(core
) &&
3908 !(core
->phy
[MII_BMSR
] & MII_BMSR_AN_COMP
)) {
3909 qemu_get_queue(core
->owner_nic
)->link_down
= false;
3910 timer_mod(core
->autoneg_timer
,
3911 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + 500);
3916 igb_vm_state_change(void *opaque
, bool running
, RunState state
)
3918 IGBCore
*core
= opaque
;
3921 trace_e1000e_vm_state_running();
3922 igb_intrmgr_resume(core
);
3923 igb_autoneg_resume(core
);
3925 trace_e1000e_vm_state_stopped();
3926 igb_autoneg_pause(core
);
3927 igb_intrmgr_pause(core
);
3932 igb_core_pci_realize(IGBCore
*core
,
3933 const uint16_t *eeprom_templ
,
3934 uint32_t eeprom_size
,
3935 const uint8_t *macaddr
)
3939 core
->autoneg_timer
= timer_new_ms(QEMU_CLOCK_VIRTUAL
,
3940 igb_autoneg_timer
, core
);
3941 igb_intrmgr_pci_realize(core
);
3943 core
->vmstate
= qemu_add_vm_change_state_handler(igb_vm_state_change
, core
);
3945 for (i
= 0; i
< IGB_NUM_QUEUES
; i
++) {
3946 net_tx_pkt_init(&core
->tx
[i
].tx_pkt
, E1000E_MAX_TX_FRAGS
);
3949 net_rx_pkt_init(&core
->rx_pkt
);
3951 e1000x_core_prepare_eeprom(core
->eeprom
,
3954 PCI_DEVICE_GET_CLASS(core
->owner
)->device_id
,
3956 igb_update_rx_offloads(core
);
3960 igb_core_pci_uninit(IGBCore
*core
)
3964 timer_free(core
->autoneg_timer
);
3966 igb_intrmgr_pci_unint(core
);
3968 qemu_del_vm_change_state_handler(core
->vmstate
);
3970 for (i
= 0; i
< IGB_NUM_QUEUES
; i
++) {
3971 net_tx_pkt_uninit(core
->tx
[i
].tx_pkt
);
3974 net_rx_pkt_uninit(core
->rx_pkt
);
3977 static const uint16_t
3978 igb_phy_reg_init
[] = {
3979 [MII_BMCR
] = MII_BMCR_SPEED1000
|
3983 [MII_BMSR
] = MII_BMSR_EXTCAP
|
3993 [MII_PHYID1
] = IGP03E1000_E_PHY_ID
>> 16,
3994 [MII_PHYID2
] = (IGP03E1000_E_PHY_ID
& 0xfff0) | 1,
3995 [MII_ANAR
] = MII_ANAR_CSMACD
| MII_ANAR_10
|
3996 MII_ANAR_10FD
| MII_ANAR_TX
|
3997 MII_ANAR_TXFD
| MII_ANAR_PAUSE
|
3998 MII_ANAR_PAUSE_ASYM
,
3999 [MII_ANLPAR
] = MII_ANLPAR_10
| MII_ANLPAR_10FD
|
4000 MII_ANLPAR_TX
| MII_ANLPAR_TXFD
|
4001 MII_ANLPAR_T4
| MII_ANLPAR_PAUSE
,
4002 [MII_ANER
] = MII_ANER_NP
| MII_ANER_NWAY
,
4003 [MII_ANNP
] = 0x1 | MII_ANNP_MP
,
4004 [MII_CTRL1000
] = MII_CTRL1000_HALF
| MII_CTRL1000_FULL
|
4005 MII_CTRL1000_PORT
| MII_CTRL1000_MASTER
,
4006 [MII_STAT1000
] = MII_STAT1000_HALF
| MII_STAT1000_FULL
|
4007 MII_STAT1000_ROK
| MII_STAT1000_LOK
,
4008 [MII_EXTSTAT
] = MII_EXTSTAT_1000T_HD
| MII_EXTSTAT_1000T_FD
,
4010 [IGP01E1000_PHY_PORT_CONFIG
] = BIT(5) | BIT(8),
4011 [IGP01E1000_PHY_PORT_STATUS
] = IGP01E1000_PSSR_SPEED_1000MBPS
,
4012 [IGP02E1000_PHY_POWER_MGMT
] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU
|
4013 IGP01E1000_PSCFR_SMART_SPEED
4016 static const uint32_t igb_mac_reg_init
[] = {
4017 [LEDCTL
] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24),
4018 [EEMNGCTL
] = BIT(31),
4019 [TXDCTL0
] = E1000_TXDCTL_QUEUE_ENABLE
,
4020 [RXDCTL0
] = E1000_RXDCTL_QUEUE_ENABLE
| (1 << 16),
4021 [RXDCTL1
] = 1 << 16,
4022 [RXDCTL2
] = 1 << 16,
4023 [RXDCTL3
] = 1 << 16,
4024 [RXDCTL4
] = 1 << 16,
4025 [RXDCTL5
] = 1 << 16,
4026 [RXDCTL6
] = 1 << 16,
4027 [RXDCTL7
] = 1 << 16,
4028 [RXDCTL8
] = 1 << 16,
4029 [RXDCTL9
] = 1 << 16,
4030 [RXDCTL10
] = 1 << 16,
4031 [RXDCTL11
] = 1 << 16,
4032 [RXDCTL12
] = 1 << 16,
4033 [RXDCTL13
] = 1 << 16,
4034 [RXDCTL14
] = 1 << 16,
4035 [RXDCTL15
] = 1 << 16,
4036 [TIPG
] = 0x08 | (0x04 << 10) | (0x06 << 20),
4037 [CTRL
] = E1000_CTRL_FD
| E1000_CTRL_LRST
| E1000_CTRL_SPD_1000
|
4038 E1000_CTRL_ADVD3WUC
,
4039 [STATUS
] = E1000_STATUS_PHYRA
| BIT(31),
4040 [EECD
] = E1000_EECD_FWE_DIS
| E1000_EECD_PRES
|
4041 (2 << E1000_EECD_SIZE_EX_SHIFT
),
4042 [GCR
] = E1000_L0S_ADJUST
|
4043 E1000_GCR_CMPL_TMOUT_RESEND
|
4044 E1000_GCR_CAP_VER2
|
4045 E1000_L1_ENTRY_LATENCY_MSB
|
4046 E1000_L1_ENTRY_LATENCY_LSB
,
4047 [RXCSUM
] = E1000_RXCSUM_IPOFLD
| E1000_RXCSUM_TUOFLD
,
4050 [TCTL
] = E1000_TCTL_PSP
| (0xF << E1000_CT_SHIFT
) |
4051 (0x40 << E1000_COLD_SHIFT
) | (0x1 << 26) | (0xA << 28),
4052 [TCTL_EXT
] = 0x40 | (0x42 << 10),
4053 [DTXCTL
] = E1000_DTXCTL_8023LL
| E1000_DTXCTL_SPOOF_INT
,
4054 [VET
] = ETH_P_VLAN
| (ETH_P_VLAN
<< 16),
4056 [V2PMAILBOX0
... V2PMAILBOX0
+ IGB_MAX_VF_FUNCTIONS
- 1] = E1000_V2PMAILBOX_RSTI
,
4060 [VMOLR0
... VMOLR0
+ 7] = 0x2600 | E1000_VMOLR_STRCRC
,
4061 [RPLOLR
] = E1000_RPLOLR_STRCRC
,
4063 [TXCTL0
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4064 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4065 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4066 [TXCTL1
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4067 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4068 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4069 [TXCTL2
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4070 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4071 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4072 [TXCTL3
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4073 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4074 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4075 [TXCTL4
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4076 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4077 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4078 [TXCTL5
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4079 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4080 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4081 [TXCTL6
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4082 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4083 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4084 [TXCTL7
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4085 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4086 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4087 [TXCTL8
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4088 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4089 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4090 [TXCTL9
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4091 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4092 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4093 [TXCTL10
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4094 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4095 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4096 [TXCTL11
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4097 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4098 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4099 [TXCTL12
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4100 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4101 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4102 [TXCTL13
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4103 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4104 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4105 [TXCTL14
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4106 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4107 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4108 [TXCTL15
] = E1000_DCA_TXCTRL_DATA_RRO_EN
|
4109 E1000_DCA_TXCTRL_TX_WB_RO_EN
|
4110 E1000_DCA_TXCTRL_DESC_RRO_EN
,
4113 static void igb_reset(IGBCore
*core
, bool sw
)
4118 timer_del(core
->autoneg_timer
);
4120 igb_intrmgr_reset(core
);
4122 memset(core
->phy
, 0, sizeof core
->phy
);
4123 memcpy(core
->phy
, igb_phy_reg_init
, sizeof igb_phy_reg_init
);
4125 for (i
= 0; i
< E1000E_MAC_SIZE
; i
++) {
4127 (i
== RXPBS
|| i
== TXPBS
||
4128 (i
>= EITR0
&& i
< EITR0
+ IGB_INTR_NUM
))) {
4132 core
->mac
[i
] = i
< ARRAY_SIZE(igb_mac_reg_init
) ?
4133 igb_mac_reg_init
[i
] : 0;
4136 if (qemu_get_queue(core
->owner_nic
)->link_down
) {
4137 igb_link_down(core
);
4140 e1000x_reset_mac_addr(core
->owner_nic
, core
->mac
, core
->permanent_mac
);
4142 for (int vfn
= 0; vfn
< IGB_MAX_VF_FUNCTIONS
; vfn
++) {
4143 /* Set RSTI, so VF can identify a PF reset is in progress */
4144 core
->mac
[V2PMAILBOX0
+ vfn
] |= E1000_V2PMAILBOX_RSTI
;
4147 for (i
= 0; i
< ARRAY_SIZE(core
->tx
); i
++) {
4149 memset(tx
->ctx
, 0, sizeof(tx
->ctx
));
4151 tx
->skip_cp
= false;
4156 igb_core_reset(IGBCore
*core
)
4158 igb_reset(core
, false);
4161 void igb_core_pre_save(IGBCore
*core
)
4164 NetClientState
*nc
= qemu_get_queue(core
->owner_nic
);
4167 * If link is down and auto-negotiation is supported and ongoing,
4168 * complete auto-negotiation immediately. This allows us to look
4169 * at MII_BMSR_AN_COMP to infer link status on load.
4171 if (nc
->link_down
&& igb_have_autoneg(core
)) {
4172 core
->phy
[MII_BMSR
] |= MII_BMSR_AN_COMP
;
4173 igb_update_flowctl_status(core
);
4176 for (i
= 0; i
< ARRAY_SIZE(core
->tx
); i
++) {
4177 if (net_tx_pkt_has_fragments(core
->tx
[i
].tx_pkt
)) {
4178 core
->tx
[i
].skip_cp
= true;
4184 igb_core_post_load(IGBCore
*core
)
4186 NetClientState
*nc
= qemu_get_queue(core
->owner_nic
);
4189 * nc.link_down can't be migrated, so infer link_down according
4190 * to link status bit in core.mac[STATUS].
4192 nc
->link_down
= (core
->mac
[STATUS
] & E1000_STATUS_LU
) == 0;