hw/mips/mipssim.c

   1 /*
   2  * QEMU/mipssim emulation
   3  *
   4  * Emulates a very simple machine model similar to the one used by the
   5  * proprietary MIPS emulator.
   6  *
   7  * Copyright (c) 2007 Thiemo Seufer
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu/datadir.h"
  31 #include "hw/clock.h"
  32 #include "hw/mips/mips.h"
  33 #include "hw/char/serial.h"
  34 #include "hw/isa/isa.h"
  35 #include "net/net.h"
  36 #include "sysemu/sysemu.h"
  37 #include "hw/boards.h"
  38 #include "hw/mips/bios.h"
  39 #include "hw/loader.h"
  40 #include "elf.h"
  41 #include "hw/sysbus.h"
  42 #include "hw/qdev-properties.h"
  43 #include "qemu/error-report.h"
  44 #include "sysemu/qtest.h"
  45 #include "sysemu/reset.h"
  46
  47 static struct _loaderparams {
  48     int ram_size;
  49     const char *kernel_filename;
  50     const char *kernel_cmdline;
  51     const char *initrd_filename;
  52 } loaderparams;
  53
  54 typedef struct ResetData {
  55     MIPSCPU *cpu;
  56     uint64_t vector;
  57 } ResetData;
  58
  59 static uint64_t load_kernel(void)
  60 {
  61     uint64_t entry, kernel_high, initrd_size;
  62     long kernel_size;
  63     ram_addr_t initrd_offset;
  64
  65     kernel_size = load_elf(loaderparams.kernel_filename, NULL,
  66                            cpu_mips_kseg0_to_phys, NULL,
  67                            &entry, NULL,
  68                            &kernel_high, NULL, TARGET_BIG_ENDIAN,
  69                            EM_MIPS, 1, 0);
  70     if (kernel_size < 0) {
  71         error_report("could not load kernel '%s': %s",
  72                      loaderparams.kernel_filename,
  73                      load_elf_strerror(kernel_size));
  74         exit(1);
  75     }
  76
  77     /* load initrd */
  78     initrd_size = 0;
  79     initrd_offset = 0;
  80     if (loaderparams.initrd_filename) {
  81         initrd_size = get_image_size(loaderparams.initrd_filename);
  82         if (initrd_size > 0) {
  83             initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE);
  84             if (initrd_offset + initrd_size > loaderparams.ram_size) {
  85                 error_report("memory too small for initial ram disk '%s'",
  86                              loaderparams.initrd_filename);
  87                 exit(1);
  88             }
  89             initrd_size = load_image_targphys(loaderparams.initrd_filename,
  90                 initrd_offset, loaderparams.ram_size - initrd_offset);
  91         }
  92         if (initrd_size == (target_ulong) -1) {
  93             error_report("could not load initial ram disk '%s'",
  94                          loaderparams.initrd_filename);
  95             exit(1);
  96         }
  97     }
  98     return entry;
  99 }
 100
 101 static void main_cpu_reset(void *opaque)
 102 {
 103     ResetData *s = (ResetData *)opaque;
 104     CPUMIPSState *env = &s->cpu->env;
 105
 106     cpu_reset(CPU(s->cpu));
 107     env->active_tc.PC = s->vector & ~(target_ulong)1;
 108     if (s->vector & 1) {
 109         env->hflags |= MIPS_HFLAG_M16;
 110     }
 111 }
 112
 113 static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd)
 114 {
 115     DeviceState *dev;
 116     SysBusDevice *s;
 117
 118     dev = qdev_new("mipsnet");
 119     qdev_set_nic_properties(dev, nd);
 120
 121     s = SYS_BUS_DEVICE(dev);
 122     sysbus_realize_and_unref(s, &error_fatal);
 123     sysbus_connect_irq(s, 0, irq);
 124     memory_region_add_subregion(get_system_io(),
 125                                 base,
 126                                 sysbus_mmio_get_region(s, 0));
 127 }
 128
 129 static void
 130 mips_mipssim_init(MachineState *machine)
 131 {
 132     const char *kernel_filename = machine->kernel_filename;
 133     const char *kernel_cmdline = machine->kernel_cmdline;
 134     const char *initrd_filename = machine->initrd_filename;
 135     char *filename;
 136     MemoryRegion *address_space_mem = get_system_memory();
 137     MemoryRegion *isa = g_new(MemoryRegion, 1);
 138     MemoryRegion *bios = g_new(MemoryRegion, 1);
 139     Clock *cpuclk;
 140     MIPSCPU *cpu;
 141     CPUMIPSState *env;
 142     ResetData *reset_info;
 143     int bios_size;
 144
 145     cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
 146 #ifdef TARGET_MIPS64
 147     clock_set_hz(cpuclk, 6000000); /* 6 MHz */
 148 #else
 149     clock_set_hz(cpuclk, 12000000); /* 12 MHz */
 150 #endif
 151
 152     /* Init CPUs. */
 153     cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
 154     env = &cpu->env;
 155
 156     reset_info = g_new0(ResetData, 1);
 157     reset_info->cpu = cpu;
 158     reset_info->vector = env->active_tc.PC;
 159     qemu_register_reset(main_cpu_reset, reset_info);
 160
 161     /* Allocate RAM. */
 162     memory_region_init_rom(bios, NULL, "mips_mipssim.bios", BIOS_SIZE,
 163                            &error_fatal);
 164
 165     memory_region_add_subregion(address_space_mem, 0, machine->ram);
 166
 167     /* Map the BIOS / boot exception handler. */
 168     memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
 169     /* Load a BIOS / boot exception handler image. */
 170     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME);
 171     if (filename) {
 172         bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
 173         g_free(filename);
 174     } else {
 175         bios_size = -1;
 176     }
 177     if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
 178         machine->firmware && !qtest_enabled()) {
 179         /* Bail out if we have neither a kernel image nor boot vector code. */
 180         error_report("Could not load MIPS bios '%s'", machine->firmware);
 181         exit(1);
 182     } else {
 183         /* We have a boot vector start address. */
 184         env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
 185     }
 186
 187     if (kernel_filename) {
 188         loaderparams.ram_size = machine->ram_size;
 189         loaderparams.kernel_filename = kernel_filename;
 190         loaderparams.kernel_cmdline = kernel_cmdline;
 191         loaderparams.initrd_filename = initrd_filename;
 192         reset_info->vector = load_kernel();
 193     }
 194
 195     /* Init CPU internal devices. */
 196     cpu_mips_irq_init_cpu(cpu);
 197     cpu_mips_clock_init(cpu);
 198
 199     /* Register 64 KB of ISA IO space at 0x1fd00000. */
 200     memory_region_init_alias(isa, NULL, "isa_mmio",
 201                              get_system_io(), 0, 0x00010000);
 202     memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
 203
 204     /*
 205      * A single 16450 sits at offset 0x3f8. It is attached to
 206      * MIPS CPU INT2, which is interrupt 4.
 207      */
 208     if (serial_hd(0)) {
 209         DeviceState *dev = qdev_new(TYPE_SERIAL_MM);
 210
 211         qdev_prop_set_chr(dev, "chardev", serial_hd(0));
 212         qdev_prop_set_uint8(dev, "regshift", 0);
 213         qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN);
 214         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 215         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
 216         sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8,
 217                       sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
 218     }
 219
 220     if (nd_table[0].used)
 221         /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
 222         mipsnet_init(0x4200, env->irq[2], &nd_table[0]);
 223 }
 224
 225 static void mips_mipssim_machine_init(MachineClass *mc)
 226 {
 227     mc->desc = "MIPS MIPSsim platform";
 228     mc->init = mips_mipssim_init;
 229 #ifdef TARGET_MIPS64
 230     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kf");
 231 #else
 232     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
 233 #endif
 234     mc->default_ram_id = "mips_mipssim.ram";
 235 }
 236
 237 DEFINE_MACHINE("mipssim", mips_mipssim_machine_init)