hw/arm/realview.c

   1 /*
   2  * ARM RealView Baseboard System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "cpu.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/arm/boot.h"
  15 #include "hw/arm/primecell.h"
  16 #include "hw/core/split-irq.h"
  17 #include "hw/net/lan9118.h"
  18 #include "hw/net/smc91c111.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/qdev-core.h"
  21 #include "net/net.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/boards.h"
  24 #include "hw/i2c/i2c.h"
  25 #include "qemu/error-report.h"
  26 #include "hw/char/pl011.h"
  27 #include "hw/cpu/a9mpcore.h"
  28 #include "hw/intc/realview_gic.h"
  29 #include "hw/irq.h"
  30 #include "hw/i2c/arm_sbcon_i2c.h"
  31 #include "hw/sd/sd.h"
  32 #include "audio/audio.h"
  33
  34 #define SMP_BOOT_ADDR 0xe0000000
  35 #define SMP_BOOTREG_ADDR 0x10000030
  36
  37 /* Board init.  */
  38
  39 static struct arm_boot_info realview_binfo = {
  40     .smp_loader_start = SMP_BOOT_ADDR,
  41     .smp_bootreg_addr = SMP_BOOTREG_ADDR,
  42 };
  43
  44 /* The following two lists must be consistent.  */
  45 enum realview_board_type {
  46     BOARD_EB,
  47     BOARD_EB_MPCORE,
  48     BOARD_PB_A8,
  49     BOARD_PBX_A9,
  50 };
  51
  52 static const int realview_board_id[] = {
  53     0x33b,
  54     0x33b,
  55     0x769,
  56     0x76d
  57 };
  58
  59 static void split_irq_from_named(DeviceState *src, const char* outname,
  60                                  qemu_irq out1, qemu_irq out2) {
  61     DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
  62
  63     qdev_prop_set_uint32(splitter, "num-lines", 2);
  64
  65     qdev_realize_and_unref(splitter, NULL, &error_fatal);
  66
  67     qdev_connect_gpio_out(splitter, 0, out1);
  68     qdev_connect_gpio_out(splitter, 1, out2);
  69     qdev_connect_gpio_out_named(src, outname, 0,
  70                                 qdev_get_gpio_in(splitter, 0));
  71 }
  72
  73 static void realview_init(MachineState *machine,
  74                           enum realview_board_type board_type)
  75 {
  76     ARMCPU *cpu = NULL;
  77     CPUARMState *env;
  78     MemoryRegion *sysmem = get_system_memory();
  79     MemoryRegion *ram_lo;
  80     MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
  81     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
  82     MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
  83     DeviceState *dev, *sysctl, *gpio2, *pl041;
  84     SysBusDevice *busdev;
  85     qemu_irq pic[64];
  86     PCIBus *pci_bus = NULL;
  87     NICInfo *nd;
  88     DriveInfo *dinfo;
  89     I2CBus *i2c;
  90     int n;
  91     unsigned int smp_cpus = machine->smp.cpus;
  92     int done_nic = 0;
  93     qemu_irq cpu_irq[4];
  94     int is_mpcore = 0;
  95     int is_pb = 0;
  96     uint32_t proc_id = 0;
  97     uint32_t sys_id;
  98     ram_addr_t low_ram_size;
  99     ram_addr_t ram_size = machine->ram_size;
 100     hwaddr periphbase = 0;
 101
 102     switch (board_type) {
 103     case BOARD_EB:
 104         break;
 105     case BOARD_EB_MPCORE:
 106         is_mpcore = 1;
 107         periphbase = 0x10100000;
 108         break;
 109     case BOARD_PB_A8:
 110         is_pb = 1;
 111         break;
 112     case BOARD_PBX_A9:
 113         is_mpcore = 1;
 114         is_pb = 1;
 115         periphbase = 0x1f000000;
 116         break;
 117     }
 118
 119     for (n = 0; n < smp_cpus; n++) {
 120         Object *cpuobj = object_new(machine->cpu_type);
 121
 122         /* By default A9,A15 and ARM1176 CPUs have EL3 enabled.  This board
 123          * does not currently support EL3 so the CPU EL3 property is disabled
 124          * before realization.
 125          */
 126         if (object_property_find(cpuobj, "has_el3")) {
 127             object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
 128         }
 129
 130         if (is_pb && is_mpcore) {
 131             object_property_set_int(cpuobj, "reset-cbar", periphbase,
 132                                     &error_fatal);
 133         }
 134
 135         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 136
 137         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
 138     }
 139     cpu = ARM_CPU(first_cpu);
 140     env = &cpu->env;
 141     if (arm_feature(env, ARM_FEATURE_V7)) {
 142         if (is_mpcore) {
 143             proc_id = 0x0c000000;
 144         } else {
 145             proc_id = 0x0e000000;
 146         }
 147     } else if (arm_feature(env, ARM_FEATURE_V6K)) {
 148         proc_id = 0x06000000;
 149     } else if (arm_feature(env, ARM_FEATURE_V6)) {
 150         proc_id = 0x04000000;
 151     } else {
 152         proc_id = 0x02000000;
 153     }
 154
 155     if (is_pb && ram_size > 0x20000000) {
 156         /* Core tile RAM.  */
 157         ram_lo = g_new(MemoryRegion, 1);
 158         low_ram_size = ram_size - 0x20000000;
 159         ram_size = 0x20000000;
 160         memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size,
 161                                &error_fatal);
 162         memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
 163     }
 164
 165     memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size,
 166                            &error_fatal);
 167     low_ram_size = ram_size;
 168     if (low_ram_size > 0x10000000)
 169       low_ram_size = 0x10000000;
 170     /* SDRAM at address zero.  */
 171     memory_region_init_alias(ram_alias, NULL, "realview.alias",
 172                              ram_hi, 0, low_ram_size);
 173     memory_region_add_subregion(sysmem, 0, ram_alias);
 174     if (is_pb) {
 175         /* And again at a high address.  */
 176         memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
 177     } else {
 178         ram_size = low_ram_size;
 179     }
 180
 181     sys_id = is_pb ? 0x01780500 : 0xc1400400;
 182     sysctl = qdev_new("realview_sysctl");
 183     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 184     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 185     sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
 186     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
 187
 188     if (is_mpcore) {
 189         dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
 190         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 191         busdev = SYS_BUS_DEVICE(dev);
 192         sysbus_realize_and_unref(busdev, &error_fatal);
 193         sysbus_mmio_map(busdev, 0, periphbase);
 194         for (n = 0; n < smp_cpus; n++) {
 195             sysbus_connect_irq(busdev, n, cpu_irq[n]);
 196         }
 197         sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
 198         /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
 199         realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
 200     } else {
 201         uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 202         /* For now just create the nIRQ GIC, and ignore the others.  */
 203         dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);
 204     }
 205     for (n = 0; n < 64; n++) {
 206         pic[n] = qdev_get_gpio_in(dev, n);
 207     }
 208
 209     pl041 = qdev_new("pl041");
 210     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 211     if (machine->audiodev) {
 212         qdev_prop_set_string(pl041, "audiodev", machine->audiodev);
 213     }
 214     sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
 215     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
 216     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
 217
 218     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 219     sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 220
 221     pl011_create(0x10009000, pic[12], serial_hd(0));
 222     pl011_create(0x1000a000, pic[13], serial_hd(1));
 223     pl011_create(0x1000b000, pic[14], serial_hd(2));
 224     pl011_create(0x1000c000, pic[15], serial_hd(3));
 225
 226     /* DMA controller is optional, apparently.  */
 227     dev = qdev_new("pl081");
 228     object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem),
 229                              &error_fatal);
 230     busdev = SYS_BUS_DEVICE(dev);
 231     sysbus_realize_and_unref(busdev, &error_fatal);
 232     sysbus_mmio_map(busdev, 0, 0x10030000);
 233     sysbus_connect_irq(busdev, 0, pic[24]);
 234
 235     sysbus_create_simple("sp804", 0x10011000, pic[4]);
 236     sysbus_create_simple("sp804", 0x10012000, pic[5]);
 237
 238     sysbus_create_simple("pl061", 0x10013000, pic[6]);
 239     sysbus_create_simple("pl061", 0x10014000, pic[7]);
 240     gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
 241
 242     sysbus_create_simple("pl111", 0x10020000, pic[23]);
 243
 244     dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 245     /* Wire up MMC card detect and read-only signals. These have
 246      * to go to both the PL061 GPIO and the sysctl register.
 247      * Note that the PL181 orders these lines (readonly,inserted)
 248      * and the PL061 has them the other way about. Also the card
 249      * detect line is inverted.
 250      */
 251     split_irq_from_named(dev, "card-read-only",
 252                    qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 253                    qdev_get_gpio_in(gpio2, 1));
 254
 255     split_irq_from_named(dev, "card-inserted",
 256                    qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 257                    qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 258
 259     dinfo = drive_get(IF_SD, 0, 0);
 260     if (dinfo) {
 261         DeviceState *card;
 262
 263         card = qdev_new(TYPE_SD_CARD);
 264         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 265                                 &error_fatal);
 266         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
 267                                &error_fatal);
 268     }
 269
 270     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 271
 272     if (!is_pb) {
 273         dev = qdev_new("realview_pci");
 274         busdev = SYS_BUS_DEVICE(dev);
 275         sysbus_realize_and_unref(busdev, &error_fatal);
 276         sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
 277         sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
 278         sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
 279         sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
 280         sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
 281         sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
 282         sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
 283         sysbus_connect_irq(busdev, 0, pic[48]);
 284         sysbus_connect_irq(busdev, 1, pic[49]);
 285         sysbus_connect_irq(busdev, 2, pic[50]);
 286         sysbus_connect_irq(busdev, 3, pic[51]);
 287         pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 288         if (machine_usb(machine)) {
 289             pci_create_simple(pci_bus, -1, "pci-ohci");
 290         }
 291         n = drive_get_max_bus(IF_SCSI);
 292         while (n >= 0) {
 293             dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
 294             lsi53c8xx_handle_legacy_cmdline(dev);
 295             n--;
 296         }
 297     }
 298     for(n = 0; n < nb_nics; n++) {
 299         nd = &nd_table[n];
 300
 301         if (!done_nic && (!nd->model ||
 302                     strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
 303             if (is_pb) {
 304                 lan9118_init(nd, 0x4e000000, pic[28]);
 305             } else {
 306                 smc91c111_init(nd, 0x4e000000, pic[28]);
 307             }
 308             done_nic = 1;
 309         } else {
 310             if (pci_bus) {
 311                 pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
 312             }
 313         }
 314     }
 315
 316     dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL);
 317     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 318     i2c_slave_create_simple(i2c, "ds1338", 0x68);
 319
 320     /* Memory map for RealView Emulation Baseboard:  */
 321     /* 0x10000000 System registers.  */
 322     /*  0x10001000 System controller.  */
 323     /* 0x10002000 Two-Wire Serial Bus.  */
 324     /* 0x10003000 Reserved.  */
 325     /*  0x10004000 AACI.  */
 326     /*  0x10005000 MCI.  */
 327     /* 0x10006000 KMI0.  */
 328     /* 0x10007000 KMI1.  */
 329     /*  0x10008000 Character LCD. (EB) */
 330     /* 0x10009000 UART0.  */
 331     /* 0x1000a000 UART1.  */
 332     /* 0x1000b000 UART2.  */
 333     /* 0x1000c000 UART3.  */
 334     /*  0x1000d000 SSPI.  */
 335     /*  0x1000e000 SCI.  */
 336     /* 0x1000f000 Reserved.  */
 337     /*  0x10010000 Watchdog.  */
 338     /* 0x10011000 Timer 0+1.  */
 339     /* 0x10012000 Timer 2+3.  */
 340     /*  0x10013000 GPIO 0.  */
 341     /*  0x10014000 GPIO 1.  */
 342     /*  0x10015000 GPIO 2.  */
 343     /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 344     /* 0x10017000 RTC.  */
 345     /*  0x10018000 DMC.  */
 346     /*  0x10019000 PCI controller config.  */
 347     /*  0x10020000 CLCD.  */
 348     /* 0x10030000 DMA Controller.  */
 349     /* 0x10040000 GIC1. (EB) */
 350     /*  0x10050000 GIC2. (EB) */
 351     /*  0x10060000 GIC3. (EB) */
 352     /*  0x10070000 GIC4. (EB) */
 353     /*  0x10080000 SMC.  */
 354     /* 0x1e000000 GIC1. (PB) */
 355     /*  0x1e001000 GIC2. (PB) */
 356     /*  0x1e002000 GIC3. (PB) */
 357     /*  0x1e003000 GIC4. (PB) */
 358     /*  0x40000000 NOR flash.  */
 359     /*  0x44000000 DoC flash.  */
 360     /*  0x48000000 SRAM.  */
 361     /*  0x4c000000 Configuration flash.  */
 362     /* 0x4e000000 Ethernet.  */
 363     /*  0x4f000000 USB.  */
 364     /*  0x50000000 PISMO.  */
 365     /*  0x54000000 PISMO.  */
 366     /*  0x58000000 PISMO.  */
 367     /*  0x5c000000 PISMO.  */
 368     /* 0x60000000 PCI.  */
 369     /* 0x60000000 PCI Self Config.  */
 370     /* 0x61000000 PCI Config.  */
 371     /* 0x62000000 PCI IO.  */
 372     /* 0x63000000 PCI mem 0.  */
 373     /* 0x64000000 PCI mem 1.  */
 374     /* 0x68000000 PCI mem 2.  */
 375
 376     /* ??? Hack to map an additional page of ram for the secondary CPU
 377        startup code.  I guess this works on real hardware because the
 378        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 379        until after Linux boots the secondary CPUs.  */
 380     memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000,
 381                            &error_fatal);
 382     memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
 383
 384     realview_binfo.ram_size = ram_size;
 385     realview_binfo.board_id = realview_board_id[board_type];
 386     realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
 387     arm_load_kernel(cpu, machine, &realview_binfo);
 388 }
 389
 390 static void realview_eb_init(MachineState *machine)
 391 {
 392     realview_init(machine, BOARD_EB);
 393 }
 394
 395 static void realview_eb_mpcore_init(MachineState *machine)
 396 {
 397     realview_init(machine, BOARD_EB_MPCORE);
 398 }
 399
 400 static void realview_pb_a8_init(MachineState *machine)
 401 {
 402     realview_init(machine, BOARD_PB_A8);
 403 }
 404
 405 static void realview_pbx_a9_init(MachineState *machine)
 406 {
 407     realview_init(machine, BOARD_PBX_A9);
 408 }
 409
 410 static void realview_eb_class_init(ObjectClass *oc, void *data)
 411 {
 412     MachineClass *mc = MACHINE_CLASS(oc);
 413
 414     mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
 415     mc->init = realview_eb_init;
 416     mc->block_default_type = IF_SCSI;
 417     mc->ignore_memory_transaction_failures = true;
 418     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
 419
 420     machine_add_audiodev_property(mc);
 421 }
 422
 423 static const TypeInfo realview_eb_type = {
 424     .name = MACHINE_TYPE_NAME("realview-eb"),
 425     .parent = TYPE_MACHINE,
 426     .class_init = realview_eb_class_init,
 427 };
 428
 429 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
 430 {
 431     MachineClass *mc = MACHINE_CLASS(oc);
 432
 433     mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
 434     mc->init = realview_eb_mpcore_init;
 435     mc->block_default_type = IF_SCSI;
 436     mc->max_cpus = 4;
 437     mc->ignore_memory_transaction_failures = true;
 438     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
 439
 440     machine_add_audiodev_property(mc);
 441 }
 442
 443 static const TypeInfo realview_eb_mpcore_type = {
 444     .name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
 445     .parent = TYPE_MACHINE,
 446     .class_init = realview_eb_mpcore_class_init,
 447 };
 448
 449 static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
 450 {
 451     MachineClass *mc = MACHINE_CLASS(oc);
 452
 453     mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
 454     mc->init = realview_pb_a8_init;
 455     mc->ignore_memory_transaction_failures = true;
 456     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
 457
 458     machine_add_audiodev_property(mc);
 459 }
 460
 461 static const TypeInfo realview_pb_a8_type = {
 462     .name = MACHINE_TYPE_NAME("realview-pb-a8"),
 463     .parent = TYPE_MACHINE,
 464     .class_init = realview_pb_a8_class_init,
 465 };
 466
 467 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
 468 {
 469     MachineClass *mc = MACHINE_CLASS(oc);
 470
 471     mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
 472     mc->init = realview_pbx_a9_init;
 473     mc->max_cpus = 4;
 474     mc->ignore_memory_transaction_failures = true;
 475     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 476
 477     machine_add_audiodev_property(mc);
 478 }
 479
 480 static const TypeInfo realview_pbx_a9_type = {
 481     .name = MACHINE_TYPE_NAME("realview-pbx-a9"),
 482     .parent = TYPE_MACHINE,
 483     .class_init = realview_pbx_a9_class_init,
 484 };
 485
 486 static void realview_machine_init(void)
 487 {
 488     type_register_static(&realview_eb_type);
 489     type_register_static(&realview_eb_mpcore_type);
 490     type_register_static(&realview_pb_a8_type);
 491     type_register_static(&realview_pbx_a9_type);
 492 }
 493
 494 type_init(realview_machine_init)