hw/hppa/lasi.c

   1 /*
   2  * HP-PARISC Lasi chipset emulation.
   3  *
   4  * (C) 2019 by Helge Deller <deller@gmx.de>
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  *
   8  * Documentation available at:
   9  * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qemu/units.h"
  14 #include "qemu/log.h"
  15 #include "qapi/error.h"
  16 #include "trace.h"
  17 #include "hw/irq.h"
  18 #include "sysemu/sysemu.h"
  19 #include "sysemu/runstate.h"
  20 #include "hppa_sys.h"
  21 #include "hw/net/lasi_82596.h"
  22 #include "hw/char/parallel.h"
  23 #include "hw/char/serial.h"
  24 #include "hw/input/lasips2.h"
  25 #include "migration/vmstate.h"
  26 #include "qom/object.h"
  27 #include "lasi.h"
  28
  29
  30 static bool lasi_chip_mem_valid(void *opaque, hwaddr addr,
  31                                 unsigned size, bool is_write,
  32                                 MemTxAttrs attrs)
  33 {
  34     bool ret = false;
  35
  36     switch (addr) {
  37     case LASI_IRR:
  38     case LASI_IMR:
  39     case LASI_IPR:
  40     case LASI_ICR:
  41     case LASI_IAR:
  42
  43     case (LASI_LAN_HPA - LASI_HPA):
  44     case (LASI_LPT_HPA - LASI_HPA):
  45     case (LASI_UART_HPA - LASI_HPA):
  46     case (LASI_RTC_HPA - LASI_HPA):
  47
  48     case LASI_PCR ... LASI_AMR:
  49         ret = true;
  50     }
  51
  52     trace_lasi_chip_mem_valid(addr, ret);
  53     return ret;
  54 }
  55
  56 static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr,
  57                                              uint64_t *data, unsigned size,
  58                                              MemTxAttrs attrs)
  59 {
  60     LasiState *s = opaque;
  61     MemTxResult ret = MEMTX_OK;
  62     uint32_t val;
  63
  64     switch (addr) {
  65     case LASI_IRR:
  66         val = s->irr;
  67         break;
  68     case LASI_IMR:
  69         val = s->imr;
  70         break;
  71     case LASI_IPR:
  72         val = s->ipr;
  73         /* Any read to IPR clears the register.  */
  74         s->ipr = 0;
  75         break;
  76     case LASI_ICR:
  77         val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */
  78         break;
  79     case LASI_IAR:
  80         val = s->iar;
  81         break;
  82
  83     case (LASI_LAN_HPA - LASI_HPA):
  84     case (LASI_LPT_HPA - LASI_HPA):
  85     case (LASI_UART_HPA - LASI_HPA):
  86         val = 0;
  87         break;
  88     case (LASI_RTC_HPA - LASI_HPA):
  89         val = time(NULL);
  90         val += s->rtc_ref;
  91         break;
  92
  93     case LASI_PCR:
  94     case LASI_VER:      /* only version 0 existed. */
  95     case LASI_IORESET:
  96         val = 0;
  97         break;
  98     case LASI_ERRLOG:
  99         val = s->errlog;
 100         break;
 101     case LASI_AMR:
 102         val = s->amr;
 103         break;
 104
 105     default:
 106         /* Controlled by lasi_chip_mem_valid above. */
 107         g_assert_not_reached();
 108     }
 109
 110     trace_lasi_chip_read(addr, val);
 111
 112     *data = val;
 113     return ret;
 114 }
 115
 116 static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr,
 117                                               uint64_t val, unsigned size,
 118                                               MemTxAttrs attrs)
 119 {
 120     LasiState *s = opaque;
 121
 122     trace_lasi_chip_write(addr, val);
 123
 124     switch (addr) {
 125     case LASI_IRR:
 126         /* read-only.  */
 127         break;
 128     case LASI_IMR:
 129         s->imr = val;
 130         if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) {
 131             qemu_log_mask(LOG_GUEST_ERROR,
 132                 "LASI: tried to set invalid %lx IMR value.\n",
 133                 (unsigned long) val);
 134         }
 135         break;
 136     case LASI_IPR:
 137         /* Any write to IPR clears the register. */
 138         s->ipr = 0;
 139         break;
 140     case LASI_ICR:
 141         s->icr = val;
 142         /* if (val & ICR_TOC_BIT) issue_toc(); */
 143         break;
 144     case LASI_IAR:
 145         s->iar = val;
 146         break;
 147
 148     case (LASI_LAN_HPA - LASI_HPA):
 149         /* XXX: reset LAN card */
 150         break;
 151     case (LASI_LPT_HPA - LASI_HPA):
 152         /* XXX: reset parallel port */
 153         break;
 154     case (LASI_UART_HPA - LASI_HPA):
 155         /* XXX: reset serial port */
 156         break;
 157     case (LASI_RTC_HPA - LASI_HPA):
 158         s->rtc_ref = val - time(NULL);
 159         break;
 160
 161     case LASI_PCR:
 162         if (val == 0x02) { /* immediately power off */
 163             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 164         }
 165         break;
 166     case LASI_ERRLOG:
 167         s->errlog = val;
 168         break;
 169     case LASI_VER:
 170         /* read-only.  */
 171         break;
 172     case LASI_IORESET:
 173         break;  /* XXX: TODO: Reset various devices. */
 174     case LASI_AMR:
 175         s->amr = val;
 176         break;
 177
 178     default:
 179         /* Controlled by lasi_chip_mem_valid above. */
 180         g_assert_not_reached();
 181     }
 182     return MEMTX_OK;
 183 }
 184
 185 static const MemoryRegionOps lasi_chip_ops = {
 186     .read_with_attrs = lasi_chip_read_with_attrs,
 187     .write_with_attrs = lasi_chip_write_with_attrs,
 188     .endianness = DEVICE_BIG_ENDIAN,
 189     .valid = {
 190         .min_access_size = 1,
 191         .max_access_size = 4,
 192         .accepts = lasi_chip_mem_valid,
 193     },
 194     .impl = {
 195         .min_access_size = 1,
 196         .max_access_size = 4,
 197     },
 198 };
 199
 200 static const VMStateDescription vmstate_lasi = {
 201     .name = "Lasi",
 202     .version_id = 1,
 203     .minimum_version_id = 1,
 204     .fields = (VMStateField[]) {
 205         VMSTATE_UINT32(irr, LasiState),
 206         VMSTATE_UINT32(imr, LasiState),
 207         VMSTATE_UINT32(ipr, LasiState),
 208         VMSTATE_UINT32(icr, LasiState),
 209         VMSTATE_UINT32(iar, LasiState),
 210         VMSTATE_UINT32(errlog, LasiState),
 211         VMSTATE_UINT32(amr, LasiState),
 212         VMSTATE_END_OF_LIST()
 213     }
 214 };
 215
 216
 217 static void lasi_set_irq(void *opaque, int irq, int level)
 218 {
 219     LasiState *s = opaque;
 220     uint32_t bit = 1u << irq;
 221
 222     if (level) {
 223         s->ipr |= bit;
 224         if (bit & s->imr) {
 225             uint32_t iar = s->iar;
 226             s->irr |= bit;
 227             if ((s->icr & ICR_BUS_ERROR_BIT) == 0) {
 228                 stl_be_phys(&address_space_memory, iar & -32, iar & 31);
 229             }
 230         }
 231     }
 232 }
 233
 234 DeviceState *lasi_initfn(MemoryRegion *address_space)
 235 {
 236     DeviceState *dev;
 237
 238     dev = qdev_new(TYPE_LASI_CHIP);
 239     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 240
 241     /* LAN */
 242     if (enable_lasi_lan()) {
 243         lasi_82596_init(address_space, LASI_LAN_HPA,
 244                         qdev_get_gpio_in(dev, LASI_IRQ_LAN_HPA));
 245     }
 246
 247     /* Parallel port */
 248     parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0,
 249                      qdev_get_gpio_in(dev, LASI_IRQ_LAN_HPA),
 250                      parallel_hds[0]);
 251
 252     if (serial_hd(1)) {
 253         /* Serial port */
 254         serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0,
 255                 qdev_get_gpio_in(dev, LASI_IRQ_UART_HPA), 8000000 / 16,
 256                 serial_hd(0), DEVICE_NATIVE_ENDIAN);
 257     }
 258
 259     /* PS/2 Keyboard/Mouse */
 260     lasips2_init(address_space, LASI_PS2KBD_HPA,
 261                  qdev_get_gpio_in(dev, LASI_IRQ_PS2KBD_HPA));
 262
 263     return dev;
 264 }
 265
 266 static void lasi_reset(DeviceState *dev)
 267 {
 268     LasiState *s = LASI_CHIP(dev);
 269
 270     s->iar = CPU_HPA + 3;
 271
 272     /* Real time clock (RTC), it's only one 32-bit counter @9000 */
 273     s->rtc = time(NULL);
 274     s->rtc_ref = 0;
 275 }
 276
 277 static void lasi_init(Object *obj)
 278 {
 279     LasiState *s = LASI_CHIP(obj);
 280     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 281
 282     memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops,
 283                           s, "lasi", 0x100000);
 284
 285     sysbus_init_mmio(sbd, &s->this_mem);
 286
 287     qdev_init_gpio_in(DEVICE(obj), lasi_set_irq, LASI_IRQS);
 288 }
 289
 290 static void lasi_class_init(ObjectClass *klass, void *data)
 291 {
 292     DeviceClass *dc = DEVICE_CLASS(klass);
 293
 294     dc->reset = lasi_reset;
 295     dc->vmsd = &vmstate_lasi;
 296 }
 297
 298 static const TypeInfo lasi_pcihost_info = {
 299     .name          = TYPE_LASI_CHIP,
 300     .parent        = TYPE_SYS_BUS_DEVICE,
 301     .instance_init = lasi_init,
 302     .instance_size = sizeof(LasiState),
 303     .class_init    = lasi_class_init,
 304 };
 305
 306 static void lasi_register_types(void)
 307 {
 308     type_register_static(&lasi_pcihost_info);
 309 }
 310
 311 type_init(lasi_register_types)