2 * QEMU Arm CPU -- feature test functions
4 * Copyright (c) 2023 Linaro Ltd
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef TARGET_ARM_FEATURES_H
21 #define TARGET_ARM_FEATURES_H
23 #include "hw/registerfields.h"
26 * Naming convention for isar_feature functions:
27 * Functions which test 32-bit ID registers should have _aa32_ in
28 * their name. Functions which test 64-bit ID registers should have
29 * _aa64_ in their name. These must only be used in code where we
30 * know for certain that the CPU has AArch32 or AArch64 respectively
31 * or where the correct answer for a CPU which doesn't implement that
32 * CPU state is "false" (eg when generating A32 or A64 code, if adding
33 * system registers that are specific to that CPU state, for "should
34 * we let this system register bit be set" tests where the 32-bit
35 * flavour of the register doesn't have the bit, and so on).
36 * Functions which simply ask "does this feature exist at all" have
37 * _any_ in their name, and always return the logical OR of the _aa64_
38 * and the _aa32_ function.
42 * 32-bit feature tests via id registers.
44 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters
*id
)
46 return FIELD_EX32(id
->id_isar0
, ID_ISAR0
, DIVIDE
) != 0;
49 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters
*id
)
51 return FIELD_EX32(id
->id_isar0
, ID_ISAR0
, DIVIDE
) > 1;
54 static inline bool isar_feature_aa32_lob(const ARMISARegisters
*id
)
56 /* (M-profile) low-overhead loops and branch future */
57 return FIELD_EX32(id
->id_isar0
, ID_ISAR0
, CMPBRANCH
) >= 3;
60 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters
*id
)
62 return FIELD_EX32(id
->id_isar1
, ID_ISAR1
, JAZELLE
) != 0;
65 static inline bool isar_feature_aa32_aes(const ARMISARegisters
*id
)
67 return FIELD_EX32(id
->id_isar5
, ID_ISAR5
, AES
) != 0;
70 static inline bool isar_feature_aa32_pmull(const ARMISARegisters
*id
)
72 return FIELD_EX32(id
->id_isar5
, ID_ISAR5
, AES
) > 1;
75 static inline bool isar_feature_aa32_sha1(const ARMISARegisters
*id
)
77 return FIELD_EX32(id
->id_isar5
, ID_ISAR5
, SHA1
) != 0;
80 static inline bool isar_feature_aa32_sha2(const ARMISARegisters
*id
)
82 return FIELD_EX32(id
->id_isar5
, ID_ISAR5
, SHA2
) != 0;
85 static inline bool isar_feature_aa32_crc32(const ARMISARegisters
*id
)
87 return FIELD_EX32(id
->id_isar5
, ID_ISAR5
, CRC32
) != 0;
90 static inline bool isar_feature_aa32_rdm(const ARMISARegisters
*id
)
92 return FIELD_EX32(id
->id_isar5
, ID_ISAR5
, RDM
) != 0;
95 static inline bool isar_feature_aa32_vcma(const ARMISARegisters
*id
)
97 return FIELD_EX32(id
->id_isar5
, ID_ISAR5
, VCMA
) != 0;
100 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters
*id
)
102 return FIELD_EX32(id
->id_isar6
, ID_ISAR6
, JSCVT
) != 0;
105 static inline bool isar_feature_aa32_dp(const ARMISARegisters
*id
)
107 return FIELD_EX32(id
->id_isar6
, ID_ISAR6
, DP
) != 0;
110 static inline bool isar_feature_aa32_fhm(const ARMISARegisters
*id
)
112 return FIELD_EX32(id
->id_isar6
, ID_ISAR6
, FHM
) != 0;
115 static inline bool isar_feature_aa32_sb(const ARMISARegisters
*id
)
117 return FIELD_EX32(id
->id_isar6
, ID_ISAR6
, SB
) != 0;
120 static inline bool isar_feature_aa32_predinv(const ARMISARegisters
*id
)
122 return FIELD_EX32(id
->id_isar6
, ID_ISAR6
, SPECRES
) != 0;
125 static inline bool isar_feature_aa32_bf16(const ARMISARegisters
*id
)
127 return FIELD_EX32(id
->id_isar6
, ID_ISAR6
, BF16
) != 0;
130 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters
*id
)
132 return FIELD_EX32(id
->id_isar6
, ID_ISAR6
, I8MM
) != 0;
135 static inline bool isar_feature_aa32_ras(const ARMISARegisters
*id
)
137 return FIELD_EX32(id
->id_pfr0
, ID_PFR0
, RAS
) != 0;
140 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters
*id
)
142 return FIELD_EX32(id
->id_pfr1
, ID_PFR1
, MPROGMOD
) != 0;
145 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters
*id
)
148 * Return true if M-profile state handling insns
149 * (VSCCLRM, CLRM, FPCTX access insns) are implemented
151 return FIELD_EX32(id
->id_pfr1
, ID_PFR1
, SECURITY
) >= 3;
154 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters
*id
)
156 /* Sadly this is encoded differently for A-profile and M-profile */
157 if (isar_feature_aa32_mprofile(id
)) {
158 return FIELD_EX32(id
->mvfr1
, MVFR1
, FP16
) > 0;
160 return FIELD_EX32(id
->mvfr1
, MVFR1
, FPHP
) >= 3;
164 static inline bool isar_feature_aa32_mve(const ARMISARegisters
*id
)
167 * Return true if MVE is supported (either integer or floating point).
168 * We must check for M-profile as the MVFR1 field means something
169 * else for A-profile.
171 return isar_feature_aa32_mprofile(id
) &&
172 FIELD_EX32(id
->mvfr1
, MVFR1
, MVE
) > 0;
175 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters
*id
)
178 * Return true if MVE is supported (either integer or floating point).
179 * We must check for M-profile as the MVFR1 field means something
180 * else for A-profile.
182 return isar_feature_aa32_mprofile(id
) &&
183 FIELD_EX32(id
->mvfr1
, MVFR1
, MVE
) >= 2;
186 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters
*id
)
189 * Return true if either VFP or SIMD is implemented.
190 * In this case, a minimum of VFP w/ D0-D15.
192 return FIELD_EX32(id
->mvfr0
, MVFR0
, SIMDREG
) > 0;
195 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters
*id
)
197 /* Return true if D16-D31 are implemented */
198 return FIELD_EX32(id
->mvfr0
, MVFR0
, SIMDREG
) >= 2;
201 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters
*id
)
203 return FIELD_EX32(id
->mvfr0
, MVFR0
, FPSHVEC
) > 0;
206 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters
*id
)
208 /* Return true if CPU supports single precision floating point, VFPv2 */
209 return FIELD_EX32(id
->mvfr0
, MVFR0
, FPSP
) > 0;
212 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters
*id
)
214 /* Return true if CPU supports single precision floating point, VFPv3 */
215 return FIELD_EX32(id
->mvfr0
, MVFR0
, FPSP
) >= 2;
218 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters
*id
)
220 /* Return true if CPU supports double precision floating point, VFPv2 */
221 return FIELD_EX32(id
->mvfr0
, MVFR0
, FPDP
) > 0;
224 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters
*id
)
226 /* Return true if CPU supports double precision floating point, VFPv3 */
227 return FIELD_EX32(id
->mvfr0
, MVFR0
, FPDP
) >= 2;
230 static inline bool isar_feature_aa32_vfp(const ARMISARegisters
*id
)
232 return isar_feature_aa32_fpsp_v2(id
) || isar_feature_aa32_fpdp_v2(id
);
236 * We always set the FP and SIMD FP16 fields to indicate identical
237 * levels of support (assuming SIMD is implemented at all), so
238 * we only need one set of accessors.
240 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters
*id
)
242 return FIELD_EX32(id
->mvfr1
, MVFR1
, FPHP
) > 0;
245 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters
*id
)
247 return FIELD_EX32(id
->mvfr1
, MVFR1
, FPHP
) > 1;
251 * Note that this ID register field covers both VFP and Neon FMAC,
252 * so should usually be tested in combination with some other
253 * check that confirms the presence of whichever of VFP or Neon is
254 * relevant, to avoid accidentally enabling a Neon feature on
255 * a VFP-no-Neon core or vice-versa.
257 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters
*id
)
259 return FIELD_EX32(id
->mvfr1
, MVFR1
, SIMDFMAC
) != 0;
262 static inline bool isar_feature_aa32_vsel(const ARMISARegisters
*id
)
264 return FIELD_EX32(id
->mvfr2
, MVFR2
, FPMISC
) >= 1;
267 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters
*id
)
269 return FIELD_EX32(id
->mvfr2
, MVFR2
, FPMISC
) >= 2;
272 static inline bool isar_feature_aa32_vrint(const ARMISARegisters
*id
)
274 return FIELD_EX32(id
->mvfr2
, MVFR2
, FPMISC
) >= 3;
277 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters
*id
)
279 return FIELD_EX32(id
->mvfr2
, MVFR2
, FPMISC
) >= 4;
282 static inline bool isar_feature_aa32_pxn(const ARMISARegisters
*id
)
284 return FIELD_EX32(id
->id_mmfr0
, ID_MMFR0
, VMSA
) >= 4;
287 static inline bool isar_feature_aa32_pan(const ARMISARegisters
*id
)
289 return FIELD_EX32(id
->id_mmfr3
, ID_MMFR3
, PAN
) != 0;
292 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters
*id
)
294 return FIELD_EX32(id
->id_mmfr3
, ID_MMFR3
, PAN
) >= 2;
297 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters
*id
)
299 /* 0xf means "non-standard IMPDEF PMU" */
300 return FIELD_EX32(id
->id_dfr0
, ID_DFR0
, PERFMON
) >= 4 &&
301 FIELD_EX32(id
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf;
304 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters
*id
)
306 /* 0xf means "non-standard IMPDEF PMU" */
307 return FIELD_EX32(id
->id_dfr0
, ID_DFR0
, PERFMON
) >= 5 &&
308 FIELD_EX32(id
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf;
311 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters
*id
)
313 /* 0xf means "non-standard IMPDEF PMU" */
314 return FIELD_EX32(id
->id_dfr0
, ID_DFR0
, PERFMON
) >= 6 &&
315 FIELD_EX32(id
->id_dfr0
, ID_DFR0
, PERFMON
) != 0xf;
318 static inline bool isar_feature_aa32_hpd(const ARMISARegisters
*id
)
320 return FIELD_EX32(id
->id_mmfr4
, ID_MMFR4
, HPDS
) != 0;
323 static inline bool isar_feature_aa32_ac2(const ARMISARegisters
*id
)
325 return FIELD_EX32(id
->id_mmfr4
, ID_MMFR4
, AC2
) != 0;
328 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters
*id
)
330 return FIELD_EX32(id
->id_mmfr4
, ID_MMFR4
, CCIDX
) != 0;
333 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters
*id
)
335 return FIELD_EX32(id
->id_mmfr4
, ID_MMFR4
, XNX
) != 0;
338 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters
*id
)
340 return FIELD_EX32(id
->id_mmfr4
, ID_MMFR4
, EVT
) >= 1;
343 static inline bool isar_feature_aa32_evt(const ARMISARegisters
*id
)
345 return FIELD_EX32(id
->id_mmfr4
, ID_MMFR4
, EVT
) >= 2;
348 static inline bool isar_feature_aa32_dit(const ARMISARegisters
*id
)
350 return FIELD_EX32(id
->id_pfr0
, ID_PFR0
, DIT
) != 0;
353 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters
*id
)
355 return FIELD_EX32(id
->id_pfr2
, ID_PFR2
, SSBS
) != 0;
358 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters
*id
)
360 return FIELD_EX32(id
->id_dfr0
, ID_DFR0
, COPDBG
) >= 5;
363 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters
*id
)
365 return FIELD_EX32(id
->id_dfr0
, ID_DFR0
, COPDBG
) >= 8;
368 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters
*id
)
370 return FIELD_EX32(id
->dbgdevid
, DBGDEVID
, DOUBLELOCK
) > 0;
374 * 64-bit feature tests via id registers.
376 static inline bool isar_feature_aa64_aes(const ARMISARegisters
*id
)
378 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, AES
) != 0;
381 static inline bool isar_feature_aa64_pmull(const ARMISARegisters
*id
)
383 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, AES
) > 1;
386 static inline bool isar_feature_aa64_sha1(const ARMISARegisters
*id
)
388 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, SHA1
) != 0;
391 static inline bool isar_feature_aa64_sha256(const ARMISARegisters
*id
)
393 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, SHA2
) != 0;
396 static inline bool isar_feature_aa64_sha512(const ARMISARegisters
*id
)
398 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, SHA2
) > 1;
401 static inline bool isar_feature_aa64_crc32(const ARMISARegisters
*id
)
403 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, CRC32
) != 0;
406 static inline bool isar_feature_aa64_atomics(const ARMISARegisters
*id
)
408 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, ATOMIC
) != 0;
411 static inline bool isar_feature_aa64_rdm(const ARMISARegisters
*id
)
413 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, RDM
) != 0;
416 static inline bool isar_feature_aa64_sha3(const ARMISARegisters
*id
)
418 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, SHA3
) != 0;
421 static inline bool isar_feature_aa64_sm3(const ARMISARegisters
*id
)
423 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, SM3
) != 0;
426 static inline bool isar_feature_aa64_sm4(const ARMISARegisters
*id
)
428 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, SM4
) != 0;
431 static inline bool isar_feature_aa64_dp(const ARMISARegisters
*id
)
433 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, DP
) != 0;
436 static inline bool isar_feature_aa64_fhm(const ARMISARegisters
*id
)
438 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, FHM
) != 0;
441 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters
*id
)
443 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, TS
) != 0;
446 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters
*id
)
448 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, TS
) >= 2;
451 static inline bool isar_feature_aa64_rndr(const ARMISARegisters
*id
)
453 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, RNDR
) != 0;
456 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters
*id
)
458 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, TLB
) == 2;
461 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters
*id
)
463 return FIELD_EX64(id
->id_aa64isar0
, ID_AA64ISAR0
, TLB
) != 0;
466 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters
*id
)
468 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, JSCVT
) != 0;
471 static inline bool isar_feature_aa64_fcma(const ARMISARegisters
*id
)
473 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, FCMA
) != 0;
477 * These are the values from APA/API/APA3.
478 * In general these must be compared '>=', per the normal Arm ARM
479 * treatment of fields in ID registers.
487 PauthFeat_FPACCOMBINED
= 5,
490 static inline ARMPauthFeature
491 isar_feature_pauth_feature(const ARMISARegisters
*id
)
494 * Architecturally, only one of {APA,API,APA3} may be active (non-zero)
495 * and the other two must be zero. Thus we may avoid conditionals.
497 return (FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, APA
) |
498 FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, API
) |
499 FIELD_EX64(id
->id_aa64isar2
, ID_AA64ISAR2
, APA3
));
502 static inline bool isar_feature_aa64_pauth(const ARMISARegisters
*id
)
505 * Return true if any form of pauth is enabled, as this
506 * predicate controls migration of the 128-bit keys.
508 return isar_feature_pauth_feature(id
) != PauthFeat_None
;
511 static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters
*id
)
514 * Return true if pauth is enabled with the architected QARMA5 algorithm.
515 * QEMU will always enable or disable both APA and GPA.
517 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, APA
) != 0;
520 static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters
*id
)
523 * Return true if pauth is enabled with the architected QARMA3 algorithm.
524 * QEMU will always enable or disable both APA3 and GPA3.
526 return FIELD_EX64(id
->id_aa64isar2
, ID_AA64ISAR2
, APA3
) != 0;
529 static inline bool isar_feature_aa64_sb(const ARMISARegisters
*id
)
531 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, SB
) != 0;
534 static inline bool isar_feature_aa64_predinv(const ARMISARegisters
*id
)
536 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, SPECRES
) != 0;
539 static inline bool isar_feature_aa64_frint(const ARMISARegisters
*id
)
541 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, FRINTTS
) != 0;
544 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters
*id
)
546 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, DPB
) != 0;
549 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters
*id
)
551 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, DPB
) >= 2;
554 static inline bool isar_feature_aa64_bf16(const ARMISARegisters
*id
)
556 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, BF16
) != 0;
559 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters
*id
)
561 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, LRCPC
) != 0;
564 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters
*id
)
566 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, LRCPC
) >= 2;
569 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters
*id
)
571 return FIELD_EX64(id
->id_aa64isar1
, ID_AA64ISAR1
, I8MM
) != 0;
574 static inline bool isar_feature_aa64_hbc(const ARMISARegisters
*id
)
576 return FIELD_EX64(id
->id_aa64isar2
, ID_AA64ISAR2
, BC
) != 0;
579 static inline bool isar_feature_aa64_mops(const ARMISARegisters
*id
)
581 return FIELD_EX64(id
->id_aa64isar2
, ID_AA64ISAR2
, MOPS
);
584 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters
*id
)
586 /* We always set the AdvSIMD and FP fields identically. */
587 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, FP
) != 0xf;
590 static inline bool isar_feature_aa64_fp16(const ARMISARegisters
*id
)
592 /* We always set the AdvSIMD and FP fields identically wrt FP16. */
593 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, FP
) == 1;
596 static inline bool isar_feature_aa64_aa32(const ARMISARegisters
*id
)
598 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, EL0
) >= 2;
601 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters
*id
)
603 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, EL1
) >= 2;
606 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters
*id
)
608 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, EL2
) >= 2;
611 static inline bool isar_feature_aa64_ras(const ARMISARegisters
*id
)
613 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, RAS
) != 0;
616 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters
*id
)
618 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, RAS
) >= 2;
621 static inline bool isar_feature_aa64_sve(const ARMISARegisters
*id
)
623 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, SVE
) != 0;
626 static inline bool isar_feature_aa64_sel2(const ARMISARegisters
*id
)
628 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, SEL2
) != 0;
631 static inline bool isar_feature_aa64_rme(const ARMISARegisters
*id
)
633 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, RME
) != 0;
636 static inline bool isar_feature_aa64_dit(const ARMISARegisters
*id
)
638 return FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, DIT
) != 0;
641 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters
*id
)
643 int key
= FIELD_EX64(id
->id_aa64pfr0
, ID_AA64PFR0
, CSV2
);
645 return true; /* FEAT_CSV2_2 */
648 key
= FIELD_EX64(id
->id_aa64pfr1
, ID_AA64PFR1
, CSV2_FRAC
);
649 return key
>= 2; /* FEAT_CSV2_1p2 */
654 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters
*id
)
656 return FIELD_EX64(id
->id_aa64pfr1
, ID_AA64PFR1
, SSBS
) != 0;
659 static inline bool isar_feature_aa64_bti(const ARMISARegisters
*id
)
661 return FIELD_EX64(id
->id_aa64pfr1
, ID_AA64PFR1
, BT
) != 0;
664 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters
*id
)
666 return FIELD_EX64(id
->id_aa64pfr1
, ID_AA64PFR1
, MTE
) != 0;
669 static inline bool isar_feature_aa64_mte(const ARMISARegisters
*id
)
671 return FIELD_EX64(id
->id_aa64pfr1
, ID_AA64PFR1
, MTE
) >= 2;
674 static inline bool isar_feature_aa64_mte3(const ARMISARegisters
*id
)
676 return FIELD_EX64(id
->id_aa64pfr1
, ID_AA64PFR1
, MTE
) >= 3;
679 static inline bool isar_feature_aa64_sme(const ARMISARegisters
*id
)
681 return FIELD_EX64(id
->id_aa64pfr1
, ID_AA64PFR1
, SME
) != 0;
684 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters
*id
)
686 return FIELD_SEX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN4
) >= 1;
689 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters
*id
)
691 unsigned t
= FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN4_2
);
692 return t
>= 3 || (t
== 0 && isar_feature_aa64_tgran4_lpa2(id
));
695 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters
*id
)
697 return FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN16
) >= 2;
700 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters
*id
)
702 unsigned t
= FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN16_2
);
703 return t
>= 3 || (t
== 0 && isar_feature_aa64_tgran16_lpa2(id
));
706 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters
*id
)
708 return FIELD_SEX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN4
) >= 0;
711 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters
*id
)
713 return FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN16
) >= 1;
716 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters
*id
)
718 return FIELD_SEX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN64
) >= 0;
721 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters
*id
)
723 unsigned t
= FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN4_2
);
724 return t
>= 2 || (t
== 0 && isar_feature_aa64_tgran4(id
));
727 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters
*id
)
729 unsigned t
= FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN16_2
);
730 return t
>= 2 || (t
== 0 && isar_feature_aa64_tgran16(id
));
733 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters
*id
)
735 unsigned t
= FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, TGRAN64_2
);
736 return t
>= 2 || (t
== 0 && isar_feature_aa64_tgran64(id
));
739 static inline bool isar_feature_aa64_fgt(const ARMISARegisters
*id
)
741 return FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, FGT
) != 0;
744 static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters
*id
)
746 return FIELD_EX64(id
->id_aa64mmfr0
, ID_AA64MMFR0
, ECV
) > 0;
749 static inline bool isar_feature_aa64_vh(const ARMISARegisters
*id
)
751 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, VH
) != 0;
754 static inline bool isar_feature_aa64_lor(const ARMISARegisters
*id
)
756 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, LO
) != 0;
759 static inline bool isar_feature_aa64_pan(const ARMISARegisters
*id
)
761 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, PAN
) != 0;
764 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters
*id
)
766 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, PAN
) >= 2;
769 static inline bool isar_feature_aa64_pan3(const ARMISARegisters
*id
)
771 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, PAN
) >= 3;
774 static inline bool isar_feature_aa64_hcx(const ARMISARegisters
*id
)
776 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, HCX
) != 0;
779 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters
*id
)
781 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, TIDCP1
) != 0;
784 static inline bool isar_feature_aa64_hafs(const ARMISARegisters
*id
)
786 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, HAFDBS
) != 0;
789 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters
*id
)
791 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, HAFDBS
) >= 2;
794 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters
*id
)
796 return FIELD_EX64(id
->id_aa64mmfr1
, ID_AA64MMFR1
, XNX
) != 0;
799 static inline bool isar_feature_aa64_uao(const ARMISARegisters
*id
)
801 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, UAO
) != 0;
804 static inline bool isar_feature_aa64_st(const ARMISARegisters
*id
)
806 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, ST
) != 0;
809 static inline bool isar_feature_aa64_lse2(const ARMISARegisters
*id
)
811 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, AT
) != 0;
814 static inline bool isar_feature_aa64_fwb(const ARMISARegisters
*id
)
816 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, FWB
) != 0;
819 static inline bool isar_feature_aa64_ids(const ARMISARegisters
*id
)
821 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, IDS
) != 0;
824 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters
*id
)
826 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, EVT
) >= 1;
829 static inline bool isar_feature_aa64_evt(const ARMISARegisters
*id
)
831 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, EVT
) >= 2;
834 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters
*id
)
836 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, CCIDX
) != 0;
839 static inline bool isar_feature_aa64_lva(const ARMISARegisters
*id
)
841 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, VARANGE
) != 0;
844 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters
*id
)
846 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, E0PD
) != 0;
849 static inline bool isar_feature_aa64_nv(const ARMISARegisters
*id
)
851 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, NV
) != 0;
854 static inline bool isar_feature_aa64_nv2(const ARMISARegisters
*id
)
856 return FIELD_EX64(id
->id_aa64mmfr2
, ID_AA64MMFR2
, NV
) >= 2;
859 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters
*id
)
861 return FIELD_EX64(id
->id_aa64dfr0
, ID_AA64DFR0
, PMUVER
) >= 4 &&
862 FIELD_EX64(id
->id_aa64dfr0
, ID_AA64DFR0
, PMUVER
) != 0xf;
865 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters
*id
)
867 return FIELD_EX64(id
->id_aa64dfr0
, ID_AA64DFR0
, PMUVER
) >= 5 &&
868 FIELD_EX64(id
->id_aa64dfr0
, ID_AA64DFR0
, PMUVER
) != 0xf;
871 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters
*id
)
873 return FIELD_EX64(id
->id_aa64dfr0
, ID_AA64DFR0
, PMUVER
) >= 6 &&
874 FIELD_EX64(id
->id_aa64dfr0
, ID_AA64DFR0
, PMUVER
) != 0xf;
877 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters
*id
)
879 return FIELD_EX64(id
->id_aa64dfr0
, ID_AA64DFR0
, DEBUGVER
) >= 8;
882 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters
*id
)
884 return FIELD_SEX64(id
->id_aa64dfr0
, ID_AA64DFR0
, DOUBLELOCK
) >= 0;
887 static inline bool isar_feature_aa64_sve2(const ARMISARegisters
*id
)
889 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, SVEVER
) != 0;
892 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters
*id
)
894 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, AES
) != 0;
897 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters
*id
)
899 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, AES
) >= 2;
902 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters
*id
)
904 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, BITPERM
) != 0;
907 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters
*id
)
909 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, BFLOAT16
) != 0;
912 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters
*id
)
914 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, SHA3
) != 0;
917 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters
*id
)
919 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, SM4
) != 0;
922 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters
*id
)
924 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, I8MM
) != 0;
927 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters
*id
)
929 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, F32MM
) != 0;
932 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters
*id
)
934 return FIELD_EX64(id
->id_aa64zfr0
, ID_AA64ZFR0
, F64MM
) != 0;
937 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters
*id
)
939 return FIELD_EX64(id
->id_aa64smfr0
, ID_AA64SMFR0
, F64F64
);
942 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters
*id
)
944 return FIELD_EX64(id
->id_aa64smfr0
, ID_AA64SMFR0
, I16I64
) == 0xf;
947 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters
*id
)
949 return FIELD_EX64(id
->id_aa64smfr0
, ID_AA64SMFR0
, FA64
);
953 * Feature tests for "does this exist in either 32-bit or 64-bit?"
955 static inline bool isar_feature_any_fp16(const ARMISARegisters
*id
)
957 return isar_feature_aa64_fp16(id
) || isar_feature_aa32_fp16_arith(id
);
960 static inline bool isar_feature_any_predinv(const ARMISARegisters
*id
)
962 return isar_feature_aa64_predinv(id
) || isar_feature_aa32_predinv(id
);
965 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters
*id
)
967 return isar_feature_aa64_pmuv3p1(id
) || isar_feature_aa32_pmuv3p1(id
);
970 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters
*id
)
972 return isar_feature_aa64_pmuv3p4(id
) || isar_feature_aa32_pmuv3p4(id
);
975 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters
*id
)
977 return isar_feature_aa64_pmuv3p5(id
) || isar_feature_aa32_pmuv3p5(id
);
980 static inline bool isar_feature_any_ccidx(const ARMISARegisters
*id
)
982 return isar_feature_aa64_ccidx(id
) || isar_feature_aa32_ccidx(id
);
985 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters
*id
)
987 return isar_feature_aa64_tts2uxn(id
) || isar_feature_aa32_tts2uxn(id
);
990 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters
*id
)
992 return isar_feature_aa64_debugv8p2(id
) || isar_feature_aa32_debugv8p2(id
);
995 static inline bool isar_feature_any_ras(const ARMISARegisters
*id
)
997 return isar_feature_aa64_ras(id
) || isar_feature_aa32_ras(id
);
1000 static inline bool isar_feature_any_half_evt(const ARMISARegisters
*id
)
1002 return isar_feature_aa64_half_evt(id
) || isar_feature_aa32_half_evt(id
);
1005 static inline bool isar_feature_any_evt(const ARMISARegisters
*id
)
1007 return isar_feature_aa64_evt(id
) || isar_feature_aa32_evt(id
);
1011 * Forward to the above feature tests given an ARMCPU pointer.
1013 #define cpu_isar_feature(name, cpu) \
1014 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })