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target/i386/WHPX: Fix error message when fail to set ProcessorCount
[qemu/armbru.git] / hw / ppc / pegasos2.c
blobaf5489de26ed05a41cf4c28d5b59860b64eb5622
1 /*
2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
3 *
4 * Copyright (c) 2018-2021 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/units.h"
12 #include "qapi/error.h"
13 #include "hw/ppc/ppc.h"
14 #include "hw/sysbus.h"
15 #include "hw/pci/pci_host.h"
16 #include "hw/irq.h"
17 #include "hw/pci-host/mv64361.h"
18 #include "hw/isa/vt82c686.h"
19 #include "hw/ide/pci.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/qdev-properties.h"
22 #include "sysemu/reset.h"
23 #include "sysemu/runstate.h"
24 #include "sysemu/qtest.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/fw-path-provider.h"
28 #include "elf.h"
29 #include "qemu/log.h"
30 #include "qemu/error-report.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33 #include "exec/address-spaces.h"
34 #include "qom/qom-qobject.h"
35 #include "qapi/qmp/qdict.h"
36 #include "trace.h"
37 #include "qemu/datadir.h"
38 #include "sysemu/device_tree.h"
39 #include "hw/ppc/vof.h"
40
41 #include <libfdt.h>
42
43 #define PROM_FILENAME "vof.bin"
44 #define PROM_ADDR 0xfff00000
45 #define PROM_SIZE 0x80000
46
47 #define KVMPPC_HCALL_BASE 0xf000
48 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
49 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
50
51 #define H_SUCCESS 0
52 #define H_PRIVILEGE -3 /* Caller not privileged */
53 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
54
55 #define BUS_FREQ_HZ 133333333
56
57 #define PCI0_CFG_ADDR 0xcf8
58 #define PCI0_MEM_BASE 0xc0000000
59 #define PCI0_MEM_SIZE 0x20000000
60 #define PCI0_IO_BASE 0xf8000000
61 #define PCI0_IO_SIZE 0x10000
62
63 #define PCI1_CFG_ADDR 0xc78
64 #define PCI1_MEM_BASE 0x80000000
65 #define PCI1_MEM_SIZE 0x40000000
66 #define PCI1_IO_BASE 0xfe000000
67 #define PCI1_IO_SIZE 0x10000
68
69 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2")
70 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
71
72 struct Pegasos2MachineState {
73 MachineState parent_obj;
74 PowerPCCPU *cpu;
75 DeviceState *mv;
76 qemu_irq mv_pirq[PCI_NUM_PINS];
77 qemu_irq via_pirq[PCI_NUM_PINS];
78 Vof *vof;
79 void *fdt_blob;
80 uint64_t kernel_addr;
81 uint64_t kernel_entry;
82 uint64_t kernel_size;
83 };
84
85 static void *build_fdt(MachineState *machine, int *fdt_size);
86
87 static void pegasos2_cpu_reset(void *opaque)
88 {
89 PowerPCCPU *cpu = opaque;
90 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine);
91
92 cpu_reset(CPU(cpu));
93 cpu->env.spr[SPR_HID1] = 7ULL << 28;
94 if (pm->vof) {
95 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
96 cpu->env.nip = 0x100;
97 }
98 }
99
100 static void pegasos2_pci_irq(void *opaque, int n, int level)
101 {
102 Pegasos2MachineState *pm = opaque;
103
104 /* PCI interrupt lines are connected to both MV64361 and VT8231 */
105 qemu_set_irq(pm->mv_pirq[n], level);
106 qemu_set_irq(pm->via_pirq[n], level);
107 }
108
109 static void pegasos2_init(MachineState *machine)
110 {
111 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
112 CPUPPCState *env;
113 MemoryRegion *rom = g_new(MemoryRegion, 1);
114 PCIBus *pci_bus;
115 Object *via;
116 PCIDevice *dev;
117 I2CBus *i2c_bus;
118 const char *fwname = machine->firmware ?: PROM_FILENAME;
119 char *filename;
120 int i, sz;
121 uint8_t *spd_data;
122
123 /* init CPU */
124 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
125 env = &pm->cpu->env;
126 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
127 error_report("Incompatible CPU, only 6xx bus supported");
128 exit(1);
129 }
130
131 /* Set time-base frequency */
132 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
133 qemu_register_reset(pegasos2_cpu_reset, pm->cpu);
134
135 /* RAM */
136 if (machine->ram_size > 2 * GiB) {
137 error_report("RAM size more than 2 GiB is not supported");
138 exit(1);
139 }
140 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
141
142 /* allocate and load firmware */
143 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
144 if (!filename) {
145 error_report("Could not find firmware '%s'", fwname);
146 exit(1);
147 }
148 if (!machine->firmware && !pm->vof) {
149 pm->vof = g_malloc0(sizeof(*pm->vof));
150 }
151 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
152 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
153 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1,
154 PPC_ELF_MACHINE, 0, 0);
155 if (sz <= 0) {
156 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE);
157 }
158 if (sz <= 0 || sz > PROM_SIZE) {
159 error_report("Could not load firmware '%s'", filename);
160 exit(1);
161 }
162 g_free(filename);
163 if (pm->vof) {
164 pm->vof->fw_size = sz;
165 }
166
167 /* Marvell Discovery II system controller */
168 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
169 qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
170 for (i = 0; i < PCI_NUM_PINS; i++) {
171 pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i);
172 }
173 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
174 pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS);
175
176 /* VIA VT8231 South Bridge (multifunction PCI device) */
177 via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0),
178 true, TYPE_VT8231_ISA));
179 for (i = 0; i < PCI_NUM_PINS; i++) {
180 pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i);
181 }
182 object_property_add_alias(OBJECT(machine), "rtc-time",
183 object_resolve_path_component(via, "rtc"),
184 "date");
185 qdev_connect_gpio_out(DEVICE(via), 0,
186 qdev_get_gpio_in_named(pm->mv, "gpp", 31));
187
188 dev = PCI_DEVICE(object_resolve_path_component(via, "ide"));
189 pci_ide_create_devs(dev);
190
191 dev = PCI_DEVICE(object_resolve_path_component(via, "pm"));
192 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
193 spd_data = spd_data_generate(DDR, machine->ram_size);
194 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
195
196 /* other PC hardware */
197 pci_vga_init(pci_bus);
198
199 if (machine->kernel_filename) {
200 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
201 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,
202 PPC_ELF_MACHINE, 0, 0);
203 if (sz <= 0) {
204 error_report("Could not load kernel '%s'",
205 machine->kernel_filename);
206 exit(1);
207 }
208 pm->kernel_size = sz;
209 if (!pm->vof) {
210 warn_report("Option -kernel may be ineffective with -bios.");
211 }
212 } else if (pm->vof && !qtest_enabled()) {
213 warn_report("Using Virtual OpenFirmware but no -kernel option.");
214 }
215
216 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
217 warn_report("Option -append may be ineffective with -bios.");
218 }
219 }
220
221 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm,
222 uint32_t addr, uint32_t len)
223 {
224 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
225 uint64_t val = 0xffffffffULL;
226 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE,
227 MEMTXATTRS_UNSPECIFIED);
228 return val;
229 }
230
231 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr,
232 uint32_t len, uint32_t val)
233 {
234 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
235 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE,
236 MEMTXATTRS_UNSPECIFIED);
237 }
238
239 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus,
240 uint32_t addr, uint32_t len)
241 {
242 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
243 uint64_t val = 0xffffffffULL;
244
245 if (len <= 4) {
246 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
247 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len);
248 }
249 return val;
250 }
251
252 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus,
253 uint32_t addr, uint32_t len, uint32_t val)
254 {
255 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
256
257 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
258 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
259 }
260
261 static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason)
262 {
263 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
264 void *fdt;
265 uint64_t d[2];
266 int sz;
267
268 qemu_devices_reset(reason);
269 if (!pm->vof) {
270 return; /* Firmware should set up machine so nothing to do */
271 }
272
273 /* Otherwise, set up devices that board firmware would normally do */
274 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
275 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc);
276 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400);
277 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000);
278 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000);
279 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
280 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
281 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
282 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
283
284 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
285 PCI_INTERRUPT_LINE, 2, 0x9);
286 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
287 0x50, 1, 0x2);
288 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
289 0x55, 1, 0x90);
290 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
291 0x56, 1, 0x99);
292 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
293 0x57, 1, 0x90);
294
295 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
296 PCI_INTERRUPT_LINE, 2, 0x109);
297 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
298 PCI_CLASS_PROG, 1, 0xf);
299 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
300 0x40, 1, 0xb);
301 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
302 0x50, 4, 0x17171717);
303 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
304 PCI_COMMAND, 2, 0x87);
305
306 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
307 PCI_INTERRUPT_LINE, 2, 0x409);
308
309 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
310 PCI_INTERRUPT_LINE, 2, 0x409);
311
312 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
313 PCI_INTERRUPT_LINE, 2, 0x9);
314 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
315 0x48, 4, 0xf00);
316 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
317 0x40, 4, 0x558020);
318 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
319 0x90, 4, 0xd00);
320
321 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) |
322 PCI_INTERRUPT_LINE, 2, 0x309);
323
324 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) |
325 PCI_INTERRUPT_LINE, 2, 0x309);
326
327 /* Device tree and VOF set up */
328 vof_init(pm->vof, machine->ram_size, &error_fatal);
329 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
330 error_report("Memory allocation for stack failed");
331 exit(1);
332 }
333 if (pm->kernel_size &&
334 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
335 error_report("Memory for kernel is in use");
336 exit(1);
337 }
338 fdt = build_fdt(machine, &sz);
339 /* FIXME: VOF assumes entry is same as load address */
340 d[0] = cpu_to_be64(pm->kernel_entry);
341 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
342 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
343
344 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
345 g_free(pm->fdt_blob);
346 pm->fdt_blob = fdt;
347
348 vof_build_dt(fdt, pm->vof);
349 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
350
351 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
352 machine->fdt = fdt;
353
354 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
355 }
356
357 enum pegasos2_rtas_tokens {
358 RTAS_RESTART_RTAS = 0,
359 RTAS_NVRAM_FETCH = 1,
360 RTAS_NVRAM_STORE = 2,
361 RTAS_GET_TIME_OF_DAY = 3,
362 RTAS_SET_TIME_OF_DAY = 4,
363 RTAS_EVENT_SCAN = 6,
364 RTAS_CHECK_EXCEPTION = 7,
365 RTAS_READ_PCI_CONFIG = 8,
366 RTAS_WRITE_PCI_CONFIG = 9,
367 RTAS_DISPLAY_CHARACTER = 10,
368 RTAS_SET_INDICATOR = 11,
369 RTAS_POWER_OFF = 17,
370 RTAS_SUSPEND = 18,
371 RTAS_HIBERNATE = 19,
372 RTAS_SYSTEM_REBOOT = 20,
373 };
374
375 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm,
376 target_ulong args_real)
377 {
378 AddressSpace *as = CPU(cpu)->as;
379 uint32_t token = ldl_be_phys(as, args_real);
380 uint32_t nargs = ldl_be_phys(as, args_real + 4);
381 uint32_t nrets = ldl_be_phys(as, args_real + 8);
382 uint32_t args = args_real + 12;
383 uint32_t rets = args_real + 12 + nargs * 4;
384
385 if (nrets < 1) {
386 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n");
387 return H_PARAMETER;
388 }
389 switch (token) {
390 case RTAS_GET_TIME_OF_DAY:
391 {
392 QObject *qo = object_property_get_qobject(qdev_get_machine(),
393 "rtc-time", &error_fatal);
394 QDict *qd = qobject_to(QDict, qo);
395
396 if (nargs != 0 || nrets != 8 || !qd) {
397 stl_be_phys(as, rets, -1);
398 qobject_unref(qo);
399 return H_PARAMETER;
400 }
401
402 stl_be_phys(as, rets, 0);
403 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
404 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
405 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
406 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
407 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
408 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
409 stl_be_phys(as, rets + 28, 0);
410 qobject_unref(qo);
411 return H_SUCCESS;
412 }
413 case RTAS_READ_PCI_CONFIG:
414 {
415 uint32_t addr, len, val;
416
417 if (nargs != 2 || nrets != 2) {
418 stl_be_phys(as, rets, -1);
419 return H_PARAMETER;
420 }
421 addr = ldl_be_phys(as, args);
422 len = ldl_be_phys(as, args + 4);
423 val = pegasos2_pci_config_read(pm, !(addr >> 24),
424 addr & 0x0fffffff, len);
425 stl_be_phys(as, rets, 0);
426 stl_be_phys(as, rets + 4, val);
427 return H_SUCCESS;
428 }
429 case RTAS_WRITE_PCI_CONFIG:
430 {
431 uint32_t addr, len, val;
432
433 if (nargs != 3 || nrets != 1) {
434 stl_be_phys(as, rets, -1);
435 return H_PARAMETER;
436 }
437 addr = ldl_be_phys(as, args);
438 len = ldl_be_phys(as, args + 4);
439 val = ldl_be_phys(as, args + 8);
440 pegasos2_pci_config_write(pm, !(addr >> 24),
441 addr & 0x0fffffff, len, val);
442 stl_be_phys(as, rets, 0);
443 return H_SUCCESS;
444 }
445 case RTAS_DISPLAY_CHARACTER:
446 if (nargs != 1 || nrets != 1) {
447 stl_be_phys(as, rets, -1);
448 return H_PARAMETER;
449 }
450 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
451 stl_be_phys(as, rets, 0);
452 return H_SUCCESS;
453 case RTAS_POWER_OFF:
454 {
455 if (nargs != 2 || nrets != 1) {
456 stl_be_phys(as, rets, -1);
457 return H_PARAMETER;
458 }
459 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
460 stl_be_phys(as, rets, 0);
461 return H_SUCCESS;
462 }
463 default:
464 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
465 token, nargs, nrets);
466 stl_be_phys(as, rets, 0);
467 return H_SUCCESS;
468 }
469 }
470
471 static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu)
472 {
473 return false;
474 }
475
476 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
477 {
478 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
479 CPUPPCState *env = &cpu->env;
480
481 /* The TCG path should also be holding the BQL at this point */
482 g_assert(qemu_mutex_iothread_locked());
483
484 if (FIELD_EX64(env->msr, MSR, PR)) {
485 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
486 env->gpr[3] = H_PRIVILEGE;
487 } else if (env->gpr[3] == KVMPPC_H_RTAS) {
488 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]);
489 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
490 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob,
491 env->gpr[4]);
492 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
493 } else {
494 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
495 "\n", env->gpr[3]);
496 env->gpr[3] = -1;
497 }
498 }
499
500 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
501 {
502 }
503
504 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
505 {
506 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
507 }
508
509 static bool pegasos2_setprop(MachineState *ms, const char *path,
510 const char *propname, void *val, int vallen)
511 {
512 return true;
513 }
514
515 static void pegasos2_machine_class_init(ObjectClass *oc, void *data)
516 {
517 MachineClass *mc = MACHINE_CLASS(oc);
518 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
519 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc);
520
521 mc->desc = "Genesi/bPlan Pegasos II";
522 mc->init = pegasos2_init;
523 mc->reset = pegasos2_machine_reset;
524 mc->block_default_type = IF_IDE;
525 mc->default_boot_order = "cd";
526 mc->default_display = "std";
527 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2");
528 mc->default_ram_id = "pegasos2.ram";
529 mc->default_ram_size = 512 * MiB;
530
531 vhc->cpu_in_nested = pegasos2_cpu_in_nested;
532 vhc->hypercall = pegasos2_hypercall;
533 vhc->cpu_exec_enter = vhyp_nop;
534 vhc->cpu_exec_exit = vhyp_nop;
535 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
536
537 vmc->setprop = pegasos2_setprop;
538 }
539
540 static const TypeInfo pegasos2_machine_info = {
541 .name = TYPE_PEGASOS2_MACHINE,
542 .parent = TYPE_MACHINE,
543 .class_init = pegasos2_machine_class_init,
544 .instance_size = sizeof(Pegasos2MachineState),
545 .interfaces = (InterfaceInfo[]) {
546 { TYPE_PPC_VIRTUAL_HYPERVISOR },
547 { TYPE_VOF_MACHINE_IF },
548 { }
549 },
550 };
551
552 static void pegasos2_machine_register_types(void)
553 {
554 type_register_static(&pegasos2_machine_info);
555 }
556
557 type_init(pegasos2_machine_register_types)
558
559 /* FDT creation for passing to firmware */
560
561 typedef struct {
562 void *fdt;
563 const char *path;
564 } FDTInfo;
565
566 /* We do everything in reverse order so it comes out right in the tree */
567
568 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
569 {
570 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
571 }
572
573 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
574 {
575 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
576 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
577 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
578 }
579
580 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
581 {
582 GString *name = g_string_sized_new(64);
583 uint32_t cells[3];
584
585 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1);
586 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2);
587 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
588 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
589
590 /* additional devices */
591 g_string_printf(name, "%s/lpt@i3bc", fi->path);
592 qemu_fdt_add_subnode(fi->fdt, name->str);
593 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
594 cells[0] = cpu_to_be32(7);
595 cells[1] = 0;
596 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
597 cells, 2 * sizeof(cells[0]));
598 cells[0] = cpu_to_be32(1);
599 cells[1] = cpu_to_be32(0x3bc);
600 cells[2] = cpu_to_be32(8);
601 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
602 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt");
603 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt");
604
605 g_string_printf(name, "%s/fdc@i3f0", fi->path);
606 qemu_fdt_add_subnode(fi->fdt, name->str);
607 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
608 cells[0] = cpu_to_be32(6);
609 cells[1] = 0;
610 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
611 cells, 2 * sizeof(cells[0]));
612 cells[0] = cpu_to_be32(1);
613 cells[1] = cpu_to_be32(0x3f0);
614 cells[2] = cpu_to_be32(8);
615 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
616 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc");
617 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc");
618
619 g_string_printf(name, "%s/timer@i40", fi->path);
620 qemu_fdt_add_subnode(fi->fdt, name->str);
621 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
622 cells[0] = cpu_to_be32(1);
623 cells[1] = cpu_to_be32(0x40);
624 cells[2] = cpu_to_be32(8);
625 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
626 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer");
627 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer");
628
629 g_string_printf(name, "%s/rtc@i70", fi->path);
630 qemu_fdt_add_subnode(fi->fdt, name->str);
631 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc");
632 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
633 cells[0] = cpu_to_be32(8);
634 cells[1] = 0;
635 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
636 cells, 2 * sizeof(cells[0]));
637 cells[0] = cpu_to_be32(1);
638 cells[1] = cpu_to_be32(0x70);
639 cells[2] = cpu_to_be32(2);
640 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
641 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc");
642 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc");
643
644 g_string_printf(name, "%s/keyboard@i60", fi->path);
645 qemu_fdt_add_subnode(fi->fdt, name->str);
646 cells[0] = cpu_to_be32(1);
647 cells[1] = 0;
648 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
649 cells, 2 * sizeof(cells[0]));
650 cells[0] = cpu_to_be32(1);
651 cells[1] = cpu_to_be32(0x60);
652 cells[2] = cpu_to_be32(5);
653 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
654 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard");
655 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard");
656
657 g_string_printf(name, "%s/8042@i60", fi->path);
658 qemu_fdt_add_subnode(fi->fdt, name->str);
659 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2);
660 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0);
661 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1);
662 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", "");
663 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
664 cells[0] = cpu_to_be32(1);
665 cells[1] = cpu_to_be32(0x60);
666 cells[2] = cpu_to_be32(5);
667 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
668 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "");
669 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042");
670
671 g_string_printf(name, "%s/serial@i2f8", fi->path);
672 qemu_fdt_add_subnode(fi->fdt, name->str);
673 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
674 cells[0] = cpu_to_be32(3);
675 cells[1] = 0;
676 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
677 cells, 2 * sizeof(cells[0]));
678 cells[0] = cpu_to_be32(1);
679 cells[1] = cpu_to_be32(0x2f8);
680 cells[2] = cpu_to_be32(8);
681 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
682 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial");
683 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial");
684
685 g_string_free(name, TRUE);
686 }
687
688 static struct {
689 const char *id;
690 const char *name;
691 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
692 } device_map[] = {
693 { "pci11ab,6460", "host", NULL },
694 { "pci1106,8231", "isa", dt_isa },
695 { "pci1106,571", "ide", dt_ide },
696 { "pci1106,3044", "firewire", NULL },
697 { "pci1106,3038", "usb", dt_usb },
698 { "pci1106,8235", "other", NULL },
699 { "pci1106,3058", "sound", NULL },
700 { NULL, NULL }
701 };
702
703 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
704 {
705 FDTInfo *fi = opaque;
706 GString *node = g_string_new(NULL);
707 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
708 int i, j;
709 const char *name = NULL;
710 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
711 pci_get_word(&d->config[PCI_VENDOR_ID]),
712 pci_get_word(&d->config[PCI_DEVICE_ID]));
713
714 for (i = 0; device_map[i].id; i++) {
715 if (!strcmp(pn, device_map[i].id)) {
716 name = device_map[i].name;
717 break;
718 }
719 }
720 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
721 PCI_SLOT(d->devfn));
722 if (PCI_FUNC(d->devfn)) {
723 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
724 }
725
726 qemu_fdt_add_subnode(fi->fdt, node->str);
727 if (device_map[i].dtf) {
728 FDTInfo cfi = { fi->fdt, node->str };
729 device_map[i].dtf(bus, d, &cfi);
730 }
731 cells[0] = cpu_to_be32(d->devfn << 8);
732 cells[1] = 0;
733 cells[2] = 0;
734 cells[3] = 0;
735 cells[4] = 0;
736 j = 5;
737 for (i = 0; i < PCI_NUM_REGIONS; i++) {
738 if (!d->io_regions[i].size) {
739 continue;
740 }
741 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
742 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
743 cells[j] |= cpu_to_be32(1 << 24);
744 } else {
745 cells[j] |= cpu_to_be32(2 << 24);
746 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
747 cells[j] |= cpu_to_be32(4 << 28);
748 }
749 }
750 cells[j + 1] = 0;
751 cells[j + 2] = 0;
752 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
753 cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
754 j += 5;
755 }
756 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
757 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn);
758 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
759 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
760 pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
761 }
762 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
763 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
764 pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
765 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
766 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
767 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
768 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
769 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
770 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
771 pci_get_word(&d->config[PCI_DEVICE_ID]));
772 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
773 pci_get_word(&d->config[PCI_VENDOR_ID]));
774
775 g_string_free(node, TRUE);
776 }
777
778 static void *build_fdt(MachineState *machine, int *fdt_size)
779 {
780 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
781 PowerPCCPU *cpu = pm->cpu;
782 PCIBus *pci_bus;
783 FDTInfo fi;
784 uint32_t cells[16];
785 void *fdt = create_device_tree(fdt_size);
786
787 fi.fdt = fdt;
788
789 /* root node */
790 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description",
791 "Pegasos CHRP PowerPC System");
792 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2");
793 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH");
794 qemu_fdt_setprop_string(fdt, "/", "revision", "2B");
795 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2");
796 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp");
797 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1);
798 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
799
800 /* pci@c0000000 */
801 qemu_fdt_add_subnode(fdt, "/pci@c0000000");
802 cells[0] = 0;
803 cells[1] = 0;
804 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range",
805 cells, 2 * sizeof(cells[0]));
806 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1);
807 cells[0] = cpu_to_be32(PCI0_MEM_BASE);
808 cells[1] = cpu_to_be32(PCI0_MEM_SIZE);
809 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0]));
810 cells[0] = cpu_to_be32(0x01000000);
811 cells[1] = 0;
812 cells[2] = 0;
813 cells[3] = cpu_to_be32(PCI0_IO_BASE);
814 cells[4] = 0;
815 cells[5] = cpu_to_be32(PCI0_IO_SIZE);
816 cells[6] = cpu_to_be32(0x02000000);
817 cells[7] = 0;
818 cells[8] = cpu_to_be32(PCI0_MEM_BASE);
819 cells[9] = cpu_to_be32(PCI0_MEM_BASE);
820 cells[10] = 0;
821 cells[11] = cpu_to_be32(PCI0_MEM_SIZE);
822 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges",
823 cells, 12 * sizeof(cells[0]));
824 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2);
825 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3);
826 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci");
827 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci");
828
829 fi.path = "/pci@c0000000";
830 pci_bus = mv64361_get_pci_bus(pm->mv, 0);
831 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
832
833 /* pci@80000000 */
834 qemu_fdt_add_subnode(fdt, "/pci@80000000");
835 cells[0] = 0;
836 cells[1] = 0;
837 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range",
838 cells, 2 * sizeof(cells[0]));
839 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0);
840 cells[0] = cpu_to_be32(PCI1_MEM_BASE);
841 cells[1] = cpu_to_be32(PCI1_MEM_SIZE);
842 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0]));
843 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge",
844 0xf1000cb4);
845 cells[0] = cpu_to_be32(0x01000000);
846 cells[1] = 0;
847 cells[2] = 0;
848 cells[3] = cpu_to_be32(PCI1_IO_BASE);
849 cells[4] = 0;
850 cells[5] = cpu_to_be32(PCI1_IO_SIZE);
851 cells[6] = cpu_to_be32(0x02000000);
852 cells[7] = 0;
853 cells[8] = cpu_to_be32(PCI1_MEM_BASE);
854 cells[9] = cpu_to_be32(PCI1_MEM_BASE);
855 cells[10] = 0;
856 cells[11] = cpu_to_be32(PCI1_MEM_SIZE);
857 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges",
858 cells, 12 * sizeof(cells[0]));
859 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2);
860 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3);
861 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci");
862 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci");
863
864 fi.path = "/pci@80000000";
865 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
866 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
867
868 qemu_fdt_add_subnode(fdt, "/failsafe");
869 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial");
870 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe");
871
872 qemu_fdt_add_subnode(fdt, "/rtas");
873 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT);
874 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE);
875 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND);
876 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF);
877 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR);
878 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character",
879 RTAS_DISPLAY_CHARACTER);
880 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config",
881 RTAS_WRITE_PCI_CONFIG);
882 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config",
883 RTAS_READ_PCI_CONFIG);
884 /* Pegasos2 firmware misspells check-exception and guests use that */
885 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption",
886 RTAS_CHECK_EXCEPTION);
887 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN);
888 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day",
889 RTAS_SET_TIME_OF_DAY);
890 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day",
891 RTAS_GET_TIME_OF_DAY);
892 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE);
893 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH);
894 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS);
895 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0);
896 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0);
897 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0);
898 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20);
899 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1);
900
901 /* cpus */
902 qemu_fdt_add_subnode(fdt, "/cpus");
903 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1);
904 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
905 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
906 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus");
907
908 /* FIXME Get CPU name from CPU object */
909 const char *cp = "/cpus/PowerPC,G4";
910 qemu_fdt_add_subnode(fdt, cp);
911 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
912 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
913 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
914 cpu->env.dcache_line_size);
915 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
916 cpu->env.dcache_line_size);
917 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
918 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
919 cpu->env.icache_line_size);
920 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
921 cpu->env.icache_line_size);
922 if (cpu->env.id_tlbs) {
923 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
924 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
925 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
926 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
927 qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
928 }
929 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
930 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
931 qemu_fdt_setprop_string(fdt, cp, "state", "running");
932 if (cpu->env.insns_flags & PPC_ALTIVEC) {
933 qemu_fdt_setprop_string(fdt, cp, "altivec", "");
934 qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
935 }
936 /*
937 * FIXME What flags do data-streams, external-control and
938 * performance-monitor depend on?
939 */
940 qemu_fdt_setprop_string(fdt, cp, "external-control", "");
941 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
942 qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
943 }
944 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
945 if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
946 qemu_fdt_setprop_string(fdt, cp, "graphics", "");
947 }
948 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
949 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
950 cpu->env.tb_env->tb_freq);
951 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ);
952 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5);
953 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
954 cells[0] = 0;
955 cells[1] = 0;
956 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
957 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
958 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1);
959
960 /* memory */
961 qemu_fdt_add_subnode(fdt, "/memory@0");
962 cells[0] = 0;
963 cells[1] = cpu_to_be32(machine->ram_size);
964 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0]));
965 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory");
966 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
967
968 qemu_fdt_add_subnode(fdt, "/chosen");
969 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
970 machine->kernel_cmdline ?: "");
971 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
972
973 qemu_fdt_add_subnode(fdt, "/openprom");
974 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1");
975
976 return fdt;
977 }
armbru's QEMU hackery