include/exec/cpu-all.h

   1 /*
   2  * defines common to all virtual CPUs
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ALL_H
  20 #define CPU_ALL_H
  21
  22 #include "exec/cpu-common.h"
  23 #include "exec/memory.h"
  24 #include "exec/tswap.h"
  25 #include "hw/core/cpu.h"
  26
  27 /* some important defines:
  28  *
  29  * HOST_BIG_ENDIAN : whether the host cpu is big endian and
  30  * otherwise little endian.
  31  *
  32  * TARGET_BIG_ENDIAN : same for the target cpu
  33  */
  34
  35 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
  36 #define BSWAP_NEEDED
  37 #endif
  38
  39 /* Target-endianness CPU memory access functions. These fit into the
  40  * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
  41  */
  42 #if TARGET_BIG_ENDIAN
  43 #define lduw_p(p) lduw_be_p(p)
  44 #define ldsw_p(p) ldsw_be_p(p)
  45 #define ldl_p(p) ldl_be_p(p)
  46 #define ldq_p(p) ldq_be_p(p)
  47 #define stw_p(p, v) stw_be_p(p, v)
  48 #define stl_p(p, v) stl_be_p(p, v)
  49 #define stq_p(p, v) stq_be_p(p, v)
  50 #define ldn_p(p, sz) ldn_be_p(p, sz)
  51 #define stn_p(p, sz, v) stn_be_p(p, sz, v)
  52 #else
  53 #define lduw_p(p) lduw_le_p(p)
  54 #define ldsw_p(p) ldsw_le_p(p)
  55 #define ldl_p(p) ldl_le_p(p)
  56 #define ldq_p(p) ldq_le_p(p)
  57 #define stw_p(p, v) stw_le_p(p, v)
  58 #define stl_p(p, v) stl_le_p(p, v)
  59 #define stq_p(p, v) stq_le_p(p, v)
  60 #define ldn_p(p, sz) ldn_le_p(p, sz)
  61 #define stn_p(p, sz, v) stn_le_p(p, sz, v)
  62 #endif
  63
  64 /* MMU memory access macros */
  65
  66 #if defined(CONFIG_USER_ONLY)
  67 #include "exec/user/abitypes.h"
  68 #include "user/guest-base.h"
  69
  70 extern bool have_guest_base;
  71
  72 /*
  73  * If non-zero, the guest virtual address space is a contiguous subset
  74  * of the host virtual address space, i.e. '-R reserved_va' is in effect
  75  * either from the command-line or by default.  The value is the last
  76  * byte of the guest address space e.g. UINT32_MAX.
  77  *
  78  * If zero, the host and guest virtual address spaces are intermingled.
  79  */
  80 extern unsigned long reserved_va;
  81
  82 /*
  83  * Limit the guest addresses as best we can.
  84  *
  85  * When not using -R reserved_va, we cannot really limit the guest
  86  * to less address space than the host.  For 32-bit guests, this
  87  * acts as a sanity check that we're not giving the guest an address
  88  * that it cannot even represent.  For 64-bit guests... the address
  89  * might not be what the real kernel would give, but it is at least
  90  * representable in the guest.
  91  *
  92  * TODO: Improve address allocation to avoid this problem, and to
  93  * avoid setting bits at the top of guest addresses that might need
  94  * to be used for tags.
  95  */
  96 #define GUEST_ADDR_MAX_                                                 \
  97     ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ?  \
  98      UINT32_MAX : ~0ul)
  99 #define GUEST_ADDR_MAX    (reserved_va ? : GUEST_ADDR_MAX_)
 100
 101 #else
 102
 103 #include "exec/hwaddr.h"
 104
 105 #define SUFFIX
 106 #define ARG1         as
 107 #define ARG1_DECL    AddressSpace *as
 108 #define TARGET_ENDIANNESS
 109 #include "exec/memory_ldst.h.inc"
 110
 111 #define SUFFIX       _cached_slow
 112 #define ARG1         cache
 113 #define ARG1_DECL    MemoryRegionCache *cache
 114 #define TARGET_ENDIANNESS
 115 #include "exec/memory_ldst.h.inc"
 116
 117 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
 118 {
 119     address_space_stl_notdirty(as, addr, val,
 120                                MEMTXATTRS_UNSPECIFIED, NULL);
 121 }
 122
 123 #define SUFFIX
 124 #define ARG1         as
 125 #define ARG1_DECL    AddressSpace *as
 126 #define TARGET_ENDIANNESS
 127 #include "exec/memory_ldst_phys.h.inc"
 128
 129 /* Inline fast path for direct RAM access.  */
 130 #define ENDIANNESS
 131 #include "exec/memory_ldst_cached.h.inc"
 132
 133 #define SUFFIX       _cached
 134 #define ARG1         cache
 135 #define ARG1_DECL    MemoryRegionCache *cache
 136 #define TARGET_ENDIANNESS
 137 #include "exec/memory_ldst_phys.h.inc"
 138 #endif
 139
 140 /* page related stuff */
 141
 142 #ifdef TARGET_PAGE_BITS_VARY
 143 # include "exec/page-vary.h"
 144 extern const TargetPageBits target_page;
 145 #ifdef CONFIG_DEBUG_TCG
 146 #define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
 147 #define TARGET_PAGE_MASK   ({ assert(target_page.decided); \
 148                               (target_long)target_page.mask; })
 149 #else
 150 #define TARGET_PAGE_BITS   target_page.bits
 151 #define TARGET_PAGE_MASK   ((target_long)target_page.mask)
 152 #endif
 153 #define TARGET_PAGE_SIZE   (-(int)TARGET_PAGE_MASK)
 154 #else
 155 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
 156 #define TARGET_PAGE_SIZE   (1 << TARGET_PAGE_BITS)
 157 #define TARGET_PAGE_MASK   ((target_long)-1 << TARGET_PAGE_BITS)
 158 #endif
 159
 160 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
 161
 162 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
 163 /* FIXME: Code that sets/uses this is broken and needs to go away.  */
 164 #define PAGE_RESERVED  0x0100
 165 #endif
 166 /*
 167  * For linux-user, indicates that the page is mapped with the same semantics
 168  * in both guest and host.
 169  */
 170 #define PAGE_PASSTHROUGH 0x0800
 171
 172 #if defined(CONFIG_USER_ONLY)
 173 void page_dump(FILE *f);
 174
 175 typedef int (*walk_memory_regions_fn)(void *, target_ulong,
 176                                       target_ulong, unsigned long);
 177 int walk_memory_regions(void *, walk_memory_regions_fn);
 178
 179 int page_get_flags(target_ulong address);
 180 void page_set_flags(target_ulong start, target_ulong last, int flags);
 181 void page_reset_target_data(target_ulong start, target_ulong last);
 182
 183 /**
 184  * page_check_range
 185  * @start: first byte of range
 186  * @len: length of range
 187  * @flags: flags required for each page
 188  *
 189  * Return true if every page in [@start, @start+@len) has @flags set.
 190  * Return false if any page is unmapped.  Thus testing flags == 0 is
 191  * equivalent to testing for flags == PAGE_VALID.
 192  */
 193 bool page_check_range(target_ulong start, target_ulong last, int flags);
 194
 195 /**
 196  * page_check_range_empty:
 197  * @start: first byte of range
 198  * @last: last byte of range
 199  * Context: holding mmap lock
 200  *
 201  * Return true if the entire range [@start, @last] is unmapped.
 202  * The memory lock must be held so that the caller will can ensure
 203  * the result stays true until a new mapping can be installed.
 204  */
 205 bool page_check_range_empty(target_ulong start, target_ulong last);
 206
 207 /**
 208  * page_find_range_empty
 209  * @min: first byte of search range
 210  * @max: last byte of search range
 211  * @len: size of the hole required
 212  * @align: alignment of the hole required (power of 2)
 213  *
 214  * If there is a range [x, x+@len) within [@min, @max] such that
 215  * x % @align == 0, then return x.  Otherwise return -1.
 216  * The memory lock must be held, as the caller will want to ensure
 217  * the returned range stays empty until a new mapping can be installed.
 218  */
 219 target_ulong page_find_range_empty(target_ulong min, target_ulong max,
 220                                    target_ulong len, target_ulong align);
 221
 222 /**
 223  * page_get_target_data(address)
 224  * @address: guest virtual address
 225  *
 226  * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate
 227  * with the guest page at @address, allocating it if necessary.  The
 228  * caller should already have verified that the address is valid.
 229  *
 230  * The memory will be freed when the guest page is deallocated,
 231  * e.g. with the munmap system call.
 232  */
 233 void *page_get_target_data(target_ulong address)
 234     __attribute__((returns_nonnull));
 235 #endif
 236
 237 CPUArchState *cpu_copy(CPUArchState *env);
 238
 239 /* Flags for use in ENV->INTERRUPT_PENDING.
 240
 241    The numbers assigned here are non-sequential in order to preserve
 242    binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
 243    previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
 244    the vmstate dump.  */
 245
 246 /* External hardware interrupt pending.  This is typically used for
 247    interrupts from devices.  */
 248 #define CPU_INTERRUPT_HARD        0x0002
 249
 250 /* Exit the current TB.  This is typically used when some system-level device
 251    makes some change to the memory mapping.  E.g. the a20 line change.  */
 252 #define CPU_INTERRUPT_EXITTB      0x0004
 253
 254 /* Halt the CPU.  */
 255 #define CPU_INTERRUPT_HALT        0x0020
 256
 257 /* Debug event pending.  */
 258 #define CPU_INTERRUPT_DEBUG       0x0080
 259
 260 /* Reset signal.  */
 261 #define CPU_INTERRUPT_RESET       0x0400
 262
 263 /* Several target-specific external hardware interrupts.  Each target/cpu.h
 264    should define proper names based on these defines.  */
 265 #define CPU_INTERRUPT_TGT_EXT_0   0x0008
 266 #define CPU_INTERRUPT_TGT_EXT_1   0x0010
 267 #define CPU_INTERRUPT_TGT_EXT_2   0x0040
 268 #define CPU_INTERRUPT_TGT_EXT_3   0x0200
 269 #define CPU_INTERRUPT_TGT_EXT_4   0x1000
 270
 271 /* Several target-specific internal interrupts.  These differ from the
 272    preceding target-specific interrupts in that they are intended to
 273    originate from within the cpu itself, typically in response to some
 274    instruction being executed.  These, therefore, are not masked while
 275    single-stepping within the debugger.  */
 276 #define CPU_INTERRUPT_TGT_INT_0   0x0100
 277 #define CPU_INTERRUPT_TGT_INT_1   0x0800
 278 #define CPU_INTERRUPT_TGT_INT_2   0x2000
 279
 280 /* First unused bit: 0x4000.  */
 281
 282 /* The set of all bits that should be masked when single-stepping.  */
 283 #define CPU_INTERRUPT_SSTEP_MASK \
 284     (CPU_INTERRUPT_HARD          \
 285      | CPU_INTERRUPT_TGT_EXT_0   \
 286      | CPU_INTERRUPT_TGT_EXT_1   \
 287      | CPU_INTERRUPT_TGT_EXT_2   \
 288      | CPU_INTERRUPT_TGT_EXT_3   \
 289      | CPU_INTERRUPT_TGT_EXT_4)
 290
 291 #ifdef CONFIG_USER_ONLY
 292
 293 /*
 294  * Allow some level of source compatibility with softmmu.  We do not
 295  * support any of the more exotic features, so only invalid pages may
 296  * be signaled by probe_access_flags().
 297  */
 298 #define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS_MIN - 1))
 299 #define TLB_MMIO            (1 << (TARGET_PAGE_BITS_MIN - 2))
 300 #define TLB_WATCHPOINT      0
 301
 302 static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
 303 {
 304     return MMU_USER_IDX;
 305 }
 306 #else
 307
 308 /*
 309  * Flags stored in the low bits of the TLB virtual address.
 310  * These are defined so that fast path ram access is all zeros.
 311  * The flags all must be between TARGET_PAGE_BITS and
 312  * maximum address alignment bit.
 313  *
 314  * Use TARGET_PAGE_BITS_MIN so that these bits are constant
 315  * when TARGET_PAGE_BITS_VARY is in effect.
 316  *
 317  * The count, if not the placement of these bits is known
 318  * to tcg/tcg-op-ldst.c, check_max_alignment().
 319  */
 320 /* Zero if TLB entry is valid.  */
 321 #define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS_MIN - 1))
 322 /* Set if TLB entry references a clean RAM page.  The iotlb entry will
 323    contain the page physical address.  */
 324 #define TLB_NOTDIRTY        (1 << (TARGET_PAGE_BITS_MIN - 2))
 325 /* Set if TLB entry is an IO callback.  */
 326 #define TLB_MMIO            (1 << (TARGET_PAGE_BITS_MIN - 3))
 327 /* Set if TLB entry writes ignored.  */
 328 #define TLB_DISCARD_WRITE   (1 << (TARGET_PAGE_BITS_MIN - 4))
 329 /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
 330 #define TLB_FORCE_SLOW      (1 << (TARGET_PAGE_BITS_MIN - 5))
 331
 332 /*
 333  * Use this mask to check interception with an alignment mask
 334  * in a TCG backend.
 335  */
 336 #define TLB_FLAGS_MASK \
 337     (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
 338     | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
 339
 340 /*
 341  * Flags stored in CPUTLBEntryFull.slow_flags[x].
 342  * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
 343  */
 344 /* Set if TLB entry requires byte swap.  */
 345 #define TLB_BSWAP            (1 << 0)
 346 /* Set if TLB entry contains a watchpoint.  */
 347 #define TLB_WATCHPOINT       (1 << 1)
 348 /* Set if TLB entry requires aligned accesses.  */
 349 #define TLB_CHECK_ALIGNED    (1 << 2)
 350
 351 #define TLB_SLOW_FLAGS_MASK  (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
 352
 353 /* The two sets of flags must not overlap. */
 354 QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
 355
 356 /**
 357  * tlb_hit_page: return true if page aligned @addr is a hit against the
 358  * TLB entry @tlb_addr
 359  *
 360  * @addr: virtual address to test (must be page aligned)
 361  * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
 362  */
 363 static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
 364 {
 365     return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
 366 }
 367
 368 /**
 369  * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
 370  *
 371  * @addr: virtual address to test (need not be page aligned)
 372  * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
 373  */
 374 static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
 375 {
 376     return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
 377 }
 378
 379 #endif /* !CONFIG_USER_ONLY */
 380
 381 /* Validate correct placement of CPUArchState. */
 382 #include "cpu.h"
 383 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
 384 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
 385
 386 #endif /* CPU_ALL_H */