tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "cpu.h"
  29 #include "exec/memop.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/queue.h"
  33 #include "tcg-mo.h"
  34 #include "tcg-target.h"
  35 #include "qemu/int128.h"
  36
  37 /* XXX: make safe guess about sizes */
  38 #define MAX_OP_PER_INSTR 266
  39
  40 #if HOST_LONG_BITS == 32
  41 #define MAX_OPC_PARAM_PER_ARG 2
  42 #else
  43 #define MAX_OPC_PARAM_PER_ARG 1
  44 #endif
  45 #define MAX_OPC_PARAM_IARGS 6
  46 #define MAX_OPC_PARAM_OARGS 1
  47 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  48
  49 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  50  * and up to 4 + N parameters on 64-bit archs
  51  * (N = number of input arguments + output arguments).  */
  52 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  53
  54 #define CPU_TEMP_BUF_NLONGS 128
  55
  56 /* Default target word size to pointer size.  */
  57 #ifndef TCG_TARGET_REG_BITS
  58 # if UINTPTR_MAX == UINT32_MAX
  59 #  define TCG_TARGET_REG_BITS 32
  60 # elif UINTPTR_MAX == UINT64_MAX
  61 #  define TCG_TARGET_REG_BITS 64
  62 # else
  63 #  error Unknown pointer size for tcg target
  64 # endif
  65 #endif
  66
  67 #if TCG_TARGET_REG_BITS == 32
  68 typedef int32_t tcg_target_long;
  69 typedef uint32_t tcg_target_ulong;
  70 #define TCG_PRIlx PRIx32
  71 #define TCG_PRIld PRId32
  72 #elif TCG_TARGET_REG_BITS == 64
  73 typedef int64_t tcg_target_long;
  74 typedef uint64_t tcg_target_ulong;
  75 #define TCG_PRIlx PRIx64
  76 #define TCG_PRIld PRId64
  77 #else
  78 #error unsupported
  79 #endif
  80
  81 /* Oversized TCG guests make things like MTTCG hard
  82  * as we can't use atomics for cputlb updates.
  83  */
  84 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  85 #define TCG_OVERSIZED_GUEST 1
  86 #else
  87 #define TCG_OVERSIZED_GUEST 0
  88 #endif
  89
  90 #if TCG_TARGET_NB_REGS <= 32
  91 typedef uint32_t TCGRegSet;
  92 #elif TCG_TARGET_NB_REGS <= 64
  93 typedef uint64_t TCGRegSet;
  94 #else
  95 #error unsupported
  96 #endif
  97
  98 #if TCG_TARGET_REG_BITS == 32
  99 /* Turn some undef macros into false macros.  */
 100 #define TCG_TARGET_HAS_extrl_i64_i32    0
 101 #define TCG_TARGET_HAS_extrh_i64_i32    0
 102 #define TCG_TARGET_HAS_div_i64          0
 103 #define TCG_TARGET_HAS_rem_i64          0
 104 #define TCG_TARGET_HAS_div2_i64         0
 105 #define TCG_TARGET_HAS_rot_i64          0
 106 #define TCG_TARGET_HAS_ext8s_i64        0
 107 #define TCG_TARGET_HAS_ext16s_i64       0
 108 #define TCG_TARGET_HAS_ext32s_i64       0
 109 #define TCG_TARGET_HAS_ext8u_i64        0
 110 #define TCG_TARGET_HAS_ext16u_i64       0
 111 #define TCG_TARGET_HAS_ext32u_i64       0
 112 #define TCG_TARGET_HAS_bswap16_i64      0
 113 #define TCG_TARGET_HAS_bswap32_i64      0
 114 #define TCG_TARGET_HAS_bswap64_i64      0
 115 #define TCG_TARGET_HAS_neg_i64          0
 116 #define TCG_TARGET_HAS_not_i64          0
 117 #define TCG_TARGET_HAS_andc_i64         0
 118 #define TCG_TARGET_HAS_orc_i64          0
 119 #define TCG_TARGET_HAS_eqv_i64          0
 120 #define TCG_TARGET_HAS_nand_i64         0
 121 #define TCG_TARGET_HAS_nor_i64          0
 122 #define TCG_TARGET_HAS_clz_i64          0
 123 #define TCG_TARGET_HAS_ctz_i64          0
 124 #define TCG_TARGET_HAS_ctpop_i64        0
 125 #define TCG_TARGET_HAS_deposit_i64      0
 126 #define TCG_TARGET_HAS_extract_i64      0
 127 #define TCG_TARGET_HAS_sextract_i64     0
 128 #define TCG_TARGET_HAS_extract2_i64     0
 129 #define TCG_TARGET_HAS_movcond_i64      0
 130 #define TCG_TARGET_HAS_add2_i64         0
 131 #define TCG_TARGET_HAS_sub2_i64         0
 132 #define TCG_TARGET_HAS_mulu2_i64        0
 133 #define TCG_TARGET_HAS_muls2_i64        0
 134 #define TCG_TARGET_HAS_muluh_i64        0
 135 #define TCG_TARGET_HAS_mulsh_i64        0
 136 /* Turn some undef macros into true macros.  */
 137 #define TCG_TARGET_HAS_add2_i32         1
 138 #define TCG_TARGET_HAS_sub2_i32         1
 139 #endif
 140
 141 #ifndef TCG_TARGET_deposit_i32_valid
 142 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 143 #endif
 144 #ifndef TCG_TARGET_deposit_i64_valid
 145 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 146 #endif
 147 #ifndef TCG_TARGET_extract_i32_valid
 148 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 149 #endif
 150 #ifndef TCG_TARGET_extract_i64_valid
 151 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 152 #endif
 153
 154 /* Only one of DIV or DIV2 should be defined.  */
 155 #if defined(TCG_TARGET_HAS_div_i32)
 156 #define TCG_TARGET_HAS_div2_i32         0
 157 #elif defined(TCG_TARGET_HAS_div2_i32)
 158 #define TCG_TARGET_HAS_div_i32          0
 159 #define TCG_TARGET_HAS_rem_i32          0
 160 #endif
 161 #if defined(TCG_TARGET_HAS_div_i64)
 162 #define TCG_TARGET_HAS_div2_i64         0
 163 #elif defined(TCG_TARGET_HAS_div2_i64)
 164 #define TCG_TARGET_HAS_div_i64          0
 165 #define TCG_TARGET_HAS_rem_i64          0
 166 #endif
 167
 168 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 169 #if TCG_TARGET_REG_BITS == 32 \
 170     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 171          || defined(TCG_TARGET_HAS_muluh_i32))
 172 # error "Missing unsigned widening multiply"
 173 #endif
 174
 175 #if !defined(TCG_TARGET_HAS_v64) \
 176     && !defined(TCG_TARGET_HAS_v128) \
 177     && !defined(TCG_TARGET_HAS_v256)
 178 #define TCG_TARGET_MAYBE_vec            0
 179 #define TCG_TARGET_HAS_abs_vec          0
 180 #define TCG_TARGET_HAS_neg_vec          0
 181 #define TCG_TARGET_HAS_not_vec          0
 182 #define TCG_TARGET_HAS_andc_vec         0
 183 #define TCG_TARGET_HAS_orc_vec          0
 184 #define TCG_TARGET_HAS_shi_vec          0
 185 #define TCG_TARGET_HAS_shs_vec          0
 186 #define TCG_TARGET_HAS_shv_vec          0
 187 #define TCG_TARGET_HAS_mul_vec          0
 188 #define TCG_TARGET_HAS_sat_vec          0
 189 #define TCG_TARGET_HAS_minmax_vec       0
 190 #define TCG_TARGET_HAS_bitsel_vec       0
 191 #define TCG_TARGET_HAS_cmpsel_vec       0
 192 #else
 193 #define TCG_TARGET_MAYBE_vec            1
 194 #endif
 195 #ifndef TCG_TARGET_HAS_v64
 196 #define TCG_TARGET_HAS_v64              0
 197 #endif
 198 #ifndef TCG_TARGET_HAS_v128
 199 #define TCG_TARGET_HAS_v128             0
 200 #endif
 201 #ifndef TCG_TARGET_HAS_v256
 202 #define TCG_TARGET_HAS_v256             0
 203 #endif
 204
 205 #ifndef TARGET_INSN_START_EXTRA_WORDS
 206 # define TARGET_INSN_START_WORDS 1
 207 #else
 208 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 209 #endif
 210
 211 typedef enum TCGOpcode {
 212 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 213 #include "tcg-opc.h"
 214 #undef DEF
 215     NB_OPS,
 216 } TCGOpcode;
 217
 218 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 219 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 220 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 221
 222 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 223 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 224 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 225 typedef uint8_t tcg_insn_unit;
 226 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 227 typedef uint16_t tcg_insn_unit;
 228 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 229 typedef uint32_t tcg_insn_unit;
 230 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 231 typedef uint64_t tcg_insn_unit;
 232 #else
 233 /* The port better have done this.  */
 234 #endif
 235
 236
 237 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 238 # define tcg_debug_assert(X) do { assert(X); } while (0)
 239 #else
 240 # define tcg_debug_assert(X) \
 241     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 242 #endif
 243
 244 typedef struct TCGRelocation TCGRelocation;
 245 struct TCGRelocation {
 246     QSIMPLEQ_ENTRY(TCGRelocation) next;
 247     tcg_insn_unit *ptr;
 248     intptr_t addend;
 249     int type;
 250 };
 251
 252 typedef struct TCGLabel TCGLabel;
 253 struct TCGLabel {
 254     unsigned present : 1;
 255     unsigned has_value : 1;
 256     unsigned id : 14;
 257     unsigned refs : 16;
 258     union {
 259         uintptr_t value;
 260         tcg_insn_unit *value_ptr;
 261     } u;
 262     QSIMPLEQ_HEAD(, TCGRelocation) relocs;
 263     QSIMPLEQ_ENTRY(TCGLabel) next;
 264 };
 265
 266 typedef struct TCGPool {
 267     struct TCGPool *next;
 268     int size;
 269     uint8_t data[0] __attribute__ ((aligned));
 270 } TCGPool;
 271
 272 #define TCG_POOL_CHUNK_SIZE 32768
 273
 274 #define TCG_MAX_TEMPS 512
 275 #define TCG_MAX_INSNS 512
 276
 277 /* when the size of the arguments of a called function is smaller than
 278    this value, they are statically allocated in the TB stack frame */
 279 #define TCG_STATIC_CALL_ARGS_SIZE 128
 280
 281 typedef enum TCGType {
 282     TCG_TYPE_I32,
 283     TCG_TYPE_I64,
 284
 285     TCG_TYPE_V64,
 286     TCG_TYPE_V128,
 287     TCG_TYPE_V256,
 288
 289     TCG_TYPE_COUNT, /* number of different types */
 290
 291     /* An alias for the size of the host register.  */
 292 #if TCG_TARGET_REG_BITS == 32
 293     TCG_TYPE_REG = TCG_TYPE_I32,
 294 #else
 295     TCG_TYPE_REG = TCG_TYPE_I64,
 296 #endif
 297
 298     /* An alias for the size of the native pointer.  */
 299 #if UINTPTR_MAX == UINT32_MAX
 300     TCG_TYPE_PTR = TCG_TYPE_I32,
 301 #else
 302     TCG_TYPE_PTR = TCG_TYPE_I64,
 303 #endif
 304
 305     /* An alias for the size of the target "long", aka register.  */
 306 #if TARGET_LONG_BITS == 64
 307     TCG_TYPE_TL = TCG_TYPE_I64,
 308 #else
 309     TCG_TYPE_TL = TCG_TYPE_I32,
 310 #endif
 311 } TCGType;
 312
 313 /**
 314  * get_alignment_bits
 315  * @memop: MemOp value
 316  *
 317  * Extract the alignment size from the memop.
 318  */
 319 static inline unsigned get_alignment_bits(MemOp memop)
 320 {
 321     unsigned a = memop & MO_AMASK;
 322
 323     if (a == MO_UNALN) {
 324         /* No alignment required.  */
 325         a = 0;
 326     } else if (a == MO_ALIGN) {
 327         /* A natural alignment requirement.  */
 328         a = memop & MO_SIZE;
 329     } else {
 330         /* A specific alignment requirement.  */
 331         a = a >> MO_ASHIFT;
 332     }
 333 #if defined(CONFIG_SOFTMMU)
 334     /* The requested alignment cannot overlap the TLB flags.  */
 335     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 336 #endif
 337     return a;
 338 }
 339
 340 typedef tcg_target_ulong TCGArg;
 341
 342 /* Define type and accessor macros for TCG variables.
 343
 344    TCG variables are the inputs and outputs of TCG ops, as described
 345    in tcg/README. Target CPU front-end code uses these types to deal
 346    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 347    They come in several flavours:
 348     * TCGv_i32 : 32 bit integer type
 349     * TCGv_i64 : 64 bit integer type
 350     * TCGv_ptr : a host pointer type
 351     * TCGv_vec : a host vector type; the exact size is not exposed
 352                  to the CPU front-end code.
 353     * TCGv : an integer type the same size as target_ulong
 354              (an alias for either TCGv_i32 or TCGv_i64)
 355    The compiler's type checking will complain if you mix them
 356    up and pass the wrong sized TCGv to a function.
 357
 358    Users of tcg_gen_* don't need to know about any of the internal
 359    details of these, and should treat them as opaque types.
 360    You won't be able to look inside them in a debugger either.
 361
 362    Internal implementation details follow:
 363
 364    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 365    This is deliberate, because the values we store in variables of type
 366    TCGv_i32 are not really pointers-to-structures. They're just small
 367    integers, but keeping them in pointer types like this means that the
 368    compiler will complain if you accidentally pass a TCGv_i32 to a
 369    function which takes a TCGv_i64, and so on. Only the internals of
 370    TCG need to care about the actual contents of the types.  */
 371
 372 typedef struct TCGv_i32_d *TCGv_i32;
 373 typedef struct TCGv_i64_d *TCGv_i64;
 374 typedef struct TCGv_ptr_d *TCGv_ptr;
 375 typedef struct TCGv_vec_d *TCGv_vec;
 376 typedef TCGv_ptr TCGv_env;
 377 #if TARGET_LONG_BITS == 32
 378 #define TCGv TCGv_i32
 379 #elif TARGET_LONG_BITS == 64
 380 #define TCGv TCGv_i64
 381 #else
 382 #error Unhandled TARGET_LONG_BITS value
 383 #endif
 384
 385 /* call flags */
 386 /* Helper does not read globals (either directly or through an exception). It
 387    implies TCG_CALL_NO_WRITE_GLOBALS. */
 388 #define TCG_CALL_NO_READ_GLOBALS    0x0001
 389 /* Helper does not write globals */
 390 #define TCG_CALL_NO_WRITE_GLOBALS   0x0002
 391 /* Helper can be safely suppressed if the return value is not used. */
 392 #define TCG_CALL_NO_SIDE_EFFECTS    0x0004
 393 /* Helper is QEMU_NORETURN.  */
 394 #define TCG_CALL_NO_RETURN          0x0008
 395
 396 /* convenience version of most used call flags */
 397 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 398 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 399 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 400 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 401 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 402
 403 /* Used to align parameters.  See the comment before tcgv_i32_temp.  */
 404 #define TCG_CALL_DUMMY_ARG      ((TCGArg)0)
 405
 406 /* Conditions.  Note that these are laid out for easy manipulation by
 407    the functions below:
 408      bit 0 is used for inverting;
 409      bit 1 is signed,
 410      bit 2 is unsigned,
 411      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 412 typedef enum {
 413     /* non-signed */
 414     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 415     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 416     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 417     TCG_COND_NE     = 8 | 0 | 0 | 1,
 418     /* signed */
 419     TCG_COND_LT     = 0 | 0 | 2 | 0,
 420     TCG_COND_GE     = 0 | 0 | 2 | 1,
 421     TCG_COND_LE     = 8 | 0 | 2 | 0,
 422     TCG_COND_GT     = 8 | 0 | 2 | 1,
 423     /* unsigned */
 424     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 425     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 426     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 427     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 428 } TCGCond;
 429
 430 /* Invert the sense of the comparison.  */
 431 static inline TCGCond tcg_invert_cond(TCGCond c)
 432 {
 433     return (TCGCond)(c ^ 1);
 434 }
 435
 436 /* Swap the operands in a comparison.  */
 437 static inline TCGCond tcg_swap_cond(TCGCond c)
 438 {
 439     return c & 6 ? (TCGCond)(c ^ 9) : c;
 440 }
 441
 442 /* Create an "unsigned" version of a "signed" comparison.  */
 443 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 444 {
 445     return c & 2 ? (TCGCond)(c ^ 6) : c;
 446 }
 447
 448 /* Create a "signed" version of an "unsigned" comparison.  */
 449 static inline TCGCond tcg_signed_cond(TCGCond c)
 450 {
 451     return c & 4 ? (TCGCond)(c ^ 6) : c;
 452 }
 453
 454 /* Must a comparison be considered unsigned?  */
 455 static inline bool is_unsigned_cond(TCGCond c)
 456 {
 457     return (c & 4) != 0;
 458 }
 459
 460 /* Create a "high" version of a double-word comparison.
 461    This removes equality from a LTE or GTE comparison.  */
 462 static inline TCGCond tcg_high_cond(TCGCond c)
 463 {
 464     switch (c) {
 465     case TCG_COND_GE:
 466     case TCG_COND_LE:
 467     case TCG_COND_GEU:
 468     case TCG_COND_LEU:
 469         return (TCGCond)(c ^ 8);
 470     default:
 471         return c;
 472     }
 473 }
 474
 475 typedef enum TCGTempVal {
 476     TEMP_VAL_DEAD,
 477     TEMP_VAL_REG,
 478     TEMP_VAL_MEM,
 479     TEMP_VAL_CONST,
 480 } TCGTempVal;
 481
 482 typedef struct TCGTemp {
 483     TCGReg reg:8;
 484     TCGTempVal val_type:8;
 485     TCGType base_type:8;
 486     TCGType type:8;
 487     unsigned int fixed_reg:1;
 488     unsigned int indirect_reg:1;
 489     unsigned int indirect_base:1;
 490     unsigned int mem_coherent:1;
 491     unsigned int mem_allocated:1;
 492     /* If true, the temp is saved across both basic blocks and
 493        translation blocks.  */
 494     unsigned int temp_global:1;
 495     /* If true, the temp is saved across basic blocks but dead
 496        at the end of translation blocks.  If false, the temp is
 497        dead at the end of basic blocks.  */
 498     unsigned int temp_local:1;
 499     unsigned int temp_allocated:1;
 500
 501     tcg_target_long val;
 502     struct TCGTemp *mem_base;
 503     intptr_t mem_offset;
 504     const char *name;
 505
 506     /* Pass-specific information that can be stored for a temporary.
 507        One word worth of integer data, and one pointer to data
 508        allocated separately.  */
 509     uintptr_t state;
 510     void *state_ptr;
 511 } TCGTemp;
 512
 513 typedef struct TCGContext TCGContext;
 514
 515 typedef struct TCGTempSet {
 516     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 517 } TCGTempSet;
 518
 519 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 520    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 521    There are never more than 2 outputs, which means that we can store all
 522    dead + sync data within 16 bits.  */
 523 #define DEAD_ARG  4
 524 #define SYNC_ARG  1
 525 typedef uint16_t TCGLifeData;
 526
 527 /* The layout here is designed to avoid a bitfield crossing of
 528    a 32-bit boundary, which would cause GCC to add extra padding.  */
 529 typedef struct TCGOp {
 530     TCGOpcode opc   : 8;        /*  8 */
 531
 532     /* Parameters for this opcode.  See below.  */
 533     unsigned param1 : 4;        /* 12 */
 534     unsigned param2 : 4;        /* 16 */
 535
 536     /* Lifetime data of the operands.  */
 537     unsigned life   : 16;       /* 32 */
 538
 539     /* Next and previous opcodes.  */
 540     QTAILQ_ENTRY(TCGOp) link;
 541 #ifdef CONFIG_PLUGIN
 542     QSIMPLEQ_ENTRY(TCGOp) plugin_link;
 543 #endif
 544
 545     /* Arguments for the opcode.  */
 546     TCGArg args[MAX_OPC_PARAM];
 547
 548     /* Register preferences for the output(s).  */
 549     TCGRegSet output_pref[2];
 550 } TCGOp;
 551
 552 #define TCGOP_CALLI(X)    (X)->param1
 553 #define TCGOP_CALLO(X)    (X)->param2
 554
 555 #define TCGOP_VECL(X)     (X)->param1
 556 #define TCGOP_VECE(X)     (X)->param2
 557
 558 /* Make sure operands fit in the bitfields above.  */
 559 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 560
 561 typedef struct TCGProfile {
 562     int64_t cpu_exec_time;
 563     int64_t tb_count1;
 564     int64_t tb_count;
 565     int64_t op_count; /* total insn count */
 566     int op_count_max; /* max insn per TB */
 567     int temp_count_max;
 568     int64_t temp_count;
 569     int64_t del_op_count;
 570     int64_t code_in_len;
 571     int64_t code_out_len;
 572     int64_t search_out_len;
 573     int64_t interm_time;
 574     int64_t code_time;
 575     int64_t la_time;
 576     int64_t opt_time;
 577     int64_t restore_count;
 578     int64_t restore_time;
 579     int64_t table_op_count[NB_OPS];
 580 } TCGProfile;
 581
 582 struct TCGContext {
 583     uint8_t *pool_cur, *pool_end;
 584     TCGPool *pool_first, *pool_current, *pool_first_large;
 585     int nb_labels;
 586     int nb_globals;
 587     int nb_temps;
 588     int nb_indirects;
 589     int nb_ops;
 590
 591     /* goto_tb support */
 592     tcg_insn_unit *code_buf;
 593     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 594     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 595     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 596
 597     TCGRegSet reserved_regs;
 598     uint32_t tb_cflags; /* cflags of the current TB */
 599     intptr_t current_frame_offset;
 600     intptr_t frame_start;
 601     intptr_t frame_end;
 602     TCGTemp *frame_temp;
 603
 604     tcg_insn_unit *code_ptr;
 605
 606 #ifdef CONFIG_PROFILER
 607     TCGProfile prof;
 608 #endif
 609
 610 #ifdef CONFIG_DEBUG_TCG
 611     int temps_in_use;
 612     int goto_tb_issue_mask;
 613     const TCGOpcode *vecop_list;
 614 #endif
 615
 616     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 617        here, because there's too much arithmetic throughout that relies
 618        on addition and subtraction working on bytes.  Rely on the GCC
 619        extension that allows arithmetic on void*.  */
 620     void *code_gen_prologue;
 621     void *code_gen_epilogue;
 622     void *code_gen_buffer;
 623     size_t code_gen_buffer_size;
 624     void *code_gen_ptr;
 625     void *data_gen_ptr;
 626
 627     /* Threshold to flush the translated code buffer.  */
 628     void *code_gen_highwater;
 629
 630     size_t tb_phys_invalidate_count;
 631
 632     /* Track which vCPU triggers events */
 633     CPUState *cpu;                      /* *_trans */
 634
 635     /* These structures are private to tcg-target.inc.c.  */
 636 #ifdef TCG_TARGET_NEED_LDST_LABELS
 637     QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
 638 #endif
 639 #ifdef TCG_TARGET_NEED_POOL_LABELS
 640     struct TCGLabelPoolData *pool_labels;
 641 #endif
 642
 643     TCGLabel *exitreq_label;
 644
 645 #ifdef CONFIG_PLUGIN
 646     /*
 647      * We keep one plugin_tb struct per TCGContext. Note that on every TB
 648      * translation we clear but do not free its contents; this way we
 649      * avoid a lot of malloc/free churn, since after a few TB's it's
 650      * unlikely that we'll need to allocate either more instructions or more
 651      * space for instructions (for variable-instruction-length ISAs).
 652      */
 653     struct qemu_plugin_tb *plugin_tb;
 654
 655     /* descriptor of the instruction being translated */
 656     struct qemu_plugin_insn *plugin_insn;
 657
 658     /* list to quickly access the injected ops */
 659     QSIMPLEQ_HEAD(, TCGOp) plugin_ops;
 660 #endif
 661
 662     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 663     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 664
 665     QTAILQ_HEAD(, TCGOp) ops, free_ops;
 666     QSIMPLEQ_HEAD(, TCGLabel) labels;
 667
 668     /* Tells which temporary holds a given register.
 669        It does not take into account fixed registers */
 670     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 671
 672     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 673     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 674 };
 675
 676 extern TCGContext tcg_init_ctx;
 677 extern __thread TCGContext *tcg_ctx;
 678 extern TCGv_env cpu_env;
 679
 680 static inline size_t temp_idx(TCGTemp *ts)
 681 {
 682     ptrdiff_t n = ts - tcg_ctx->temps;
 683     tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
 684     return n;
 685 }
 686
 687 static inline TCGArg temp_arg(TCGTemp *ts)
 688 {
 689     return (uintptr_t)ts;
 690 }
 691
 692 static inline TCGTemp *arg_temp(TCGArg a)
 693 {
 694     return (TCGTemp *)(uintptr_t)a;
 695 }
 696
 697 /* Using the offset of a temporary, relative to TCGContext, rather than
 698    its index means that we don't use 0.  That leaves offset 0 free for
 699    a NULL representation without having to leave index 0 unused.  */
 700 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
 701 {
 702     uintptr_t o = (uintptr_t)v;
 703     TCGTemp *t = (void *)tcg_ctx + o;
 704     tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
 705     return t;
 706 }
 707
 708 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
 709 {
 710     return tcgv_i32_temp((TCGv_i32)v);
 711 }
 712
 713 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
 714 {
 715     return tcgv_i32_temp((TCGv_i32)v);
 716 }
 717
 718 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
 719 {
 720     return tcgv_i32_temp((TCGv_i32)v);
 721 }
 722
 723 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
 724 {
 725     return temp_arg(tcgv_i32_temp(v));
 726 }
 727
 728 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
 729 {
 730     return temp_arg(tcgv_i64_temp(v));
 731 }
 732
 733 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
 734 {
 735     return temp_arg(tcgv_ptr_temp(v));
 736 }
 737
 738 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
 739 {
 740     return temp_arg(tcgv_vec_temp(v));
 741 }
 742
 743 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
 744 {
 745     (void)temp_idx(t); /* trigger embedded assert */
 746     return (TCGv_i32)((void *)t - (void *)tcg_ctx);
 747 }
 748
 749 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
 750 {
 751     return (TCGv_i64)temp_tcgv_i32(t);
 752 }
 753
 754 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
 755 {
 756     return (TCGv_ptr)temp_tcgv_i32(t);
 757 }
 758
 759 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
 760 {
 761     return (TCGv_vec)temp_tcgv_i32(t);
 762 }
 763
 764 #if TCG_TARGET_REG_BITS == 32
 765 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
 766 {
 767     return temp_tcgv_i32(tcgv_i64_temp(t));
 768 }
 769
 770 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
 771 {
 772     return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
 773 }
 774 #endif
 775
 776 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
 777 {
 778     op->args[arg] = v;
 779 }
 780
 781 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
 782 {
 783 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
 784     tcg_set_insn_param(op, arg, v);
 785 #else
 786     tcg_set_insn_param(op, arg * 2, v);
 787     tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
 788 #endif
 789 }
 790
 791 /* The last op that was emitted.  */
 792 static inline TCGOp *tcg_last_op(void)
 793 {
 794     return QTAILQ_LAST(&tcg_ctx->ops);
 795 }
 796
 797 /* Test for whether to terminate the TB for using too many opcodes.  */
 798 static inline bool tcg_op_buf_full(void)
 799 {
 800     /* This is not a hard limit, it merely stops translation when
 801      * we have produced "enough" opcodes.  We want to limit TB size
 802      * such that a RISC host can reasonably use a 16-bit signed
 803      * branch within the TB.  We also need to be mindful of the
 804      * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
 805      * and TCGContext.gen_insn_end_off[].
 806      */
 807     return tcg_ctx->nb_ops >= 4000;
 808 }
 809
 810 /* pool based memory allocation */
 811
 812 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
 813 void *tcg_malloc_internal(TCGContext *s, int size);
 814 void tcg_pool_reset(TCGContext *s);
 815 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 816
 817 void tcg_region_init(void);
 818 void tcg_region_reset_all(void);
 819
 820 size_t tcg_code_size(void);
 821 size_t tcg_code_capacity(void);
 822
 823 void tcg_tb_insert(TranslationBlock *tb);
 824 void tcg_tb_remove(TranslationBlock *tb);
 825 size_t tcg_tb_phys_invalidate_count(void);
 826 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
 827 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
 828 size_t tcg_nb_tbs(void);
 829
 830 /* user-mode: Called with mmap_lock held.  */
 831 static inline void *tcg_malloc(int size)
 832 {
 833     TCGContext *s = tcg_ctx;
 834     uint8_t *ptr, *ptr_end;
 835
 836     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 837     size = QEMU_ALIGN_UP(size, 8);
 838
 839     ptr = s->pool_cur;
 840     ptr_end = ptr + size;
 841     if (unlikely(ptr_end > s->pool_end)) {
 842         return tcg_malloc_internal(tcg_ctx, size);
 843     } else {
 844         s->pool_cur = ptr_end;
 845         return ptr;
 846     }
 847 }
 848
 849 void tcg_context_init(TCGContext *s);
 850 void tcg_register_thread(void);
 851 void tcg_prologue_init(TCGContext *s);
 852 void tcg_func_start(TCGContext *s);
 853
 854 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 855
 856 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 857
 858 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
 859                                      intptr_t, const char *);
 860 TCGTemp *tcg_temp_new_internal(TCGType, bool);
 861 void tcg_temp_free_internal(TCGTemp *);
 862 TCGv_vec tcg_temp_new_vec(TCGType type);
 863 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 864
 865 static inline void tcg_temp_free_i32(TCGv_i32 arg)
 866 {
 867     tcg_temp_free_internal(tcgv_i32_temp(arg));
 868 }
 869
 870 static inline void tcg_temp_free_i64(TCGv_i64 arg)
 871 {
 872     tcg_temp_free_internal(tcgv_i64_temp(arg));
 873 }
 874
 875 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
 876 {
 877     tcg_temp_free_internal(tcgv_ptr_temp(arg));
 878 }
 879
 880 static inline void tcg_temp_free_vec(TCGv_vec arg)
 881 {
 882     tcg_temp_free_internal(tcgv_vec_temp(arg));
 883 }
 884
 885 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 886                                               const char *name)
 887 {
 888     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 889     return temp_tcgv_i32(t);
 890 }
 891
 892 static inline TCGv_i32 tcg_temp_new_i32(void)
 893 {
 894     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
 895     return temp_tcgv_i32(t);
 896 }
 897
 898 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 899 {
 900     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
 901     return temp_tcgv_i32(t);
 902 }
 903
 904 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 905                                               const char *name)
 906 {
 907     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 908     return temp_tcgv_i64(t);
 909 }
 910
 911 static inline TCGv_i64 tcg_temp_new_i64(void)
 912 {
 913     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
 914     return temp_tcgv_i64(t);
 915 }
 916
 917 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 918 {
 919     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
 920     return temp_tcgv_i64(t);
 921 }
 922
 923 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
 924                                               const char *name)
 925 {
 926     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
 927     return temp_tcgv_ptr(t);
 928 }
 929
 930 static inline TCGv_ptr tcg_temp_new_ptr(void)
 931 {
 932     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
 933     return temp_tcgv_ptr(t);
 934 }
 935
 936 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
 937 {
 938     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
 939     return temp_tcgv_ptr(t);
 940 }
 941
 942 #if defined(CONFIG_DEBUG_TCG)
 943 /* If you call tcg_clear_temp_count() at the start of a section of
 944  * code which is not supposed to leak any TCG temporaries, then
 945  * calling tcg_check_temp_count() at the end of the section will
 946  * return 1 if the section did in fact leak a temporary.
 947  */
 948 void tcg_clear_temp_count(void);
 949 int tcg_check_temp_count(void);
 950 #else
 951 #define tcg_clear_temp_count() do { } while (0)
 952 #define tcg_check_temp_count() 0
 953 #endif
 954
 955 int64_t tcg_cpu_exec_time(void);
 956 void tcg_dump_info(void);
 957 void tcg_dump_op_count(void);
 958
 959 #define TCG_CT_ALIAS  0x80
 960 #define TCG_CT_IALIAS 0x40
 961 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
 962 #define TCG_CT_REG    0x01
 963 #define TCG_CT_CONST  0x02 /* any constant of register size */
 964
 965 typedef struct TCGArgConstraint {
 966     uint16_t ct;
 967     uint8_t alias_index;
 968     union {
 969         TCGRegSet regs;
 970     } u;
 971 } TCGArgConstraint;
 972
 973 #define TCG_MAX_OP_ARGS 16
 974
 975 /* Bits for TCGOpDef->flags, 8 bits available.  */
 976 enum {
 977     /* Instruction exits the translation block.  */
 978     TCG_OPF_BB_EXIT      = 0x01,
 979     /* Instruction defines the end of a basic block.  */
 980     TCG_OPF_BB_END       = 0x02,
 981     /* Instruction clobbers call registers and potentially update globals.  */
 982     TCG_OPF_CALL_CLOBBER = 0x04,
 983     /* Instruction has side effects: it cannot be removed if its outputs
 984        are not used, and might trigger exceptions.  */
 985     TCG_OPF_SIDE_EFFECTS = 0x08,
 986     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 987     TCG_OPF_64BIT        = 0x10,
 988     /* Instruction is optional and not implemented by the host, or insn
 989        is generic and should not be implemened by the host.  */
 990     TCG_OPF_NOT_PRESENT  = 0x20,
 991     /* Instruction operands are vectors.  */
 992     TCG_OPF_VECTOR       = 0x40,
 993 };
 994
 995 typedef struct TCGOpDef {
 996     const char *name;
 997     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 998     uint8_t flags;
 999     TCGArgConstraint *args_ct;
1000     int *sorted_args;
1001 #if defined(CONFIG_DEBUG_TCG)
1002     int used;
1003 #endif
1004 } TCGOpDef;
1005
1006 extern TCGOpDef tcg_op_defs[];
1007 extern const size_t tcg_op_defs_max;
1008
1009 typedef struct TCGTargetOpDef {
1010     TCGOpcode op;
1011     const char *args_ct_str[TCG_MAX_OP_ARGS];
1012 } TCGTargetOpDef;
1013
1014 #define tcg_abort() \
1015 do {\
1016     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1017     abort();\
1018 } while (0)
1019
1020 bool tcg_op_supported(TCGOpcode op);
1021
1022 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1023
1024 TCGOp *tcg_emit_op(TCGOpcode opc);
1025 void tcg_op_remove(TCGContext *s, TCGOp *op);
1026 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
1027 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
1028
1029 void tcg_optimize(TCGContext *s);
1030
1031 TCGv_i32 tcg_const_i32(int32_t val);
1032 TCGv_i64 tcg_const_i64(int64_t val);
1033 TCGv_i32 tcg_const_local_i32(int32_t val);
1034 TCGv_i64 tcg_const_local_i64(int64_t val);
1035 TCGv_vec tcg_const_zeros_vec(TCGType);
1036 TCGv_vec tcg_const_ones_vec(TCGType);
1037 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1038 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1039
1040 #if UINTPTR_MAX == UINT32_MAX
1041 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1042 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1043 #else
1044 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1045 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1046 #endif
1047
1048 TCGLabel *gen_new_label(void);
1049
1050 /**
1051  * label_arg
1052  * @l: label
1053  *
1054  * Encode a label for storage in the TCG opcode stream.
1055  */
1056
1057 static inline TCGArg label_arg(TCGLabel *l)
1058 {
1059     return (uintptr_t)l;
1060 }
1061
1062 /**
1063  * arg_label
1064  * @i: value
1065  *
1066  * The opposite of label_arg.  Retrieve a label from the
1067  * encoding of the TCG opcode stream.
1068  */
1069
1070 static inline TCGLabel *arg_label(TCGArg i)
1071 {
1072     return (TCGLabel *)(uintptr_t)i;
1073 }
1074
1075 /**
1076  * tcg_ptr_byte_diff
1077  * @a, @b: addresses to be differenced
1078  *
1079  * There are many places within the TCG backends where we need a byte
1080  * difference between two pointers.  While this can be accomplished
1081  * with local casting, it's easy to get wrong -- especially if one is
1082  * concerned with the signedness of the result.
1083  *
1084  * This version relies on GCC's void pointer arithmetic to get the
1085  * correct result.
1086  */
1087
1088 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1089 {
1090     return a - b;
1091 }
1092
1093 /**
1094  * tcg_pcrel_diff
1095  * @s: the tcg context
1096  * @target: address of the target
1097  *
1098  * Produce a pc-relative difference, from the current code_ptr
1099  * to the destination address.
1100  */
1101
1102 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1103 {
1104     return tcg_ptr_byte_diff(target, s->code_ptr);
1105 }
1106
1107 /**
1108  * tcg_current_code_size
1109  * @s: the tcg context
1110  *
1111  * Compute the current code size within the translation block.
1112  * This is used to fill in qemu's data structures for goto_tb.
1113  */
1114
1115 static inline size_t tcg_current_code_size(TCGContext *s)
1116 {
1117     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1118 }
1119
1120 /* Combine the MemOp and mmu_idx parameters into a single value.  */
1121 typedef uint32_t TCGMemOpIdx;
1122
1123 /**
1124  * make_memop_idx
1125  * @op: memory operation
1126  * @idx: mmu index
1127  *
1128  * Encode these values into a single parameter.
1129  */
1130 static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
1131 {
1132     tcg_debug_assert(idx <= 15);
1133     return (op << 4) | idx;
1134 }
1135
1136 /**
1137  * get_memop
1138  * @oi: combined op/idx parameter
1139  *
1140  * Extract the memory operation from the combined value.
1141  */
1142 static inline MemOp get_memop(TCGMemOpIdx oi)
1143 {
1144     return oi >> 4;
1145 }
1146
1147 /**
1148  * get_mmuidx
1149  * @oi: combined op/idx parameter
1150  *
1151  * Extract the mmu index from the combined value.
1152  */
1153 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1154 {
1155     return oi & 15;
1156 }
1157
1158 /**
1159  * tcg_qemu_tb_exec:
1160  * @env: pointer to CPUArchState for the CPU
1161  * @tb_ptr: address of generated code for the TB to execute
1162  *
1163  * Start executing code from a given translation block.
1164  * Where translation blocks have been linked, execution
1165  * may proceed from the given TB into successive ones.
1166  * Control eventually returns only when some action is needed
1167  * from the top-level loop: either control must pass to a TB
1168  * which has not yet been directly linked, or an asynchronous
1169  * event such as an interrupt needs handling.
1170  *
1171  * Return: The return value is the value passed to the corresponding
1172  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1173  * The value is either zero or a 4-byte aligned pointer to that TB combined
1174  * with additional information in its two least significant bits. The
1175  * additional information is encoded as follows:
1176  *  0, 1: the link between this TB and the next is via the specified
1177  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1178  *        of) "goto_tb <index>". The main loop uses this to determine
1179  *        how to link the TB just executed to the next.
1180  *  2:    we are using instruction counting code generation, and we
1181  *        did not start executing this TB because the instruction counter
1182  *        would hit zero midway through it. In this case the pointer
1183  *        returned is the TB we were about to execute, and the caller must
1184  *        arrange to execute the remaining count of instructions.
1185  *  3:    we stopped because the CPU's exit_request flag was set
1186  *        (usually meaning that there is an interrupt that needs to be
1187  *        handled). The pointer returned is the TB we were about to execute
1188  *        when we noticed the pending exit request.
1189  *
1190  * If the bottom two bits indicate an exit-via-index then the CPU
1191  * state is correctly synchronised and ready for execution of the next
1192  * TB (and in particular the guest PC is the address to execute next).
1193  * Otherwise, we gave up on execution of this TB before it started, and
1194  * the caller must fix up the CPU state by calling the CPU's
1195  * synchronize_from_tb() method with the TB pointer we return (falling
1196  * back to calling the CPU's set_pc method with tb->pb if no
1197  * synchronize_from_tb() method exists).
1198  *
1199  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1200  * to this default (which just calls the prologue.code emitted by
1201  * tcg_target_qemu_prologue()).
1202  */
1203 #define TB_EXIT_MASK      3
1204 #define TB_EXIT_IDX0      0
1205 #define TB_EXIT_IDX1      1
1206 #define TB_EXIT_IDXMAX    1
1207 #define TB_EXIT_REQUESTED 3
1208
1209 #ifdef HAVE_TCG_QEMU_TB_EXEC
1210 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1211 #else
1212 # define tcg_qemu_tb_exec(env, tb_ptr) \
1213     ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1214 #endif
1215
1216 void tcg_register_jit(void *buf, size_t buf_size);
1217
1218 #if TCG_TARGET_MAYBE_vec
1219 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1220    return > 0 if it is directly supportable;
1221    return < 0 if we must call tcg_expand_vec_op.  */
1222 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1223 #else
1224 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1225 {
1226     return 0;
1227 }
1228 #endif
1229
1230 /* Expand the tuple (opc, type, vece) on the given arguments.  */
1231 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1232
1233 /* Replicate a constant C accoring to the log2 of the element size.  */
1234 uint64_t dup_const(unsigned vece, uint64_t c);
1235
1236 #define dup_const(VECE, C)                                         \
1237     (__builtin_constant_p(VECE)                                    \
1238      ? (  (VECE) == MO_8  ? 0x0101010101010101ull * (uint8_t)(C)   \
1239         : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C)  \
1240         : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C)  \
1241         : dup_const(VECE, C))                                      \
1242      : dup_const(VECE, C))
1243
1244
1245 /*
1246  * Memory helpers that will be used by TCG generated code.
1247  */
1248 #ifdef CONFIG_SOFTMMU
1249 /* Value zero-extended to tcg register size.  */
1250 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1251                                      TCGMemOpIdx oi, uintptr_t retaddr);
1252 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1253                                     TCGMemOpIdx oi, uintptr_t retaddr);
1254 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1255                                     TCGMemOpIdx oi, uintptr_t retaddr);
1256 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1257                            TCGMemOpIdx oi, uintptr_t retaddr);
1258 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1259                                     TCGMemOpIdx oi, uintptr_t retaddr);
1260 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1261                                     TCGMemOpIdx oi, uintptr_t retaddr);
1262 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1263                            TCGMemOpIdx oi, uintptr_t retaddr);
1264
1265 /* Value sign-extended to tcg register size.  */
1266 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1267                                      TCGMemOpIdx oi, uintptr_t retaddr);
1268 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1269                                     TCGMemOpIdx oi, uintptr_t retaddr);
1270 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1271                                     TCGMemOpIdx oi, uintptr_t retaddr);
1272 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1273                                     TCGMemOpIdx oi, uintptr_t retaddr);
1274 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1275                                     TCGMemOpIdx oi, uintptr_t retaddr);
1276
1277 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1278                         TCGMemOpIdx oi, uintptr_t retaddr);
1279 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1280                        TCGMemOpIdx oi, uintptr_t retaddr);
1281 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1282                        TCGMemOpIdx oi, uintptr_t retaddr);
1283 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1284                        TCGMemOpIdx oi, uintptr_t retaddr);
1285 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1286                        TCGMemOpIdx oi, uintptr_t retaddr);
1287 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1288                        TCGMemOpIdx oi, uintptr_t retaddr);
1289 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1290                        TCGMemOpIdx oi, uintptr_t retaddr);
1291
1292 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1293                             TCGMemOpIdx oi, uintptr_t retaddr);
1294 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1295                             TCGMemOpIdx oi, uintptr_t retaddr);
1296 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1297                             TCGMemOpIdx oi, uintptr_t retaddr);
1298 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1299                             TCGMemOpIdx oi, uintptr_t retaddr);
1300 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1301                             TCGMemOpIdx oi, uintptr_t retaddr);
1302 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1303                             TCGMemOpIdx oi, uintptr_t retaddr);
1304 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1305                             TCGMemOpIdx oi, uintptr_t retaddr);
1306
1307 /* Temporary aliases until backends are converted.  */
1308 #ifdef TARGET_WORDS_BIGENDIAN
1309 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1310 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1311 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1312 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1313 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1314 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1315 # define helper_ret_stw_mmu   helper_be_stw_mmu
1316 # define helper_ret_stl_mmu   helper_be_stl_mmu
1317 # define helper_ret_stq_mmu   helper_be_stq_mmu
1318 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1319 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1320 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1321 #else
1322 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1323 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1324 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1325 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1326 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1327 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1328 # define helper_ret_stw_mmu   helper_le_stw_mmu
1329 # define helper_ret_stl_mmu   helper_le_stl_mmu
1330 # define helper_ret_stq_mmu   helper_le_stq_mmu
1331 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1332 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1333 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1334 #endif
1335
1336 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1337                                     uint32_t cmpv, uint32_t newv,
1338                                     TCGMemOpIdx oi, uintptr_t retaddr);
1339 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1340                                        uint32_t cmpv, uint32_t newv,
1341                                        TCGMemOpIdx oi, uintptr_t retaddr);
1342 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1343                                        uint32_t cmpv, uint32_t newv,
1344                                        TCGMemOpIdx oi, uintptr_t retaddr);
1345 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1346                                        uint64_t cmpv, uint64_t newv,
1347                                        TCGMemOpIdx oi, uintptr_t retaddr);
1348 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1349                                        uint32_t cmpv, uint32_t newv,
1350                                        TCGMemOpIdx oi, uintptr_t retaddr);
1351 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1352                                        uint32_t cmpv, uint32_t newv,
1353                                        TCGMemOpIdx oi, uintptr_t retaddr);
1354 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1355                                        uint64_t cmpv, uint64_t newv,
1356                                        TCGMemOpIdx oi, uintptr_t retaddr);
1357
1358 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1359 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1360     (CPUArchState *env, target_ulong addr, TYPE val,  \
1361      TCGMemOpIdx oi, uintptr_t retaddr);
1362
1363 #ifdef CONFIG_ATOMIC64
1364 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1365     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1366     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1367     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1368     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1369     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1370     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1371     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1372 #else
1373 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1374     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1375     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1376     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1377     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1378     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1379 #endif
1380
1381 GEN_ATOMIC_HELPER_ALL(fetch_add)
1382 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1383 GEN_ATOMIC_HELPER_ALL(fetch_and)
1384 GEN_ATOMIC_HELPER_ALL(fetch_or)
1385 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1386 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1387 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1388 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1389 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1390
1391 GEN_ATOMIC_HELPER_ALL(add_fetch)
1392 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1393 GEN_ATOMIC_HELPER_ALL(and_fetch)
1394 GEN_ATOMIC_HELPER_ALL(or_fetch)
1395 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1396 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1397 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1398 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1399 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1400
1401 GEN_ATOMIC_HELPER_ALL(xchg)
1402
1403 #undef GEN_ATOMIC_HELPER_ALL
1404 #undef GEN_ATOMIC_HELPER
1405 #endif /* CONFIG_SOFTMMU */
1406
1407 /*
1408  * These aren't really a "proper" helpers because TCG cannot manage Int128.
1409  * However, use the same format as the others, for use by the backends.
1410  *
1411  * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1412  * the ld/st functions are only defined if HAVE_ATOMIC128,
1413  * as defined by <qemu/atomic128.h>.
1414  */
1415 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1416                                      Int128 cmpv, Int128 newv,
1417                                      TCGMemOpIdx oi, uintptr_t retaddr);
1418 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1419                                      Int128 cmpv, Int128 newv,
1420                                      TCGMemOpIdx oi, uintptr_t retaddr);
1421
1422 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1423                                 TCGMemOpIdx oi, uintptr_t retaddr);
1424 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1425                                 TCGMemOpIdx oi, uintptr_t retaddr);
1426 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1427                               TCGMemOpIdx oi, uintptr_t retaddr);
1428 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1429                               TCGMemOpIdx oi, uintptr_t retaddr);
1430
1431 #ifdef CONFIG_DEBUG_TCG
1432 void tcg_assert_listed_vecop(TCGOpcode);
1433 #else
1434 static inline void tcg_assert_listed_vecop(TCGOpcode op) { }
1435 #endif
1436
1437 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n)
1438 {
1439 #ifdef CONFIG_DEBUG_TCG
1440     const TCGOpcode *o = tcg_ctx->vecop_list;
1441     tcg_ctx->vecop_list = n;
1442     return o;
1443 #else
1444     return NULL;
1445 #endif
1446 }
1447
1448 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned);
1449
1450 #endif /* TCG_H */