2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
18 #include "qemu/osdep.h"
20 #include "hw/pci/pci.h"
21 #include "hw/qdev-properties.h"
23 #include "net/checksum.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu/bswap.h"
27 #include "qemu/module.h"
28 #include "hw/pci/msix.h"
29 #include "hw/pci/msi.h"
30 #include "migration/register.h"
31 #include "migration/vmstate.h"
34 #include "vmxnet3_defs.h"
35 #include "vmxnet_debug.h"
36 #include "vmware_utils.h"
37 #include "net_tx_pkt.h"
38 #include "net_rx_pkt.h"
39 #include "qom/object.h"
41 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
42 #define VMXNET3_MSIX_BAR_SIZE 0x2000
44 /* Compatibility flags for migration */
45 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
46 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
47 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
48 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
49 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
50 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
52 #define VMXNET3_EXP_EP_OFFSET (0x48)
53 #define VMXNET3_MSI_OFFSET(s) \
54 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
55 #define VMXNET3_MSIX_OFFSET(s) \
56 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
57 #define VMXNET3_DSN_OFFSET (0x100)
59 #define VMXNET3_BAR0_IDX (0)
60 #define VMXNET3_BAR1_IDX (1)
61 #define VMXNET3_MSIX_BAR_IDX (2)
63 #define VMXNET3_OFF_MSIX_TABLE (0x000)
64 #define VMXNET3_OFF_MSIX_PBA(s) \
65 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
67 /* Link speed in Mbps should be shifted by 16 */
68 #define VMXNET3_LINK_SPEED (1000 << 16)
70 /* Link status: 1 - up, 0 - down. */
71 #define VMXNET3_LINK_STATUS_UP 0x1
73 /* Least significant bit should be set for revision and version */
74 #define VMXNET3_UPT_REVISION 0x1
75 #define VMXNET3_DEVICE_REVISION 0x1
77 /* Number of interrupt vectors for non-MSIx modes */
78 #define VMXNET3_MAX_NMSIX_INTRS (1)
80 /* Macros for rings descriptors access */
81 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
82 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
84 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
85 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
87 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
88 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
90 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
91 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
93 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
94 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
96 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
97 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
99 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
100 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
102 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
103 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
105 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
106 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
108 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
109 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
111 /* Macros for guest driver shared area access */
112 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
113 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
115 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
116 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
118 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
119 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
121 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
122 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
124 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
125 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
127 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
128 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
130 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
132 struct VMXNET3Class
{
133 PCIDeviceClass parent_class
;
134 DeviceRealize parent_dc_realize
;
136 typedef struct VMXNET3Class VMXNET3Class
;
138 DECLARE_CLASS_CHECKERS(VMXNET3Class
, VMXNET3_DEVICE
,
141 static inline void vmxnet3_ring_init(PCIDevice
*d
,
150 ring
->cell_size
= cell_size
;
151 ring
->gen
= VMXNET3_INIT_GEN
;
155 vmw_shmem_set(d
, pa
, 0, size
* cell_size
);
159 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
160 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
161 (ring_name), (ridx), \
162 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
164 static inline void vmxnet3_ring_inc(Vmxnet3Ring
*ring
)
166 if (++ring
->next
>= ring
->size
) {
172 static inline void vmxnet3_ring_dec(Vmxnet3Ring
*ring
)
174 if (ring
->next
-- == 0) {
175 ring
->next
= ring
->size
- 1;
180 static inline hwaddr
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring
*ring
)
182 return ring
->pa
+ ring
->next
* ring
->cell_size
;
185 static inline void vmxnet3_ring_read_curr_cell(PCIDevice
*d
, Vmxnet3Ring
*ring
,
188 vmw_shmem_read(d
, vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
191 static inline void vmxnet3_ring_write_curr_cell(PCIDevice
*d
, Vmxnet3Ring
*ring
,
194 vmw_shmem_write(d
, vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
197 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring
*ring
)
202 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring
*ring
)
207 /* Debug trace-related functions */
209 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc
*descr
)
211 VMW_PKPRN("TX DESCR: "
212 "addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
213 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
214 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
215 descr
->addr
, descr
->len
, descr
->gen
, descr
->rsvd
,
216 descr
->dtype
, descr
->ext1
, descr
->msscof
, descr
->hlen
, descr
->om
,
217 descr
->eop
, descr
->cq
, descr
->ext2
, descr
->ti
, descr
->tci
);
221 vmxnet3_dump_virt_hdr(struct virtio_net_hdr
*vhdr
)
223 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
224 "csum_start: %d, csum_offset: %d",
225 vhdr
->flags
, vhdr
->gso_type
, vhdr
->hdr_len
, vhdr
->gso_size
,
226 vhdr
->csum_start
, vhdr
->csum_offset
);
230 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc
*descr
)
232 VMW_PKPRN("RX DESCR: addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
233 "dtype: %d, ext1: %d, btype: %d",
234 descr
->addr
, descr
->len
, descr
->gen
,
235 descr
->rsvd
, descr
->dtype
, descr
->ext1
, descr
->btype
);
238 /* Interrupt management */
241 * This function returns sign whether interrupt line is in asserted state
242 * This depends on the type of interrupt used. For INTX interrupt line will
243 * be asserted until explicit deassertion, for MSI(X) interrupt line will
244 * be deasserted automatically due to notification semantics of the MSI(X)
247 static bool _vmxnet3_assert_interrupt_line(VMXNET3State
*s
, uint32_t int_idx
)
249 PCIDevice
*d
= PCI_DEVICE(s
);
251 if (s
->msix_used
&& msix_enabled(d
)) {
252 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx
);
253 msix_notify(d
, int_idx
);
256 if (msi_enabled(d
)) {
257 VMW_IRPRN("Sending MSI notification for vector %u", int_idx
);
258 msi_notify(d
, int_idx
);
262 VMW_IRPRN("Asserting line for interrupt %u", int_idx
);
267 static void _vmxnet3_deassert_interrupt_line(VMXNET3State
*s
, int lidx
)
269 PCIDevice
*d
= PCI_DEVICE(s
);
272 * This function should never be called for MSI(X) interrupts
273 * because deassertion never required for message interrupts
275 assert(!s
->msix_used
|| !msix_enabled(d
));
277 * This function should never be called for MSI(X) interrupts
278 * because deassertion never required for message interrupts
280 assert(!msi_enabled(d
));
282 VMW_IRPRN("Deasserting line for interrupt %u", lidx
);
286 static void vmxnet3_update_interrupt_line_state(VMXNET3State
*s
, int lidx
)
288 if (!s
->interrupt_states
[lidx
].is_pending
&&
289 s
->interrupt_states
[lidx
].is_asserted
) {
290 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx
);
291 _vmxnet3_deassert_interrupt_line(s
, lidx
);
292 s
->interrupt_states
[lidx
].is_asserted
= false;
296 if (s
->interrupt_states
[lidx
].is_pending
&&
297 !s
->interrupt_states
[lidx
].is_masked
&&
298 !s
->interrupt_states
[lidx
].is_asserted
) {
299 VMW_IRPRN("New interrupt line state for index %d is UP", lidx
);
300 s
->interrupt_states
[lidx
].is_asserted
=
301 _vmxnet3_assert_interrupt_line(s
, lidx
);
302 s
->interrupt_states
[lidx
].is_pending
= false;
307 static void vmxnet3_trigger_interrupt(VMXNET3State
*s
, int lidx
)
309 PCIDevice
*d
= PCI_DEVICE(s
);
310 s
->interrupt_states
[lidx
].is_pending
= true;
311 vmxnet3_update_interrupt_line_state(s
, lidx
);
313 if (s
->msix_used
&& msix_enabled(d
) && s
->auto_int_masking
) {
317 if (msi_enabled(d
) && s
->auto_int_masking
) {
324 s
->interrupt_states
[lidx
].is_masked
= true;
325 vmxnet3_update_interrupt_line_state(s
, lidx
);
328 static bool vmxnet3_interrupt_asserted(VMXNET3State
*s
, int lidx
)
330 return s
->interrupt_states
[lidx
].is_asserted
;
333 static void vmxnet3_clear_interrupt(VMXNET3State
*s
, int int_idx
)
335 s
->interrupt_states
[int_idx
].is_pending
= false;
336 if (s
->auto_int_masking
) {
337 s
->interrupt_states
[int_idx
].is_masked
= true;
339 vmxnet3_update_interrupt_line_state(s
, int_idx
);
343 vmxnet3_on_interrupt_mask_changed(VMXNET3State
*s
, int lidx
, bool is_masked
)
345 s
->interrupt_states
[lidx
].is_masked
= is_masked
;
346 vmxnet3_update_interrupt_line_state(s
, lidx
);
349 static bool vmxnet3_verify_driver_magic(PCIDevice
*d
, hwaddr dshmem
)
351 return (VMXNET3_READ_DRV_SHARED32(d
, dshmem
, magic
) == VMXNET3_REV1_MAGIC
);
354 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
355 #define VMXNET3_MAKE_BYTE(byte_num, val) \
356 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
358 static void vmxnet3_set_variable_mac(VMXNET3State
*s
, uint32_t h
, uint32_t l
)
360 s
->conf
.macaddr
.a
[0] = VMXNET3_GET_BYTE(l
, 0);
361 s
->conf
.macaddr
.a
[1] = VMXNET3_GET_BYTE(l
, 1);
362 s
->conf
.macaddr
.a
[2] = VMXNET3_GET_BYTE(l
, 2);
363 s
->conf
.macaddr
.a
[3] = VMXNET3_GET_BYTE(l
, 3);
364 s
->conf
.macaddr
.a
[4] = VMXNET3_GET_BYTE(h
, 0);
365 s
->conf
.macaddr
.a
[5] = VMXNET3_GET_BYTE(h
, 1);
367 VMW_CFPRN("Variable MAC: " MAC_FMT
, MAC_ARG(s
->conf
.macaddr
.a
));
369 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
372 static uint64_t vmxnet3_get_mac_low(MACAddr
*addr
)
374 return VMXNET3_MAKE_BYTE(0, addr
->a
[0]) |
375 VMXNET3_MAKE_BYTE(1, addr
->a
[1]) |
376 VMXNET3_MAKE_BYTE(2, addr
->a
[2]) |
377 VMXNET3_MAKE_BYTE(3, addr
->a
[3]);
380 static uint64_t vmxnet3_get_mac_high(MACAddr
*addr
)
382 return VMXNET3_MAKE_BYTE(0, addr
->a
[4]) |
383 VMXNET3_MAKE_BYTE(1, addr
->a
[5]);
387 vmxnet3_inc_tx_consumption_counter(VMXNET3State
*s
, int qidx
)
389 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].tx_ring
);
393 vmxnet3_inc_rx_consumption_counter(VMXNET3State
*s
, int qidx
, int ridx
)
395 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].rx_ring
[ridx
]);
399 vmxnet3_inc_tx_completion_counter(VMXNET3State
*s
, int qidx
)
401 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].comp_ring
);
405 vmxnet3_inc_rx_completion_counter(VMXNET3State
*s
, int qidx
)
407 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].comp_ring
);
411 vmxnet3_dec_rx_completion_counter(VMXNET3State
*s
, int qidx
)
413 vmxnet3_ring_dec(&s
->rxq_descr
[qidx
].comp_ring
);
416 static void vmxnet3_complete_packet(VMXNET3State
*s
, int qidx
, uint32_t tx_ridx
)
418 struct Vmxnet3_TxCompDesc txcq_descr
;
419 PCIDevice
*d
= PCI_DEVICE(s
);
421 VMXNET3_RING_DUMP(VMW_RIPRN
, "TXC", qidx
, &s
->txq_descr
[qidx
].comp_ring
);
423 memset(&txcq_descr
, 0, sizeof(txcq_descr
));
424 txcq_descr
.txdIdx
= tx_ridx
;
425 txcq_descr
.gen
= vmxnet3_ring_curr_gen(&s
->txq_descr
[qidx
].comp_ring
);
426 txcq_descr
.val1
= cpu_to_le32(txcq_descr
.val1
);
427 txcq_descr
.val2
= cpu_to_le32(txcq_descr
.val2
);
428 vmxnet3_ring_write_curr_cell(d
, &s
->txq_descr
[qidx
].comp_ring
, &txcq_descr
);
430 /* Flush changes in TX descriptor before changing the counter value */
433 vmxnet3_inc_tx_completion_counter(s
, qidx
);
434 vmxnet3_trigger_interrupt(s
, s
->txq_descr
[qidx
].intr_idx
);
438 vmxnet3_setup_tx_offloads(VMXNET3State
*s
)
440 switch (s
->offload_mode
) {
441 case VMXNET3_OM_NONE
:
442 return net_tx_pkt_build_vheader(s
->tx_pkt
, false, false, 0);
444 case VMXNET3_OM_CSUM
:
445 VMW_PKPRN("L4 CSO requested\n");
446 return net_tx_pkt_build_vheader(s
->tx_pkt
, false, true, 0);
449 VMW_PKPRN("GSO offload requested.");
450 if (!net_tx_pkt_build_vheader(s
->tx_pkt
, true, true,
451 s
->cso_or_gso_size
)) {
454 net_tx_pkt_update_ip_checksums(s
->tx_pkt
);
458 g_assert_not_reached();
466 vmxnet3_tx_retrieve_metadata(VMXNET3State
*s
,
467 const struct Vmxnet3_TxDesc
*txd
)
469 s
->offload_mode
= txd
->om
;
470 s
->cso_or_gso_size
= txd
->msscof
;
472 s
->needs_vlan
= txd
->ti
;
476 VMXNET3_PKT_STATUS_OK
,
477 VMXNET3_PKT_STATUS_ERROR
,
478 VMXNET3_PKT_STATUS_DISCARD
,/* only for tx */
479 VMXNET3_PKT_STATUS_OUT_OF_BUF
/* only for rx */
483 vmxnet3_on_tx_done_update_stats(VMXNET3State
*s
, int qidx
,
484 Vmxnet3PktStatus status
)
486 size_t tot_len
= net_tx_pkt_get_total_len(s
->tx_pkt
);
487 struct UPT1_TxStats
*stats
= &s
->txq_descr
[qidx
].txq_stats
;
490 case VMXNET3_PKT_STATUS_OK
:
491 switch (net_tx_pkt_get_packet_type(s
->tx_pkt
)) {
493 stats
->bcastPktsTxOK
++;
494 stats
->bcastBytesTxOK
+= tot_len
;
497 stats
->mcastPktsTxOK
++;
498 stats
->mcastBytesTxOK
+= tot_len
;
501 stats
->ucastPktsTxOK
++;
502 stats
->ucastBytesTxOK
+= tot_len
;
505 g_assert_not_reached();
508 if (s
->offload_mode
== VMXNET3_OM_TSO
) {
510 * According to VMWARE headers this statistic is a number
511 * of packets after segmentation but since we don't have
512 * this information in QEMU model, the best we can do is to
513 * provide number of non-segmented packets
515 stats
->TSOPktsTxOK
++;
516 stats
->TSOBytesTxOK
+= tot_len
;
520 case VMXNET3_PKT_STATUS_DISCARD
:
521 stats
->pktsTxDiscard
++;
524 case VMXNET3_PKT_STATUS_ERROR
:
525 stats
->pktsTxError
++;
529 g_assert_not_reached();
534 vmxnet3_on_rx_done_update_stats(VMXNET3State
*s
,
536 Vmxnet3PktStatus status
)
538 struct UPT1_RxStats
*stats
= &s
->rxq_descr
[qidx
].rxq_stats
;
539 size_t tot_len
= net_rx_pkt_get_total_len(s
->rx_pkt
);
542 case VMXNET3_PKT_STATUS_OUT_OF_BUF
:
543 stats
->pktsRxOutOfBuf
++;
546 case VMXNET3_PKT_STATUS_ERROR
:
547 stats
->pktsRxError
++;
549 case VMXNET3_PKT_STATUS_OK
:
550 switch (net_rx_pkt_get_packet_type(s
->rx_pkt
)) {
552 stats
->bcastPktsRxOK
++;
553 stats
->bcastBytesRxOK
+= tot_len
;
556 stats
->mcastPktsRxOK
++;
557 stats
->mcastBytesRxOK
+= tot_len
;
560 stats
->ucastPktsRxOK
++;
561 stats
->ucastBytesRxOK
+= tot_len
;
564 g_assert_not_reached();
567 if (tot_len
> s
->mtu
) {
568 stats
->LROPktsRxOK
++;
569 stats
->LROBytesRxOK
+= tot_len
;
573 g_assert_not_reached();
578 vmxnet3_ring_read_curr_txdesc(PCIDevice
*pcidev
, Vmxnet3Ring
*ring
,
579 struct Vmxnet3_TxDesc
*txd
)
581 vmxnet3_ring_read_curr_cell(pcidev
, ring
, txd
);
582 txd
->addr
= le64_to_cpu(txd
->addr
);
583 txd
->val1
= le32_to_cpu(txd
->val1
);
584 txd
->val2
= le32_to_cpu(txd
->val2
);
588 vmxnet3_pop_next_tx_descr(VMXNET3State
*s
,
590 struct Vmxnet3_TxDesc
*txd
,
593 Vmxnet3Ring
*ring
= &s
->txq_descr
[qidx
].tx_ring
;
594 PCIDevice
*d
= PCI_DEVICE(s
);
596 vmxnet3_ring_read_curr_txdesc(d
, ring
, txd
);
597 if (txd
->gen
== vmxnet3_ring_curr_gen(ring
)) {
598 /* Only read after generation field verification */
600 /* Re-read to be sure we got the latest version */
601 vmxnet3_ring_read_curr_txdesc(d
, ring
, txd
);
602 VMXNET3_RING_DUMP(VMW_RIPRN
, "TX", qidx
, ring
);
603 *descr_idx
= vmxnet3_ring_curr_cell_idx(ring
);
604 vmxnet3_inc_tx_consumption_counter(s
, qidx
);
612 vmxnet3_send_packet(VMXNET3State
*s
, uint32_t qidx
)
614 Vmxnet3PktStatus status
= VMXNET3_PKT_STATUS_OK
;
616 if (!vmxnet3_setup_tx_offloads(s
)) {
617 status
= VMXNET3_PKT_STATUS_ERROR
;
622 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s
->tx_pkt
));
623 net_tx_pkt_dump(s
->tx_pkt
);
625 if (!net_tx_pkt_send(s
->tx_pkt
, qemu_get_queue(s
->nic
))) {
626 status
= VMXNET3_PKT_STATUS_DISCARD
;
631 vmxnet3_on_tx_done_update_stats(s
, qidx
, status
);
632 return (status
== VMXNET3_PKT_STATUS_OK
);
635 static void vmxnet3_process_tx_queue(VMXNET3State
*s
, int qidx
)
637 struct Vmxnet3_TxDesc txd
;
643 if (!vmxnet3_pop_next_tx_descr(s
, qidx
, &txd
, &txd_idx
)) {
647 vmxnet3_dump_tx_descr(&txd
);
649 if (!s
->skip_current_tx_pkt
) {
650 data_len
= (txd
.len
> 0) ? txd
.len
: VMXNET3_MAX_TX_BUF_SIZE
;
653 if (!net_tx_pkt_add_raw_fragment_pci(s
->tx_pkt
, PCI_DEVICE(s
),
654 data_pa
, data_len
)) {
655 s
->skip_current_tx_pkt
= true;
660 vmxnet3_tx_retrieve_metadata(s
, &txd
);
665 if (!s
->skip_current_tx_pkt
&& net_tx_pkt_parse(s
->tx_pkt
)) {
667 net_tx_pkt_setup_vlan_header(s
->tx_pkt
, s
->tci
);
670 vmxnet3_send_packet(s
, qidx
);
672 vmxnet3_on_tx_done_update_stats(s
, qidx
,
673 VMXNET3_PKT_STATUS_ERROR
);
676 vmxnet3_complete_packet(s
, qidx
, txd_idx
);
678 s
->skip_current_tx_pkt
= false;
679 net_tx_pkt_reset(s
->tx_pkt
,
680 net_tx_pkt_unmap_frag_pci
, PCI_DEVICE(s
));
684 net_tx_pkt_reset(s
->tx_pkt
, net_tx_pkt_unmap_frag_pci
, PCI_DEVICE(s
));
688 vmxnet3_read_next_rx_descr(VMXNET3State
*s
, int qidx
, int ridx
,
689 struct Vmxnet3_RxDesc
*dbuf
, uint32_t *didx
)
691 PCIDevice
*d
= PCI_DEVICE(s
);
693 Vmxnet3Ring
*ring
= &s
->rxq_descr
[qidx
].rx_ring
[ridx
];
694 *didx
= vmxnet3_ring_curr_cell_idx(ring
);
695 vmxnet3_ring_read_curr_cell(d
, ring
, dbuf
);
696 dbuf
->addr
= le64_to_cpu(dbuf
->addr
);
697 dbuf
->val1
= le32_to_cpu(dbuf
->val1
);
698 dbuf
->ext1
= le32_to_cpu(dbuf
->ext1
);
701 static inline uint8_t
702 vmxnet3_get_rx_ring_gen(VMXNET3State
*s
, int qidx
, int ridx
)
704 return s
->rxq_descr
[qidx
].rx_ring
[ridx
].gen
;
708 vmxnet3_pop_rxc_descr(VMXNET3State
*s
, int qidx
, uint32_t *descr_gen
)
711 struct Vmxnet3_RxCompDesc rxcd
;
714 vmxnet3_ring_curr_cell_pa(&s
->rxq_descr
[qidx
].comp_ring
);
716 pci_dma_read(PCI_DEVICE(s
),
717 daddr
, &rxcd
, sizeof(struct Vmxnet3_RxCompDesc
));
718 rxcd
.val1
= le32_to_cpu(rxcd
.val1
);
719 rxcd
.val2
= le32_to_cpu(rxcd
.val2
);
720 rxcd
.val3
= le32_to_cpu(rxcd
.val3
);
721 ring_gen
= vmxnet3_ring_curr_gen(&s
->rxq_descr
[qidx
].comp_ring
);
723 if (rxcd
.gen
!= ring_gen
) {
724 *descr_gen
= ring_gen
;
725 vmxnet3_inc_rx_completion_counter(s
, qidx
);
733 vmxnet3_revert_rxc_descr(VMXNET3State
*s
, int qidx
)
735 vmxnet3_dec_rx_completion_counter(s
, qidx
);
739 #define RX_HEAD_BODY_RING (0)
740 #define RX_BODY_ONLY_RING (1)
743 vmxnet3_get_next_head_rx_descr(VMXNET3State
*s
,
744 struct Vmxnet3_RxDesc
*descr_buf
,
750 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
751 descr_buf
, descr_idx
);
753 /* If no more free descriptors - return */
754 ring_gen
= vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
755 if (descr_buf
->gen
!= ring_gen
) {
759 /* Only read after generation field verification */
761 /* Re-read to be sure we got the latest version */
762 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
763 descr_buf
, descr_idx
);
765 /* Mark current descriptor as used/skipped */
766 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
768 /* If this is what we are looking for - return */
769 if (descr_buf
->btype
== VMXNET3_RXD_BTYPE_HEAD
) {
770 *ridx
= RX_HEAD_BODY_RING
;
777 vmxnet3_get_next_body_rx_descr(VMXNET3State
*s
,
778 struct Vmxnet3_RxDesc
*d
,
782 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
784 /* Try to find corresponding descriptor in head/body ring */
785 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
)) {
786 /* Only read after generation field verification */
788 /* Re-read to be sure we got the latest version */
789 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
790 if (d
->btype
== VMXNET3_RXD_BTYPE_BODY
) {
791 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
792 *ridx
= RX_HEAD_BODY_RING
;
798 * If there is no free descriptors on head/body ring or next free
799 * descriptor is a head descriptor switch to body only ring
801 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
803 /* If no more free descriptors - return */
804 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_BODY_ONLY_RING
)) {
805 /* Only read after generation field verification */
807 /* Re-read to be sure we got the latest version */
808 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
809 assert(d
->btype
== VMXNET3_RXD_BTYPE_BODY
);
810 *ridx
= RX_BODY_ONLY_RING
;
811 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_BODY_ONLY_RING
);
819 vmxnet3_get_next_rx_descr(VMXNET3State
*s
, bool is_head
,
820 struct Vmxnet3_RxDesc
*descr_buf
,
824 if (is_head
|| !s
->rx_packets_compound
) {
825 return vmxnet3_get_next_head_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
827 return vmxnet3_get_next_body_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
831 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
832 * the implementation always passes an RxCompDesc with a "Checksum
833 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
834 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
836 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
837 * and place a fully computed checksum into the tcp/udp header.
838 * Otherwise, the OS driver will receive a checksum-correct indication
839 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
840 * having just the pseudo header csum value.
842 * While this is not a problem if packet is destined for local delivery,
843 * in the case the host OS performs forwarding, it will forward an
844 * incorrectly checksummed packet.
846 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt
*pkt
,
847 const void *pkt_data
,
850 struct virtio_net_hdr
*vhdr
;
852 EthL4HdrProto l4hdr_proto
;
856 vhdr
= net_rx_pkt_get_vhdr(pkt
);
857 if (!VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
)) {
861 net_rx_pkt_get_protocols(pkt
, &hasip4
, &hasip6
, &l4hdr_proto
);
862 if (!(hasip4
|| hasip6
) ||
863 (l4hdr_proto
!= ETH_L4_HDR_PROTO_TCP
&&
864 l4hdr_proto
!= ETH_L4_HDR_PROTO_UDP
)) {
868 vmxnet3_dump_virt_hdr(vhdr
);
870 /* Validate packet len: csum_start + scum_offset + length of csum field */
871 if (pkt_len
< (vhdr
->csum_start
+ vhdr
->csum_offset
+ 2)) {
872 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
873 "cannot calculate checksum",
874 pkt_len
, vhdr
->csum_start
, vhdr
->csum_offset
);
878 data
= (uint8_t *)pkt_data
+ vhdr
->csum_start
;
879 len
= pkt_len
- vhdr
->csum_start
;
880 /* Put the checksum obtained into the packet */
881 stw_be_p(data
+ vhdr
->csum_offset
,
882 net_checksum_finish_nozero(net_checksum_add(len
, data
)));
884 vhdr
->flags
&= ~VIRTIO_NET_HDR_F_NEEDS_CSUM
;
885 vhdr
->flags
|= VIRTIO_NET_HDR_F_DATA_VALID
;
888 static void vmxnet3_rx_update_descr(struct NetRxPkt
*pkt
,
889 struct Vmxnet3_RxCompDesc
*rxcd
)
893 EthL4HdrProto l4hdr_proto
;
894 struct virtio_net_hdr
*vhdr
;
895 uint8_t offload_type
;
897 if (net_rx_pkt_is_vlan_stripped(pkt
)) {
899 rxcd
->tci
= net_rx_pkt_get_vlan_tag(pkt
);
902 vhdr
= net_rx_pkt_get_vhdr(pkt
);
904 * Checksum is valid when lower level tell so or when lower level
905 * requires checksum offload telling that packet produced/bridged
906 * locally and did travel over network after last checksum calculation
909 csum_ok
= VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_DATA_VALID
) ||
910 VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
);
912 offload_type
= vhdr
->gso_type
& ~VIRTIO_NET_HDR_GSO_ECN
;
913 is_gso
= (offload_type
!= VIRTIO_NET_HDR_GSO_NONE
) ? 1 : 0;
915 if (!csum_ok
&& !is_gso
) {
919 net_rx_pkt_get_protocols(pkt
, &hasip4
, &hasip6
, &l4hdr_proto
);
920 if ((l4hdr_proto
!= ETH_L4_HDR_PROTO_TCP
&&
921 l4hdr_proto
!= ETH_L4_HDR_PROTO_UDP
) ||
922 (!hasip4
&& !hasip6
)) {
927 rxcd
->v4
= hasip4
? 1 : 0;
928 rxcd
->v6
= hasip6
? 1 : 0;
929 rxcd
->tcp
= l4hdr_proto
== ETH_L4_HDR_PROTO_TCP
;
930 rxcd
->udp
= l4hdr_proto
== ETH_L4_HDR_PROTO_UDP
;
931 rxcd
->fcs
= rxcd
->tuc
= rxcd
->ipc
= 1;
940 vmxnet3_pci_dma_writev(PCIDevice
*pci_dev
,
941 const struct iovec
*iov
,
942 size_t start_iov_off
,
944 size_t bytes_to_copy
)
949 while (bytes_to_copy
) {
950 if (start_iov_off
< (curr_off
+ iov
->iov_len
)) {
952 MIN((curr_off
+ iov
->iov_len
) - start_iov_off
, bytes_to_copy
);
954 pci_dma_write(pci_dev
, target_addr
+ copied
,
955 iov
->iov_base
+ start_iov_off
- curr_off
,
959 start_iov_off
+= chunk_len
;
960 curr_off
= start_iov_off
;
961 bytes_to_copy
-= chunk_len
;
963 curr_off
+= iov
->iov_len
;
970 vmxnet3_pci_dma_write_rxcd(PCIDevice
*pcidev
, dma_addr_t pa
,
971 struct Vmxnet3_RxCompDesc
*rxcd
)
973 rxcd
->val1
= cpu_to_le32(rxcd
->val1
);
974 rxcd
->val2
= cpu_to_le32(rxcd
->val2
);
975 rxcd
->val3
= cpu_to_le32(rxcd
->val3
);
976 pci_dma_write(pcidev
, pa
, rxcd
, sizeof(*rxcd
));
980 vmxnet3_indicate_packet(VMXNET3State
*s
)
982 struct Vmxnet3_RxDesc rxd
;
983 PCIDevice
*d
= PCI_DEVICE(s
);
986 uint32_t rx_ridx
= 0;
988 struct Vmxnet3_RxCompDesc rxcd
;
989 uint32_t new_rxcd_gen
= VMXNET3_INIT_GEN
;
990 hwaddr new_rxcd_pa
= 0;
991 hwaddr ready_rxcd_pa
= 0;
992 struct iovec
*data
= net_rx_pkt_get_iovec(s
->rx_pkt
);
993 size_t bytes_copied
= 0;
994 size_t bytes_left
= net_rx_pkt_get_total_len(s
->rx_pkt
);
995 uint16_t num_frags
= 0;
998 net_rx_pkt_dump(s
->rx_pkt
);
1000 while (bytes_left
> 0) {
1002 /* cannot add more frags to packet */
1003 if (num_frags
== s
->max_rx_frags
) {
1007 new_rxcd_pa
= vmxnet3_pop_rxc_descr(s
, RXQ_IDX
, &new_rxcd_gen
);
1012 if (!vmxnet3_get_next_rx_descr(s
, is_head
, &rxd
, &rxd_idx
, &rx_ridx
)) {
1016 chunk_size
= MIN(bytes_left
, rxd
.len
);
1017 vmxnet3_pci_dma_writev(d
, data
, bytes_copied
, rxd
.addr
, chunk_size
);
1018 bytes_copied
+= chunk_size
;
1019 bytes_left
-= chunk_size
;
1021 vmxnet3_dump_rx_descr(&rxd
);
1023 if (ready_rxcd_pa
!= 0) {
1024 vmxnet3_pci_dma_write_rxcd(d
, ready_rxcd_pa
, &rxcd
);
1027 memset(&rxcd
, 0, sizeof(struct Vmxnet3_RxCompDesc
));
1028 rxcd
.rxdIdx
= rxd_idx
;
1029 rxcd
.len
= chunk_size
;
1031 rxcd
.gen
= new_rxcd_gen
;
1032 rxcd
.rqID
= RXQ_IDX
+ rx_ridx
* s
->rxq_num
;
1034 if (bytes_left
== 0) {
1035 vmxnet3_rx_update_descr(s
->rx_pkt
, &rxcd
);
1038 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1039 "sop %d csum_correct %lu",
1040 (unsigned long) rx_ridx
,
1041 (unsigned long) rxcd
.rxdIdx
,
1042 (unsigned long) rxcd
.len
,
1044 (unsigned long) rxcd
.tuc
);
1047 ready_rxcd_pa
= new_rxcd_pa
;
1052 if (ready_rxcd_pa
!= 0) {
1054 rxcd
.err
= (bytes_left
!= 0);
1056 vmxnet3_pci_dma_write_rxcd(d
, ready_rxcd_pa
, &rxcd
);
1058 /* Flush RX descriptor changes */
1062 if (new_rxcd_pa
!= 0) {
1063 vmxnet3_revert_rxc_descr(s
, RXQ_IDX
);
1066 vmxnet3_trigger_interrupt(s
, s
->rxq_descr
[RXQ_IDX
].intr_idx
);
1068 if (bytes_left
== 0) {
1069 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_OK
);
1071 } else if (num_frags
== s
->max_rx_frags
) {
1072 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_ERROR
);
1075 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
,
1076 VMXNET3_PKT_STATUS_OUT_OF_BUF
);
1082 vmxnet3_io_bar0_write(void *opaque
, hwaddr addr
,
1083 uint64_t val
, unsigned size
)
1085 VMXNET3State
*s
= opaque
;
1087 if (!s
->device_active
) {
1091 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_TXPROD
,
1092 VMXNET3_DEVICE_MAX_TX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1094 VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_TXPROD
,
1096 if (tx_queue_idx
<= s
->txq_num
) {
1097 vmxnet3_process_tx_queue(s
, tx_queue_idx
);
1099 qemu_log_mask(LOG_GUEST_ERROR
, "vmxnet3: Illegal TX queue %d/%d\n",
1100 tx_queue_idx
, s
->txq_num
);
1105 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1106 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1107 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1110 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64
, l
, val
);
1112 vmxnet3_on_interrupt_mask_changed(s
, l
, val
);
1116 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD
,
1117 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
) ||
1118 VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD2
,
1119 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1123 VMW_WRPRN("BAR0 unknown write [%" PRIx64
"] = %" PRIx64
", size %d",
1124 (uint64_t) addr
, val
, size
);
1128 vmxnet3_io_bar0_read(void *opaque
, hwaddr addr
, unsigned size
)
1130 VMXNET3State
*s
= opaque
;
1132 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1133 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1134 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1136 return s
->interrupt_states
[l
].is_masked
;
1139 VMW_CBPRN("BAR0 unknown read [%" PRIx64
"], size %d", addr
, size
);
1143 static void vmxnet3_reset_interrupt_states(VMXNET3State
*s
)
1146 for (i
= 0; i
< ARRAY_SIZE(s
->interrupt_states
); i
++) {
1147 s
->interrupt_states
[i
].is_asserted
= false;
1148 s
->interrupt_states
[i
].is_pending
= false;
1149 s
->interrupt_states
[i
].is_masked
= true;
1153 static void vmxnet3_reset_mac(VMXNET3State
*s
)
1155 memcpy(&s
->conf
.macaddr
.a
, &s
->perm_mac
.a
, sizeof(s
->perm_mac
.a
));
1156 VMW_CFPRN("MAC address set to: " MAC_FMT
, MAC_ARG(s
->conf
.macaddr
.a
));
1159 static void vmxnet3_deactivate_device(VMXNET3State
*s
)
1161 if (s
->device_active
) {
1162 VMW_CBPRN("Deactivating vmxnet3...");
1163 net_tx_pkt_uninit(s
->tx_pkt
);
1164 net_rx_pkt_uninit(s
->rx_pkt
);
1165 s
->device_active
= false;
1169 static void vmxnet3_reset(VMXNET3State
*s
)
1171 VMW_CBPRN("Resetting vmxnet3...");
1173 vmxnet3_deactivate_device(s
);
1174 vmxnet3_reset_interrupt_states(s
);
1177 s
->skip_current_tx_pkt
= false;
1180 static void vmxnet3_update_rx_mode(VMXNET3State
*s
)
1182 PCIDevice
*d
= PCI_DEVICE(s
);
1184 s
->rx_mode
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
,
1185 devRead
.rxFilterConf
.rxMode
);
1186 VMW_CFPRN("RX mode: 0x%08X", s
->rx_mode
);
1189 static void vmxnet3_update_vlan_filters(VMXNET3State
*s
)
1192 PCIDevice
*d
= PCI_DEVICE(s
);
1194 /* Copy configuration from shared memory */
1195 VMXNET3_READ_DRV_SHARED(d
, s
->drv_shmem
,
1196 devRead
.rxFilterConf
.vfTable
,
1198 sizeof(s
->vlan_table
));
1200 /* Invert byte order when needed */
1201 for (i
= 0; i
< ARRAY_SIZE(s
->vlan_table
); i
++) {
1202 s
->vlan_table
[i
] = le32_to_cpu(s
->vlan_table
[i
]);
1205 /* Dump configuration for debugging purposes */
1206 VMW_CFPRN("Configured VLANs:");
1207 for (i
= 0; i
< sizeof(s
->vlan_table
) * 8; i
++) {
1208 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, i
)) {
1209 VMW_CFPRN("\tVLAN %d is present", i
);
1214 static void vmxnet3_update_mcast_filters(VMXNET3State
*s
)
1216 PCIDevice
*d
= PCI_DEVICE(s
);
1218 uint16_t list_bytes
=
1219 VMXNET3_READ_DRV_SHARED16(d
, s
->drv_shmem
,
1220 devRead
.rxFilterConf
.mfTableLen
);
1222 s
->mcast_list_len
= list_bytes
/ sizeof(s
->mcast_list
[0]);
1224 s
->mcast_list
= g_realloc(s
->mcast_list
, list_bytes
);
1225 if (!s
->mcast_list
) {
1226 if (s
->mcast_list_len
== 0) {
1227 VMW_CFPRN("Current multicast list is empty");
1229 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1232 s
->mcast_list_len
= 0;
1235 hwaddr mcast_list_pa
=
1236 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
,
1237 devRead
.rxFilterConf
.mfTablePA
);
1239 pci_dma_read(d
, mcast_list_pa
, s
->mcast_list
, list_bytes
);
1241 VMW_CFPRN("Current multicast list len is %d:", s
->mcast_list_len
);
1242 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1243 VMW_CFPRN("\t" MAC_FMT
, MAC_ARG(s
->mcast_list
[i
].a
));
1248 static void vmxnet3_setup_rx_filtering(VMXNET3State
*s
)
1250 vmxnet3_update_rx_mode(s
);
1251 vmxnet3_update_vlan_filters(s
);
1252 vmxnet3_update_mcast_filters(s
);
1255 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State
*s
)
1257 uint32_t interrupt_mode
= VMXNET3_IT_AUTO
| (VMXNET3_IMM_AUTO
<< 2);
1258 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode
);
1259 return interrupt_mode
;
1262 static void vmxnet3_fill_stats(VMXNET3State
*s
)
1265 PCIDevice
*d
= PCI_DEVICE(s
);
1267 if (!s
->device_active
)
1270 for (i
= 0; i
< s
->txq_num
; i
++) {
1272 s
->txq_descr
[i
].tx_stats_pa
,
1273 &s
->txq_descr
[i
].txq_stats
,
1274 sizeof(s
->txq_descr
[i
].txq_stats
));
1277 for (i
= 0; i
< s
->rxq_num
; i
++) {
1279 s
->rxq_descr
[i
].rx_stats_pa
,
1280 &s
->rxq_descr
[i
].rxq_stats
,
1281 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1285 static void vmxnet3_adjust_by_guest_type(VMXNET3State
*s
)
1287 struct Vmxnet3_GOSInfo gos
;
1288 PCIDevice
*d
= PCI_DEVICE(s
);
1290 VMXNET3_READ_DRV_SHARED(d
, s
->drv_shmem
, devRead
.misc
.driverInfo
.gos
,
1292 s
->rx_packets_compound
=
1293 (gos
.gosType
== VMXNET3_GOS_TYPE_WIN
) ? false : true;
1295 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s
->rx_packets_compound
);
1299 vmxnet3_dump_conf_descr(const char *name
,
1300 struct Vmxnet3_VariableLenConfDesc
*pm_descr
)
1302 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1303 name
, pm_descr
->confVer
, pm_descr
->confLen
);
1307 static void vmxnet3_update_pm_state(VMXNET3State
*s
)
1309 struct Vmxnet3_VariableLenConfDesc pm_descr
;
1310 PCIDevice
*d
= PCI_DEVICE(s
);
1313 VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confLen
);
1315 VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confVer
);
1317 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
, devRead
.pmConfDesc
.confPA
);
1319 vmxnet3_dump_conf_descr("PM State", &pm_descr
);
1322 static void vmxnet3_update_features(VMXNET3State
*s
)
1324 uint32_t guest_features
;
1325 int rxcso_supported
;
1326 PCIDevice
*d
= PCI_DEVICE(s
);
1328 guest_features
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
,
1329 devRead
.misc
.uptFeatures
);
1331 rxcso_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXCSUM
);
1332 s
->rx_vlan_stripping
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXVLAN
);
1333 s
->lro_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_LRO
);
1335 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1336 s
->lro_supported
, rxcso_supported
,
1337 s
->rx_vlan_stripping
);
1338 if (s
->peer_has_vhdr
) {
1339 qemu_set_offload(qemu_get_queue(s
->nic
)->peer
,
1350 static bool vmxnet3_verify_intx(VMXNET3State
*s
, int intx
)
1352 return s
->msix_used
|| msi_enabled(PCI_DEVICE(s
))
1353 || intx
== pci_get_byte(s
->parent_obj
.config
+ PCI_INTERRUPT_PIN
) - 1;
1356 static void vmxnet3_validate_interrupt_idx(bool is_msix
, int idx
)
1358 int max_ints
= is_msix
? VMXNET3_MAX_INTRS
: VMXNET3_MAX_NMSIX_INTRS
;
1359 if (idx
>= max_ints
) {
1360 hw_error("Bad interrupt index: %d\n", idx
);
1364 static void vmxnet3_validate_interrupts(VMXNET3State
*s
)
1368 VMW_CFPRN("Verifying event interrupt index (%d)", s
->event_int_idx
);
1369 vmxnet3_validate_interrupt_idx(s
->msix_used
, s
->event_int_idx
);
1371 for (i
= 0; i
< s
->txq_num
; i
++) {
1372 int idx
= s
->txq_descr
[i
].intr_idx
;
1373 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i
, idx
);
1374 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1377 for (i
= 0; i
< s
->rxq_num
; i
++) {
1378 int idx
= s
->rxq_descr
[i
].intr_idx
;
1379 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i
, idx
);
1380 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1384 static bool vmxnet3_validate_queues(VMXNET3State
*s
)
1387 * txq_num and rxq_num are total number of queues
1388 * configured by guest. These numbers must not
1389 * exceed corresponding maximal values.
1392 if (s
->txq_num
> VMXNET3_DEVICE_MAX_TX_QUEUES
) {
1393 qemu_log_mask(LOG_GUEST_ERROR
, "vmxnet3: Bad TX queues number: %d\n",
1398 if (s
->rxq_num
> VMXNET3_DEVICE_MAX_RX_QUEUES
) {
1399 qemu_log_mask(LOG_GUEST_ERROR
, "vmxnet3: Bad RX queues number: %d\n",
1407 static void vmxnet3_activate_device(VMXNET3State
*s
)
1410 static const uint32_t VMXNET3_DEF_TX_THRESHOLD
= 1;
1411 PCIDevice
*d
= PCI_DEVICE(s
);
1412 hwaddr qdescr_table_pa
;
1416 /* Verify configuration consistency */
1417 if (!vmxnet3_verify_driver_magic(d
, s
->drv_shmem
)) {
1418 VMW_ERPRN("Device configuration received from driver is invalid");
1422 /* Verify if device is active */
1423 if (s
->device_active
) {
1424 VMW_CFPRN("Vmxnet3 device is active");
1429 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.misc
.numTxQueues
);
1431 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.misc
.numRxQueues
);
1433 VMW_CFPRN("Number of TX/RX queues %u/%u", s
->txq_num
, s
->rxq_num
);
1434 if (!vmxnet3_validate_queues(s
)) {
1438 vmxnet3_adjust_by_guest_type(s
);
1439 vmxnet3_update_features(s
);
1440 vmxnet3_update_pm_state(s
);
1441 vmxnet3_setup_rx_filtering(s
);
1442 /* Cache fields from shared memory */
1443 s
->mtu
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, devRead
.misc
.mtu
);
1444 if (s
->mtu
< VMXNET3_MIN_MTU
|| s
->mtu
> VMXNET3_MAX_MTU
) {
1445 qemu_log_mask(LOG_GUEST_ERROR
, "vmxnet3: Bad MTU size: %u\n", s
->mtu
);
1448 VMW_CFPRN("MTU is %u", s
->mtu
);
1451 VMXNET3_READ_DRV_SHARED16(d
, s
->drv_shmem
, devRead
.misc
.maxNumRxSG
);
1453 if (s
->max_rx_frags
== 0) {
1454 s
->max_rx_frags
= 1;
1457 VMW_CFPRN("Max RX fragments is %u", s
->max_rx_frags
);
1460 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.intrConf
.eventIntrIdx
);
1461 assert(vmxnet3_verify_intx(s
, s
->event_int_idx
));
1462 VMW_CFPRN("Events interrupt line is %u", s
->event_int_idx
);
1464 s
->auto_int_masking
=
1465 VMXNET3_READ_DRV_SHARED8(d
, s
->drv_shmem
, devRead
.intrConf
.autoMask
);
1466 VMW_CFPRN("Automatic interrupt masking is %d", (int)s
->auto_int_masking
);
1469 VMXNET3_READ_DRV_SHARED64(d
, s
->drv_shmem
, devRead
.misc
.queueDescPA
);
1470 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64
, qdescr_table_pa
);
1473 * Worst-case scenario is a packet that holds all TX rings space so
1474 * we calculate total size of all TX rings for max TX fragments number
1476 s
->max_tx_frags
= 0;
1479 for (i
= 0; i
< s
->txq_num
; i
++) {
1481 qdescr_table_pa
+ i
* sizeof(struct Vmxnet3_TxQueueDesc
);
1483 /* Read interrupt number for this TX queue */
1484 s
->txq_descr
[i
].intr_idx
=
1485 VMXNET3_READ_TX_QUEUE_DESCR8(d
, qdescr_pa
, conf
.intrIdx
);
1486 assert(vmxnet3_verify_intx(s
, s
->txq_descr
[i
].intr_idx
));
1488 VMW_CFPRN("TX Queue %d interrupt: %d", i
, s
->txq_descr
[i
].intr_idx
);
1490 /* Read rings memory locations for TX queues */
1491 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(d
, qdescr_pa
, conf
.txRingBasePA
);
1492 size
= VMXNET3_READ_TX_QUEUE_DESCR32(d
, qdescr_pa
, conf
.txRingSize
);
1493 if (size
> VMXNET3_TX_RING_MAX_SIZE
) {
1494 size
= VMXNET3_TX_RING_MAX_SIZE
;
1497 vmxnet3_ring_init(d
, &s
->txq_descr
[i
].tx_ring
, pa
, size
,
1498 sizeof(struct Vmxnet3_TxDesc
), false);
1499 VMXNET3_RING_DUMP(VMW_CFPRN
, "TX", i
, &s
->txq_descr
[i
].tx_ring
);
1501 s
->max_tx_frags
+= size
;
1504 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(d
, qdescr_pa
, conf
.compRingBasePA
);
1505 size
= VMXNET3_READ_TX_QUEUE_DESCR32(d
, qdescr_pa
, conf
.compRingSize
);
1506 if (size
> VMXNET3_TC_RING_MAX_SIZE
) {
1507 size
= VMXNET3_TC_RING_MAX_SIZE
;
1509 vmxnet3_ring_init(d
, &s
->txq_descr
[i
].comp_ring
, pa
, size
,
1510 sizeof(struct Vmxnet3_TxCompDesc
), true);
1511 VMXNET3_RING_DUMP(VMW_CFPRN
, "TXC", i
, &s
->txq_descr
[i
].comp_ring
);
1513 s
->txq_descr
[i
].tx_stats_pa
=
1514 qdescr_pa
+ offsetof(struct Vmxnet3_TxQueueDesc
, stats
);
1516 memset(&s
->txq_descr
[i
].txq_stats
, 0,
1517 sizeof(s
->txq_descr
[i
].txq_stats
));
1519 /* Fill device-managed parameters for queues */
1520 VMXNET3_WRITE_TX_QUEUE_DESCR32(d
, qdescr_pa
,
1522 VMXNET3_DEF_TX_THRESHOLD
);
1525 /* Preallocate TX packet wrapper */
1526 VMW_CFPRN("Max TX fragments is %u", s
->max_tx_frags
);
1527 net_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
);
1528 net_rx_pkt_init(&s
->rx_pkt
);
1530 /* Read rings memory locations for RX queues */
1531 for (i
= 0; i
< s
->rxq_num
; i
++) {
1534 qdescr_table_pa
+ s
->txq_num
* sizeof(struct Vmxnet3_TxQueueDesc
) +
1535 i
* sizeof(struct Vmxnet3_RxQueueDesc
);
1537 /* Read interrupt number for this RX queue */
1538 s
->rxq_descr
[i
].intr_idx
=
1539 VMXNET3_READ_TX_QUEUE_DESCR8(d
, qd_pa
, conf
.intrIdx
);
1540 assert(vmxnet3_verify_intx(s
, s
->rxq_descr
[i
].intr_idx
));
1542 VMW_CFPRN("RX Queue %d interrupt: %d", i
, s
->rxq_descr
[i
].intr_idx
);
1544 /* Read rings memory locations */
1545 for (j
= 0; j
< VMXNET3_RX_RINGS_PER_QUEUE
; j
++) {
1547 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(d
, qd_pa
, conf
.rxRingBasePA
[j
]);
1548 size
= VMXNET3_READ_RX_QUEUE_DESCR32(d
, qd_pa
, conf
.rxRingSize
[j
]);
1549 if (size
> VMXNET3_RX_RING_MAX_SIZE
) {
1550 size
= VMXNET3_RX_RING_MAX_SIZE
;
1552 vmxnet3_ring_init(d
, &s
->rxq_descr
[i
].rx_ring
[j
], pa
, size
,
1553 sizeof(struct Vmxnet3_RxDesc
), false);
1554 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64
", Size: %d",
1559 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(d
, qd_pa
, conf
.compRingBasePA
);
1560 size
= VMXNET3_READ_RX_QUEUE_DESCR32(d
, qd_pa
, conf
.compRingSize
);
1561 if (size
> VMXNET3_RC_RING_MAX_SIZE
) {
1562 size
= VMXNET3_RC_RING_MAX_SIZE
;
1564 vmxnet3_ring_init(d
, &s
->rxq_descr
[i
].comp_ring
, pa
, size
,
1565 sizeof(struct Vmxnet3_RxCompDesc
), true);
1566 VMW_CFPRN("RXC queue %d: Base: %" PRIx64
", Size: %d", i
, pa
, size
);
1568 s
->rxq_descr
[i
].rx_stats_pa
=
1569 qd_pa
+ offsetof(struct Vmxnet3_RxQueueDesc
, stats
);
1570 memset(&s
->rxq_descr
[i
].rxq_stats
, 0,
1571 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1574 vmxnet3_validate_interrupts(s
);
1576 /* Make sure everything is in place before device activation */
1579 vmxnet3_reset_mac(s
);
1581 s
->device_active
= true;
1584 static void vmxnet3_handle_command(VMXNET3State
*s
, uint64_t cmd
)
1586 s
->last_command
= cmd
;
1589 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1590 VMW_CBPRN("Set: Get upper part of permanent MAC");
1593 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1594 VMW_CBPRN("Set: Get lower part of permanent MAC");
1597 case VMXNET3_CMD_GET_STATS
:
1598 VMW_CBPRN("Set: Get device statistics");
1599 vmxnet3_fill_stats(s
);
1602 case VMXNET3_CMD_ACTIVATE_DEV
:
1603 VMW_CBPRN("Set: Activating vmxnet3 device");
1604 vmxnet3_activate_device(s
);
1607 case VMXNET3_CMD_UPDATE_RX_MODE
:
1608 VMW_CBPRN("Set: Update rx mode");
1609 vmxnet3_update_rx_mode(s
);
1612 case VMXNET3_CMD_UPDATE_VLAN_FILTERS
:
1613 VMW_CBPRN("Set: Update VLAN filters");
1614 vmxnet3_update_vlan_filters(s
);
1617 case VMXNET3_CMD_UPDATE_MAC_FILTERS
:
1618 VMW_CBPRN("Set: Update MAC filters");
1619 vmxnet3_update_mcast_filters(s
);
1622 case VMXNET3_CMD_UPDATE_FEATURE
:
1623 VMW_CBPRN("Set: Update features");
1624 vmxnet3_update_features(s
);
1627 case VMXNET3_CMD_UPDATE_PMCFG
:
1628 VMW_CBPRN("Set: Update power management config");
1629 vmxnet3_update_pm_state(s
);
1632 case VMXNET3_CMD_GET_LINK
:
1633 VMW_CBPRN("Set: Get link");
1636 case VMXNET3_CMD_RESET_DEV
:
1637 VMW_CBPRN("Set: Reset device");
1641 case VMXNET3_CMD_QUIESCE_DEV
:
1642 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1643 vmxnet3_deactivate_device(s
);
1646 case VMXNET3_CMD_GET_CONF_INTR
:
1647 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1650 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1651 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1652 "adaptive ring info flags");
1655 case VMXNET3_CMD_GET_DID_LO
:
1656 VMW_CBPRN("Set: Get lower part of device ID");
1659 case VMXNET3_CMD_GET_DID_HI
:
1660 VMW_CBPRN("Set: Get upper part of device ID");
1663 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1664 VMW_CBPRN("Set: Get device extra info");
1668 VMW_CBPRN("Received unknown command: %" PRIx64
, cmd
);
1673 static uint64_t vmxnet3_get_command_status(VMXNET3State
*s
)
1677 switch (s
->last_command
) {
1678 case VMXNET3_CMD_ACTIVATE_DEV
:
1679 ret
= (s
->device_active
) ? 0 : 1;
1680 VMW_CFPRN("Device active: %" PRIx64
, ret
);
1683 case VMXNET3_CMD_RESET_DEV
:
1684 case VMXNET3_CMD_QUIESCE_DEV
:
1685 case VMXNET3_CMD_GET_QUEUE_STATUS
:
1686 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1690 case VMXNET3_CMD_GET_LINK
:
1691 ret
= s
->link_status_and_speed
;
1692 VMW_CFPRN("Link and speed: %" PRIx64
, ret
);
1695 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1696 ret
= vmxnet3_get_mac_low(&s
->perm_mac
);
1699 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1700 ret
= vmxnet3_get_mac_high(&s
->perm_mac
);
1703 case VMXNET3_CMD_GET_CONF_INTR
:
1704 ret
= vmxnet3_get_interrupt_config(s
);
1707 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1708 ret
= VMXNET3_DISABLE_ADAPTIVE_RING
;
1711 case VMXNET3_CMD_GET_DID_LO
:
1712 ret
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
1715 case VMXNET3_CMD_GET_DID_HI
:
1716 ret
= VMXNET3_DEVICE_REVISION
;
1720 VMW_WRPRN("Received request for unknown command: %x", s
->last_command
);
1728 static void vmxnet3_set_events(VMXNET3State
*s
, uint32_t val
)
1731 PCIDevice
*d
= PCI_DEVICE(s
);
1733 VMW_CBPRN("Setting events: 0x%x", val
);
1734 events
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, ecr
) | val
;
1735 VMXNET3_WRITE_DRV_SHARED32(d
, s
->drv_shmem
, ecr
, events
);
1738 static void vmxnet3_ack_events(VMXNET3State
*s
, uint32_t val
)
1740 PCIDevice
*d
= PCI_DEVICE(s
);
1743 VMW_CBPRN("Clearing events: 0x%x", val
);
1744 events
= VMXNET3_READ_DRV_SHARED32(d
, s
->drv_shmem
, ecr
) & ~val
;
1745 VMXNET3_WRITE_DRV_SHARED32(d
, s
->drv_shmem
, ecr
, events
);
1749 vmxnet3_io_bar1_write(void *opaque
,
1754 VMXNET3State
*s
= opaque
;
1757 /* Vmxnet3 Revision Report Selection */
1758 case VMXNET3_REG_VRRS
:
1759 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64
", size %d",
1763 /* UPT Version Report Selection */
1764 case VMXNET3_REG_UVRS
:
1765 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64
", size %d",
1769 /* Driver Shared Address Low */
1770 case VMXNET3_REG_DSAL
:
1771 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64
", size %d",
1774 * Guest driver will first write the low part of the shared
1775 * memory address. We save it to temp variable and set the
1776 * shared address only after we get the high part
1779 vmxnet3_deactivate_device(s
);
1781 s
->temp_shared_guest_driver_memory
= val
;
1785 /* Driver Shared Address High */
1786 case VMXNET3_REG_DSAH
:
1787 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64
", size %d",
1790 * Set the shared memory between guest driver and device.
1791 * We already should have low address part.
1793 s
->drv_shmem
= s
->temp_shared_guest_driver_memory
| (val
<< 32);
1797 case VMXNET3_REG_CMD
:
1798 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64
", size %d",
1800 vmxnet3_handle_command(s
, val
);
1803 /* MAC Address Low */
1804 case VMXNET3_REG_MACL
:
1805 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64
", size %d",
1810 /* MAC Address High */
1811 case VMXNET3_REG_MACH
:
1812 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64
", size %d",
1814 vmxnet3_set_variable_mac(s
, val
, s
->temp_mac
);
1817 /* Interrupt Cause Register */
1818 case VMXNET3_REG_ICR
:
1819 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64
", size %d",
1821 qemu_log_mask(LOG_GUEST_ERROR
,
1822 "%s: write to read-only register VMXNET3_REG_ICR\n",
1826 /* Event Cause Register */
1827 case VMXNET3_REG_ECR
:
1828 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64
", size %d",
1830 vmxnet3_ack_events(s
, val
);
1834 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64
"] = %" PRIx64
", size %d",
1841 vmxnet3_io_bar1_read(void *opaque
, hwaddr addr
, unsigned size
)
1843 VMXNET3State
*s
= opaque
;
1847 /* Vmxnet3 Revision Report Selection */
1848 case VMXNET3_REG_VRRS
:
1849 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size
);
1850 ret
= VMXNET3_DEVICE_REVISION
;
1853 /* UPT Version Report Selection */
1854 case VMXNET3_REG_UVRS
:
1855 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size
);
1856 ret
= VMXNET3_UPT_REVISION
;
1860 case VMXNET3_REG_CMD
:
1861 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size
);
1862 ret
= vmxnet3_get_command_status(s
);
1865 /* MAC Address Low */
1866 case VMXNET3_REG_MACL
:
1867 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size
);
1868 ret
= vmxnet3_get_mac_low(&s
->conf
.macaddr
);
1871 /* MAC Address High */
1872 case VMXNET3_REG_MACH
:
1873 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size
);
1874 ret
= vmxnet3_get_mac_high(&s
->conf
.macaddr
);
1878 * Interrupt Cause Register
1879 * Used for legacy interrupts only so interrupt index always 0
1881 case VMXNET3_REG_ICR
:
1882 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size
);
1883 if (vmxnet3_interrupt_asserted(s
, 0)) {
1884 vmxnet3_clear_interrupt(s
, 0);
1892 VMW_CBPRN("Unknown read BAR1[%" PRIx64
"], %d bytes", addr
, size
);
1900 vmxnet3_can_receive(NetClientState
*nc
)
1902 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1903 return s
->device_active
&&
1904 VMXNET_FLAG_IS_SET(s
->link_status_and_speed
, VMXNET3_LINK_STATUS_UP
);
1908 vmxnet3_is_registered_vlan(VMXNET3State
*s
, const void *data
)
1910 uint16_t vlan_tag
= eth_get_pkt_tci(data
) & VLAN_VID_MASK
;
1911 if (IS_SPECIAL_VLAN_ID(vlan_tag
)) {
1915 return VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, vlan_tag
);
1919 vmxnet3_is_allowed_mcast_group(VMXNET3State
*s
, const uint8_t *group_mac
)
1922 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1923 if (!memcmp(group_mac
, s
->mcast_list
[i
].a
, sizeof(s
->mcast_list
[i
]))) {
1931 vmxnet3_rx_filter_may_indicate(VMXNET3State
*s
, const void *data
,
1934 struct eth_header
*ehdr
= PKT_GET_ETH_HDR(data
);
1936 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_PROMISC
)) {
1940 if (!vmxnet3_is_registered_vlan(s
, data
)) {
1944 switch (net_rx_pkt_get_packet_type(s
->rx_pkt
)) {
1946 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_UCAST
)) {
1949 if (memcmp(s
->conf
.macaddr
.a
, ehdr
->h_dest
, ETH_ALEN
)) {
1955 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_BCAST
)) {
1961 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_ALL_MULTI
)) {
1964 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_MCAST
)) {
1967 if (!vmxnet3_is_allowed_mcast_group(s
, ehdr
->h_dest
)) {
1973 g_assert_not_reached();
1980 vmxnet3_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
1982 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1983 size_t bytes_indicated
;
1985 if (!vmxnet3_can_receive(nc
)) {
1986 VMW_PKPRN("Cannot receive now");
1990 if (s
->peer_has_vhdr
) {
1991 net_rx_pkt_set_vhdr(s
->rx_pkt
, (struct virtio_net_hdr
*)buf
);
1992 buf
+= sizeof(struct virtio_net_hdr
);
1993 size
-= sizeof(struct virtio_net_hdr
);
1996 net_rx_pkt_set_packet_type(s
->rx_pkt
,
1997 get_eth_packet_type(PKT_GET_ETH_HDR(buf
)));
1999 if (vmxnet3_rx_filter_may_indicate(s
, buf
, size
)) {
2000 struct iovec iov
= {
2001 .iov_base
= (void *)buf
,
2005 net_rx_pkt_set_protocols(s
->rx_pkt
, &iov
, 1, 0);
2006 vmxnet3_rx_need_csum_calculate(s
->rx_pkt
, buf
, size
);
2007 net_rx_pkt_attach_data(s
->rx_pkt
, buf
, size
, s
->rx_vlan_stripping
);
2008 bytes_indicated
= vmxnet3_indicate_packet(s
) ? size
: -1;
2009 if (bytes_indicated
< size
) {
2010 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated
, size
);
2013 VMW_PKPRN("Packet dropped by RX filter");
2014 bytes_indicated
= size
;
2018 assert(bytes_indicated
!= 0);
2019 return bytes_indicated
;
2022 static void vmxnet3_set_link_status(NetClientState
*nc
)
2024 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2026 if (nc
->link_down
) {
2027 s
->link_status_and_speed
&= ~VMXNET3_LINK_STATUS_UP
;
2029 s
->link_status_and_speed
|= VMXNET3_LINK_STATUS_UP
;
2032 vmxnet3_set_events(s
, VMXNET3_ECR_LINK
);
2033 vmxnet3_trigger_interrupt(s
, s
->event_int_idx
);
2036 static NetClientInfo net_vmxnet3_info
= {
2037 .type
= NET_CLIENT_DRIVER_NIC
,
2038 .size
= sizeof(NICState
),
2039 .receive
= vmxnet3_receive
,
2040 .link_status_changed
= vmxnet3_set_link_status
,
2043 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State
*s
)
2045 NetClientState
*nc
= qemu_get_queue(s
->nic
);
2047 if (qemu_has_vnet_hdr(nc
->peer
)) {
2054 static void vmxnet3_net_uninit(VMXNET3State
*s
)
2056 g_free(s
->mcast_list
);
2057 vmxnet3_deactivate_device(s
);
2058 qemu_del_nic(s
->nic
);
2061 static void vmxnet3_net_init(VMXNET3State
*s
)
2063 DeviceState
*d
= DEVICE(s
);
2065 VMW_CBPRN("vmxnet3_net_init called...");
2067 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
2069 /* Windows guest will query the address that was set on init */
2070 memcpy(&s
->perm_mac
.a
, &s
->conf
.macaddr
.a
, sizeof(s
->perm_mac
.a
));
2072 s
->mcast_list
= NULL
;
2073 s
->mcast_list_len
= 0;
2075 s
->link_status_and_speed
= VMXNET3_LINK_SPEED
| VMXNET3_LINK_STATUS_UP
;
2077 VMW_CFPRN("Permanent MAC: " MAC_FMT
, MAC_ARG(s
->perm_mac
.a
));
2079 s
->nic
= qemu_new_nic(&net_vmxnet3_info
, &s
->conf
,
2080 object_get_typename(OBJECT(s
)),
2081 d
->id
, &d
->mem_reentrancy_guard
, s
);
2083 s
->peer_has_vhdr
= vmxnet3_peer_has_vnet_hdr(s
);
2085 s
->skip_current_tx_pkt
= false;
2088 s
->rx_vlan_stripping
= false;
2089 s
->lro_supported
= false;
2091 if (s
->peer_has_vhdr
) {
2092 qemu_set_vnet_hdr_len(qemu_get_queue(s
->nic
)->peer
,
2093 sizeof(struct virtio_net_hdr
));
2096 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
2100 vmxnet3_unuse_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2102 PCIDevice
*d
= PCI_DEVICE(s
);
2104 for (i
= 0; i
< num_vectors
; i
++) {
2105 msix_vector_unuse(d
, i
);
2110 vmxnet3_use_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2112 PCIDevice
*d
= PCI_DEVICE(s
);
2114 for (i
= 0; i
< num_vectors
; i
++) {
2115 msix_vector_use(d
, i
);
2120 vmxnet3_init_msix(VMXNET3State
*s
)
2122 PCIDevice
*d
= PCI_DEVICE(s
);
2123 int res
= msix_init(d
, VMXNET3_MAX_INTRS
,
2125 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_TABLE
,
2127 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_PBA(s
),
2128 VMXNET3_MSIX_OFFSET(s
), NULL
);
2131 VMW_WRPRN("Failed to initialize MSI-X, error %d", res
);
2132 s
->msix_used
= false;
2134 vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2135 s
->msix_used
= true;
2137 return s
->msix_used
;
2141 vmxnet3_cleanup_msix(VMXNET3State
*s
)
2143 PCIDevice
*d
= PCI_DEVICE(s
);
2146 vmxnet3_unuse_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2147 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2152 vmxnet3_cleanup_msi(VMXNET3State
*s
)
2154 PCIDevice
*d
= PCI_DEVICE(s
);
2159 static const MemoryRegionOps b0_ops
= {
2160 .read
= vmxnet3_io_bar0_read
,
2161 .write
= vmxnet3_io_bar0_write
,
2162 .endianness
= DEVICE_LITTLE_ENDIAN
,
2164 .min_access_size
= 4,
2165 .max_access_size
= 4,
2169 static const MemoryRegionOps b1_ops
= {
2170 .read
= vmxnet3_io_bar1_read
,
2171 .write
= vmxnet3_io_bar1_write
,
2172 .endianness
= DEVICE_LITTLE_ENDIAN
,
2174 .min_access_size
= 4,
2175 .max_access_size
= 4,
2179 static uint64_t vmxnet3_device_serial_num(VMXNET3State
*s
)
2181 uint64_t dsn_payload
;
2182 uint8_t *dsnp
= (uint8_t *)&dsn_payload
;
2185 dsnp
[1] = s
->conf
.macaddr
.a
[3];
2186 dsnp
[2] = s
->conf
.macaddr
.a
[4];
2187 dsnp
[3] = s
->conf
.macaddr
.a
[5];
2188 dsnp
[4] = s
->conf
.macaddr
.a
[0];
2189 dsnp
[5] = s
->conf
.macaddr
.a
[1];
2190 dsnp
[6] = s
->conf
.macaddr
.a
[2];
2196 #define VMXNET3_USE_64BIT (true)
2197 #define VMXNET3_PER_VECTOR_MASK (false)
2199 static void vmxnet3_pci_realize(PCIDevice
*pci_dev
, Error
**errp
)
2201 VMXNET3State
*s
= VMXNET3(pci_dev
);
2204 VMW_CBPRN("Starting init...");
2206 memory_region_init_io(&s
->bar0
, OBJECT(s
), &b0_ops
, s
,
2207 "vmxnet3-b0", VMXNET3_PT_REG_SIZE
);
2208 pci_register_bar(pci_dev
, VMXNET3_BAR0_IDX
,
2209 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
2211 memory_region_init_io(&s
->bar1
, OBJECT(s
), &b1_ops
, s
,
2212 "vmxnet3-b1", VMXNET3_VD_REG_SIZE
);
2213 pci_register_bar(pci_dev
, VMXNET3_BAR1_IDX
,
2214 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
2216 memory_region_init(&s
->msix_bar
, OBJECT(s
), "vmxnet3-msix-bar",
2217 VMXNET3_MSIX_BAR_SIZE
);
2218 pci_register_bar(pci_dev
, VMXNET3_MSIX_BAR_IDX
,
2219 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->msix_bar
);
2221 vmxnet3_reset_interrupt_states(s
);
2223 /* Interrupt pin A */
2224 pci_dev
->config
[PCI_INTERRUPT_PIN
] = 0x01;
2226 ret
= msi_init(pci_dev
, VMXNET3_MSI_OFFSET(s
), VMXNET3_MAX_NMSIX_INTRS
,
2227 VMXNET3_USE_64BIT
, VMXNET3_PER_VECTOR_MASK
, NULL
);
2228 /* Any error other than -ENOTSUP(board's MSI support is broken)
2229 * is a programming error. Fall back to INTx silently on -ENOTSUP */
2230 assert(!ret
|| ret
== -ENOTSUP
);
2232 if (!vmxnet3_init_msix(s
)) {
2233 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2236 vmxnet3_net_init(s
);
2238 if (pci_is_express(pci_dev
)) {
2239 if (pci_bus_is_express(pci_get_bus(pci_dev
))) {
2240 pcie_endpoint_cap_init(pci_dev
, VMXNET3_EXP_EP_OFFSET
);
2243 pcie_dev_ser_num_init(pci_dev
, VMXNET3_DSN_OFFSET
,
2244 vmxnet3_device_serial_num(s
));
2248 static void vmxnet3_instance_init(Object
*obj
)
2250 VMXNET3State
*s
= VMXNET3(obj
);
2251 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
2252 "bootindex", "/ethernet-phy@0",
2256 static void vmxnet3_pci_uninit(PCIDevice
*pci_dev
)
2258 VMXNET3State
*s
= VMXNET3(pci_dev
);
2260 VMW_CBPRN("Starting uninit...");
2262 vmxnet3_net_uninit(s
);
2264 vmxnet3_cleanup_msix(s
);
2266 vmxnet3_cleanup_msi(s
);
2269 static void vmxnet3_qdev_reset(DeviceState
*dev
)
2271 PCIDevice
*d
= PCI_DEVICE(dev
);
2272 VMXNET3State
*s
= VMXNET3(d
);
2274 VMW_CBPRN("Starting QDEV reset...");
2278 static bool vmxnet3_mc_list_needed(void *opaque
)
2283 static int vmxnet3_mcast_list_pre_load(void *opaque
)
2285 VMXNET3State
*s
= opaque
;
2287 s
->mcast_list
= g_malloc(s
->mcast_list_buff_size
);
2293 static int vmxnet3_pre_save(void *opaque
)
2295 VMXNET3State
*s
= opaque
;
2297 s
->mcast_list_buff_size
= s
->mcast_list_len
* sizeof(MACAddr
);
2302 static const VMStateDescription vmxstate_vmxnet3_mcast_list
= {
2303 .name
= "vmxnet3/mcast_list",
2305 .minimum_version_id
= 1,
2306 .pre_load
= vmxnet3_mcast_list_pre_load
,
2307 .needed
= vmxnet3_mc_list_needed
,
2308 .fields
= (const VMStateField
[]) {
2309 VMSTATE_VBUFFER_UINT32(mcast_list
, VMXNET3State
, 0, NULL
,
2310 mcast_list_buff_size
),
2311 VMSTATE_END_OF_LIST()
2315 static const VMStateDescription vmstate_vmxnet3_ring
= {
2316 .name
= "vmxnet3-ring",
2318 .fields
= (const VMStateField
[]) {
2319 VMSTATE_UINT64(pa
, Vmxnet3Ring
),
2320 VMSTATE_UINT32(size
, Vmxnet3Ring
),
2321 VMSTATE_UINT32(cell_size
, Vmxnet3Ring
),
2322 VMSTATE_UINT32(next
, Vmxnet3Ring
),
2323 VMSTATE_UINT8(gen
, Vmxnet3Ring
),
2324 VMSTATE_END_OF_LIST()
2328 static const VMStateDescription vmstate_vmxnet3_tx_stats
= {
2329 .name
= "vmxnet3-tx-stats",
2331 .fields
= (const VMStateField
[]) {
2332 VMSTATE_UINT64(TSOPktsTxOK
, struct UPT1_TxStats
),
2333 VMSTATE_UINT64(TSOBytesTxOK
, struct UPT1_TxStats
),
2334 VMSTATE_UINT64(ucastPktsTxOK
, struct UPT1_TxStats
),
2335 VMSTATE_UINT64(ucastBytesTxOK
, struct UPT1_TxStats
),
2336 VMSTATE_UINT64(mcastPktsTxOK
, struct UPT1_TxStats
),
2337 VMSTATE_UINT64(mcastBytesTxOK
, struct UPT1_TxStats
),
2338 VMSTATE_UINT64(bcastPktsTxOK
, struct UPT1_TxStats
),
2339 VMSTATE_UINT64(bcastBytesTxOK
, struct UPT1_TxStats
),
2340 VMSTATE_UINT64(pktsTxError
, struct UPT1_TxStats
),
2341 VMSTATE_UINT64(pktsTxDiscard
, struct UPT1_TxStats
),
2342 VMSTATE_END_OF_LIST()
2346 static const VMStateDescription vmstate_vmxnet3_txq_descr
= {
2347 .name
= "vmxnet3-txq-descr",
2349 .fields
= (const VMStateField
[]) {
2350 VMSTATE_STRUCT(tx_ring
, Vmxnet3TxqDescr
, 0, vmstate_vmxnet3_ring
,
2352 VMSTATE_STRUCT(comp_ring
, Vmxnet3TxqDescr
, 0, vmstate_vmxnet3_ring
,
2354 VMSTATE_UINT8(intr_idx
, Vmxnet3TxqDescr
),
2355 VMSTATE_UINT64(tx_stats_pa
, Vmxnet3TxqDescr
),
2356 VMSTATE_STRUCT(txq_stats
, Vmxnet3TxqDescr
, 0, vmstate_vmxnet3_tx_stats
,
2357 struct UPT1_TxStats
),
2358 VMSTATE_END_OF_LIST()
2362 static const VMStateDescription vmstate_vmxnet3_rx_stats
= {
2363 .name
= "vmxnet3-rx-stats",
2365 .fields
= (const VMStateField
[]) {
2366 VMSTATE_UINT64(LROPktsRxOK
, struct UPT1_RxStats
),
2367 VMSTATE_UINT64(LROBytesRxOK
, struct UPT1_RxStats
),
2368 VMSTATE_UINT64(ucastPktsRxOK
, struct UPT1_RxStats
),
2369 VMSTATE_UINT64(ucastBytesRxOK
, struct UPT1_RxStats
),
2370 VMSTATE_UINT64(mcastPktsRxOK
, struct UPT1_RxStats
),
2371 VMSTATE_UINT64(mcastBytesRxOK
, struct UPT1_RxStats
),
2372 VMSTATE_UINT64(bcastPktsRxOK
, struct UPT1_RxStats
),
2373 VMSTATE_UINT64(bcastBytesRxOK
, struct UPT1_RxStats
),
2374 VMSTATE_UINT64(pktsRxOutOfBuf
, struct UPT1_RxStats
),
2375 VMSTATE_UINT64(pktsRxError
, struct UPT1_RxStats
),
2376 VMSTATE_END_OF_LIST()
2380 static const VMStateDescription vmstate_vmxnet3_rxq_descr
= {
2381 .name
= "vmxnet3-rxq-descr",
2383 .fields
= (const VMStateField
[]) {
2384 VMSTATE_STRUCT_ARRAY(rx_ring
, Vmxnet3RxqDescr
,
2385 VMXNET3_RX_RINGS_PER_QUEUE
, 0,
2386 vmstate_vmxnet3_ring
, Vmxnet3Ring
),
2387 VMSTATE_STRUCT(comp_ring
, Vmxnet3RxqDescr
, 0, vmstate_vmxnet3_ring
,
2389 VMSTATE_UINT8(intr_idx
, Vmxnet3RxqDescr
),
2390 VMSTATE_UINT64(rx_stats_pa
, Vmxnet3RxqDescr
),
2391 VMSTATE_STRUCT(rxq_stats
, Vmxnet3RxqDescr
, 0, vmstate_vmxnet3_rx_stats
,
2392 struct UPT1_RxStats
),
2393 VMSTATE_END_OF_LIST()
2397 static int vmxnet3_post_load(void *opaque
, int version_id
)
2399 VMXNET3State
*s
= opaque
;
2401 net_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
);
2402 net_rx_pkt_init(&s
->rx_pkt
);
2405 vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2408 if (!vmxnet3_validate_queues(s
)) {
2411 vmxnet3_validate_interrupts(s
);
2416 static const VMStateDescription vmstate_vmxnet3_int_state
= {
2417 .name
= "vmxnet3-int-state",
2419 .fields
= (const VMStateField
[]) {
2420 VMSTATE_BOOL(is_masked
, Vmxnet3IntState
),
2421 VMSTATE_BOOL(is_pending
, Vmxnet3IntState
),
2422 VMSTATE_BOOL(is_asserted
, Vmxnet3IntState
),
2423 VMSTATE_END_OF_LIST()
2427 static const VMStateDescription vmstate_vmxnet3
= {
2430 .minimum_version_id
= 1,
2431 .pre_save
= vmxnet3_pre_save
,
2432 .post_load
= vmxnet3_post_load
,
2433 .fields
= (const VMStateField
[]) {
2434 VMSTATE_PCI_DEVICE(parent_obj
, VMXNET3State
),
2435 VMSTATE_MSIX(parent_obj
, VMXNET3State
),
2436 VMSTATE_BOOL(rx_packets_compound
, VMXNET3State
),
2437 VMSTATE_BOOL(rx_vlan_stripping
, VMXNET3State
),
2438 VMSTATE_BOOL(lro_supported
, VMXNET3State
),
2439 VMSTATE_UINT32(rx_mode
, VMXNET3State
),
2440 VMSTATE_UINT32(mcast_list_len
, VMXNET3State
),
2441 VMSTATE_UINT32(mcast_list_buff_size
, VMXNET3State
),
2442 VMSTATE_UINT32_ARRAY(vlan_table
, VMXNET3State
, VMXNET3_VFT_SIZE
),
2443 VMSTATE_UINT32(mtu
, VMXNET3State
),
2444 VMSTATE_UINT16(max_rx_frags
, VMXNET3State
),
2445 VMSTATE_UINT32(max_tx_frags
, VMXNET3State
),
2446 VMSTATE_UINT8(event_int_idx
, VMXNET3State
),
2447 VMSTATE_BOOL(auto_int_masking
, VMXNET3State
),
2448 VMSTATE_UINT8(txq_num
, VMXNET3State
),
2449 VMSTATE_UINT8(rxq_num
, VMXNET3State
),
2450 VMSTATE_UINT32(device_active
, VMXNET3State
),
2451 VMSTATE_UINT32(last_command
, VMXNET3State
),
2452 VMSTATE_UINT32(link_status_and_speed
, VMXNET3State
),
2453 VMSTATE_UINT32(temp_mac
, VMXNET3State
),
2454 VMSTATE_UINT64(drv_shmem
, VMXNET3State
),
2455 VMSTATE_UINT64(temp_shared_guest_driver_memory
, VMXNET3State
),
2457 VMSTATE_STRUCT_ARRAY(txq_descr
, VMXNET3State
,
2458 VMXNET3_DEVICE_MAX_TX_QUEUES
, 0, vmstate_vmxnet3_txq_descr
,
2460 VMSTATE_STRUCT_ARRAY(rxq_descr
, VMXNET3State
,
2461 VMXNET3_DEVICE_MAX_RX_QUEUES
, 0, vmstate_vmxnet3_rxq_descr
,
2463 VMSTATE_STRUCT_ARRAY(interrupt_states
, VMXNET3State
,
2464 VMXNET3_MAX_INTRS
, 0, vmstate_vmxnet3_int_state
,
2467 VMSTATE_END_OF_LIST()
2469 .subsections
= (const VMStateDescription
* const []) {
2470 &vmxstate_vmxnet3_mcast_list
,
2475 static Property vmxnet3_properties
[] = {
2476 DEFINE_NIC_PROPERTIES(VMXNET3State
, conf
),
2477 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State
, compat_flags
,
2478 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT
, false),
2479 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State
, compat_flags
,
2480 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT
, false),
2481 DEFINE_PROP_END_OF_LIST(),
2484 static void vmxnet3_realize(DeviceState
*qdev
, Error
**errp
)
2486 VMXNET3Class
*vc
= VMXNET3_DEVICE_GET_CLASS(qdev
);
2487 PCIDevice
*pci_dev
= PCI_DEVICE(qdev
);
2488 VMXNET3State
*s
= VMXNET3(qdev
);
2490 if (!(s
->compat_flags
& VMXNET3_COMPAT_FLAG_DISABLE_PCIE
)) {
2491 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2494 vc
->parent_dc_realize(qdev
, errp
);
2497 static void vmxnet3_class_init(ObjectClass
*class, void *data
)
2499 DeviceClass
*dc
= DEVICE_CLASS(class);
2500 PCIDeviceClass
*c
= PCI_DEVICE_CLASS(class);
2501 VMXNET3Class
*vc
= VMXNET3_DEVICE_CLASS(class);
2503 c
->realize
= vmxnet3_pci_realize
;
2504 c
->exit
= vmxnet3_pci_uninit
;
2505 c
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
2506 c
->device_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2507 c
->revision
= PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION
;
2508 c
->romfile
= "efi-vmxnet3.rom";
2509 c
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2510 c
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
2511 c
->subsystem_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2512 device_class_set_parent_realize(dc
, vmxnet3_realize
,
2513 &vc
->parent_dc_realize
);
2514 dc
->desc
= "VMWare Paravirtualized Ethernet v3";
2515 dc
->reset
= vmxnet3_qdev_reset
;
2516 dc
->vmsd
= &vmstate_vmxnet3
;
2517 device_class_set_props(dc
, vmxnet3_properties
);
2518 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
2521 static const TypeInfo vmxnet3_info
= {
2522 .name
= TYPE_VMXNET3
,
2523 .parent
= TYPE_PCI_DEVICE
,
2524 .class_size
= sizeof(VMXNET3Class
),
2525 .instance_size
= sizeof(VMXNET3State
),
2526 .class_init
= vmxnet3_class_init
,
2527 .instance_init
= vmxnet3_instance_init
,
2528 .interfaces
= (InterfaceInfo
[]) {
2529 { INTERFACE_PCIE_DEVICE
},
2530 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
2535 static void vmxnet3_register_types(void)
2537 VMW_CBPRN("vmxnet3_register_types called...");
2538 type_register_static(&vmxnet3_info
);
2541 type_init(vmxnet3_register_types
)