4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
26 #include "internals.h"
27 #include "time_helper.h"
28 #include "exec/exec-all.h"
29 #include "qapi/error.h"
30 #include "qemu/error-report.h"
31 #include "hw/qdev-properties.h"
32 #include "migration/vmstate.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "sysemu/kvm.h"
35 #include "kvm_riscv.h"
37 /* RISC-V CPU definitions */
39 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
40 (QEMU_VERSION_MINOR << 8) | \
42 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID
44 static const char riscv_single_letter_exts
[] = "IEMAFDQCPVH";
50 int ext_enable_offset
;
53 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \
54 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
57 * Here are the ordering rules of extension naming defined by RISC-V
59 * 1. All extensions should be separated from other multi-letter extensions
61 * 2. The first letter following the 'Z' conventionally indicates the most
62 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
63 * If multiple 'Z' extensions are named, they should be ordered first
64 * by category, then alphabetically within a category.
65 * 3. Standard supervisor-level extensions (starts with 'S') should be
66 * listed after standard unprivileged extensions. If multiple
67 * supervisor-level extensions are listed, they should be ordered
69 * 4. Non-standard extensions (starts with 'X') must be listed after all
70 * standard extensions. They must be separated from other multi-letter
71 * extensions by an underscore.
73 static const struct isa_ext_data isa_edata_arr
[] = {
74 ISA_EXT_DATA_ENTRY(h
, false, PRIV_VERSION_1_12_0
, ext_h
),
75 ISA_EXT_DATA_ENTRY(v
, false, PRIV_VERSION_1_12_0
, ext_v
),
76 ISA_EXT_DATA_ENTRY(zicsr
, true, PRIV_VERSION_1_10_0
, ext_icsr
),
77 ISA_EXT_DATA_ENTRY(zifencei
, true, PRIV_VERSION_1_10_0
, ext_ifencei
),
78 ISA_EXT_DATA_ENTRY(zihintpause
, true, PRIV_VERSION_1_10_0
, ext_zihintpause
),
79 ISA_EXT_DATA_ENTRY(zawrs
, true, PRIV_VERSION_1_12_0
, ext_zawrs
),
80 ISA_EXT_DATA_ENTRY(zfh
, true, PRIV_VERSION_1_12_0
, ext_zfh
),
81 ISA_EXT_DATA_ENTRY(zfhmin
, true, PRIV_VERSION_1_12_0
, ext_zfhmin
),
82 ISA_EXT_DATA_ENTRY(zfinx
, true, PRIV_VERSION_1_12_0
, ext_zfinx
),
83 ISA_EXT_DATA_ENTRY(zdinx
, true, PRIV_VERSION_1_12_0
, ext_zdinx
),
84 ISA_EXT_DATA_ENTRY(zba
, true, PRIV_VERSION_1_12_0
, ext_zba
),
85 ISA_EXT_DATA_ENTRY(zbb
, true, PRIV_VERSION_1_12_0
, ext_zbb
),
86 ISA_EXT_DATA_ENTRY(zbc
, true, PRIV_VERSION_1_12_0
, ext_zbc
),
87 ISA_EXT_DATA_ENTRY(zbkb
, true, PRIV_VERSION_1_12_0
, ext_zbkb
),
88 ISA_EXT_DATA_ENTRY(zbkc
, true, PRIV_VERSION_1_12_0
, ext_zbkc
),
89 ISA_EXT_DATA_ENTRY(zbkx
, true, PRIV_VERSION_1_12_0
, ext_zbkx
),
90 ISA_EXT_DATA_ENTRY(zbs
, true, PRIV_VERSION_1_12_0
, ext_zbs
),
91 ISA_EXT_DATA_ENTRY(zk
, true, PRIV_VERSION_1_12_0
, ext_zk
),
92 ISA_EXT_DATA_ENTRY(zkn
, true, PRIV_VERSION_1_12_0
, ext_zkn
),
93 ISA_EXT_DATA_ENTRY(zknd
, true, PRIV_VERSION_1_12_0
, ext_zknd
),
94 ISA_EXT_DATA_ENTRY(zkne
, true, PRIV_VERSION_1_12_0
, ext_zkne
),
95 ISA_EXT_DATA_ENTRY(zknh
, true, PRIV_VERSION_1_12_0
, ext_zknh
),
96 ISA_EXT_DATA_ENTRY(zkr
, true, PRIV_VERSION_1_12_0
, ext_zkr
),
97 ISA_EXT_DATA_ENTRY(zks
, true, PRIV_VERSION_1_12_0
, ext_zks
),
98 ISA_EXT_DATA_ENTRY(zksed
, true, PRIV_VERSION_1_12_0
, ext_zksed
),
99 ISA_EXT_DATA_ENTRY(zksh
, true, PRIV_VERSION_1_12_0
, ext_zksh
),
100 ISA_EXT_DATA_ENTRY(zkt
, true, PRIV_VERSION_1_12_0
, ext_zkt
),
101 ISA_EXT_DATA_ENTRY(zve32f
, true, PRIV_VERSION_1_12_0
, ext_zve32f
),
102 ISA_EXT_DATA_ENTRY(zve64f
, true, PRIV_VERSION_1_12_0
, ext_zve64f
),
103 ISA_EXT_DATA_ENTRY(zhinx
, true, PRIV_VERSION_1_12_0
, ext_zhinx
),
104 ISA_EXT_DATA_ENTRY(zhinxmin
, true, PRIV_VERSION_1_12_0
, ext_zhinxmin
),
105 ISA_EXT_DATA_ENTRY(smaia
, true, PRIV_VERSION_1_12_0
, ext_smaia
),
106 ISA_EXT_DATA_ENTRY(ssaia
, true, PRIV_VERSION_1_12_0
, ext_ssaia
),
107 ISA_EXT_DATA_ENTRY(sscofpmf
, true, PRIV_VERSION_1_12_0
, ext_sscofpmf
),
108 ISA_EXT_DATA_ENTRY(sstc
, true, PRIV_VERSION_1_12_0
, ext_sstc
),
109 ISA_EXT_DATA_ENTRY(svinval
, true, PRIV_VERSION_1_12_0
, ext_svinval
),
110 ISA_EXT_DATA_ENTRY(svnapot
, true, PRIV_VERSION_1_12_0
, ext_svnapot
),
111 ISA_EXT_DATA_ENTRY(svpbmt
, true, PRIV_VERSION_1_12_0
, ext_svpbmt
),
112 ISA_EXT_DATA_ENTRY(xventanacondops
, true, PRIV_VERSION_1_12_0
, ext_XVentanaCondOps
),
115 static bool isa_ext_is_enabled(RISCVCPU
*cpu
,
116 const struct isa_ext_data
*edata
)
118 bool *ext_enabled
= (void *)&cpu
->cfg
+ edata
->ext_enable_offset
;
123 static void isa_ext_update_enabled(RISCVCPU
*cpu
,
124 const struct isa_ext_data
*edata
, bool en
)
126 bool *ext_enabled
= (void *)&cpu
->cfg
+ edata
->ext_enable_offset
;
131 const char * const riscv_int_regnames
[] = {
132 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
133 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
134 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
135 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
136 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
139 const char * const riscv_int_regnamesh
[] = {
140 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
141 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
142 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
143 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
144 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
145 "x30h/t5h", "x31h/t6h"
148 const char * const riscv_fpr_regnames
[] = {
149 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
150 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
151 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
152 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
153 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
154 "f30/ft10", "f31/ft11"
157 static const char * const riscv_excp_names
[] = {
160 "illegal_instruction",
178 "guest_exec_page_fault",
179 "guest_load_page_fault",
181 "guest_store_page_fault",
184 static const char * const riscv_intr_names
[] = {
203 static void register_cpu_props(DeviceState
*dev
);
205 const char *riscv_cpu_get_trap_name(target_ulong cause
, bool async
)
208 return (cause
< ARRAY_SIZE(riscv_intr_names
)) ?
209 riscv_intr_names
[cause
] : "(unknown)";
211 return (cause
< ARRAY_SIZE(riscv_excp_names
)) ?
212 riscv_excp_names
[cause
] : "(unknown)";
216 static void set_misa(CPURISCVState
*env
, RISCVMXL mxl
, uint32_t ext
)
218 env
->misa_mxl_max
= env
->misa_mxl
= mxl
;
219 env
->misa_ext_mask
= env
->misa_ext
= ext
;
222 static void set_priv_version(CPURISCVState
*env
, int priv_ver
)
224 env
->priv_ver
= priv_ver
;
227 static void set_vext_version(CPURISCVState
*env
, int vext_ver
)
229 env
->vext_ver
= vext_ver
;
232 static void riscv_any_cpu_init(Object
*obj
)
234 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
235 #if defined(TARGET_RISCV32)
236 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
237 #elif defined(TARGET_RISCV64)
238 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVU
);
240 set_priv_version(env
, PRIV_VERSION_1_12_0
);
241 register_cpu_props(DEVICE(obj
));
244 #if defined(TARGET_RISCV64)
245 static void rv64_base_cpu_init(Object
*obj
)
247 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
248 /* We set this in the realise function */
249 set_misa(env
, MXL_RV64
, 0);
250 register_cpu_props(DEVICE(obj
));
251 /* Set latest version of privileged specification */
252 set_priv_version(env
, PRIV_VERSION_1_12_0
);
255 static void rv64_sifive_u_cpu_init(Object
*obj
)
257 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
258 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
259 register_cpu_props(DEVICE(obj
));
260 set_priv_version(env
, PRIV_VERSION_1_10_0
);
263 static void rv64_sifive_e_cpu_init(Object
*obj
)
265 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
266 RISCVCPU
*cpu
= RISCV_CPU(obj
);
268 set_misa(env
, MXL_RV64
, RVI
| RVM
| RVA
| RVC
| RVU
);
269 register_cpu_props(DEVICE(obj
));
270 set_priv_version(env
, PRIV_VERSION_1_10_0
);
271 cpu
->cfg
.mmu
= false;
274 static void rv128_base_cpu_init(Object
*obj
)
276 if (qemu_tcg_mttcg_enabled()) {
277 /* Missing 128-bit aligned atomics */
278 error_report("128-bit RISC-V currently does not work with Multi "
279 "Threaded TCG. Please use: -accel tcg,thread=single");
282 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
283 /* We set this in the realise function */
284 set_misa(env
, MXL_RV128
, 0);
285 register_cpu_props(DEVICE(obj
));
286 /* Set latest version of privileged specification */
287 set_priv_version(env
, PRIV_VERSION_1_12_0
);
290 static void rv32_base_cpu_init(Object
*obj
)
292 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
293 /* We set this in the realise function */
294 set_misa(env
, MXL_RV32
, 0);
295 register_cpu_props(DEVICE(obj
));
296 /* Set latest version of privileged specification */
297 set_priv_version(env
, PRIV_VERSION_1_12_0
);
300 static void rv32_sifive_u_cpu_init(Object
*obj
)
302 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
303 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
304 register_cpu_props(DEVICE(obj
));
305 set_priv_version(env
, PRIV_VERSION_1_10_0
);
308 static void rv32_sifive_e_cpu_init(Object
*obj
)
310 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
311 RISCVCPU
*cpu
= RISCV_CPU(obj
);
313 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVC
| RVU
);
314 register_cpu_props(DEVICE(obj
));
315 set_priv_version(env
, PRIV_VERSION_1_10_0
);
316 cpu
->cfg
.mmu
= false;
319 static void rv32_ibex_cpu_init(Object
*obj
)
321 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
322 RISCVCPU
*cpu
= RISCV_CPU(obj
);
324 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVC
| RVU
);
325 register_cpu_props(DEVICE(obj
));
326 set_priv_version(env
, PRIV_VERSION_1_11_0
);
327 cpu
->cfg
.mmu
= false;
328 cpu
->cfg
.epmp
= true;
331 static void rv32_imafcu_nommu_cpu_init(Object
*obj
)
333 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
334 RISCVCPU
*cpu
= RISCV_CPU(obj
);
336 set_misa(env
, MXL_RV32
, RVI
| RVM
| RVA
| RVF
| RVC
| RVU
);
337 register_cpu_props(DEVICE(obj
));
338 set_priv_version(env
, PRIV_VERSION_1_10_0
);
339 cpu
->cfg
.mmu
= false;
343 #if defined(CONFIG_KVM)
344 static void riscv_host_cpu_init(Object
*obj
)
346 CPURISCVState
*env
= &RISCV_CPU(obj
)->env
;
347 #if defined(TARGET_RISCV32)
348 set_misa(env
, MXL_RV32
, 0);
349 #elif defined(TARGET_RISCV64)
350 set_misa(env
, MXL_RV64
, 0);
352 register_cpu_props(DEVICE(obj
));
356 static ObjectClass
*riscv_cpu_class_by_name(const char *cpu_model
)
362 cpuname
= g_strsplit(cpu_model
, ",", 1);
363 typename
= g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname
[0]);
364 oc
= object_class_by_name(typename
);
367 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_RISCV_CPU
) ||
368 object_class_is_abstract(oc
)) {
374 static void riscv_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
376 RISCVCPU
*cpu
= RISCV_CPU(cs
);
377 CPURISCVState
*env
= &cpu
->env
;
380 #if !defined(CONFIG_USER_ONLY)
381 if (riscv_has_ext(env
, RVH
)) {
382 qemu_fprintf(f
, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env
));
385 qemu_fprintf(f
, " %s " TARGET_FMT_lx
"\n", "pc ", env
->pc
);
386 #ifndef CONFIG_USER_ONLY
388 static const int dump_csrs
[] = {
393 * CSR_SSTATUS is intentionally omitted here as its value
394 * can be figured out by looking at CSR_MSTATUS
429 for (int i
= 0; i
< ARRAY_SIZE(dump_csrs
); ++i
) {
430 int csrno
= dump_csrs
[i
];
431 target_ulong val
= 0;
432 RISCVException res
= riscv_csrrw_debug(env
, csrno
, &val
, 0, 0);
435 * Rely on the smode, hmode, etc, predicates within csr.c
436 * to do the filtering of the registers that are present.
438 if (res
== RISCV_EXCP_NONE
) {
439 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
"\n",
440 csr_ops
[csrno
].name
, val
);
446 for (i
= 0; i
< 32; i
++) {
447 qemu_fprintf(f
, " %-8s " TARGET_FMT_lx
,
448 riscv_int_regnames
[i
], env
->gpr
[i
]);
450 qemu_fprintf(f
, "\n");
453 if (flags
& CPU_DUMP_FPU
) {
454 for (i
= 0; i
< 32; i
++) {
455 qemu_fprintf(f
, " %-8s %016" PRIx64
,
456 riscv_fpr_regnames
[i
], env
->fpr
[i
]);
458 qemu_fprintf(f
, "\n");
464 static void riscv_cpu_set_pc(CPUState
*cs
, vaddr value
)
466 RISCVCPU
*cpu
= RISCV_CPU(cs
);
467 CPURISCVState
*env
= &cpu
->env
;
469 if (env
->xl
== MXL_RV32
) {
470 env
->pc
= (int32_t)value
;
476 static vaddr
riscv_cpu_get_pc(CPUState
*cs
)
478 RISCVCPU
*cpu
= RISCV_CPU(cs
);
479 CPURISCVState
*env
= &cpu
->env
;
481 /* Match cpu_get_tb_cpu_state. */
482 if (env
->xl
== MXL_RV32
) {
483 return env
->pc
& UINT32_MAX
;
488 static void riscv_cpu_synchronize_from_tb(CPUState
*cs
,
489 const TranslationBlock
*tb
)
491 RISCVCPU
*cpu
= RISCV_CPU(cs
);
492 CPURISCVState
*env
= &cpu
->env
;
493 RISCVMXL xl
= FIELD_EX32(tb
->flags
, TB_FLAGS
, XL
);
495 if (xl
== MXL_RV32
) {
496 env
->pc
= (int32_t)tb_pc(tb
);
502 static bool riscv_cpu_has_work(CPUState
*cs
)
504 #ifndef CONFIG_USER_ONLY
505 RISCVCPU
*cpu
= RISCV_CPU(cs
);
506 CPURISCVState
*env
= &cpu
->env
;
508 * Definition of the WFI instruction requires it to ignore the privilege
509 * mode and delegation registers, but respect individual enables
511 return riscv_cpu_all_pending(env
) != 0;
517 static void riscv_restore_state_to_opc(CPUState
*cs
,
518 const TranslationBlock
*tb
,
519 const uint64_t *data
)
521 RISCVCPU
*cpu
= RISCV_CPU(cs
);
522 CPURISCVState
*env
= &cpu
->env
;
523 RISCVMXL xl
= FIELD_EX32(tb
->flags
, TB_FLAGS
, XL
);
525 if (xl
== MXL_RV32
) {
526 env
->pc
= (int32_t)data
[0];
533 static void riscv_cpu_reset_hold(Object
*obj
)
535 #ifndef CONFIG_USER_ONLY
539 CPUState
*cs
= CPU(obj
);
540 RISCVCPU
*cpu
= RISCV_CPU(cs
);
541 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(cpu
);
542 CPURISCVState
*env
= &cpu
->env
;
544 if (mcc
->parent_phases
.hold
) {
545 mcc
->parent_phases
.hold(obj
);
547 #ifndef CONFIG_USER_ONLY
548 env
->misa_mxl
= env
->misa_mxl_max
;
550 env
->mstatus
&= ~(MSTATUS_MIE
| MSTATUS_MPRV
);
551 if (env
->misa_mxl
> MXL_RV32
) {
553 * The reset status of SXL/UXL is undefined, but mstatus is WARL
554 * and we must ensure that the value after init is valid for read.
556 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_SXL
, env
->misa_mxl
);
557 env
->mstatus
= set_field(env
->mstatus
, MSTATUS64_UXL
, env
->misa_mxl
);
558 if (riscv_has_ext(env
, RVH
)) {
559 env
->vsstatus
= set_field(env
->vsstatus
,
560 MSTATUS64_SXL
, env
->misa_mxl
);
561 env
->vsstatus
= set_field(env
->vsstatus
,
562 MSTATUS64_UXL
, env
->misa_mxl
);
563 env
->mstatus_hs
= set_field(env
->mstatus_hs
,
564 MSTATUS64_SXL
, env
->misa_mxl
);
565 env
->mstatus_hs
= set_field(env
->mstatus_hs
,
566 MSTATUS64_UXL
, env
->misa_mxl
);
570 env
->miclaim
= MIP_SGEIP
;
571 env
->pc
= env
->resetvec
;
573 env
->two_stage_lookup
= false;
575 /* Initialized default priorities of local interrupts. */
576 for (i
= 0; i
< ARRAY_SIZE(env
->miprio
); i
++) {
577 iprio
= riscv_cpu_default_priority(i
);
578 env
->miprio
[i
] = (i
== IRQ_M_EXT
) ? 0 : iprio
;
579 env
->siprio
[i
] = (i
== IRQ_S_EXT
) ? 0 : iprio
;
583 while (!riscv_cpu_hviprio_index2irq(i
, &irq
, &rdzero
)) {
585 env
->hviprio
[irq
] = env
->miprio
[irq
];
589 /* mmte is supposed to have pm.current hardwired to 1 */
590 env
->mmte
|= (PM_EXT_INITIAL
| MMTE_M_PM_CURRENT
);
592 env
->xl
= riscv_cpu_mxl(env
);
593 riscv_cpu_update_mask(env
);
594 cs
->exception_index
= RISCV_EXCP_NONE
;
596 set_default_nan_mode(1, &env
->fp_status
);
598 #ifndef CONFIG_USER_ONLY
599 if (riscv_feature(env
, RISCV_FEATURE_DEBUG
)) {
600 riscv_trigger_init(env
);
604 kvm_riscv_reset_vcpu(cpu
);
609 static void riscv_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
611 RISCVCPU
*cpu
= RISCV_CPU(s
);
613 switch (riscv_cpu_mxl(&cpu
->env
)) {
615 info
->print_insn
= print_insn_riscv32
;
618 info
->print_insn
= print_insn_riscv64
;
621 info
->print_insn
= print_insn_riscv128
;
624 g_assert_not_reached();
628 static void riscv_cpu_realize(DeviceState
*dev
, Error
**errp
)
630 CPUState
*cs
= CPU(dev
);
631 RISCVCPU
*cpu
= RISCV_CPU(dev
);
632 CPURISCVState
*env
= &cpu
->env
;
633 RISCVCPUClass
*mcc
= RISCV_CPU_GET_CLASS(dev
);
634 CPUClass
*cc
= CPU_CLASS(mcc
);
635 int i
, priv_version
= -1;
636 Error
*local_err
= NULL
;
638 cpu_exec_realizefn(cs
, &local_err
);
639 if (local_err
!= NULL
) {
640 error_propagate(errp
, local_err
);
644 if (cpu
->cfg
.priv_spec
) {
645 if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.12.0")) {
646 priv_version
= PRIV_VERSION_1_12_0
;
647 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.11.0")) {
648 priv_version
= PRIV_VERSION_1_11_0
;
649 } else if (!g_strcmp0(cpu
->cfg
.priv_spec
, "v1.10.0")) {
650 priv_version
= PRIV_VERSION_1_10_0
;
653 "Unsupported privilege spec version '%s'",
659 if (priv_version
>= PRIV_VERSION_1_10_0
) {
660 set_priv_version(env
, priv_version
);
663 /* Force disable extensions if priv spec version does not match */
664 for (i
= 0; i
< ARRAY_SIZE(isa_edata_arr
); i
++) {
665 if (isa_ext_is_enabled(cpu
, &isa_edata_arr
[i
]) &&
666 (env
->priv_ver
< isa_edata_arr
[i
].min_version
)) {
667 isa_ext_update_enabled(cpu
, &isa_edata_arr
[i
], false);
668 #ifndef CONFIG_USER_ONLY
669 warn_report("disabling %s extension for hart 0x%lx because "
670 "privilege spec version does not match",
671 isa_edata_arr
[i
].name
, (unsigned long)env
->mhartid
);
673 warn_report("disabling %s extension because "
674 "privilege spec version does not match",
675 isa_edata_arr
[i
].name
);
681 riscv_set_feature(env
, RISCV_FEATURE_MMU
);
685 riscv_set_feature(env
, RISCV_FEATURE_PMP
);
688 * Enhanced PMP should only be available
689 * on harts with PMP support
692 riscv_set_feature(env
, RISCV_FEATURE_EPMP
);
696 if (cpu
->cfg
.debug
) {
697 riscv_set_feature(env
, RISCV_FEATURE_DEBUG
);
701 #ifndef CONFIG_USER_ONLY
702 if (cpu
->cfg
.ext_sstc
) {
703 riscv_timer_init(cpu
);
705 #endif /* CONFIG_USER_ONLY */
707 /* Validate that MISA_MXL is set properly. */
708 switch (env
->misa_mxl_max
) {
709 #ifdef TARGET_RISCV64
712 cc
->gdb_core_xml_file
= "riscv-64bit-cpu.xml";
716 cc
->gdb_core_xml_file
= "riscv-32bit-cpu.xml";
719 g_assert_not_reached();
721 assert(env
->misa_mxl_max
== env
->misa_mxl
);
723 /* If only MISA_EXT is unset for misa, then set it from properties */
724 if (env
->misa_ext
== 0) {
727 /* Do some ISA extension error checking */
728 if (cpu
->cfg
.ext_g
&& !(cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_m
&&
729 cpu
->cfg
.ext_a
&& cpu
->cfg
.ext_f
&&
731 cpu
->cfg
.ext_icsr
&& cpu
->cfg
.ext_ifencei
)) {
732 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
733 cpu
->cfg
.ext_i
= true;
734 cpu
->cfg
.ext_m
= true;
735 cpu
->cfg
.ext_a
= true;
736 cpu
->cfg
.ext_f
= true;
737 cpu
->cfg
.ext_d
= true;
738 cpu
->cfg
.ext_icsr
= true;
739 cpu
->cfg
.ext_ifencei
= true;
742 if (cpu
->cfg
.ext_i
&& cpu
->cfg
.ext_e
) {
744 "I and E extensions are incompatible");
748 if (!cpu
->cfg
.ext_i
&& !cpu
->cfg
.ext_e
) {
750 "Either I or E extension must be set");
754 if (cpu
->cfg
.ext_s
&& !cpu
->cfg
.ext_u
) {
756 "Setting S extension without U extension is illegal");
760 if (cpu
->cfg
.ext_h
&& !cpu
->cfg
.ext_i
) {
762 "H depends on an I base integer ISA with 32 x registers");
766 if (cpu
->cfg
.ext_h
&& !cpu
->cfg
.ext_s
) {
767 error_setg(errp
, "H extension implicitly requires S-mode");
771 if (cpu
->cfg
.ext_f
&& !cpu
->cfg
.ext_icsr
) {
772 error_setg(errp
, "F extension requires Zicsr");
776 if ((cpu
->cfg
.ext_zawrs
) && !cpu
->cfg
.ext_a
) {
777 error_setg(errp
, "Zawrs extension requires A extension");
781 if ((cpu
->cfg
.ext_zfh
|| cpu
->cfg
.ext_zfhmin
) && !cpu
->cfg
.ext_f
) {
782 error_setg(errp
, "Zfh/Zfhmin extensions require F extension");
786 if (cpu
->cfg
.ext_d
&& !cpu
->cfg
.ext_f
) {
787 error_setg(errp
, "D extension requires F extension");
791 if (cpu
->cfg
.ext_v
&& !cpu
->cfg
.ext_d
) {
792 error_setg(errp
, "V extension requires D extension");
796 if ((cpu
->cfg
.ext_zve32f
|| cpu
->cfg
.ext_zve64f
) && !cpu
->cfg
.ext_f
) {
797 error_setg(errp
, "Zve32f/Zve64f extensions require F extension");
801 /* Set the ISA extensions, checks should have happened above */
802 if (cpu
->cfg
.ext_zdinx
|| cpu
->cfg
.ext_zhinx
||
803 cpu
->cfg
.ext_zhinxmin
) {
804 cpu
->cfg
.ext_zfinx
= true;
807 if (cpu
->cfg
.ext_zfinx
) {
808 if (!cpu
->cfg
.ext_icsr
) {
809 error_setg(errp
, "Zfinx extension requires Zicsr");
812 if (cpu
->cfg
.ext_f
) {
814 "Zfinx cannot be supported together with F extension");
819 if (cpu
->cfg
.ext_zk
) {
820 cpu
->cfg
.ext_zkn
= true;
821 cpu
->cfg
.ext_zkr
= true;
822 cpu
->cfg
.ext_zkt
= true;
825 if (cpu
->cfg
.ext_zkn
) {
826 cpu
->cfg
.ext_zbkb
= true;
827 cpu
->cfg
.ext_zbkc
= true;
828 cpu
->cfg
.ext_zbkx
= true;
829 cpu
->cfg
.ext_zkne
= true;
830 cpu
->cfg
.ext_zknd
= true;
831 cpu
->cfg
.ext_zknh
= true;
834 if (cpu
->cfg
.ext_zks
) {
835 cpu
->cfg
.ext_zbkb
= true;
836 cpu
->cfg
.ext_zbkc
= true;
837 cpu
->cfg
.ext_zbkx
= true;
838 cpu
->cfg
.ext_zksed
= true;
839 cpu
->cfg
.ext_zksh
= true;
842 if (cpu
->cfg
.ext_i
) {
845 if (cpu
->cfg
.ext_e
) {
848 if (cpu
->cfg
.ext_m
) {
851 if (cpu
->cfg
.ext_a
) {
854 if (cpu
->cfg
.ext_f
) {
857 if (cpu
->cfg
.ext_d
) {
860 if (cpu
->cfg
.ext_c
) {
863 if (cpu
->cfg
.ext_s
) {
866 if (cpu
->cfg
.ext_u
) {
869 if (cpu
->cfg
.ext_h
) {
872 if (cpu
->cfg
.ext_v
) {
873 int vext_version
= VEXT_VERSION_1_00_0
;
875 if (!is_power_of_2(cpu
->cfg
.vlen
)) {
877 "Vector extension VLEN must be power of 2");
880 if (cpu
->cfg
.vlen
> RV_VLEN_MAX
|| cpu
->cfg
.vlen
< 128) {
882 "Vector extension implementation only supports VLEN "
883 "in the range [128, %d]", RV_VLEN_MAX
);
886 if (!is_power_of_2(cpu
->cfg
.elen
)) {
888 "Vector extension ELEN must be power of 2");
891 if (cpu
->cfg
.elen
> 64 || cpu
->cfg
.elen
< 8) {
893 "Vector extension implementation only supports ELEN "
894 "in the range [8, 64]");
897 if (cpu
->cfg
.vext_spec
) {
898 if (!g_strcmp0(cpu
->cfg
.vext_spec
, "v1.0")) {
899 vext_version
= VEXT_VERSION_1_00_0
;
902 "Unsupported vector spec version '%s'",
907 qemu_log("vector version is not specified, "
908 "use the default value v1.0\n");
910 set_vext_version(env
, vext_version
);
912 if (cpu
->cfg
.ext_j
) {
916 set_misa(env
, env
->misa_mxl
, ext
);
919 #ifndef CONFIG_USER_ONLY
920 if (cpu
->cfg
.pmu_num
) {
921 if (!riscv_pmu_init(cpu
, cpu
->cfg
.pmu_num
) && cpu
->cfg
.ext_sscofpmf
) {
922 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
923 riscv_pmu_timer_cb
, cpu
);
928 riscv_cpu_register_gdb_regs_for_features(cs
);
933 mcc
->parent_realize(dev
, errp
);
936 #ifndef CONFIG_USER_ONLY
937 static void riscv_cpu_set_irq(void *opaque
, int irq
, int level
)
939 RISCVCPU
*cpu
= RISCV_CPU(opaque
);
940 CPURISCVState
*env
= &cpu
->env
;
942 if (irq
< IRQ_LOCAL_MAX
) {
956 kvm_riscv_set_irq(cpu
, irq
, level
);
958 riscv_cpu_update_mip(cpu
, 1 << irq
, BOOL_TO_MASK(level
));
963 kvm_riscv_set_irq(cpu
, irq
, level
);
965 env
->external_seip
= level
;
966 riscv_cpu_update_mip(cpu
, 1 << irq
,
967 BOOL_TO_MASK(level
| env
->software_seip
));
971 g_assert_not_reached();
973 } else if (irq
< (IRQ_LOCAL_MAX
+ IRQ_LOCAL_GUEST_MAX
)) {
974 /* Require H-extension for handling guest local interrupts */
975 if (!riscv_has_ext(env
, RVH
)) {
976 g_assert_not_reached();
979 /* Compute bit position in HGEIP CSR */
980 irq
= irq
- IRQ_LOCAL_MAX
+ 1;
981 if (env
->geilen
< irq
) {
982 g_assert_not_reached();
985 /* Update HGEIP CSR */
986 env
->hgeip
&= ~((target_ulong
)1 << irq
);
988 env
->hgeip
|= (target_ulong
)1 << irq
;
991 /* Update mip.SGEIP bit */
992 riscv_cpu_update_mip(cpu
, MIP_SGEIP
,
993 BOOL_TO_MASK(!!(env
->hgeie
& env
->hgeip
)));
995 g_assert_not_reached();
998 #endif /* CONFIG_USER_ONLY */
1000 static void riscv_cpu_init(Object
*obj
)
1002 RISCVCPU
*cpu
= RISCV_CPU(obj
);
1004 cpu
->cfg
.ext_ifencei
= true;
1005 cpu
->cfg
.ext_icsr
= true;
1006 cpu
->cfg
.mmu
= true;
1007 cpu
->cfg
.pmp
= true;
1009 cpu_set_cpustate_pointers(cpu
);
1011 #ifndef CONFIG_USER_ONLY
1012 qdev_init_gpio_in(DEVICE(cpu
), riscv_cpu_set_irq
,
1013 IRQ_LOCAL_MAX
+ IRQ_LOCAL_GUEST_MAX
);
1014 #endif /* CONFIG_USER_ONLY */
1017 static Property riscv_cpu_extensions
[] = {
1018 /* Defaults for standard extensions */
1019 DEFINE_PROP_BOOL("i", RISCVCPU
, cfg
.ext_i
, true),
1020 DEFINE_PROP_BOOL("e", RISCVCPU
, cfg
.ext_e
, false),
1021 DEFINE_PROP_BOOL("g", RISCVCPU
, cfg
.ext_g
, false),
1022 DEFINE_PROP_BOOL("m", RISCVCPU
, cfg
.ext_m
, true),
1023 DEFINE_PROP_BOOL("a", RISCVCPU
, cfg
.ext_a
, true),
1024 DEFINE_PROP_BOOL("f", RISCVCPU
, cfg
.ext_f
, true),
1025 DEFINE_PROP_BOOL("d", RISCVCPU
, cfg
.ext_d
, true),
1026 DEFINE_PROP_BOOL("c", RISCVCPU
, cfg
.ext_c
, true),
1027 DEFINE_PROP_BOOL("s", RISCVCPU
, cfg
.ext_s
, true),
1028 DEFINE_PROP_BOOL("u", RISCVCPU
, cfg
.ext_u
, true),
1029 DEFINE_PROP_BOOL("v", RISCVCPU
, cfg
.ext_v
, false),
1030 DEFINE_PROP_BOOL("h", RISCVCPU
, cfg
.ext_h
, true),
1031 DEFINE_PROP_UINT8("pmu-num", RISCVCPU
, cfg
.pmu_num
, 16),
1032 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU
, cfg
.ext_sscofpmf
, false),
1033 DEFINE_PROP_BOOL("Zifencei", RISCVCPU
, cfg
.ext_ifencei
, true),
1034 DEFINE_PROP_BOOL("Zicsr", RISCVCPU
, cfg
.ext_icsr
, true),
1035 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU
, cfg
.ext_zihintpause
, true),
1036 DEFINE_PROP_BOOL("Zawrs", RISCVCPU
, cfg
.ext_zawrs
, true),
1037 DEFINE_PROP_BOOL("Zfh", RISCVCPU
, cfg
.ext_zfh
, false),
1038 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU
, cfg
.ext_zfhmin
, false),
1039 DEFINE_PROP_BOOL("Zve32f", RISCVCPU
, cfg
.ext_zve32f
, false),
1040 DEFINE_PROP_BOOL("Zve64f", RISCVCPU
, cfg
.ext_zve64f
, false),
1041 DEFINE_PROP_BOOL("mmu", RISCVCPU
, cfg
.mmu
, true),
1042 DEFINE_PROP_BOOL("pmp", RISCVCPU
, cfg
.pmp
, true),
1043 DEFINE_PROP_BOOL("sstc", RISCVCPU
, cfg
.ext_sstc
, true),
1045 DEFINE_PROP_STRING("priv_spec", RISCVCPU
, cfg
.priv_spec
),
1046 DEFINE_PROP_STRING("vext_spec", RISCVCPU
, cfg
.vext_spec
),
1047 DEFINE_PROP_UINT16("vlen", RISCVCPU
, cfg
.vlen
, 128),
1048 DEFINE_PROP_UINT16("elen", RISCVCPU
, cfg
.elen
, 64),
1050 DEFINE_PROP_BOOL("svinval", RISCVCPU
, cfg
.ext_svinval
, false),
1051 DEFINE_PROP_BOOL("svnapot", RISCVCPU
, cfg
.ext_svnapot
, false),
1052 DEFINE_PROP_BOOL("svpbmt", RISCVCPU
, cfg
.ext_svpbmt
, false),
1054 DEFINE_PROP_BOOL("zba", RISCVCPU
, cfg
.ext_zba
, true),
1055 DEFINE_PROP_BOOL("zbb", RISCVCPU
, cfg
.ext_zbb
, true),
1056 DEFINE_PROP_BOOL("zbc", RISCVCPU
, cfg
.ext_zbc
, true),
1057 DEFINE_PROP_BOOL("zbkb", RISCVCPU
, cfg
.ext_zbkb
, false),
1058 DEFINE_PROP_BOOL("zbkc", RISCVCPU
, cfg
.ext_zbkc
, false),
1059 DEFINE_PROP_BOOL("zbkx", RISCVCPU
, cfg
.ext_zbkx
, false),
1060 DEFINE_PROP_BOOL("zbs", RISCVCPU
, cfg
.ext_zbs
, true),
1061 DEFINE_PROP_BOOL("zk", RISCVCPU
, cfg
.ext_zk
, false),
1062 DEFINE_PROP_BOOL("zkn", RISCVCPU
, cfg
.ext_zkn
, false),
1063 DEFINE_PROP_BOOL("zknd", RISCVCPU
, cfg
.ext_zknd
, false),
1064 DEFINE_PROP_BOOL("zkne", RISCVCPU
, cfg
.ext_zkne
, false),
1065 DEFINE_PROP_BOOL("zknh", RISCVCPU
, cfg
.ext_zknh
, false),
1066 DEFINE_PROP_BOOL("zkr", RISCVCPU
, cfg
.ext_zkr
, false),
1067 DEFINE_PROP_BOOL("zks", RISCVCPU
, cfg
.ext_zks
, false),
1068 DEFINE_PROP_BOOL("zksed", RISCVCPU
, cfg
.ext_zksed
, false),
1069 DEFINE_PROP_BOOL("zksh", RISCVCPU
, cfg
.ext_zksh
, false),
1070 DEFINE_PROP_BOOL("zkt", RISCVCPU
, cfg
.ext_zkt
, false),
1072 DEFINE_PROP_BOOL("zdinx", RISCVCPU
, cfg
.ext_zdinx
, false),
1073 DEFINE_PROP_BOOL("zfinx", RISCVCPU
, cfg
.ext_zfinx
, false),
1074 DEFINE_PROP_BOOL("zhinx", RISCVCPU
, cfg
.ext_zhinx
, false),
1075 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU
, cfg
.ext_zhinxmin
, false),
1077 DEFINE_PROP_BOOL("zmmul", RISCVCPU
, cfg
.ext_zmmul
, false),
1079 /* Vendor-specific custom extensions */
1080 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU
, cfg
.ext_XVentanaCondOps
, false),
1082 /* These are experimental so mark with 'x-' */
1083 DEFINE_PROP_BOOL("x-j", RISCVCPU
, cfg
.ext_j
, false),
1085 DEFINE_PROP_BOOL("x-epmp", RISCVCPU
, cfg
.epmp
, false),
1086 DEFINE_PROP_BOOL("x-smaia", RISCVCPU
, cfg
.ext_smaia
, false),
1087 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU
, cfg
.ext_ssaia
, false),
1089 DEFINE_PROP_END_OF_LIST(),
1093 * Register CPU props based on env.misa_ext. If a non-zero
1094 * value was set, register only the required cpu->cfg.ext_*
1095 * properties and leave. env.misa_ext = 0 means that we want
1096 * all the default properties to be registered.
1098 static void register_cpu_props(DeviceState
*dev
)
1100 RISCVCPU
*cpu
= RISCV_CPU(OBJECT(dev
));
1101 uint32_t misa_ext
= cpu
->env
.misa_ext
;
1105 * If misa_ext is not zero, set cfg properties now to
1106 * allow them to be read during riscv_cpu_realize()
1109 if (cpu
->env
.misa_ext
!= 0) {
1110 cpu
->cfg
.ext_i
= misa_ext
& RVI
;
1111 cpu
->cfg
.ext_e
= misa_ext
& RVE
;
1112 cpu
->cfg
.ext_m
= misa_ext
& RVM
;
1113 cpu
->cfg
.ext_a
= misa_ext
& RVA
;
1114 cpu
->cfg
.ext_f
= misa_ext
& RVF
;
1115 cpu
->cfg
.ext_d
= misa_ext
& RVD
;
1116 cpu
->cfg
.ext_v
= misa_ext
& RVV
;
1117 cpu
->cfg
.ext_c
= misa_ext
& RVC
;
1118 cpu
->cfg
.ext_s
= misa_ext
& RVS
;
1119 cpu
->cfg
.ext_u
= misa_ext
& RVU
;
1120 cpu
->cfg
.ext_h
= misa_ext
& RVH
;
1121 cpu
->cfg
.ext_j
= misa_ext
& RVJ
;
1124 * We don't want to set the default riscv_cpu_extensions
1130 for (prop
= riscv_cpu_extensions
; prop
&& prop
->name
; prop
++) {
1131 qdev_property_add_static(dev
, prop
);
1135 static Property riscv_cpu_properties
[] = {
1136 DEFINE_PROP_BOOL("debug", RISCVCPU
, cfg
.debug
, true),
1138 DEFINE_PROP_UINT32("mvendorid", RISCVCPU
, cfg
.mvendorid
, 0),
1139 DEFINE_PROP_UINT64("marchid", RISCVCPU
, cfg
.marchid
, RISCV_CPU_MARCHID
),
1140 DEFINE_PROP_UINT64("mimpid", RISCVCPU
, cfg
.mimpid
, RISCV_CPU_MIMPID
),
1142 #ifndef CONFIG_USER_ONLY
1143 DEFINE_PROP_UINT64("resetvec", RISCVCPU
, env
.resetvec
, DEFAULT_RSTVEC
),
1146 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU
, cfg
.short_isa_string
, false),
1148 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU
, cfg
.rvv_ta_all_1s
, false),
1149 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU
, cfg
.rvv_ma_all_1s
, false),
1150 DEFINE_PROP_END_OF_LIST(),
1153 static gchar
*riscv_gdb_arch_name(CPUState
*cs
)
1155 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1156 CPURISCVState
*env
= &cpu
->env
;
1158 switch (riscv_cpu_mxl(env
)) {
1160 return g_strdup("riscv:rv32");
1163 return g_strdup("riscv:rv64");
1165 g_assert_not_reached();
1169 static const char *riscv_gdb_get_dynamic_xml(CPUState
*cs
, const char *xmlname
)
1171 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1173 if (strcmp(xmlname
, "riscv-csr.xml") == 0) {
1174 return cpu
->dyn_csr_xml
;
1175 } else if (strcmp(xmlname
, "riscv-vector.xml") == 0) {
1176 return cpu
->dyn_vreg_xml
;
1182 #ifndef CONFIG_USER_ONLY
1183 #include "hw/core/sysemu-cpu-ops.h"
1185 static const struct SysemuCPUOps riscv_sysemu_ops
= {
1186 .get_phys_page_debug
= riscv_cpu_get_phys_page_debug
,
1187 .write_elf64_note
= riscv_cpu_write_elf64_note
,
1188 .write_elf32_note
= riscv_cpu_write_elf32_note
,
1189 .legacy_vmsd
= &vmstate_riscv_cpu
,
1193 #include "hw/core/tcg-cpu-ops.h"
1195 static const struct TCGCPUOps riscv_tcg_ops
= {
1196 .initialize
= riscv_translate_init
,
1197 .synchronize_from_tb
= riscv_cpu_synchronize_from_tb
,
1198 .restore_state_to_opc
= riscv_restore_state_to_opc
,
1200 #ifndef CONFIG_USER_ONLY
1201 .tlb_fill
= riscv_cpu_tlb_fill
,
1202 .cpu_exec_interrupt
= riscv_cpu_exec_interrupt
,
1203 .do_interrupt
= riscv_cpu_do_interrupt
,
1204 .do_transaction_failed
= riscv_cpu_do_transaction_failed
,
1205 .do_unaligned_access
= riscv_cpu_do_unaligned_access
,
1206 .debug_excp_handler
= riscv_cpu_debug_excp_handler
,
1207 .debug_check_breakpoint
= riscv_cpu_debug_check_breakpoint
,
1208 .debug_check_watchpoint
= riscv_cpu_debug_check_watchpoint
,
1209 #endif /* !CONFIG_USER_ONLY */
1212 static void riscv_cpu_class_init(ObjectClass
*c
, void *data
)
1214 RISCVCPUClass
*mcc
= RISCV_CPU_CLASS(c
);
1215 CPUClass
*cc
= CPU_CLASS(c
);
1216 DeviceClass
*dc
= DEVICE_CLASS(c
);
1217 ResettableClass
*rc
= RESETTABLE_CLASS(c
);
1219 device_class_set_parent_realize(dc
, riscv_cpu_realize
,
1220 &mcc
->parent_realize
);
1222 resettable_class_set_parent_phases(rc
, NULL
, riscv_cpu_reset_hold
, NULL
,
1223 &mcc
->parent_phases
);
1225 cc
->class_by_name
= riscv_cpu_class_by_name
;
1226 cc
->has_work
= riscv_cpu_has_work
;
1227 cc
->dump_state
= riscv_cpu_dump_state
;
1228 cc
->set_pc
= riscv_cpu_set_pc
;
1229 cc
->get_pc
= riscv_cpu_get_pc
;
1230 cc
->gdb_read_register
= riscv_cpu_gdb_read_register
;
1231 cc
->gdb_write_register
= riscv_cpu_gdb_write_register
;
1232 cc
->gdb_num_core_regs
= 33;
1233 cc
->gdb_stop_before_watchpoint
= true;
1234 cc
->disas_set_info
= riscv_cpu_disas_set_info
;
1235 #ifndef CONFIG_USER_ONLY
1236 cc
->sysemu_ops
= &riscv_sysemu_ops
;
1238 cc
->gdb_arch_name
= riscv_gdb_arch_name
;
1239 cc
->gdb_get_dynamic_xml
= riscv_gdb_get_dynamic_xml
;
1240 cc
->tcg_ops
= &riscv_tcg_ops
;
1242 device_class_set_props(dc
, riscv_cpu_properties
);
1245 static void riscv_isa_string_ext(RISCVCPU
*cpu
, char **isa_str
, int max_str_len
)
1247 char *old
= *isa_str
;
1248 char *new = *isa_str
;
1251 for (i
= 0; i
< ARRAY_SIZE(isa_edata_arr
); i
++) {
1252 if (isa_edata_arr
[i
].multi_letter
&&
1253 isa_ext_is_enabled(cpu
, &isa_edata_arr
[i
])) {
1254 new = g_strconcat(old
, "_", isa_edata_arr
[i
].name
, NULL
);
1263 char *riscv_isa_string(RISCVCPU
*cpu
)
1266 const size_t maxlen
= sizeof("rv128") + sizeof(riscv_single_letter_exts
);
1267 char *isa_str
= g_new(char, maxlen
);
1268 char *p
= isa_str
+ snprintf(isa_str
, maxlen
, "rv%d", TARGET_LONG_BITS
);
1269 for (i
= 0; i
< sizeof(riscv_single_letter_exts
) - 1; i
++) {
1270 if (cpu
->env
.misa_ext
& RV(riscv_single_letter_exts
[i
])) {
1271 *p
++ = qemu_tolower(riscv_single_letter_exts
[i
]);
1275 if (!cpu
->cfg
.short_isa_string
) {
1276 riscv_isa_string_ext(cpu
, &isa_str
, maxlen
);
1281 static gint
riscv_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1283 ObjectClass
*class_a
= (ObjectClass
*)a
;
1284 ObjectClass
*class_b
= (ObjectClass
*)b
;
1285 const char *name_a
, *name_b
;
1287 name_a
= object_class_get_name(class_a
);
1288 name_b
= object_class_get_name(class_b
);
1289 return strcmp(name_a
, name_b
);
1292 static void riscv_cpu_list_entry(gpointer data
, gpointer user_data
)
1294 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
1295 int len
= strlen(typename
) - strlen(RISCV_CPU_TYPE_SUFFIX
);
1297 qemu_printf("%.*s\n", len
, typename
);
1300 void riscv_cpu_list(void)
1304 list
= object_class_get_list(TYPE_RISCV_CPU
, false);
1305 list
= g_slist_sort(list
, riscv_cpu_list_compare
);
1306 g_slist_foreach(list
, riscv_cpu_list_entry
, NULL
);
1310 #define DEFINE_CPU(type_name, initfn) \
1312 .name = type_name, \
1313 .parent = TYPE_RISCV_CPU, \
1314 .instance_init = initfn \
1317 static const TypeInfo riscv_cpu_type_infos
[] = {
1319 .name
= TYPE_RISCV_CPU
,
1321 .instance_size
= sizeof(RISCVCPU
),
1322 .instance_align
= __alignof__(RISCVCPU
),
1323 .instance_init
= riscv_cpu_init
,
1325 .class_size
= sizeof(RISCVCPUClass
),
1326 .class_init
= riscv_cpu_class_init
,
1328 DEFINE_CPU(TYPE_RISCV_CPU_ANY
, riscv_any_cpu_init
),
1329 #if defined(CONFIG_KVM)
1330 DEFINE_CPU(TYPE_RISCV_CPU_HOST
, riscv_host_cpu_init
),
1332 #if defined(TARGET_RISCV32)
1333 DEFINE_CPU(TYPE_RISCV_CPU_BASE32
, rv32_base_cpu_init
),
1334 DEFINE_CPU(TYPE_RISCV_CPU_IBEX
, rv32_ibex_cpu_init
),
1335 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31
, rv32_sifive_e_cpu_init
),
1336 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34
, rv32_imafcu_nommu_cpu_init
),
1337 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34
, rv32_sifive_u_cpu_init
),
1338 #elif defined(TARGET_RISCV64)
1339 DEFINE_CPU(TYPE_RISCV_CPU_BASE64
, rv64_base_cpu_init
),
1340 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51
, rv64_sifive_e_cpu_init
),
1341 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54
, rv64_sifive_u_cpu_init
),
1342 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C
, rv64_sifive_u_cpu_init
),
1343 DEFINE_CPU(TYPE_RISCV_CPU_BASE128
, rv128_base_cpu_init
),
1347 DEFINE_TYPES(riscv_cpu_type_infos
)